2 * Marvell Wireless LAN device driver: SDIO specific definitions
4 * Copyright (C) 2011, Marvell International Ltd.
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_ids.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/host.h>
32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
42 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
44 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
46 #define SDIO_MPA_ADDR_BASE 0x1000
48 #define CTRL_PORT_MASK 0x0001
50 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
51 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
52 #define HOST_TERM_CMD53 (0x1U << 2)
54 #define MEM_PORT 0x10000
55 #define CMD_RD_LEN_0 0xB4
56 #define CMD_RD_LEN_1 0xB5
57 #define CARD_CONFIG_2_1_REG 0xCD
58 #define CMD53_NEW_MODE (0x1U << 0)
59 #define CMD_CONFIG_0 0xB8
60 #define CMD_PORT_RD_LEN_EN (0x1U << 2)
61 #define CMD_CONFIG_1 0xB9
62 #define CMD_PORT_AUTO_EN (0x1U << 0)
63 #define CMD_PORT_SLCT 0x8000
64 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
65 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
67 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
68 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
70 /* Misc. Config Register : Auto Re-enable interrupts */
71 #define AUTO_RE_ENABLE_INT BIT(4)
73 /* Host Control Registers */
74 /* Host Control Registers : I/O port 0 */
75 #define IO_PORT_0_REG 0x78
76 /* Host Control Registers : I/O port 1 */
77 #define IO_PORT_1_REG 0x79
78 /* Host Control Registers : I/O port 2 */
79 #define IO_PORT_2_REG 0x7A
81 /* Host Control Registers : Configuration */
82 #define CONFIGURATION_REG 0x00
83 /* Host Control Registers : Host power up */
84 #define HOST_POWER_UP (0x1U << 1)
86 /* Host Control Registers : Host interrupt mask */
87 #define HOST_INT_MASK_REG 0x02
88 /* Host Control Registers : Upload host interrupt mask */
89 #define UP_LD_HOST_INT_MASK (0x1U)
90 /* Host Control Registers : Download host interrupt mask */
91 #define DN_LD_HOST_INT_MASK (0x2U)
93 /* Host Control Registers : Host interrupt status */
94 #define HOST_INTSTATUS_REG 0x03
95 /* Host Control Registers : Upload host interrupt status */
96 #define UP_LD_HOST_INT_STATUS (0x1U)
97 /* Host Control Registers : Download host interrupt status */
98 #define DN_LD_HOST_INT_STATUS (0x2U)
100 /* Host Control Registers : Host interrupt RSR */
101 #define HOST_INT_RSR_REG 0x01
103 /* Host Control Registers : Host interrupt status */
104 #define HOST_INT_STATUS_REG 0x28
106 /* Card Control Registers : Card I/O ready */
107 #define CARD_IO_READY (0x1U << 3)
108 /* Card Control Registers : Download card ready */
109 #define DN_LD_CARD_RDY (0x1U << 0)
111 /* Max retry number of CMD53 write */
112 #define MAX_WRITE_IOMEM_RETRY 2
114 /* SDIO Tx aggregation in progress ? */
115 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
117 /* SDIO Tx aggregation buffer room for next packet ? */
118 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
119 <= a->mpa_tx.buf_size)
121 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
122 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
123 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
125 a->mpa_tx.buf_len += pkt_len; \
126 if (!a->mpa_tx.pkt_cnt) \
127 a->mpa_tx.start_port = port; \
128 if (a->mpa_tx.start_port <= port) \
129 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
131 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
134 a->mpa_tx.pkt_cnt++; \
137 /* SDIO Tx aggregation limit ? */
138 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
139 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
141 /* Reset SDIO Tx aggregation buffer parameters */
142 #define MP_TX_AGGR_BUF_RESET(a) do { \
143 a->mpa_tx.pkt_cnt = 0; \
144 a->mpa_tx.buf_len = 0; \
145 a->mpa_tx.ports = 0; \
146 a->mpa_tx.start_port = 0; \
149 /* SDIO Rx aggregation limit ? */
150 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
151 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
153 /* SDIO Rx aggregation in progress ? */
154 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
156 /* SDIO Rx aggregation buffer room for next packet ? */
157 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
158 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
160 /* Reset SDIO Rx aggregation buffer parameters */
161 #define MP_RX_AGGR_BUF_RESET(a) do { \
162 a->mpa_rx.pkt_cnt = 0; \
163 a->mpa_rx.buf_len = 0; \
164 a->mpa_rx.ports = 0; \
165 a->mpa_rx.start_port = 0; \
168 /* data structure for SDIO MPA TX */
169 struct mwifiex_sdio_mpa_tx
{
170 /* multiport tx aggregation buffer pointer */
181 struct mwifiex_sdio_mpa_rx
{
188 struct sk_buff
**skb_arr
;
196 int mwifiex_bus_register(void);
197 void mwifiex_bus_unregister(void);
199 struct mwifiex_sdio_card_reg
{
221 u8 card_misc_cfg_reg
;
224 struct sdio_mmc_card
{
225 struct sdio_func
*func
;
226 struct mwifiex_adapter
*adapter
;
228 const char *firmware
;
229 const struct mwifiex_sdio_card_reg
*reg
;
232 bool supports_sdio_new_mode
;
233 bool has_control_mask
;
235 u32 mp_tx_agg_buf_size
;
236 u32 mp_rx_agg_buf_size
;
242 u32 mp_data_port_mask
;
249 struct mwifiex_sdio_mpa_tx mpa_tx
;
250 struct mwifiex_sdio_mpa_rx mpa_rx
;
253 struct mwifiex_sdio_device
{
254 const char *firmware
;
255 const struct mwifiex_sdio_card_reg
*reg
;
258 bool supports_sdio_new_mode
;
259 bool has_control_mask
;
261 u32 mp_tx_agg_buf_size
;
262 u32 mp_rx_agg_buf_size
;
265 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx
= {
268 .base_0_reg
= 0x0040,
269 .base_1_reg
= 0x0041,
271 .host_int_enable
= UP_LD_HOST_INT_MASK
| DN_LD_HOST_INT_MASK
,
272 .status_reg_0
= 0x60,
273 .status_reg_1
= 0x61,
274 .sdio_int_mask
= 0x3f,
275 .data_port_mask
= 0x0000fffe,
283 .card_misc_cfg_reg
= 0x6c,
286 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897
= {
292 .host_int_enable
= UP_LD_HOST_INT_MASK
| DN_LD_HOST_INT_MASK
|
293 CMD_PORT_UPLD_INT_MASK
| CMD_PORT_DNLD_INT_MASK
,
294 .status_reg_0
= 0xc0,
295 .status_reg_1
= 0xc1,
296 .sdio_int_mask
= 0xff,
297 .data_port_mask
= 0xffffffff,
301 .rd_bitmap_1l
= 0x06,
302 .rd_bitmap_1u
= 0x07,
305 .wr_bitmap_1l
= 0x0a,
306 .wr_bitmap_1u
= 0x0b,
309 .card_misc_cfg_reg
= 0xcc,
312 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786
= {
313 .firmware
= SD8786_DEFAULT_FW_NAME
,
314 .reg
= &mwifiex_reg_sd87xx
,
316 .mp_agg_pkt_limit
= 8,
317 .supports_sdio_new_mode
= false,
318 .has_control_mask
= true,
319 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
320 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
321 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
324 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787
= {
325 .firmware
= SD8787_DEFAULT_FW_NAME
,
326 .reg
= &mwifiex_reg_sd87xx
,
328 .mp_agg_pkt_limit
= 8,
329 .supports_sdio_new_mode
= false,
330 .has_control_mask
= true,
331 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
332 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
333 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
336 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797
= {
337 .firmware
= SD8797_DEFAULT_FW_NAME
,
338 .reg
= &mwifiex_reg_sd87xx
,
340 .mp_agg_pkt_limit
= 8,
341 .supports_sdio_new_mode
= false,
342 .has_control_mask
= true,
343 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
344 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
345 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
348 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897
= {
349 .firmware
= SD8897_DEFAULT_FW_NAME
,
350 .reg
= &mwifiex_reg_sd8897
,
352 .mp_agg_pkt_limit
= 16,
353 .supports_sdio_new_mode
= true,
354 .has_control_mask
= false,
355 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_4K
,
356 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_32K
,
357 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_32K
,
361 * .cmdrsp_complete handler
363 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter
*adapter
,
366 dev_kfree_skb_any(skb
);
371 * .event_complete handler
373 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter
*adapter
,
376 dev_kfree_skb_any(skb
);
381 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card
*card
)
385 if (card
->curr_rd_port
< card
->mpa_rx
.start_port
) {
386 if (card
->supports_sdio_new_mode
)
387 tmp
= card
->mp_end_port
>> 1;
389 tmp
= card
->mp_agg_pkt_limit
;
391 if (((card
->max_ports
- card
->mpa_rx
.start_port
) +
392 card
->curr_rd_port
) >= tmp
)
396 if (!card
->supports_sdio_new_mode
)
399 if ((card
->curr_rd_port
- card
->mpa_rx
.start_port
) >=
400 (card
->mp_end_port
>> 1))
407 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card
*card
)
411 if (card
->curr_wr_port
< card
->mpa_tx
.start_port
) {
412 if (card
->supports_sdio_new_mode
)
413 tmp
= card
->mp_end_port
>> 1;
415 tmp
= card
->mp_agg_pkt_limit
;
417 if (((card
->max_ports
- card
->mpa_tx
.start_port
) +
418 card
->curr_wr_port
) >= tmp
)
422 if (!card
->supports_sdio_new_mode
)
425 if ((card
->curr_wr_port
- card
->mpa_tx
.start_port
) >=
426 (card
->mp_end_port
>> 1))
432 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
433 static inline void mp_rx_aggr_setup(struct sdio_mmc_card
*card
,
434 struct sk_buff
*skb
, u8 port
)
436 card
->mpa_rx
.buf_len
+= skb
->len
;
438 if (!card
->mpa_rx
.pkt_cnt
)
439 card
->mpa_rx
.start_port
= port
;
441 if (card
->supports_sdio_new_mode
) {
442 card
->mpa_rx
.ports
|= (1 << port
);
444 if (card
->mpa_rx
.start_port
<= port
)
445 card
->mpa_rx
.ports
|= 1 << (card
->mpa_rx
.pkt_cnt
);
447 card
->mpa_rx
.ports
|= 1 << (card
->mpa_rx
.pkt_cnt
+ 1);
449 card
->mpa_rx
.skb_arr
[card
->mpa_rx
.pkt_cnt
] = skb
;
450 card
->mpa_rx
.len_arr
[card
->mpa_rx
.pkt_cnt
] = skb
->len
;
451 card
->mpa_rx
.pkt_cnt
++;
453 #endif /* _MWIFIEX_SDIO_H */