2 * Marvell Wireless LAN device driver: SDIO specific definitions
4 * Copyright (C) 2011-2014, Marvell International Ltd.
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_ids.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/host.h>
32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
36 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
37 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
44 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
46 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
48 #define MWIFIEX_MAX_FUNC2_REG_NUM 13
49 #define MWIFIEX_SDIO_SCRATCH_SIZE 10
51 #define SDIO_MPA_ADDR_BASE 0x1000
53 #define CTRL_PORT_MASK 0x0001
55 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
56 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
57 #define HOST_TERM_CMD53 (0x1U << 2)
59 #define MEM_PORT 0x10000
61 #define CMD53_NEW_MODE (0x1U << 0)
62 #define CMD_PORT_RD_LEN_EN (0x1U << 2)
63 #define CMD_PORT_AUTO_EN (0x1U << 0)
64 #define CMD_PORT_SLCT 0x8000
65 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
66 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
68 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
69 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
70 /* we leave one block of 256 bytes for DMA alignment*/
71 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280)
73 /* Misc. Config Register : Auto Re-enable interrupts */
74 #define AUTO_RE_ENABLE_INT BIT(4)
76 /* Host Control Registers : Configuration */
77 #define CONFIGURATION_REG 0x00
78 /* Host Control Registers : Host power up */
79 #define HOST_POWER_UP (0x1U << 1)
81 /* Host Control Registers : Upload host interrupt mask */
82 #define UP_LD_HOST_INT_MASK (0x1U)
83 /* Host Control Registers : Download host interrupt mask */
84 #define DN_LD_HOST_INT_MASK (0x2U)
86 /* Host Control Registers : Upload host interrupt status */
87 #define UP_LD_HOST_INT_STATUS (0x1U)
88 /* Host Control Registers : Download host interrupt status */
89 #define DN_LD_HOST_INT_STATUS (0x2U)
91 /* Host Control Registers : Host interrupt status */
92 #define CARD_INT_STATUS_REG 0x28
94 /* Card Control Registers : Card I/O ready */
95 #define CARD_IO_READY (0x1U << 3)
96 /* Card Control Registers : Download card ready */
97 #define DN_LD_CARD_RDY (0x1U << 0)
99 /* Max retry number of CMD53 write */
100 #define MAX_WRITE_IOMEM_RETRY 2
102 /* SDIO Tx aggregation in progress ? */
103 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
105 /* SDIO Tx aggregation buffer room for next packet ? */
106 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
107 <= a->mpa_tx.buf_size)
109 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
110 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
111 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
113 a->mpa_tx.buf_len += pkt_len; \
114 if (!a->mpa_tx.pkt_cnt) \
115 a->mpa_tx.start_port = port; \
116 if (a->mpa_tx.start_port <= port) \
117 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
119 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
122 a->mpa_tx.pkt_cnt++; \
125 /* SDIO Tx aggregation limit ? */
126 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
127 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
129 /* Reset SDIO Tx aggregation buffer parameters */
130 #define MP_TX_AGGR_BUF_RESET(a) do { \
131 a->mpa_tx.pkt_cnt = 0; \
132 a->mpa_tx.buf_len = 0; \
133 a->mpa_tx.ports = 0; \
134 a->mpa_tx.start_port = 0; \
137 /* SDIO Rx aggregation limit ? */
138 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
139 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
141 /* SDIO Rx aggregation in progress ? */
142 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
144 /* SDIO Rx aggregation buffer room for next packet ? */
145 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
146 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
148 /* Reset SDIO Rx aggregation buffer parameters */
149 #define MP_RX_AGGR_BUF_RESET(a) do { \
150 a->mpa_rx.pkt_cnt = 0; \
151 a->mpa_rx.buf_len = 0; \
152 a->mpa_rx.ports = 0; \
153 a->mpa_rx.start_port = 0; \
156 /* data structure for SDIO MPA TX */
157 struct mwifiex_sdio_mpa_tx
{
158 /* multiport tx aggregation buffer pointer */
169 struct mwifiex_sdio_mpa_rx
{
176 struct sk_buff
**skb_arr
;
184 int mwifiex_bus_register(void);
185 void mwifiex_bus_unregister(void);
187 struct mwifiex_sdio_card_reg
{
195 u8 host_int_status_reg
;
196 u8 host_int_mask_reg
;
215 u8 card_misc_cfg_reg
;
228 u8 func1_dump_reg_start
;
229 u8 func1_dump_reg_end
;
230 u8 func1_scratch_reg
;
231 u8 func1_spec_reg_num
;
232 u8 func1_spec_reg_table
[MWIFIEX_MAX_FUNC2_REG_NUM
];
235 struct sdio_mmc_card
{
236 struct sdio_func
*func
;
237 struct mwifiex_adapter
*adapter
;
239 const char *firmware
;
240 const struct mwifiex_sdio_card_reg
*reg
;
244 u32 mp_tx_agg_buf_size
;
245 u32 mp_rx_agg_buf_size
;
251 u32 mp_data_port_mask
;
257 bool supports_sdio_new_mode
;
258 bool has_control_mask
;
263 struct mwifiex_sdio_mpa_tx mpa_tx
;
264 struct mwifiex_sdio_mpa_rx mpa_rx
;
266 /* needed for card reset */
267 const struct sdio_device_id
*device_id
;
270 struct mwifiex_sdio_device
{
271 const char *firmware
;
272 const struct mwifiex_sdio_card_reg
*reg
;
276 u32 mp_tx_agg_buf_size
;
277 u32 mp_rx_agg_buf_size
;
278 bool supports_sdio_new_mode
;
279 bool has_control_mask
;
285 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx
= {
288 .base_0_reg
= 0x0040,
289 .base_1_reg
= 0x0041,
291 .host_int_enable
= UP_LD_HOST_INT_MASK
| DN_LD_HOST_INT_MASK
,
292 .host_int_rsr_reg
= 0x1,
293 .host_int_mask_reg
= 0x02,
294 .host_int_status_reg
= 0x03,
295 .status_reg_0
= 0x60,
296 .status_reg_1
= 0x61,
297 .sdio_int_mask
= 0x3f,
298 .data_port_mask
= 0x0000fffe,
299 .io_port_0_reg
= 0x78,
300 .io_port_1_reg
= 0x79,
301 .io_port_2_reg
= 0x7A,
309 .card_misc_cfg_reg
= 0x6c,
310 .func1_dump_reg_start
= 0x0,
311 .func1_dump_reg_end
= 0x9,
312 .func1_scratch_reg
= 0x60,
313 .func1_spec_reg_num
= 5,
314 .func1_spec_reg_table
= {0x28, 0x30, 0x34, 0x38, 0x3c},
317 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897
= {
323 .host_int_enable
= UP_LD_HOST_INT_MASK
| DN_LD_HOST_INT_MASK
|
324 CMD_PORT_UPLD_INT_MASK
| CMD_PORT_DNLD_INT_MASK
,
325 .host_int_rsr_reg
= 0x1,
326 .host_int_status_reg
= 0x03,
327 .host_int_mask_reg
= 0x02,
328 .status_reg_0
= 0xc0,
329 .status_reg_1
= 0xc1,
330 .sdio_int_mask
= 0xff,
331 .data_port_mask
= 0xffffffff,
332 .io_port_0_reg
= 0xD8,
333 .io_port_1_reg
= 0xD9,
334 .io_port_2_reg
= 0xDA,
338 .rd_bitmap_1l
= 0x06,
339 .rd_bitmap_1u
= 0x07,
342 .wr_bitmap_1l
= 0x0a,
343 .wr_bitmap_1u
= 0x0b,
346 .card_misc_cfg_reg
= 0xcc,
347 .card_cfg_2_1_reg
= 0xcd,
348 .cmd_rd_len_0
= 0xb4,
349 .cmd_rd_len_1
= 0xb5,
350 .cmd_rd_len_2
= 0xb6,
351 .cmd_rd_len_3
= 0xb7,
356 .fw_dump_ctrl
= 0xe2,
357 .fw_dump_start
= 0xe3,
359 .func1_dump_reg_start
= 0x0,
360 .func1_dump_reg_end
= 0xb,
361 .func1_scratch_reg
= 0xc0,
362 .func1_spec_reg_num
= 8,
363 .func1_spec_reg_table
= {0x4C, 0x50, 0x54, 0x55, 0x58,
367 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887
= {
373 .host_int_enable
= UP_LD_HOST_INT_MASK
| DN_LD_HOST_INT_MASK
|
374 CMD_PORT_UPLD_INT_MASK
| CMD_PORT_DNLD_INT_MASK
,
375 .host_int_rsr_reg
= 0x4,
376 .host_int_status_reg
= 0x0C,
377 .host_int_mask_reg
= 0x08,
378 .status_reg_0
= 0x90,
379 .status_reg_1
= 0x91,
380 .sdio_int_mask
= 0xff,
381 .data_port_mask
= 0xffffffff,
382 .io_port_0_reg
= 0xE4,
383 .io_port_1_reg
= 0xE5,
384 .io_port_2_reg
= 0xE6,
388 .rd_bitmap_1l
= 0x12,
389 .rd_bitmap_1u
= 0x13,
392 .wr_bitmap_1l
= 0x16,
393 .wr_bitmap_1u
= 0x17,
396 .card_misc_cfg_reg
= 0xd8,
397 .card_cfg_2_1_reg
= 0xd9,
398 .cmd_rd_len_0
= 0xc0,
399 .cmd_rd_len_1
= 0xc1,
400 .cmd_rd_len_2
= 0xc2,
401 .cmd_rd_len_3
= 0xc3,
406 .func1_dump_reg_start
= 0x10,
407 .func1_dump_reg_end
= 0x17,
408 .func1_scratch_reg
= 0x90,
409 .func1_spec_reg_num
= 13,
410 .func1_spec_reg_table
= {0x08, 0x58, 0x5C, 0x5D, 0x60,
411 0x61, 0x62, 0x64, 0x65, 0x66,
415 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786
= {
416 .firmware
= SD8786_DEFAULT_FW_NAME
,
417 .reg
= &mwifiex_reg_sd87xx
,
419 .mp_agg_pkt_limit
= 8,
420 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
421 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
422 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
423 .supports_sdio_new_mode
= false,
424 .has_control_mask
= true,
425 .can_dump_fw
= false,
426 .can_auto_tdls
= false,
427 .can_ext_scan
= false,
430 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787
= {
431 .firmware
= SD8787_DEFAULT_FW_NAME
,
432 .reg
= &mwifiex_reg_sd87xx
,
434 .mp_agg_pkt_limit
= 8,
435 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
436 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
437 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
438 .supports_sdio_new_mode
= false,
439 .has_control_mask
= true,
440 .can_dump_fw
= false,
441 .can_auto_tdls
= false,
442 .can_ext_scan
= true,
445 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797
= {
446 .firmware
= SD8797_DEFAULT_FW_NAME
,
447 .reg
= &mwifiex_reg_sd87xx
,
449 .mp_agg_pkt_limit
= 8,
450 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
451 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
452 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
453 .supports_sdio_new_mode
= false,
454 .has_control_mask
= true,
455 .can_dump_fw
= false,
456 .can_auto_tdls
= false,
457 .can_ext_scan
= true,
460 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897
= {
461 .firmware
= SD8897_DEFAULT_FW_NAME
,
462 .reg
= &mwifiex_reg_sd8897
,
464 .mp_agg_pkt_limit
= 16,
465 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_4K
,
466 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_MAX
,
467 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_MAX
,
468 .supports_sdio_new_mode
= true,
469 .has_control_mask
= false,
471 .can_auto_tdls
= false,
472 .can_ext_scan
= true,
475 static const struct mwifiex_sdio_device mwifiex_sdio_sd8887
= {
476 .firmware
= SD8887_DEFAULT_FW_NAME
,
477 .reg
= &mwifiex_reg_sd8887
,
479 .mp_agg_pkt_limit
= 16,
480 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
481 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_32K
,
482 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_32K
,
483 .supports_sdio_new_mode
= true,
484 .has_control_mask
= false,
485 .can_dump_fw
= false,
486 .can_auto_tdls
= true,
487 .can_ext_scan
= true,
490 static const struct mwifiex_sdio_device mwifiex_sdio_sd8801
= {
491 .firmware
= SD8801_DEFAULT_FW_NAME
,
492 .reg
= &mwifiex_reg_sd87xx
,
494 .mp_agg_pkt_limit
= 8,
495 .supports_sdio_new_mode
= false,
496 .has_control_mask
= true,
497 .tx_buf_size
= MWIFIEX_TX_DATA_BUF_SIZE_2K
,
498 .mp_tx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
499 .mp_rx_agg_buf_size
= MWIFIEX_MP_AGGR_BUF_SIZE_16K
,
500 .can_dump_fw
= false,
501 .can_auto_tdls
= false,
502 .can_ext_scan
= true,
506 * .cmdrsp_complete handler
508 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter
*adapter
,
511 dev_kfree_skb_any(skb
);
516 * .event_complete handler
518 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter
*adapter
,
521 dev_kfree_skb_any(skb
);
526 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card
*card
)
530 if (card
->curr_rd_port
< card
->mpa_rx
.start_port
) {
531 if (card
->supports_sdio_new_mode
)
532 tmp
= card
->mp_end_port
>> 1;
534 tmp
= card
->mp_agg_pkt_limit
;
536 if (((card
->max_ports
- card
->mpa_rx
.start_port
) +
537 card
->curr_rd_port
) >= tmp
)
541 if (!card
->supports_sdio_new_mode
)
544 if ((card
->curr_rd_port
- card
->mpa_rx
.start_port
) >=
545 (card
->mp_end_port
>> 1))
552 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card
*card
)
556 if (card
->curr_wr_port
< card
->mpa_tx
.start_port
) {
557 if (card
->supports_sdio_new_mode
)
558 tmp
= card
->mp_end_port
>> 1;
560 tmp
= card
->mp_agg_pkt_limit
;
562 if (((card
->max_ports
- card
->mpa_tx
.start_port
) +
563 card
->curr_wr_port
) >= tmp
)
567 if (!card
->supports_sdio_new_mode
)
570 if ((card
->curr_wr_port
- card
->mpa_tx
.start_port
) >=
571 (card
->mp_end_port
>> 1))
577 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
578 static inline void mp_rx_aggr_setup(struct sdio_mmc_card
*card
,
581 card
->mpa_rx
.buf_len
+= rx_len
;
583 if (!card
->mpa_rx
.pkt_cnt
)
584 card
->mpa_rx
.start_port
= port
;
586 if (card
->supports_sdio_new_mode
) {
587 card
->mpa_rx
.ports
|= (1 << port
);
589 if (card
->mpa_rx
.start_port
<= port
)
590 card
->mpa_rx
.ports
|= 1 << (card
->mpa_rx
.pkt_cnt
);
592 card
->mpa_rx
.ports
|= 1 << (card
->mpa_rx
.pkt_cnt
+ 1);
594 card
->mpa_rx
.skb_arr
[card
->mpa_rx
.pkt_cnt
] = NULL
;
595 card
->mpa_rx
.len_arr
[card
->mpa_rx
.pkt_cnt
] = rx_len
;
596 card
->mpa_rx
.pkt_cnt
++;
598 #endif /* _MWIFIEX_SDIO_H */