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mwl8k: remove mwl8k_vif::bssid, which is now useless
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.11"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
89 };
90
91 struct mwl8k_device_info {
92 char *part_name;
93 char *helper_image;
94 char *fw_image;
95 struct rxd_ops *ap_rxd_ops;
96 };
97
98 struct mwl8k_rx_queue {
99 int rxd_count;
100
101 /* hw receives here */
102 int head;
103
104 /* refill descs here */
105 int tail;
106
107 void *rxd;
108 dma_addr_t rxd_dma;
109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
113 };
114
115 struct mwl8k_tx_queue {
116 /* hw transmits here */
117 int head;
118
119 /* sw appends here */
120 int tail;
121
122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
126 };
127
128 struct mwl8k_priv {
129 struct ieee80211_hw *hw;
130 struct pci_dev *pdev;
131
132 struct mwl8k_device_info *device_info;
133
134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
140
141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
144
145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
148 int fw_mutex_depth;
149 struct completion *hostcmd_wait;
150
151 /* lock held over TX and TX reap */
152 spinlock_t tx_lock;
153
154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
156
157 struct ieee80211_vif *vif;
158
159 struct ieee80211_channel *current_channel;
160
161 /* power management status cookie from firmware */
162 u32 *cookie;
163 dma_addr_t cookie_dma;
164
165 u16 num_mcaddrs;
166 u8 hw_rev;
167 u32 fw_rev;
168
169 /*
170 * Running count of TX packets in flight, to avoid
171 * iterating over the transmit rings each time.
172 */
173 int pending_tx_pkts;
174
175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
177
178 /* PHY parameters */
179 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14];
181 struct ieee80211_rate rates[14];
182
183 bool radio_on;
184 bool radio_short_preamble;
185 bool sniffer_enabled;
186 bool wmm_enabled;
187
188 struct work_struct sta_notify_worker;
189 spinlock_t sta_notify_list_lock;
190 struct list_head sta_notify_list;
191
192 /* XXX need to convert this to handle multiple interfaces */
193 bool capture_beacon;
194 u8 capture_bssid[ETH_ALEN];
195 struct sk_buff *beacon_skb;
196
197 /*
198 * This FJ worker has to be global as it is scheduled from the
199 * RX handler. At this point we don't know which interface it
200 * belongs to until the list of bssids waiting to complete join
201 * is checked.
202 */
203 struct work_struct finalize_join_worker;
204
205 /* Tasklet to reclaim TX descriptors and buffers after tx */
206 struct tasklet_struct tx_reclaim_task;
207 };
208
209 /* Per interface specific private data */
210 struct mwl8k_vif {
211 /* Local MAC address. */
212 u8 mac_addr[ETH_ALEN];
213
214 /* Index into station database. Returned by UPDATE_STADB. */
215 u8 peer_id;
216
217 /* Non AMPDU sequence number assigned by driver */
218 u16 seqno;
219 };
220
221 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
222
223 static const struct ieee80211_channel mwl8k_channels[] = {
224 { .center_freq = 2412, .hw_value = 1, },
225 { .center_freq = 2417, .hw_value = 2, },
226 { .center_freq = 2422, .hw_value = 3, },
227 { .center_freq = 2427, .hw_value = 4, },
228 { .center_freq = 2432, .hw_value = 5, },
229 { .center_freq = 2437, .hw_value = 6, },
230 { .center_freq = 2442, .hw_value = 7, },
231 { .center_freq = 2447, .hw_value = 8, },
232 { .center_freq = 2452, .hw_value = 9, },
233 { .center_freq = 2457, .hw_value = 10, },
234 { .center_freq = 2462, .hw_value = 11, },
235 { .center_freq = 2467, .hw_value = 12, },
236 { .center_freq = 2472, .hw_value = 13, },
237 { .center_freq = 2484, .hw_value = 14, },
238 };
239
240 static const struct ieee80211_rate mwl8k_rates[] = {
241 { .bitrate = 10, .hw_value = 2, },
242 { .bitrate = 20, .hw_value = 4, },
243 { .bitrate = 55, .hw_value = 11, },
244 { .bitrate = 110, .hw_value = 22, },
245 { .bitrate = 220, .hw_value = 44, },
246 { .bitrate = 60, .hw_value = 12, },
247 { .bitrate = 90, .hw_value = 18, },
248 { .bitrate = 120, .hw_value = 24, },
249 { .bitrate = 180, .hw_value = 36, },
250 { .bitrate = 240, .hw_value = 48, },
251 { .bitrate = 360, .hw_value = 72, },
252 { .bitrate = 480, .hw_value = 96, },
253 { .bitrate = 540, .hw_value = 108, },
254 { .bitrate = 720, .hw_value = 144, },
255 };
256
257 static const u8 mwl8k_rateids[12] = {
258 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
259 };
260
261 /* Set or get info from Firmware */
262 #define MWL8K_CMD_SET 0x0001
263 #define MWL8K_CMD_GET 0x0000
264
265 /* Firmware command codes */
266 #define MWL8K_CMD_CODE_DNLD 0x0001
267 #define MWL8K_CMD_GET_HW_SPEC 0x0003
268 #define MWL8K_CMD_SET_HW_SPEC 0x0004
269 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
270 #define MWL8K_CMD_GET_STAT 0x0014
271 #define MWL8K_CMD_RADIO_CONTROL 0x001c
272 #define MWL8K_CMD_RF_TX_POWER 0x001e
273 #define MWL8K_CMD_RF_ANTENNA 0x0020
274 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
275 #define MWL8K_CMD_SET_POST_SCAN 0x0108
276 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
277 #define MWL8K_CMD_SET_AID 0x010d
278 #define MWL8K_CMD_SET_RATE 0x0110
279 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
280 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
281 #define MWL8K_CMD_SET_SLOT 0x0114
282 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
283 #define MWL8K_CMD_SET_WMM_MODE 0x0123
284 #define MWL8K_CMD_MIMO_CONFIG 0x0125
285 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
286 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
287 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
288 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
289 #define MWL8K_CMD_UPDATE_STADB 0x1123
290
291 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
292 {
293 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
294 snprintf(buf, bufsize, "%s", #x);\
295 return buf;\
296 } while (0)
297 switch (cmd & ~0x8000) {
298 MWL8K_CMDNAME(CODE_DNLD);
299 MWL8K_CMDNAME(GET_HW_SPEC);
300 MWL8K_CMDNAME(SET_HW_SPEC);
301 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
302 MWL8K_CMDNAME(GET_STAT);
303 MWL8K_CMDNAME(RADIO_CONTROL);
304 MWL8K_CMDNAME(RF_TX_POWER);
305 MWL8K_CMDNAME(RF_ANTENNA);
306 MWL8K_CMDNAME(SET_PRE_SCAN);
307 MWL8K_CMDNAME(SET_POST_SCAN);
308 MWL8K_CMDNAME(SET_RF_CHANNEL);
309 MWL8K_CMDNAME(SET_AID);
310 MWL8K_CMDNAME(SET_RATE);
311 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
312 MWL8K_CMDNAME(RTS_THRESHOLD);
313 MWL8K_CMDNAME(SET_SLOT);
314 MWL8K_CMDNAME(SET_EDCA_PARAMS);
315 MWL8K_CMDNAME(SET_WMM_MODE);
316 MWL8K_CMDNAME(MIMO_CONFIG);
317 MWL8K_CMDNAME(USE_FIXED_RATE);
318 MWL8K_CMDNAME(ENABLE_SNIFFER);
319 MWL8K_CMDNAME(SET_MAC_ADDR);
320 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
321 MWL8K_CMDNAME(UPDATE_STADB);
322 default:
323 snprintf(buf, bufsize, "0x%x", cmd);
324 }
325 #undef MWL8K_CMDNAME
326
327 return buf;
328 }
329
330 /* Hardware and firmware reset */
331 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
332 {
333 iowrite32(MWL8K_H2A_INT_RESET,
334 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
335 iowrite32(MWL8K_H2A_INT_RESET,
336 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
337 msleep(20);
338 }
339
340 /* Release fw image */
341 static void mwl8k_release_fw(struct firmware **fw)
342 {
343 if (*fw == NULL)
344 return;
345 release_firmware(*fw);
346 *fw = NULL;
347 }
348
349 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
350 {
351 mwl8k_release_fw(&priv->fw_ucode);
352 mwl8k_release_fw(&priv->fw_helper);
353 }
354
355 /* Request fw image */
356 static int mwl8k_request_fw(struct mwl8k_priv *priv,
357 const char *fname, struct firmware **fw)
358 {
359 /* release current image */
360 if (*fw != NULL)
361 mwl8k_release_fw(fw);
362
363 return request_firmware((const struct firmware **)fw,
364 fname, &priv->pdev->dev);
365 }
366
367 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
368 {
369 struct mwl8k_device_info *di = priv->device_info;
370 int rc;
371
372 if (di->helper_image != NULL) {
373 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
374 if (rc) {
375 printk(KERN_ERR "%s: Error requesting helper "
376 "firmware file %s\n", pci_name(priv->pdev),
377 di->helper_image);
378 return rc;
379 }
380 }
381
382 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
383 if (rc) {
384 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
385 pci_name(priv->pdev), di->fw_image);
386 mwl8k_release_fw(&priv->fw_helper);
387 return rc;
388 }
389
390 return 0;
391 }
392
393 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
394 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
395
396 struct mwl8k_cmd_pkt {
397 __le16 code;
398 __le16 length;
399 __le16 seq_num;
400 __le16 result;
401 char payload[0];
402 } __attribute__((packed));
403
404 /*
405 * Firmware loading.
406 */
407 static int
408 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
409 {
410 void __iomem *regs = priv->regs;
411 dma_addr_t dma_addr;
412 int loops;
413
414 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
415 if (pci_dma_mapping_error(priv->pdev, dma_addr))
416 return -ENOMEM;
417
418 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
419 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
420 iowrite32(MWL8K_H2A_INT_DOORBELL,
421 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
422 iowrite32(MWL8K_H2A_INT_DUMMY,
423 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
424
425 loops = 1000;
426 do {
427 u32 int_code;
428
429 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
430 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
431 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
432 break;
433 }
434
435 cond_resched();
436 udelay(1);
437 } while (--loops);
438
439 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
440
441 return loops ? 0 : -ETIMEDOUT;
442 }
443
444 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
445 const u8 *data, size_t length)
446 {
447 struct mwl8k_cmd_pkt *cmd;
448 int done;
449 int rc = 0;
450
451 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
452 if (cmd == NULL)
453 return -ENOMEM;
454
455 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
456 cmd->seq_num = 0;
457 cmd->result = 0;
458
459 done = 0;
460 while (length) {
461 int block_size = length > 256 ? 256 : length;
462
463 memcpy(cmd->payload, data + done, block_size);
464 cmd->length = cpu_to_le16(block_size);
465
466 rc = mwl8k_send_fw_load_cmd(priv, cmd,
467 sizeof(*cmd) + block_size);
468 if (rc)
469 break;
470
471 done += block_size;
472 length -= block_size;
473 }
474
475 if (!rc) {
476 cmd->length = 0;
477 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
478 }
479
480 kfree(cmd);
481
482 return rc;
483 }
484
485 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
486 const u8 *data, size_t length)
487 {
488 unsigned char *buffer;
489 int may_continue, rc = 0;
490 u32 done, prev_block_size;
491
492 buffer = kmalloc(1024, GFP_KERNEL);
493 if (buffer == NULL)
494 return -ENOMEM;
495
496 done = 0;
497 prev_block_size = 0;
498 may_continue = 1000;
499 while (may_continue > 0) {
500 u32 block_size;
501
502 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
503 if (block_size & 1) {
504 block_size &= ~1;
505 may_continue--;
506 } else {
507 done += prev_block_size;
508 length -= prev_block_size;
509 }
510
511 if (block_size > 1024 || block_size > length) {
512 rc = -EOVERFLOW;
513 break;
514 }
515
516 if (length == 0) {
517 rc = 0;
518 break;
519 }
520
521 if (block_size == 0) {
522 rc = -EPROTO;
523 may_continue--;
524 udelay(1);
525 continue;
526 }
527
528 prev_block_size = block_size;
529 memcpy(buffer, data + done, block_size);
530
531 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
532 if (rc)
533 break;
534 }
535
536 if (!rc && length != 0)
537 rc = -EREMOTEIO;
538
539 kfree(buffer);
540
541 return rc;
542 }
543
544 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
545 {
546 struct mwl8k_priv *priv = hw->priv;
547 struct firmware *fw = priv->fw_ucode;
548 int rc;
549 int loops;
550
551 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
552 struct firmware *helper = priv->fw_helper;
553
554 if (helper == NULL) {
555 printk(KERN_ERR "%s: helper image needed but none "
556 "given\n", pci_name(priv->pdev));
557 return -EINVAL;
558 }
559
560 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
561 if (rc) {
562 printk(KERN_ERR "%s: unable to load firmware "
563 "helper image\n", pci_name(priv->pdev));
564 return rc;
565 }
566 msleep(5);
567
568 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
569 } else {
570 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
571 }
572
573 if (rc) {
574 printk(KERN_ERR "%s: unable to load firmware image\n",
575 pci_name(priv->pdev));
576 return rc;
577 }
578
579 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
580
581 loops = 500000;
582 do {
583 u32 ready_code;
584
585 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
586 if (ready_code == MWL8K_FWAP_READY) {
587 priv->ap_fw = 1;
588 break;
589 } else if (ready_code == MWL8K_FWSTA_READY) {
590 priv->ap_fw = 0;
591 break;
592 }
593
594 cond_resched();
595 udelay(1);
596 } while (--loops);
597
598 return loops ? 0 : -ETIMEDOUT;
599 }
600
601
602 /* DMA header used by firmware and hardware. */
603 struct mwl8k_dma_data {
604 __le16 fwlen;
605 struct ieee80211_hdr wh;
606 char data[0];
607 } __attribute__((packed));
608
609 /* Routines to add/remove DMA header from skb. */
610 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
611 {
612 struct mwl8k_dma_data *tr;
613 int hdrlen;
614
615 tr = (struct mwl8k_dma_data *)skb->data;
616 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
617
618 if (hdrlen != sizeof(tr->wh)) {
619 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
620 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
621 *((__le16 *)(tr->data - 2)) = qos;
622 } else {
623 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
624 }
625 }
626
627 if (hdrlen != sizeof(*tr))
628 skb_pull(skb, sizeof(*tr) - hdrlen);
629 }
630
631 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
632 {
633 struct ieee80211_hdr *wh;
634 int hdrlen;
635 struct mwl8k_dma_data *tr;
636
637 /*
638 * Add a firmware DMA header; the firmware requires that we
639 * present a 2-byte payload length followed by a 4-address
640 * header (without QoS field), followed (optionally) by any
641 * WEP/ExtIV header (but only filled in for CCMP).
642 */
643 wh = (struct ieee80211_hdr *)skb->data;
644
645 hdrlen = ieee80211_hdrlen(wh->frame_control);
646 if (hdrlen != sizeof(*tr))
647 skb_push(skb, sizeof(*tr) - hdrlen);
648
649 if (ieee80211_is_data_qos(wh->frame_control))
650 hdrlen -= 2;
651
652 tr = (struct mwl8k_dma_data *)skb->data;
653 if (wh != &tr->wh)
654 memmove(&tr->wh, wh, hdrlen);
655 if (hdrlen != sizeof(tr->wh))
656 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
657
658 /*
659 * Firmware length is the length of the fully formed "802.11
660 * payload". That is, everything except for the 802.11 header.
661 * This includes all crypto material including the MIC.
662 */
663 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
664 }
665
666
667 /*
668 * Packet reception for 88w8366 AP firmware.
669 */
670 struct mwl8k_rxd_8366_ap {
671 __le16 pkt_len;
672 __u8 sq2;
673 __u8 rate;
674 __le32 pkt_phys_addr;
675 __le32 next_rxd_phys_addr;
676 __le16 qos_control;
677 __le16 htsig2;
678 __le32 hw_rssi_info;
679 __le32 hw_noise_floor_info;
680 __u8 noise_floor;
681 __u8 pad0[3];
682 __u8 rssi;
683 __u8 rx_status;
684 __u8 channel;
685 __u8 rx_ctrl;
686 } __attribute__((packed));
687
688 #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
689 #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
690 #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
691
692 #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
693
694 static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
695 {
696 struct mwl8k_rxd_8366_ap *rxd = _rxd;
697
698 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
699 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
700 }
701
702 static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
703 {
704 struct mwl8k_rxd_8366_ap *rxd = _rxd;
705
706 rxd->pkt_len = cpu_to_le16(len);
707 rxd->pkt_phys_addr = cpu_to_le32(addr);
708 wmb();
709 rxd->rx_ctrl = 0;
710 }
711
712 static int
713 mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
714 __le16 *qos)
715 {
716 struct mwl8k_rxd_8366_ap *rxd = _rxd;
717
718 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
719 return -1;
720 rmb();
721
722 memset(status, 0, sizeof(*status));
723
724 status->signal = -rxd->rssi;
725 status->noise = -rxd->noise_floor;
726
727 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
728 status->flag |= RX_FLAG_HT;
729 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
730 status->flag |= RX_FLAG_40MHZ;
731 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
732 } else {
733 int i;
734
735 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
736 if (mwl8k_rates[i].hw_value == rxd->rate) {
737 status->rate_idx = i;
738 break;
739 }
740 }
741 }
742
743 status->band = IEEE80211_BAND_2GHZ;
744 status->freq = ieee80211_channel_to_frequency(rxd->channel);
745
746 *qos = rxd->qos_control;
747
748 return le16_to_cpu(rxd->pkt_len);
749 }
750
751 static struct rxd_ops rxd_8366_ap_ops = {
752 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
753 .rxd_init = mwl8k_rxd_8366_ap_init,
754 .rxd_refill = mwl8k_rxd_8366_ap_refill,
755 .rxd_process = mwl8k_rxd_8366_ap_process,
756 };
757
758 /*
759 * Packet reception for STA firmware.
760 */
761 struct mwl8k_rxd_sta {
762 __le16 pkt_len;
763 __u8 link_quality;
764 __u8 noise_level;
765 __le32 pkt_phys_addr;
766 __le32 next_rxd_phys_addr;
767 __le16 qos_control;
768 __le16 rate_info;
769 __le32 pad0[4];
770 __u8 rssi;
771 __u8 channel;
772 __le16 pad1;
773 __u8 rx_ctrl;
774 __u8 rx_status;
775 __u8 pad2[2];
776 } __attribute__((packed));
777
778 #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
779 #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
780 #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
781 #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
782 #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
783 #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
784
785 #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
786
787 static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
788 {
789 struct mwl8k_rxd_sta *rxd = _rxd;
790
791 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
792 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
793 }
794
795 static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
796 {
797 struct mwl8k_rxd_sta *rxd = _rxd;
798
799 rxd->pkt_len = cpu_to_le16(len);
800 rxd->pkt_phys_addr = cpu_to_le32(addr);
801 wmb();
802 rxd->rx_ctrl = 0;
803 }
804
805 static int
806 mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
807 __le16 *qos)
808 {
809 struct mwl8k_rxd_sta *rxd = _rxd;
810 u16 rate_info;
811
812 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
813 return -1;
814 rmb();
815
816 rate_info = le16_to_cpu(rxd->rate_info);
817
818 memset(status, 0, sizeof(*status));
819
820 status->signal = -rxd->rssi;
821 status->noise = -rxd->noise_level;
822 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
823 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
824
825 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
826 status->flag |= RX_FLAG_SHORTPRE;
827 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
828 status->flag |= RX_FLAG_40MHZ;
829 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
830 status->flag |= RX_FLAG_SHORT_GI;
831 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
832 status->flag |= RX_FLAG_HT;
833
834 status->band = IEEE80211_BAND_2GHZ;
835 status->freq = ieee80211_channel_to_frequency(rxd->channel);
836
837 *qos = rxd->qos_control;
838
839 return le16_to_cpu(rxd->pkt_len);
840 }
841
842 static struct rxd_ops rxd_sta_ops = {
843 .rxd_size = sizeof(struct mwl8k_rxd_sta),
844 .rxd_init = mwl8k_rxd_sta_init,
845 .rxd_refill = mwl8k_rxd_sta_refill,
846 .rxd_process = mwl8k_rxd_sta_process,
847 };
848
849
850 #define MWL8K_RX_DESCS 256
851 #define MWL8K_RX_MAXSZ 3800
852
853 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
854 {
855 struct mwl8k_priv *priv = hw->priv;
856 struct mwl8k_rx_queue *rxq = priv->rxq + index;
857 int size;
858 int i;
859
860 rxq->rxd_count = 0;
861 rxq->head = 0;
862 rxq->tail = 0;
863
864 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
865
866 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
867 if (rxq->rxd == NULL) {
868 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
869 wiphy_name(hw->wiphy));
870 return -ENOMEM;
871 }
872 memset(rxq->rxd, 0, size);
873
874 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
875 if (rxq->buf == NULL) {
876 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
877 wiphy_name(hw->wiphy));
878 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
879 return -ENOMEM;
880 }
881 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
882
883 for (i = 0; i < MWL8K_RX_DESCS; i++) {
884 int desc_size;
885 void *rxd;
886 int nexti;
887 dma_addr_t next_dma_addr;
888
889 desc_size = priv->rxd_ops->rxd_size;
890 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
891
892 nexti = i + 1;
893 if (nexti == MWL8K_RX_DESCS)
894 nexti = 0;
895 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
896
897 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
898 }
899
900 return 0;
901 }
902
903 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
904 {
905 struct mwl8k_priv *priv = hw->priv;
906 struct mwl8k_rx_queue *rxq = priv->rxq + index;
907 int refilled;
908
909 refilled = 0;
910 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
911 struct sk_buff *skb;
912 dma_addr_t addr;
913 int rx;
914 void *rxd;
915
916 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
917 if (skb == NULL)
918 break;
919
920 addr = pci_map_single(priv->pdev, skb->data,
921 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
922
923 rxq->rxd_count++;
924 rx = rxq->tail++;
925 if (rxq->tail == MWL8K_RX_DESCS)
926 rxq->tail = 0;
927 rxq->buf[rx].skb = skb;
928 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
929
930 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
931 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
932
933 refilled++;
934 }
935
936 return refilled;
937 }
938
939 /* Must be called only when the card's reception is completely halted */
940 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
941 {
942 struct mwl8k_priv *priv = hw->priv;
943 struct mwl8k_rx_queue *rxq = priv->rxq + index;
944 int i;
945
946 for (i = 0; i < MWL8K_RX_DESCS; i++) {
947 if (rxq->buf[i].skb != NULL) {
948 pci_unmap_single(priv->pdev,
949 pci_unmap_addr(&rxq->buf[i], dma),
950 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
951 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
952
953 kfree_skb(rxq->buf[i].skb);
954 rxq->buf[i].skb = NULL;
955 }
956 }
957
958 kfree(rxq->buf);
959 rxq->buf = NULL;
960
961 pci_free_consistent(priv->pdev,
962 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
963 rxq->rxd, rxq->rxd_dma);
964 rxq->rxd = NULL;
965 }
966
967
968 /*
969 * Scan a list of BSSIDs to process for finalize join.
970 * Allows for extension to process multiple BSSIDs.
971 */
972 static inline int
973 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
974 {
975 return priv->capture_beacon &&
976 ieee80211_is_beacon(wh->frame_control) &&
977 !compare_ether_addr(wh->addr3, priv->capture_bssid);
978 }
979
980 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
981 struct sk_buff *skb)
982 {
983 struct mwl8k_priv *priv = hw->priv;
984
985 priv->capture_beacon = false;
986 memset(priv->capture_bssid, 0, ETH_ALEN);
987
988 /*
989 * Use GFP_ATOMIC as rxq_process is called from
990 * the primary interrupt handler, memory allocation call
991 * must not sleep.
992 */
993 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
994 if (priv->beacon_skb != NULL)
995 ieee80211_queue_work(hw, &priv->finalize_join_worker);
996 }
997
998 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
999 {
1000 struct mwl8k_priv *priv = hw->priv;
1001 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1002 int processed;
1003
1004 processed = 0;
1005 while (rxq->rxd_count && limit--) {
1006 struct sk_buff *skb;
1007 void *rxd;
1008 int pkt_len;
1009 struct ieee80211_rx_status status;
1010 __le16 qos;
1011
1012 skb = rxq->buf[rxq->head].skb;
1013 if (skb == NULL)
1014 break;
1015
1016 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1017
1018 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1019 if (pkt_len < 0)
1020 break;
1021
1022 rxq->buf[rxq->head].skb = NULL;
1023
1024 pci_unmap_single(priv->pdev,
1025 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1026 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1027 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1028
1029 rxq->head++;
1030 if (rxq->head == MWL8K_RX_DESCS)
1031 rxq->head = 0;
1032
1033 rxq->rxd_count--;
1034
1035 skb_put(skb, pkt_len);
1036 mwl8k_remove_dma_header(skb, qos);
1037
1038 /*
1039 * Check for a pending join operation. Save a
1040 * copy of the beacon and schedule a tasklet to
1041 * send a FINALIZE_JOIN command to the firmware.
1042 */
1043 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1044 mwl8k_save_beacon(hw, skb);
1045
1046 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1047 ieee80211_rx_irqsafe(hw, skb);
1048
1049 processed++;
1050 }
1051
1052 return processed;
1053 }
1054
1055
1056 /*
1057 * Packet transmission.
1058 */
1059
1060 #define MWL8K_TXD_STATUS_OK 0x00000001
1061 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1062 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1063 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1064 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1065
1066 #define MWL8K_QOS_QLEN_UNSPEC 0xff00
1067 #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1068 #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1069 #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1070 #define MWL8K_QOS_EOSP 0x0010
1071
1072 struct mwl8k_tx_desc {
1073 __le32 status;
1074 __u8 data_rate;
1075 __u8 tx_priority;
1076 __le16 qos_control;
1077 __le32 pkt_phys_addr;
1078 __le16 pkt_len;
1079 __u8 dest_MAC_addr[ETH_ALEN];
1080 __le32 next_txd_phys_addr;
1081 __le32 reserved;
1082 __le16 rate_info;
1083 __u8 peer_id;
1084 __u8 tx_frag_cnt;
1085 } __attribute__((packed));
1086
1087 #define MWL8K_TX_DESCS 128
1088
1089 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1090 {
1091 struct mwl8k_priv *priv = hw->priv;
1092 struct mwl8k_tx_queue *txq = priv->txq + index;
1093 int size;
1094 int i;
1095
1096 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1097 txq->stats.limit = MWL8K_TX_DESCS;
1098 txq->head = 0;
1099 txq->tail = 0;
1100
1101 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1102
1103 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1104 if (txq->txd == NULL) {
1105 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1106 wiphy_name(hw->wiphy));
1107 return -ENOMEM;
1108 }
1109 memset(txq->txd, 0, size);
1110
1111 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1112 if (txq->skb == NULL) {
1113 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1114 wiphy_name(hw->wiphy));
1115 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1116 return -ENOMEM;
1117 }
1118 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1119
1120 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1121 struct mwl8k_tx_desc *tx_desc;
1122 int nexti;
1123
1124 tx_desc = txq->txd + i;
1125 nexti = (i + 1) % MWL8K_TX_DESCS;
1126
1127 tx_desc->status = 0;
1128 tx_desc->next_txd_phys_addr =
1129 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1130 }
1131
1132 return 0;
1133 }
1134
1135 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1136 {
1137 iowrite32(MWL8K_H2A_INT_PPA_READY,
1138 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1139 iowrite32(MWL8K_H2A_INT_DUMMY,
1140 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1141 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1142 }
1143
1144 static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
1145 {
1146 struct mwl8k_priv *priv = hw->priv;
1147 int i;
1148
1149 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1150 struct mwl8k_tx_queue *txq = priv->txq + i;
1151 int fw_owned = 0;
1152 int drv_owned = 0;
1153 int unused = 0;
1154 int desc;
1155
1156 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1157 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1158 u32 status;
1159
1160 status = le32_to_cpu(tx_desc->status);
1161 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1162 fw_owned++;
1163 else
1164 drv_owned++;
1165
1166 if (tx_desc->pkt_len == 0)
1167 unused++;
1168 }
1169
1170 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1171 "fw_owned=%d drv_owned=%d unused=%d\n",
1172 wiphy_name(hw->wiphy), i,
1173 txq->stats.len, txq->head, txq->tail,
1174 fw_owned, drv_owned, unused);
1175 }
1176 }
1177
1178 /*
1179 * Must be called with priv->fw_mutex held and tx queues stopped.
1180 */
1181 #define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1182
1183 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1184 {
1185 struct mwl8k_priv *priv = hw->priv;
1186 DECLARE_COMPLETION_ONSTACK(tx_wait);
1187 int retry;
1188 int rc;
1189
1190 might_sleep();
1191
1192 /*
1193 * The TX queues are stopped at this point, so this test
1194 * doesn't need to take ->tx_lock.
1195 */
1196 if (!priv->pending_tx_pkts)
1197 return 0;
1198
1199 retry = 0;
1200 rc = 0;
1201
1202 spin_lock_bh(&priv->tx_lock);
1203 priv->tx_wait = &tx_wait;
1204 while (!rc) {
1205 int oldcount;
1206 unsigned long timeout;
1207
1208 oldcount = priv->pending_tx_pkts;
1209
1210 spin_unlock_bh(&priv->tx_lock);
1211 timeout = wait_for_completion_timeout(&tx_wait,
1212 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
1213 spin_lock_bh(&priv->tx_lock);
1214
1215 if (timeout) {
1216 WARN_ON(priv->pending_tx_pkts);
1217 if (retry) {
1218 printk(KERN_NOTICE "%s: tx rings drained\n",
1219 wiphy_name(hw->wiphy));
1220 }
1221 break;
1222 }
1223
1224 if (priv->pending_tx_pkts < oldcount) {
1225 printk(KERN_NOTICE "%s: waiting for tx rings "
1226 "to drain (%d -> %d pkts)\n",
1227 wiphy_name(hw->wiphy), oldcount,
1228 priv->pending_tx_pkts);
1229 retry = 1;
1230 continue;
1231 }
1232
1233 priv->tx_wait = NULL;
1234
1235 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1236 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1237 mwl8k_dump_tx_rings(hw);
1238
1239 rc = -ETIMEDOUT;
1240 }
1241 spin_unlock_bh(&priv->tx_lock);
1242
1243 return rc;
1244 }
1245
1246 #define MWL8K_TXD_SUCCESS(status) \
1247 ((status) & (MWL8K_TXD_STATUS_OK | \
1248 MWL8K_TXD_STATUS_OK_RETRY | \
1249 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1250
1251 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1252 {
1253 struct mwl8k_priv *priv = hw->priv;
1254 struct mwl8k_tx_queue *txq = priv->txq + index;
1255 int wake = 0;
1256
1257 while (txq->stats.len > 0) {
1258 int tx;
1259 struct mwl8k_tx_desc *tx_desc;
1260 unsigned long addr;
1261 int size;
1262 struct sk_buff *skb;
1263 struct ieee80211_tx_info *info;
1264 u32 status;
1265
1266 tx = txq->head;
1267 tx_desc = txq->txd + tx;
1268
1269 status = le32_to_cpu(tx_desc->status);
1270
1271 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1272 if (!force)
1273 break;
1274 tx_desc->status &=
1275 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1276 }
1277
1278 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1279 BUG_ON(txq->stats.len == 0);
1280 txq->stats.len--;
1281 priv->pending_tx_pkts--;
1282
1283 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1284 size = le16_to_cpu(tx_desc->pkt_len);
1285 skb = txq->skb[tx];
1286 txq->skb[tx] = NULL;
1287
1288 BUG_ON(skb == NULL);
1289 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1290
1291 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1292
1293 /* Mark descriptor as unused */
1294 tx_desc->pkt_phys_addr = 0;
1295 tx_desc->pkt_len = 0;
1296
1297 info = IEEE80211_SKB_CB(skb);
1298 ieee80211_tx_info_clear_status(info);
1299 if (MWL8K_TXD_SUCCESS(status))
1300 info->flags |= IEEE80211_TX_STAT_ACK;
1301
1302 ieee80211_tx_status_irqsafe(hw, skb);
1303
1304 wake = 1;
1305 }
1306
1307 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1308 ieee80211_wake_queue(hw, index);
1309 }
1310
1311 /* must be called only when the card's transmit is completely halted */
1312 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1313 {
1314 struct mwl8k_priv *priv = hw->priv;
1315 struct mwl8k_tx_queue *txq = priv->txq + index;
1316
1317 mwl8k_txq_reclaim(hw, index, 1);
1318
1319 kfree(txq->skb);
1320 txq->skb = NULL;
1321
1322 pci_free_consistent(priv->pdev,
1323 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1324 txq->txd, txq->txd_dma);
1325 txq->txd = NULL;
1326 }
1327
1328 static int
1329 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1330 {
1331 struct mwl8k_priv *priv = hw->priv;
1332 struct ieee80211_tx_info *tx_info;
1333 struct mwl8k_vif *mwl8k_vif;
1334 struct ieee80211_hdr *wh;
1335 struct mwl8k_tx_queue *txq;
1336 struct mwl8k_tx_desc *tx;
1337 dma_addr_t dma;
1338 u32 txstatus;
1339 u8 txdatarate;
1340 u16 qos;
1341
1342 wh = (struct ieee80211_hdr *)skb->data;
1343 if (ieee80211_is_data_qos(wh->frame_control))
1344 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1345 else
1346 qos = 0;
1347
1348 mwl8k_add_dma_header(skb);
1349 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1350
1351 tx_info = IEEE80211_SKB_CB(skb);
1352 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1353
1354 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1355 u16 seqno = mwl8k_vif->seqno;
1356
1357 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1358 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1359 mwl8k_vif->seqno = seqno++ % 4096;
1360 }
1361
1362 /* Setup firmware control bit fields for each frame type. */
1363 txstatus = 0;
1364 txdatarate = 0;
1365 if (ieee80211_is_mgmt(wh->frame_control) ||
1366 ieee80211_is_ctl(wh->frame_control)) {
1367 txdatarate = 0;
1368 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
1369 } else if (ieee80211_is_data(wh->frame_control)) {
1370 txdatarate = 1;
1371 if (is_multicast_ether_addr(wh->addr1))
1372 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1373
1374 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
1375 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1376 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
1377 else
1378 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
1379 }
1380
1381 dma = pci_map_single(priv->pdev, skb->data,
1382 skb->len, PCI_DMA_TODEVICE);
1383
1384 if (pci_dma_mapping_error(priv->pdev, dma)) {
1385 printk(KERN_DEBUG "%s: failed to dma map skb, "
1386 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1387 dev_kfree_skb(skb);
1388 return NETDEV_TX_OK;
1389 }
1390
1391 spin_lock_bh(&priv->tx_lock);
1392
1393 txq = priv->txq + index;
1394
1395 BUG_ON(txq->skb[txq->tail] != NULL);
1396 txq->skb[txq->tail] = skb;
1397
1398 tx = txq->txd + txq->tail;
1399 tx->data_rate = txdatarate;
1400 tx->tx_priority = index;
1401 tx->qos_control = cpu_to_le16(qos);
1402 tx->pkt_phys_addr = cpu_to_le32(dma);
1403 tx->pkt_len = cpu_to_le16(skb->len);
1404 tx->rate_info = 0;
1405 tx->peer_id = mwl8k_vif->peer_id;
1406 wmb();
1407 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1408
1409 txq->stats.count++;
1410 txq->stats.len++;
1411 priv->pending_tx_pkts++;
1412
1413 txq->tail++;
1414 if (txq->tail == MWL8K_TX_DESCS)
1415 txq->tail = 0;
1416
1417 if (txq->head == txq->tail)
1418 ieee80211_stop_queue(hw, index);
1419
1420 mwl8k_tx_start(priv);
1421
1422 spin_unlock_bh(&priv->tx_lock);
1423
1424 return NETDEV_TX_OK;
1425 }
1426
1427
1428 /*
1429 * Firmware access.
1430 *
1431 * We have the following requirements for issuing firmware commands:
1432 * - Some commands require that the packet transmit path is idle when
1433 * the command is issued. (For simplicity, we'll just quiesce the
1434 * transmit path for every command.)
1435 * - There are certain sequences of commands that need to be issued to
1436 * the hardware sequentially, with no other intervening commands.
1437 *
1438 * This leads to an implementation of a "firmware lock" as a mutex that
1439 * can be taken recursively, and which is taken by both the low-level
1440 * command submission function (mwl8k_post_cmd) as well as any users of
1441 * that function that require issuing of an atomic sequence of commands,
1442 * and quiesces the transmit path whenever it's taken.
1443 */
1444 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1445 {
1446 struct mwl8k_priv *priv = hw->priv;
1447
1448 if (priv->fw_mutex_owner != current) {
1449 int rc;
1450
1451 mutex_lock(&priv->fw_mutex);
1452 ieee80211_stop_queues(hw);
1453
1454 rc = mwl8k_tx_wait_empty(hw);
1455 if (rc) {
1456 ieee80211_wake_queues(hw);
1457 mutex_unlock(&priv->fw_mutex);
1458
1459 return rc;
1460 }
1461
1462 priv->fw_mutex_owner = current;
1463 }
1464
1465 priv->fw_mutex_depth++;
1466
1467 return 0;
1468 }
1469
1470 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1471 {
1472 struct mwl8k_priv *priv = hw->priv;
1473
1474 if (!--priv->fw_mutex_depth) {
1475 ieee80211_wake_queues(hw);
1476 priv->fw_mutex_owner = NULL;
1477 mutex_unlock(&priv->fw_mutex);
1478 }
1479 }
1480
1481
1482 /*
1483 * Command processing.
1484 */
1485
1486 /* Timeout firmware commands after 10s */
1487 #define MWL8K_CMD_TIMEOUT_MS 10000
1488
1489 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1490 {
1491 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1492 struct mwl8k_priv *priv = hw->priv;
1493 void __iomem *regs = priv->regs;
1494 dma_addr_t dma_addr;
1495 unsigned int dma_size;
1496 int rc;
1497 unsigned long timeout = 0;
1498 u8 buf[32];
1499
1500 cmd->result = 0xffff;
1501 dma_size = le16_to_cpu(cmd->length);
1502 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1503 PCI_DMA_BIDIRECTIONAL);
1504 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1505 return -ENOMEM;
1506
1507 rc = mwl8k_fw_lock(hw);
1508 if (rc) {
1509 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1510 PCI_DMA_BIDIRECTIONAL);
1511 return rc;
1512 }
1513
1514 priv->hostcmd_wait = &cmd_wait;
1515 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1516 iowrite32(MWL8K_H2A_INT_DOORBELL,
1517 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1518 iowrite32(MWL8K_H2A_INT_DUMMY,
1519 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1520
1521 timeout = wait_for_completion_timeout(&cmd_wait,
1522 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1523
1524 priv->hostcmd_wait = NULL;
1525
1526 mwl8k_fw_unlock(hw);
1527
1528 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1529 PCI_DMA_BIDIRECTIONAL);
1530
1531 if (!timeout) {
1532 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1533 wiphy_name(hw->wiphy),
1534 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1535 MWL8K_CMD_TIMEOUT_MS);
1536 rc = -ETIMEDOUT;
1537 } else {
1538 int ms;
1539
1540 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1541
1542 rc = cmd->result ? -EINVAL : 0;
1543 if (rc)
1544 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1545 wiphy_name(hw->wiphy),
1546 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1547 le16_to_cpu(cmd->result));
1548 else if (ms > 2000)
1549 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1550 wiphy_name(hw->wiphy),
1551 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1552 ms);
1553 }
1554
1555 return rc;
1556 }
1557
1558 /*
1559 * CMD_GET_HW_SPEC (STA version).
1560 */
1561 struct mwl8k_cmd_get_hw_spec_sta {
1562 struct mwl8k_cmd_pkt header;
1563 __u8 hw_rev;
1564 __u8 host_interface;
1565 __le16 num_mcaddrs;
1566 __u8 perm_addr[ETH_ALEN];
1567 __le16 region_code;
1568 __le32 fw_rev;
1569 __le32 ps_cookie;
1570 __le32 caps;
1571 __u8 mcs_bitmap[16];
1572 __le32 rx_queue_ptr;
1573 __le32 num_tx_queues;
1574 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1575 __le32 caps2;
1576 __le32 num_tx_desc_per_queue;
1577 __le32 total_rxd;
1578 } __attribute__((packed));
1579
1580 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1581 {
1582 struct mwl8k_priv *priv = hw->priv;
1583 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1584 int rc;
1585 int i;
1586
1587 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1588 if (cmd == NULL)
1589 return -ENOMEM;
1590
1591 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1592 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1593
1594 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1595 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1596 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1597 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1598 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1599 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1600 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1601 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1602
1603 rc = mwl8k_post_cmd(hw, &cmd->header);
1604
1605 if (!rc) {
1606 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1607 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1608 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1609 priv->hw_rev = cmd->hw_rev;
1610 }
1611
1612 kfree(cmd);
1613 return rc;
1614 }
1615
1616 /*
1617 * CMD_GET_HW_SPEC (AP version).
1618 */
1619 struct mwl8k_cmd_get_hw_spec_ap {
1620 struct mwl8k_cmd_pkt header;
1621 __u8 hw_rev;
1622 __u8 host_interface;
1623 __le16 num_wcb;
1624 __le16 num_mcaddrs;
1625 __u8 perm_addr[ETH_ALEN];
1626 __le16 region_code;
1627 __le16 num_antenna;
1628 __le32 fw_rev;
1629 __le32 wcbbase0;
1630 __le32 rxwrptr;
1631 __le32 rxrdptr;
1632 __le32 ps_cookie;
1633 __le32 wcbbase1;
1634 __le32 wcbbase2;
1635 __le32 wcbbase3;
1636 } __attribute__((packed));
1637
1638 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1639 {
1640 struct mwl8k_priv *priv = hw->priv;
1641 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1642 int rc;
1643
1644 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1645 if (cmd == NULL)
1646 return -ENOMEM;
1647
1648 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1649 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1650
1651 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1652 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1653
1654 rc = mwl8k_post_cmd(hw, &cmd->header);
1655
1656 if (!rc) {
1657 int off;
1658
1659 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1660 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1661 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1662 priv->hw_rev = cmd->hw_rev;
1663
1664 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1665 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1666
1667 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1668 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1669
1670 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1671 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1672
1673 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1674 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1675
1676 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1677 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1678
1679 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1680 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1681 }
1682
1683 kfree(cmd);
1684 return rc;
1685 }
1686
1687 /*
1688 * CMD_SET_HW_SPEC.
1689 */
1690 struct mwl8k_cmd_set_hw_spec {
1691 struct mwl8k_cmd_pkt header;
1692 __u8 hw_rev;
1693 __u8 host_interface;
1694 __le16 num_mcaddrs;
1695 __u8 perm_addr[ETH_ALEN];
1696 __le16 region_code;
1697 __le32 fw_rev;
1698 __le32 ps_cookie;
1699 __le32 caps;
1700 __le32 rx_queue_ptr;
1701 __le32 num_tx_queues;
1702 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1703 __le32 flags;
1704 __le32 num_tx_desc_per_queue;
1705 __le32 total_rxd;
1706 } __attribute__((packed));
1707
1708 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1709
1710 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1711 {
1712 struct mwl8k_priv *priv = hw->priv;
1713 struct mwl8k_cmd_set_hw_spec *cmd;
1714 int rc;
1715 int i;
1716
1717 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1718 if (cmd == NULL)
1719 return -ENOMEM;
1720
1721 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1722 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1723
1724 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1725 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1726 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1727 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1728 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1729 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1730 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1731 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1732
1733 rc = mwl8k_post_cmd(hw, &cmd->header);
1734 kfree(cmd);
1735
1736 return rc;
1737 }
1738
1739 /*
1740 * CMD_MAC_MULTICAST_ADR.
1741 */
1742 struct mwl8k_cmd_mac_multicast_adr {
1743 struct mwl8k_cmd_pkt header;
1744 __le16 action;
1745 __le16 numaddr;
1746 __u8 addr[0][ETH_ALEN];
1747 };
1748
1749 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1750 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1751 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1752 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1753
1754 static struct mwl8k_cmd_pkt *
1755 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1756 int mc_count, struct dev_addr_list *mclist)
1757 {
1758 struct mwl8k_priv *priv = hw->priv;
1759 struct mwl8k_cmd_mac_multicast_adr *cmd;
1760 int size;
1761
1762 if (allmulti || mc_count > priv->num_mcaddrs) {
1763 allmulti = 1;
1764 mc_count = 0;
1765 }
1766
1767 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1768
1769 cmd = kzalloc(size, GFP_ATOMIC);
1770 if (cmd == NULL)
1771 return NULL;
1772
1773 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1774 cmd->header.length = cpu_to_le16(size);
1775 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1776 MWL8K_ENABLE_RX_BROADCAST);
1777
1778 if (allmulti) {
1779 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1780 } else if (mc_count) {
1781 int i;
1782
1783 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1784 cmd->numaddr = cpu_to_le16(mc_count);
1785 for (i = 0; i < mc_count && mclist; i++) {
1786 if (mclist->da_addrlen != ETH_ALEN) {
1787 kfree(cmd);
1788 return NULL;
1789 }
1790 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1791 mclist = mclist->next;
1792 }
1793 }
1794
1795 return &cmd->header;
1796 }
1797
1798 /*
1799 * CMD_GET_STAT.
1800 */
1801 struct mwl8k_cmd_get_stat {
1802 struct mwl8k_cmd_pkt header;
1803 __le32 stats[64];
1804 } __attribute__((packed));
1805
1806 #define MWL8K_STAT_ACK_FAILURE 9
1807 #define MWL8K_STAT_RTS_FAILURE 12
1808 #define MWL8K_STAT_FCS_ERROR 24
1809 #define MWL8K_STAT_RTS_SUCCESS 11
1810
1811 static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1812 struct ieee80211_low_level_stats *stats)
1813 {
1814 struct mwl8k_cmd_get_stat *cmd;
1815 int rc;
1816
1817 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1818 if (cmd == NULL)
1819 return -ENOMEM;
1820
1821 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1822 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1823
1824 rc = mwl8k_post_cmd(hw, &cmd->header);
1825 if (!rc) {
1826 stats->dot11ACKFailureCount =
1827 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1828 stats->dot11RTSFailureCount =
1829 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1830 stats->dot11FCSErrorCount =
1831 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1832 stats->dot11RTSSuccessCount =
1833 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1834 }
1835 kfree(cmd);
1836
1837 return rc;
1838 }
1839
1840 /*
1841 * CMD_RADIO_CONTROL.
1842 */
1843 struct mwl8k_cmd_radio_control {
1844 struct mwl8k_cmd_pkt header;
1845 __le16 action;
1846 __le16 control;
1847 __le16 radio_on;
1848 } __attribute__((packed));
1849
1850 static int
1851 mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1852 {
1853 struct mwl8k_priv *priv = hw->priv;
1854 struct mwl8k_cmd_radio_control *cmd;
1855 int rc;
1856
1857 if (enable == priv->radio_on && !force)
1858 return 0;
1859
1860 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1861 if (cmd == NULL)
1862 return -ENOMEM;
1863
1864 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1865 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1866 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1867 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1868 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1869
1870 rc = mwl8k_post_cmd(hw, &cmd->header);
1871 kfree(cmd);
1872
1873 if (!rc)
1874 priv->radio_on = enable;
1875
1876 return rc;
1877 }
1878
1879 static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
1880 {
1881 return mwl8k_cmd_radio_control(hw, 0, 0);
1882 }
1883
1884 static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
1885 {
1886 return mwl8k_cmd_radio_control(hw, 1, 0);
1887 }
1888
1889 static int
1890 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1891 {
1892 struct mwl8k_priv *priv = hw->priv;
1893
1894 priv->radio_short_preamble = short_preamble;
1895
1896 return mwl8k_cmd_radio_control(hw, 1, 1);
1897 }
1898
1899 /*
1900 * CMD_RF_TX_POWER.
1901 */
1902 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1903
1904 struct mwl8k_cmd_rf_tx_power {
1905 struct mwl8k_cmd_pkt header;
1906 __le16 action;
1907 __le16 support_level;
1908 __le16 current_level;
1909 __le16 reserved;
1910 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1911 } __attribute__((packed));
1912
1913 static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1914 {
1915 struct mwl8k_cmd_rf_tx_power *cmd;
1916 int rc;
1917
1918 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1919 if (cmd == NULL)
1920 return -ENOMEM;
1921
1922 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1923 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1924 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1925 cmd->support_level = cpu_to_le16(dBm);
1926
1927 rc = mwl8k_post_cmd(hw, &cmd->header);
1928 kfree(cmd);
1929
1930 return rc;
1931 }
1932
1933 /*
1934 * CMD_RF_ANTENNA.
1935 */
1936 struct mwl8k_cmd_rf_antenna {
1937 struct mwl8k_cmd_pkt header;
1938 __le16 antenna;
1939 __le16 mode;
1940 } __attribute__((packed));
1941
1942 #define MWL8K_RF_ANTENNA_RX 1
1943 #define MWL8K_RF_ANTENNA_TX 2
1944
1945 static int
1946 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
1947 {
1948 struct mwl8k_cmd_rf_antenna *cmd;
1949 int rc;
1950
1951 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1952 if (cmd == NULL)
1953 return -ENOMEM;
1954
1955 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
1956 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1957 cmd->antenna = cpu_to_le16(antenna);
1958 cmd->mode = cpu_to_le16(mask);
1959
1960 rc = mwl8k_post_cmd(hw, &cmd->header);
1961 kfree(cmd);
1962
1963 return rc;
1964 }
1965
1966 /*
1967 * CMD_SET_PRE_SCAN.
1968 */
1969 struct mwl8k_cmd_set_pre_scan {
1970 struct mwl8k_cmd_pkt header;
1971 } __attribute__((packed));
1972
1973 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1974 {
1975 struct mwl8k_cmd_set_pre_scan *cmd;
1976 int rc;
1977
1978 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1979 if (cmd == NULL)
1980 return -ENOMEM;
1981
1982 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1983 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1984
1985 rc = mwl8k_post_cmd(hw, &cmd->header);
1986 kfree(cmd);
1987
1988 return rc;
1989 }
1990
1991 /*
1992 * CMD_SET_POST_SCAN.
1993 */
1994 struct mwl8k_cmd_set_post_scan {
1995 struct mwl8k_cmd_pkt header;
1996 __le32 isibss;
1997 __u8 bssid[ETH_ALEN];
1998 } __attribute__((packed));
1999
2000 static int
2001 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
2002 {
2003 struct mwl8k_cmd_set_post_scan *cmd;
2004 int rc;
2005
2006 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2007 if (cmd == NULL)
2008 return -ENOMEM;
2009
2010 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2011 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2012 cmd->isibss = 0;
2013 memcpy(cmd->bssid, mac, ETH_ALEN);
2014
2015 rc = mwl8k_post_cmd(hw, &cmd->header);
2016 kfree(cmd);
2017
2018 return rc;
2019 }
2020
2021 /*
2022 * CMD_SET_RF_CHANNEL.
2023 */
2024 struct mwl8k_cmd_set_rf_channel {
2025 struct mwl8k_cmd_pkt header;
2026 __le16 action;
2027 __u8 current_channel;
2028 __le32 channel_flags;
2029 } __attribute__((packed));
2030
2031 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2032 struct ieee80211_channel *channel)
2033 {
2034 struct mwl8k_cmd_set_rf_channel *cmd;
2035 int rc;
2036
2037 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2038 if (cmd == NULL)
2039 return -ENOMEM;
2040
2041 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2042 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2043 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2044 cmd->current_channel = channel->hw_value;
2045 if (channel->band == IEEE80211_BAND_2GHZ)
2046 cmd->channel_flags = cpu_to_le32(0x00000081);
2047 else
2048 cmd->channel_flags = cpu_to_le32(0x00000000);
2049
2050 rc = mwl8k_post_cmd(hw, &cmd->header);
2051 kfree(cmd);
2052
2053 return rc;
2054 }
2055
2056 /*
2057 * CMD_SET_AID.
2058 */
2059 #define MWL8K_FRAME_PROT_DISABLED 0x00
2060 #define MWL8K_FRAME_PROT_11G 0x07
2061 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2062 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2063
2064 struct mwl8k_cmd_update_set_aid {
2065 struct mwl8k_cmd_pkt header;
2066 __le16 aid;
2067
2068 /* AP's MAC address (BSSID) */
2069 __u8 bssid[ETH_ALEN];
2070 __le16 protection_mode;
2071 __u8 supp_rates[14];
2072 } __attribute__((packed));
2073
2074 static int
2075 mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2076 {
2077 struct mwl8k_cmd_update_set_aid *cmd;
2078 u16 prot_mode;
2079 int rc;
2080
2081 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2082 if (cmd == NULL)
2083 return -ENOMEM;
2084
2085 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2086 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2087 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
2088
2089 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
2090
2091 if (vif->bss_conf.use_cts_prot) {
2092 prot_mode = MWL8K_FRAME_PROT_11G;
2093 } else {
2094 switch (vif->bss_conf.ht_operation_mode &
2095 IEEE80211_HT_OP_MODE_PROTECTION) {
2096 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2097 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2098 break;
2099 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2100 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2101 break;
2102 default:
2103 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2104 break;
2105 }
2106 }
2107 cmd->protection_mode = cpu_to_le16(prot_mode);
2108
2109 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2110
2111 rc = mwl8k_post_cmd(hw, &cmd->header);
2112 kfree(cmd);
2113
2114 return rc;
2115 }
2116
2117 /*
2118 * CMD_SET_RATE.
2119 */
2120 struct mwl8k_cmd_set_rate {
2121 struct mwl8k_cmd_pkt header;
2122 __u8 legacy_rates[14];
2123
2124 /* Bitmap for supported MCS codes. */
2125 __u8 mcs_set[16];
2126 __u8 reserved[16];
2127 } __attribute__((packed));
2128
2129 static int
2130 mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2131 {
2132 struct mwl8k_cmd_set_rate *cmd;
2133 int rc;
2134
2135 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2136 if (cmd == NULL)
2137 return -ENOMEM;
2138
2139 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2140 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2141 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2142
2143 rc = mwl8k_post_cmd(hw, &cmd->header);
2144 kfree(cmd);
2145
2146 return rc;
2147 }
2148
2149 /*
2150 * CMD_FINALIZE_JOIN.
2151 */
2152 #define MWL8K_FJ_BEACON_MAXLEN 128
2153
2154 struct mwl8k_cmd_finalize_join {
2155 struct mwl8k_cmd_pkt header;
2156 __le32 sleep_interval; /* Number of beacon periods to sleep */
2157 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2158 } __attribute__((packed));
2159
2160 static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2161 int framelen, int dtim)
2162 {
2163 struct mwl8k_cmd_finalize_join *cmd;
2164 struct ieee80211_mgmt *payload = frame;
2165 int payload_len;
2166 int rc;
2167
2168 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2169 if (cmd == NULL)
2170 return -ENOMEM;
2171
2172 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2173 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2174 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2175
2176 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2177 if (payload_len < 0)
2178 payload_len = 0;
2179 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2180 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2181
2182 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2183
2184 rc = mwl8k_post_cmd(hw, &cmd->header);
2185 kfree(cmd);
2186
2187 return rc;
2188 }
2189
2190 /*
2191 * CMD_SET_RTS_THRESHOLD.
2192 */
2193 struct mwl8k_cmd_set_rts_threshold {
2194 struct mwl8k_cmd_pkt header;
2195 __le16 action;
2196 __le16 threshold;
2197 } __attribute__((packed));
2198
2199 static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
2200 u16 action, u16 threshold)
2201 {
2202 struct mwl8k_cmd_set_rts_threshold *cmd;
2203 int rc;
2204
2205 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2206 if (cmd == NULL)
2207 return -ENOMEM;
2208
2209 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2210 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2211 cmd->action = cpu_to_le16(action);
2212 cmd->threshold = cpu_to_le16(threshold);
2213
2214 rc = mwl8k_post_cmd(hw, &cmd->header);
2215 kfree(cmd);
2216
2217 return rc;
2218 }
2219
2220 /*
2221 * CMD_SET_SLOT.
2222 */
2223 struct mwl8k_cmd_set_slot {
2224 struct mwl8k_cmd_pkt header;
2225 __le16 action;
2226 __u8 short_slot;
2227 } __attribute__((packed));
2228
2229 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2230 {
2231 struct mwl8k_cmd_set_slot *cmd;
2232 int rc;
2233
2234 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2235 if (cmd == NULL)
2236 return -ENOMEM;
2237
2238 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2239 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2240 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2241 cmd->short_slot = short_slot_time;
2242
2243 rc = mwl8k_post_cmd(hw, &cmd->header);
2244 kfree(cmd);
2245
2246 return rc;
2247 }
2248
2249 /*
2250 * CMD_SET_EDCA_PARAMS.
2251 */
2252 struct mwl8k_cmd_set_edca_params {
2253 struct mwl8k_cmd_pkt header;
2254
2255 /* See MWL8K_SET_EDCA_XXX below */
2256 __le16 action;
2257
2258 /* TX opportunity in units of 32 us */
2259 __le16 txop;
2260
2261 union {
2262 struct {
2263 /* Log exponent of max contention period: 0...15 */
2264 __le32 log_cw_max;
2265
2266 /* Log exponent of min contention period: 0...15 */
2267 __le32 log_cw_min;
2268
2269 /* Adaptive interframe spacing in units of 32us */
2270 __u8 aifs;
2271
2272 /* TX queue to configure */
2273 __u8 txq;
2274 } ap;
2275 struct {
2276 /* Log exponent of max contention period: 0...15 */
2277 __u8 log_cw_max;
2278
2279 /* Log exponent of min contention period: 0...15 */
2280 __u8 log_cw_min;
2281
2282 /* Adaptive interframe spacing in units of 32us */
2283 __u8 aifs;
2284
2285 /* TX queue to configure */
2286 __u8 txq;
2287 } sta;
2288 };
2289 } __attribute__((packed));
2290
2291 #define MWL8K_SET_EDCA_CW 0x01
2292 #define MWL8K_SET_EDCA_TXOP 0x02
2293 #define MWL8K_SET_EDCA_AIFS 0x04
2294
2295 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2296 MWL8K_SET_EDCA_TXOP | \
2297 MWL8K_SET_EDCA_AIFS)
2298
2299 static int
2300 mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2301 __u16 cw_min, __u16 cw_max,
2302 __u8 aifs, __u16 txop)
2303 {
2304 struct mwl8k_priv *priv = hw->priv;
2305 struct mwl8k_cmd_set_edca_params *cmd;
2306 int rc;
2307
2308 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2309 if (cmd == NULL)
2310 return -ENOMEM;
2311
2312 /*
2313 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2314 * this call.
2315 */
2316 qnum ^= !(qnum >> 1);
2317
2318 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2319 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2320 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2321 cmd->txop = cpu_to_le16(txop);
2322 if (priv->ap_fw) {
2323 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2324 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2325 cmd->ap.aifs = aifs;
2326 cmd->ap.txq = qnum;
2327 } else {
2328 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2329 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2330 cmd->sta.aifs = aifs;
2331 cmd->sta.txq = qnum;
2332 }
2333
2334 rc = mwl8k_post_cmd(hw, &cmd->header);
2335 kfree(cmd);
2336
2337 return rc;
2338 }
2339
2340 /*
2341 * CMD_SET_WMM_MODE.
2342 */
2343 struct mwl8k_cmd_set_wmm_mode {
2344 struct mwl8k_cmd_pkt header;
2345 __le16 action;
2346 } __attribute__((packed));
2347
2348 static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
2349 {
2350 struct mwl8k_priv *priv = hw->priv;
2351 struct mwl8k_cmd_set_wmm_mode *cmd;
2352 int rc;
2353
2354 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2355 if (cmd == NULL)
2356 return -ENOMEM;
2357
2358 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2359 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2360 cmd->action = cpu_to_le16(!!enable);
2361
2362 rc = mwl8k_post_cmd(hw, &cmd->header);
2363 kfree(cmd);
2364
2365 if (!rc)
2366 priv->wmm_enabled = enable;
2367
2368 return rc;
2369 }
2370
2371 /*
2372 * CMD_MIMO_CONFIG.
2373 */
2374 struct mwl8k_cmd_mimo_config {
2375 struct mwl8k_cmd_pkt header;
2376 __le32 action;
2377 __u8 rx_antenna_map;
2378 __u8 tx_antenna_map;
2379 } __attribute__((packed));
2380
2381 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2382 {
2383 struct mwl8k_cmd_mimo_config *cmd;
2384 int rc;
2385
2386 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2387 if (cmd == NULL)
2388 return -ENOMEM;
2389
2390 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2391 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2392 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2393 cmd->rx_antenna_map = rx;
2394 cmd->tx_antenna_map = tx;
2395
2396 rc = mwl8k_post_cmd(hw, &cmd->header);
2397 kfree(cmd);
2398
2399 return rc;
2400 }
2401
2402 /*
2403 * CMD_USE_FIXED_RATE.
2404 */
2405 #define MWL8K_RATE_TABLE_SIZE 8
2406 #define MWL8K_UCAST_RATE 0
2407 #define MWL8K_USE_AUTO_RATE 0x0002
2408
2409 struct mwl8k_rate_entry {
2410 /* Set to 1 if HT rate, 0 if legacy. */
2411 __le32 is_ht_rate;
2412
2413 /* Set to 1 to use retry_count field. */
2414 __le32 enable_retry;
2415
2416 /* Specified legacy rate or MCS. */
2417 __le32 rate;
2418
2419 /* Number of allowed retries. */
2420 __le32 retry_count;
2421 } __attribute__((packed));
2422
2423 struct mwl8k_rate_table {
2424 /* 1 to allow specified rate and below */
2425 __le32 allow_rate_drop;
2426 __le32 num_rates;
2427 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2428 } __attribute__((packed));
2429
2430 struct mwl8k_cmd_use_fixed_rate {
2431 struct mwl8k_cmd_pkt header;
2432 __le32 action;
2433 struct mwl8k_rate_table rate_table;
2434
2435 /* Unicast, Broadcast or Multicast */
2436 __le32 rate_type;
2437 __le32 reserved1;
2438 __le32 reserved2;
2439 } __attribute__((packed));
2440
2441 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2442 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2443 {
2444 struct mwl8k_cmd_use_fixed_rate *cmd;
2445 int count;
2446 int rc;
2447
2448 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2449 if (cmd == NULL)
2450 return -ENOMEM;
2451
2452 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2453 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2454
2455 cmd->action = cpu_to_le32(action);
2456 cmd->rate_type = cpu_to_le32(rate_type);
2457
2458 if (rate_table != NULL) {
2459 /*
2460 * Copy over each field manually so that endian
2461 * conversion can be done.
2462 */
2463 cmd->rate_table.allow_rate_drop =
2464 cpu_to_le32(rate_table->allow_rate_drop);
2465 cmd->rate_table.num_rates =
2466 cpu_to_le32(rate_table->num_rates);
2467
2468 for (count = 0; count < rate_table->num_rates; count++) {
2469 struct mwl8k_rate_entry *dst =
2470 &cmd->rate_table.rate_entry[count];
2471 struct mwl8k_rate_entry *src =
2472 &rate_table->rate_entry[count];
2473
2474 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2475 dst->enable_retry = cpu_to_le32(src->enable_retry);
2476 dst->rate = cpu_to_le32(src->rate);
2477 dst->retry_count = cpu_to_le32(src->retry_count);
2478 }
2479 }
2480
2481 rc = mwl8k_post_cmd(hw, &cmd->header);
2482 kfree(cmd);
2483
2484 return rc;
2485 }
2486
2487 /*
2488 * CMD_ENABLE_SNIFFER.
2489 */
2490 struct mwl8k_cmd_enable_sniffer {
2491 struct mwl8k_cmd_pkt header;
2492 __le32 action;
2493 } __attribute__((packed));
2494
2495 static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2496 {
2497 struct mwl8k_cmd_enable_sniffer *cmd;
2498 int rc;
2499
2500 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2501 if (cmd == NULL)
2502 return -ENOMEM;
2503
2504 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2505 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2506 cmd->action = cpu_to_le32(!!enable);
2507
2508 rc = mwl8k_post_cmd(hw, &cmd->header);
2509 kfree(cmd);
2510
2511 return rc;
2512 }
2513
2514 /*
2515 * CMD_SET_MAC_ADDR.
2516 */
2517 struct mwl8k_cmd_set_mac_addr {
2518 struct mwl8k_cmd_pkt header;
2519 union {
2520 struct {
2521 __le16 mac_type;
2522 __u8 mac_addr[ETH_ALEN];
2523 } mbss;
2524 __u8 mac_addr[ETH_ALEN];
2525 };
2526 } __attribute__((packed));
2527
2528 static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2529 {
2530 struct mwl8k_priv *priv = hw->priv;
2531 struct mwl8k_cmd_set_mac_addr *cmd;
2532 int rc;
2533
2534 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2535 if (cmd == NULL)
2536 return -ENOMEM;
2537
2538 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2539 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2540 if (priv->ap_fw) {
2541 cmd->mbss.mac_type = 0;
2542 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2543 } else {
2544 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2545 }
2546
2547 rc = mwl8k_post_cmd(hw, &cmd->header);
2548 kfree(cmd);
2549
2550 return rc;
2551 }
2552
2553 /*
2554 * CMD_SET_RATEADAPT_MODE.
2555 */
2556 struct mwl8k_cmd_set_rate_adapt_mode {
2557 struct mwl8k_cmd_pkt header;
2558 __le16 action;
2559 __le16 mode;
2560 } __attribute__((packed));
2561
2562 static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2563 {
2564 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2565 int rc;
2566
2567 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2568 if (cmd == NULL)
2569 return -ENOMEM;
2570
2571 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2572 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2573 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2574 cmd->mode = cpu_to_le16(mode);
2575
2576 rc = mwl8k_post_cmd(hw, &cmd->header);
2577 kfree(cmd);
2578
2579 return rc;
2580 }
2581
2582 /*
2583 * CMD_UPDATE_STADB.
2584 */
2585 #define MWL8K_STA_DB_ADD_ENTRY 0
2586 #define MWL8K_STA_DB_MODIFY_ENTRY 1
2587 #define MWL8K_STA_DB_DEL_ENTRY 2
2588 #define MWL8K_STA_DB_FLUSH 3
2589
2590 /* Peer Entry flags - used to define the type of the peer node */
2591 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
2592
2593 struct ewc_ht_info {
2594 __le16 control1;
2595 __le16 control2;
2596 __le16 control3;
2597 } __attribute__((packed));
2598
2599 struct peer_capability_info {
2600 /* Peer type - AP vs. STA. */
2601 __u8 peer_type;
2602
2603 /* Basic 802.11 capabilities from assoc resp. */
2604 __le16 basic_caps;
2605
2606 /* Set if peer supports 802.11n high throughput (HT). */
2607 __u8 ht_support;
2608
2609 /* Valid if HT is supported. */
2610 __le16 ht_caps;
2611 __u8 extended_ht_caps;
2612 struct ewc_ht_info ewc_info;
2613
2614 /* Legacy rate table. Intersection of our rates and peer rates. */
2615 __u8 legacy_rates[12];
2616
2617 /* HT rate table. Intersection of our rates and peer rates. */
2618 __u8 ht_rates[16];
2619 __u8 pad[16];
2620
2621 /* If set, interoperability mode, no proprietary extensions. */
2622 __u8 interop;
2623 __u8 pad2;
2624 __u8 station_id;
2625 __le16 amsdu_enabled;
2626 } __attribute__((packed));
2627
2628 struct mwl8k_cmd_update_stadb {
2629 struct mwl8k_cmd_pkt header;
2630
2631 /* See STADB_ACTION_TYPE */
2632 __le32 action;
2633
2634 /* Peer MAC address */
2635 __u8 peer_addr[ETH_ALEN];
2636
2637 __le32 reserved;
2638
2639 /* Peer info - valid during add/update. */
2640 struct peer_capability_info peer_info;
2641 } __attribute__((packed));
2642
2643 static int mwl8k_cmd_update_stadb(struct ieee80211_hw *hw,
2644 struct ieee80211_vif *vif, __u32 action, u8 *addr)
2645 {
2646 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2647 struct mwl8k_cmd_update_stadb *cmd;
2648 struct peer_capability_info *peer_info;
2649 int rc;
2650
2651 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2652 if (cmd == NULL)
2653 return -ENOMEM;
2654
2655 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2656 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2657
2658 cmd->action = cpu_to_le32(action);
2659 peer_info = &cmd->peer_info;
2660 memcpy(cmd->peer_addr, addr, ETH_ALEN);
2661
2662 switch (action) {
2663 case MWL8K_STA_DB_ADD_ENTRY:
2664 case MWL8K_STA_DB_MODIFY_ENTRY:
2665 /* Build peer_info block */
2666 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2667 peer_info->basic_caps =
2668 cpu_to_le16(vif->bss_conf.assoc_capability);
2669 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2670 sizeof(mwl8k_rateids));
2671 peer_info->interop = 1;
2672 peer_info->amsdu_enabled = 0;
2673
2674 rc = mwl8k_post_cmd(hw, &cmd->header);
2675 if (rc == 0)
2676 mv_vif->peer_id = peer_info->station_id;
2677
2678 break;
2679
2680 case MWL8K_STA_DB_DEL_ENTRY:
2681 case MWL8K_STA_DB_FLUSH:
2682 default:
2683 rc = mwl8k_post_cmd(hw, &cmd->header);
2684 if (rc == 0)
2685 mv_vif->peer_id = 0;
2686 break;
2687 }
2688 kfree(cmd);
2689
2690 return rc;
2691 }
2692
2693
2694 /*
2695 * Interrupt handling.
2696 */
2697 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2698 {
2699 struct ieee80211_hw *hw = dev_id;
2700 struct mwl8k_priv *priv = hw->priv;
2701 u32 status;
2702
2703 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2704 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2705
2706 if (!status)
2707 return IRQ_NONE;
2708
2709 if (status & MWL8K_A2H_INT_TX_DONE)
2710 tasklet_schedule(&priv->tx_reclaim_task);
2711
2712 if (status & MWL8K_A2H_INT_RX_READY) {
2713 while (rxq_process(hw, 0, 1))
2714 rxq_refill(hw, 0, 1);
2715 }
2716
2717 if (status & MWL8K_A2H_INT_OPC_DONE) {
2718 if (priv->hostcmd_wait != NULL)
2719 complete(priv->hostcmd_wait);
2720 }
2721
2722 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2723 if (!mutex_is_locked(&priv->fw_mutex) &&
2724 priv->radio_on && priv->pending_tx_pkts)
2725 mwl8k_tx_start(priv);
2726 }
2727
2728 return IRQ_HANDLED;
2729 }
2730
2731
2732 /*
2733 * Core driver operations.
2734 */
2735 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2736 {
2737 struct mwl8k_priv *priv = hw->priv;
2738 int index = skb_get_queue_mapping(skb);
2739 int rc;
2740
2741 if (priv->current_channel == NULL) {
2742 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2743 "disabled\n", wiphy_name(hw->wiphy));
2744 dev_kfree_skb(skb);
2745 return NETDEV_TX_OK;
2746 }
2747
2748 rc = mwl8k_txq_xmit(hw, index, skb);
2749
2750 return rc;
2751 }
2752
2753 static int mwl8k_start(struct ieee80211_hw *hw)
2754 {
2755 struct mwl8k_priv *priv = hw->priv;
2756 int rc;
2757
2758 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2759 IRQF_SHARED, MWL8K_NAME, hw);
2760 if (rc) {
2761 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2762 wiphy_name(hw->wiphy));
2763 return -EIO;
2764 }
2765
2766 /* Enable tx reclaim tasklet */
2767 tasklet_enable(&priv->tx_reclaim_task);
2768
2769 /* Enable interrupts */
2770 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2771
2772 rc = mwl8k_fw_lock(hw);
2773 if (!rc) {
2774 rc = mwl8k_cmd_radio_enable(hw);
2775
2776 if (!priv->ap_fw) {
2777 if (!rc)
2778 rc = mwl8k_cmd_enable_sniffer(hw, 0);
2779
2780 if (!rc)
2781 rc = mwl8k_cmd_set_pre_scan(hw);
2782
2783 if (!rc)
2784 rc = mwl8k_cmd_set_post_scan(hw,
2785 "\x00\x00\x00\x00\x00\x00");
2786 }
2787
2788 if (!rc)
2789 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
2790
2791 if (!rc)
2792 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
2793
2794 mwl8k_fw_unlock(hw);
2795 }
2796
2797 if (rc) {
2798 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2799 free_irq(priv->pdev->irq, hw);
2800 tasklet_disable(&priv->tx_reclaim_task);
2801 }
2802
2803 return rc;
2804 }
2805
2806 static void mwl8k_stop(struct ieee80211_hw *hw)
2807 {
2808 struct mwl8k_priv *priv = hw->priv;
2809 int i;
2810
2811 mwl8k_cmd_radio_disable(hw);
2812
2813 ieee80211_stop_queues(hw);
2814
2815 /* Disable interrupts */
2816 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2817 free_irq(priv->pdev->irq, hw);
2818
2819 /* Stop finalize join worker */
2820 cancel_work_sync(&priv->finalize_join_worker);
2821 if (priv->beacon_skb != NULL)
2822 dev_kfree_skb(priv->beacon_skb);
2823
2824 /* Stop tx reclaim tasklet */
2825 tasklet_disable(&priv->tx_reclaim_task);
2826
2827 /* Return all skbs to mac80211 */
2828 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2829 mwl8k_txq_reclaim(hw, i, 1);
2830 }
2831
2832 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2833 struct ieee80211_vif *vif)
2834 {
2835 struct mwl8k_priv *priv = hw->priv;
2836 struct mwl8k_vif *mwl8k_vif;
2837
2838 /*
2839 * We only support one active interface at a time.
2840 */
2841 if (priv->vif != NULL)
2842 return -EBUSY;
2843
2844 /*
2845 * We only support managed interfaces for now.
2846 */
2847 if (vif->type != NL80211_IFTYPE_STATION)
2848 return -EINVAL;
2849
2850 /*
2851 * Reject interface creation if sniffer mode is active, as
2852 * STA operation is mutually exclusive with hardware sniffer
2853 * mode.
2854 */
2855 if (priv->sniffer_enabled) {
2856 printk(KERN_INFO "%s: unable to create STA "
2857 "interface due to sniffer mode being enabled\n",
2858 wiphy_name(hw->wiphy));
2859 return -EINVAL;
2860 }
2861
2862 /* Clean out driver private area */
2863 mwl8k_vif = MWL8K_VIF(vif);
2864 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2865
2866 /* Set and save the mac address */
2867 mwl8k_cmd_set_mac_addr(hw, vif->addr);
2868 memcpy(mwl8k_vif->mac_addr, vif->addr, ETH_ALEN);
2869
2870 /* Set Initial sequence number to zero */
2871 mwl8k_vif->seqno = 0;
2872
2873 priv->vif = vif;
2874 priv->current_channel = NULL;
2875
2876 return 0;
2877 }
2878
2879 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2880 struct ieee80211_vif *vif)
2881 {
2882 struct mwl8k_priv *priv = hw->priv;
2883
2884 if (priv->vif == NULL)
2885 return;
2886
2887 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2888
2889 priv->vif = NULL;
2890 }
2891
2892 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2893 {
2894 struct ieee80211_conf *conf = &hw->conf;
2895 struct mwl8k_priv *priv = hw->priv;
2896 int rc;
2897
2898 if (conf->flags & IEEE80211_CONF_IDLE) {
2899 mwl8k_cmd_radio_disable(hw);
2900 priv->current_channel = NULL;
2901 return 0;
2902 }
2903
2904 rc = mwl8k_fw_lock(hw);
2905 if (rc)
2906 return rc;
2907
2908 rc = mwl8k_cmd_radio_enable(hw);
2909 if (rc)
2910 goto out;
2911
2912 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2913 if (rc)
2914 goto out;
2915
2916 priv->current_channel = conf->channel;
2917
2918 if (conf->power_level > 18)
2919 conf->power_level = 18;
2920 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
2921 if (rc)
2922 goto out;
2923
2924 if (priv->ap_fw) {
2925 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2926 if (!rc)
2927 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2928 } else {
2929 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2930 }
2931
2932 out:
2933 mwl8k_fw_unlock(hw);
2934
2935 return rc;
2936 }
2937
2938 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2939 struct ieee80211_vif *vif,
2940 struct ieee80211_bss_conf *info,
2941 u32 changed)
2942 {
2943 struct mwl8k_priv *priv = hw->priv;
2944 int rc;
2945
2946 if ((changed & BSS_CHANGED_ASSOC) == 0)
2947 return;
2948
2949 priv->capture_beacon = false;
2950
2951 rc = mwl8k_fw_lock(hw);
2952 if (rc)
2953 return;
2954
2955 if (vif->bss_conf.assoc) {
2956 /* Install rates */
2957 rc = mwl8k_cmd_set_rate(hw, vif);
2958 if (rc)
2959 goto out;
2960
2961 /* Turn on rate adaptation */
2962 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2963 MWL8K_UCAST_RATE, NULL);
2964 if (rc)
2965 goto out;
2966
2967 /* Set radio preamble */
2968 rc = mwl8k_set_radio_preamble(hw,
2969 vif->bss_conf.use_short_preamble);
2970 if (rc)
2971 goto out;
2972
2973 /* Set slot time */
2974 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
2975 if (rc)
2976 goto out;
2977
2978 /* Set AID */
2979 rc = mwl8k_cmd_set_aid(hw, vif);
2980 if (rc)
2981 goto out;
2982
2983 /*
2984 * Finalize the join. Tell rx handler to process
2985 * next beacon from our BSSID.
2986 */
2987 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
2988 priv->capture_beacon = true;
2989 }
2990
2991 out:
2992 mwl8k_fw_unlock(hw);
2993 }
2994
2995 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2996 int mc_count, struct dev_addr_list *mclist)
2997 {
2998 struct mwl8k_cmd_pkt *cmd;
2999
3000 /*
3001 * Synthesize and return a command packet that programs the
3002 * hardware multicast address filter. At this point we don't
3003 * know whether FIF_ALLMULTI is being requested, but if it is,
3004 * we'll end up throwing this packet away and creating a new
3005 * one in mwl8k_configure_filter().
3006 */
3007 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3008
3009 return (unsigned long)cmd;
3010 }
3011
3012 static int
3013 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3014 unsigned int changed_flags,
3015 unsigned int *total_flags)
3016 {
3017 struct mwl8k_priv *priv = hw->priv;
3018
3019 /*
3020 * Hardware sniffer mode is mutually exclusive with STA
3021 * operation, so refuse to enable sniffer mode if a STA
3022 * interface is active.
3023 */
3024 if (priv->vif != NULL) {
3025 if (net_ratelimit())
3026 printk(KERN_INFO "%s: not enabling sniffer "
3027 "mode because STA interface is active\n",
3028 wiphy_name(hw->wiphy));
3029 return 0;
3030 }
3031
3032 if (!priv->sniffer_enabled) {
3033 if (mwl8k_cmd_enable_sniffer(hw, 1))
3034 return 0;
3035 priv->sniffer_enabled = true;
3036 }
3037
3038 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3039 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3040 FIF_OTHER_BSS;
3041
3042 return 1;
3043 }
3044
3045 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3046 unsigned int changed_flags,
3047 unsigned int *total_flags,
3048 u64 multicast)
3049 {
3050 struct mwl8k_priv *priv = hw->priv;
3051 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3052
3053 /*
3054 * AP firmware doesn't allow fine-grained control over
3055 * the receive filter.
3056 */
3057 if (priv->ap_fw) {
3058 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3059 kfree(cmd);
3060 return;
3061 }
3062
3063 /*
3064 * Enable hardware sniffer mode if FIF_CONTROL or
3065 * FIF_OTHER_BSS is requested.
3066 */
3067 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3068 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3069 kfree(cmd);
3070 return;
3071 }
3072
3073 /* Clear unsupported feature flags */
3074 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3075
3076 if (mwl8k_fw_lock(hw))
3077 return;
3078
3079 if (priv->sniffer_enabled) {
3080 mwl8k_cmd_enable_sniffer(hw, 0);
3081 priv->sniffer_enabled = false;
3082 }
3083
3084 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3085 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3086 /*
3087 * Disable the BSS filter.
3088 */
3089 mwl8k_cmd_set_pre_scan(hw);
3090 } else {
3091 const u8 *bssid;
3092
3093 /*
3094 * Enable the BSS filter.
3095 *
3096 * If there is an active STA interface, use that
3097 * interface's BSSID, otherwise use a dummy one
3098 * (where the OUI part needs to be nonzero for
3099 * the BSSID to be accepted by POST_SCAN).
3100 */
3101 bssid = "\x01\x00\x00\x00\x00\x00";
3102 if (priv->vif != NULL)
3103 bssid = priv->vif->bss_conf.bssid;
3104
3105 mwl8k_cmd_set_post_scan(hw, bssid);
3106 }
3107 }
3108
3109 /*
3110 * If FIF_ALLMULTI is being requested, throw away the command
3111 * packet that ->prepare_multicast() built and replace it with
3112 * a command packet that enables reception of all multicast
3113 * packets.
3114 */
3115 if (*total_flags & FIF_ALLMULTI) {
3116 kfree(cmd);
3117 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3118 }
3119
3120 if (cmd != NULL) {
3121 mwl8k_post_cmd(hw, cmd);
3122 kfree(cmd);
3123 }
3124
3125 mwl8k_fw_unlock(hw);
3126 }
3127
3128 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3129 {
3130 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
3131 }
3132
3133 struct mwl8k_sta_notify_item
3134 {
3135 struct list_head list;
3136 struct ieee80211_vif *vif;
3137 enum sta_notify_cmd cmd;
3138 u8 addr[ETH_ALEN];
3139 };
3140
3141 static void mwl8k_sta_notify_worker(struct work_struct *work)
3142 {
3143 struct mwl8k_priv *priv =
3144 container_of(work, struct mwl8k_priv, sta_notify_worker);
3145
3146 spin_lock_bh(&priv->sta_notify_list_lock);
3147 while (!list_empty(&priv->sta_notify_list)) {
3148 struct mwl8k_sta_notify_item *s;
3149 int action;
3150
3151 s = list_entry(priv->sta_notify_list.next,
3152 struct mwl8k_sta_notify_item, list);
3153 list_del(&s->list);
3154
3155 spin_unlock_bh(&priv->sta_notify_list_lock);
3156
3157 if (s->cmd == STA_NOTIFY_ADD)
3158 action = MWL8K_STA_DB_MODIFY_ENTRY;
3159 else
3160 action = MWL8K_STA_DB_DEL_ENTRY;
3161 mwl8k_cmd_update_stadb(priv->hw, s->vif, action, s->addr);
3162
3163 kfree(s);
3164
3165 spin_lock_bh(&priv->sta_notify_list_lock);
3166 }
3167 spin_unlock_bh(&priv->sta_notify_list_lock);
3168 }
3169
3170 static void
3171 mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3172 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3173 {
3174 struct mwl8k_priv *priv = hw->priv;
3175 struct mwl8k_sta_notify_item *s;
3176
3177 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3178 return;
3179
3180 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3181 if (s != NULL) {
3182 s->vif = vif;
3183 s->cmd = cmd;
3184 memcpy(s->addr, sta->addr, ETH_ALEN);
3185
3186 spin_lock(&priv->sta_notify_list_lock);
3187 list_add_tail(&s->list, &priv->sta_notify_list);
3188 spin_unlock(&priv->sta_notify_list_lock);
3189
3190 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3191 }
3192 }
3193
3194 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3195 const struct ieee80211_tx_queue_params *params)
3196 {
3197 struct mwl8k_priv *priv = hw->priv;
3198 int rc;
3199
3200 rc = mwl8k_fw_lock(hw);
3201 if (!rc) {
3202 if (!priv->wmm_enabled)
3203 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
3204
3205 if (!rc)
3206 rc = mwl8k_cmd_set_edca_params(hw, queue,
3207 params->cw_min,
3208 params->cw_max,
3209 params->aifs,
3210 params->txop);
3211
3212 mwl8k_fw_unlock(hw);
3213 }
3214
3215 return rc;
3216 }
3217
3218 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3219 struct ieee80211_tx_queue_stats *stats)
3220 {
3221 struct mwl8k_priv *priv = hw->priv;
3222 struct mwl8k_tx_queue *txq;
3223 int index;
3224
3225 spin_lock_bh(&priv->tx_lock);
3226 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3227 txq = priv->txq + index;
3228 memcpy(&stats[index], &txq->stats,
3229 sizeof(struct ieee80211_tx_queue_stats));
3230 }
3231 spin_unlock_bh(&priv->tx_lock);
3232
3233 return 0;
3234 }
3235
3236 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3237 struct ieee80211_low_level_stats *stats)
3238 {
3239 return mwl8k_cmd_get_stat(hw, stats);
3240 }
3241
3242 static const struct ieee80211_ops mwl8k_ops = {
3243 .tx = mwl8k_tx,
3244 .start = mwl8k_start,
3245 .stop = mwl8k_stop,
3246 .add_interface = mwl8k_add_interface,
3247 .remove_interface = mwl8k_remove_interface,
3248 .config = mwl8k_config,
3249 .bss_info_changed = mwl8k_bss_info_changed,
3250 .prepare_multicast = mwl8k_prepare_multicast,
3251 .configure_filter = mwl8k_configure_filter,
3252 .set_rts_threshold = mwl8k_set_rts_threshold,
3253 .sta_notify = mwl8k_sta_notify,
3254 .conf_tx = mwl8k_conf_tx,
3255 .get_tx_stats = mwl8k_get_tx_stats,
3256 .get_stats = mwl8k_get_stats,
3257 };
3258
3259 static void mwl8k_tx_reclaim_handler(unsigned long data)
3260 {
3261 int i;
3262 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3263 struct mwl8k_priv *priv = hw->priv;
3264
3265 spin_lock_bh(&priv->tx_lock);
3266 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3267 mwl8k_txq_reclaim(hw, i, 0);
3268
3269 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3270 complete(priv->tx_wait);
3271 priv->tx_wait = NULL;
3272 }
3273 spin_unlock_bh(&priv->tx_lock);
3274 }
3275
3276 static void mwl8k_finalize_join_worker(struct work_struct *work)
3277 {
3278 struct mwl8k_priv *priv =
3279 container_of(work, struct mwl8k_priv, finalize_join_worker);
3280 struct sk_buff *skb = priv->beacon_skb;
3281
3282 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3283 priv->vif->bss_conf.dtim_period);
3284 dev_kfree_skb(skb);
3285
3286 priv->beacon_skb = NULL;
3287 }
3288
3289 enum {
3290 MWL8687 = 0,
3291 MWL8366,
3292 };
3293
3294 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3295 [MWL8687] = {
3296 .part_name = "88w8687",
3297 .helper_image = "mwl8k/helper_8687.fw",
3298 .fw_image = "mwl8k/fmimage_8687.fw",
3299 },
3300 [MWL8366] = {
3301 .part_name = "88w8366",
3302 .helper_image = "mwl8k/helper_8366.fw",
3303 .fw_image = "mwl8k/fmimage_8366.fw",
3304 .ap_rxd_ops = &rxd_8366_ap_ops,
3305 },
3306 };
3307
3308 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3309 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3310 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3311 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3312 { },
3313 };
3314 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3315
3316 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3317 const struct pci_device_id *id)
3318 {
3319 static int printed_version = 0;
3320 struct ieee80211_hw *hw;
3321 struct mwl8k_priv *priv;
3322 int rc;
3323 int i;
3324
3325 if (!printed_version) {
3326 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3327 printed_version = 1;
3328 }
3329
3330
3331 rc = pci_enable_device(pdev);
3332 if (rc) {
3333 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3334 MWL8K_NAME);
3335 return rc;
3336 }
3337
3338 rc = pci_request_regions(pdev, MWL8K_NAME);
3339 if (rc) {
3340 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3341 MWL8K_NAME);
3342 goto err_disable_device;
3343 }
3344
3345 pci_set_master(pdev);
3346
3347
3348 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3349 if (hw == NULL) {
3350 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3351 rc = -ENOMEM;
3352 goto err_free_reg;
3353 }
3354
3355 SET_IEEE80211_DEV(hw, &pdev->dev);
3356 pci_set_drvdata(pdev, hw);
3357
3358 priv = hw->priv;
3359 priv->hw = hw;
3360 priv->pdev = pdev;
3361 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3362
3363
3364 priv->sram = pci_iomap(pdev, 0, 0x10000);
3365 if (priv->sram == NULL) {
3366 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3367 wiphy_name(hw->wiphy));
3368 goto err_iounmap;
3369 }
3370
3371 /*
3372 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3373 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3374 */
3375 priv->regs = pci_iomap(pdev, 1, 0x10000);
3376 if (priv->regs == NULL) {
3377 priv->regs = pci_iomap(pdev, 2, 0x10000);
3378 if (priv->regs == NULL) {
3379 printk(KERN_ERR "%s: Cannot map device registers\n",
3380 wiphy_name(hw->wiphy));
3381 goto err_iounmap;
3382 }
3383 }
3384
3385
3386 /* Reset firmware and hardware */
3387 mwl8k_hw_reset(priv);
3388
3389 /* Ask userland hotplug daemon for the device firmware */
3390 rc = mwl8k_request_firmware(priv);
3391 if (rc) {
3392 printk(KERN_ERR "%s: Firmware files not found\n",
3393 wiphy_name(hw->wiphy));
3394 goto err_stop_firmware;
3395 }
3396
3397 /* Load firmware into hardware */
3398 rc = mwl8k_load_firmware(hw);
3399 if (rc) {
3400 printk(KERN_ERR "%s: Cannot start firmware\n",
3401 wiphy_name(hw->wiphy));
3402 goto err_stop_firmware;
3403 }
3404
3405 /* Reclaim memory once firmware is successfully loaded */
3406 mwl8k_release_firmware(priv);
3407
3408
3409 if (priv->ap_fw) {
3410 priv->rxd_ops = priv->device_info->ap_rxd_ops;
3411 if (priv->rxd_ops == NULL) {
3412 printk(KERN_ERR "%s: Driver does not have AP "
3413 "firmware image support for this hardware\n",
3414 wiphy_name(hw->wiphy));
3415 goto err_stop_firmware;
3416 }
3417 } else {
3418 priv->rxd_ops = &rxd_sta_ops;
3419 }
3420
3421 priv->sniffer_enabled = false;
3422 priv->wmm_enabled = false;
3423 priv->pending_tx_pkts = 0;
3424
3425
3426 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3427 priv->band.band = IEEE80211_BAND_2GHZ;
3428 priv->band.channels = priv->channels;
3429 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3430 priv->band.bitrates = priv->rates;
3431 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3432 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3433
3434 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3435 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3436
3437 /*
3438 * Extra headroom is the size of the required DMA header
3439 * minus the size of the smallest 802.11 frame (CTS frame).
3440 */
3441 hw->extra_tx_headroom =
3442 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3443
3444 hw->channel_change_time = 10;
3445
3446 hw->queues = MWL8K_TX_QUEUES;
3447
3448 /* Set rssi and noise values to dBm */
3449 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3450 hw->vif_data_size = sizeof(struct mwl8k_vif);
3451 priv->vif = NULL;
3452
3453 /* Set default radio state and preamble */
3454 priv->radio_on = 0;
3455 priv->radio_short_preamble = 0;
3456
3457 /* Station database handling */
3458 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3459 spin_lock_init(&priv->sta_notify_list_lock);
3460 INIT_LIST_HEAD(&priv->sta_notify_list);
3461
3462 /* Finalize join worker */
3463 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3464
3465 /* TX reclaim tasklet */
3466 tasklet_init(&priv->tx_reclaim_task,
3467 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3468 tasklet_disable(&priv->tx_reclaim_task);
3469
3470 /* Power management cookie */
3471 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3472 if (priv->cookie == NULL)
3473 goto err_stop_firmware;
3474
3475 rc = mwl8k_rxq_init(hw, 0);
3476 if (rc)
3477 goto err_free_cookie;
3478 rxq_refill(hw, 0, INT_MAX);
3479
3480 mutex_init(&priv->fw_mutex);
3481 priv->fw_mutex_owner = NULL;
3482 priv->fw_mutex_depth = 0;
3483 priv->hostcmd_wait = NULL;
3484
3485 spin_lock_init(&priv->tx_lock);
3486
3487 priv->tx_wait = NULL;
3488
3489 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3490 rc = mwl8k_txq_init(hw, i);
3491 if (rc)
3492 goto err_free_queues;
3493 }
3494
3495 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3496 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3497 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3498 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3499
3500 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3501 IRQF_SHARED, MWL8K_NAME, hw);
3502 if (rc) {
3503 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3504 wiphy_name(hw->wiphy));
3505 goto err_free_queues;
3506 }
3507
3508 /*
3509 * Temporarily enable interrupts. Initial firmware host
3510 * commands use interrupts and avoids polling. Disable
3511 * interrupts when done.
3512 */
3513 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3514
3515 /* Get config data, mac addrs etc */
3516 if (priv->ap_fw) {
3517 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3518 if (!rc)
3519 rc = mwl8k_cmd_set_hw_spec(hw);
3520 } else {
3521 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3522
3523 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
3524 }
3525 if (rc) {
3526 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3527 wiphy_name(hw->wiphy));
3528 goto err_free_irq;
3529 }
3530
3531 /* Turn radio off */
3532 rc = mwl8k_cmd_radio_disable(hw);
3533 if (rc) {
3534 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3535 goto err_free_irq;
3536 }
3537
3538 /* Clear MAC address */
3539 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3540 if (rc) {
3541 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3542 wiphy_name(hw->wiphy));
3543 goto err_free_irq;
3544 }
3545
3546 /* Disable interrupts */
3547 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3548 free_irq(priv->pdev->irq, hw);
3549
3550 rc = ieee80211_register_hw(hw);
3551 if (rc) {
3552 printk(KERN_ERR "%s: Cannot register device\n",
3553 wiphy_name(hw->wiphy));
3554 goto err_free_queues;
3555 }
3556
3557 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3558 wiphy_name(hw->wiphy), priv->device_info->part_name,
3559 priv->hw_rev, hw->wiphy->perm_addr,
3560 priv->ap_fw ? "AP" : "STA",
3561 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3562 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3563
3564 return 0;
3565
3566 err_free_irq:
3567 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3568 free_irq(priv->pdev->irq, hw);
3569
3570 err_free_queues:
3571 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3572 mwl8k_txq_deinit(hw, i);
3573 mwl8k_rxq_deinit(hw, 0);
3574
3575 err_free_cookie:
3576 if (priv->cookie != NULL)
3577 pci_free_consistent(priv->pdev, 4,
3578 priv->cookie, priv->cookie_dma);
3579
3580 err_stop_firmware:
3581 mwl8k_hw_reset(priv);
3582 mwl8k_release_firmware(priv);
3583
3584 err_iounmap:
3585 if (priv->regs != NULL)
3586 pci_iounmap(pdev, priv->regs);
3587
3588 if (priv->sram != NULL)
3589 pci_iounmap(pdev, priv->sram);
3590
3591 pci_set_drvdata(pdev, NULL);
3592 ieee80211_free_hw(hw);
3593
3594 err_free_reg:
3595 pci_release_regions(pdev);
3596
3597 err_disable_device:
3598 pci_disable_device(pdev);
3599
3600 return rc;
3601 }
3602
3603 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3604 {
3605 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3606 }
3607
3608 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3609 {
3610 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3611 struct mwl8k_priv *priv;
3612 int i;
3613
3614 if (hw == NULL)
3615 return;
3616 priv = hw->priv;
3617
3618 ieee80211_stop_queues(hw);
3619
3620 ieee80211_unregister_hw(hw);
3621
3622 /* Remove tx reclaim tasklet */
3623 tasklet_kill(&priv->tx_reclaim_task);
3624
3625 /* Stop hardware */
3626 mwl8k_hw_reset(priv);
3627
3628 /* Return all skbs to mac80211 */
3629 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3630 mwl8k_txq_reclaim(hw, i, 1);
3631
3632 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3633 mwl8k_txq_deinit(hw, i);
3634
3635 mwl8k_rxq_deinit(hw, 0);
3636
3637 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3638
3639 pci_iounmap(pdev, priv->regs);
3640 pci_iounmap(pdev, priv->sram);
3641 pci_set_drvdata(pdev, NULL);
3642 ieee80211_free_hw(hw);
3643 pci_release_regions(pdev);
3644 pci_disable_device(pdev);
3645 }
3646
3647 static struct pci_driver mwl8k_driver = {
3648 .name = MWL8K_NAME,
3649 .id_table = mwl8k_pci_id_table,
3650 .probe = mwl8k_probe,
3651 .remove = __devexit_p(mwl8k_remove),
3652 .shutdown = __devexit_p(mwl8k_shutdown),
3653 };
3654
3655 static int __init mwl8k_init(void)
3656 {
3657 return pci_register_driver(&mwl8k_driver);
3658 }
3659
3660 static void __exit mwl8k_exit(void)
3661 {
3662 pci_unregister_driver(&mwl8k_driver);
3663 }
3664
3665 module_init(mwl8k_init);
3666 module_exit(mwl8k_exit);
3667
3668 MODULE_DESCRIPTION(MWL8K_DESC);
3669 MODULE_VERSION(MWL8K_VERSION);
3670 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3671 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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