2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 static int rtl8xxxu_debug
= RTL8XXXU_DEBUG_EFUSE
;
46 static bool rtl8xxxu_ht40_2g
;
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
61 module_param_named(debug
, rtl8xxxu_debug
, int, 0600);
62 MODULE_PARM_DESC(debug
, "Set debug mask");
63 module_param_named(ht40_2g
, rtl8xxxu_ht40_2g
, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g
, "Enable HT40 support on the 2.4GHz band");
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
76 struct rtl8xxxu_rx_urb
*rx_urb
);
78 static struct ieee80211_rate rtl8xxxu_rates
[] = {
79 { .bitrate
= 10, .hw_value
= DESC_RATE_1M
, .flags
= 0 },
80 { .bitrate
= 20, .hw_value
= DESC_RATE_2M
, .flags
= 0 },
81 { .bitrate
= 55, .hw_value
= DESC_RATE_5_5M
, .flags
= 0 },
82 { .bitrate
= 110, .hw_value
= DESC_RATE_11M
, .flags
= 0 },
83 { .bitrate
= 60, .hw_value
= DESC_RATE_6M
, .flags
= 0 },
84 { .bitrate
= 90, .hw_value
= DESC_RATE_9M
, .flags
= 0 },
85 { .bitrate
= 120, .hw_value
= DESC_RATE_12M
, .flags
= 0 },
86 { .bitrate
= 180, .hw_value
= DESC_RATE_18M
, .flags
= 0 },
87 { .bitrate
= 240, .hw_value
= DESC_RATE_24M
, .flags
= 0 },
88 { .bitrate
= 360, .hw_value
= DESC_RATE_36M
, .flags
= 0 },
89 { .bitrate
= 480, .hw_value
= DESC_RATE_48M
, .flags
= 0 },
90 { .bitrate
= 540, .hw_value
= DESC_RATE_54M
, .flags
= 0 },
93 static struct ieee80211_channel rtl8xxxu_channels_2g
[] = {
94 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2412,
95 .hw_value
= 1, .max_power
= 30 },
96 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2417,
97 .hw_value
= 2, .max_power
= 30 },
98 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2422,
99 .hw_value
= 3, .max_power
= 30 },
100 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2427,
101 .hw_value
= 4, .max_power
= 30 },
102 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2432,
103 .hw_value
= 5, .max_power
= 30 },
104 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2437,
105 .hw_value
= 6, .max_power
= 30 },
106 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2442,
107 .hw_value
= 7, .max_power
= 30 },
108 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2447,
109 .hw_value
= 8, .max_power
= 30 },
110 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2452,
111 .hw_value
= 9, .max_power
= 30 },
112 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2457,
113 .hw_value
= 10, .max_power
= 30 },
114 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2462,
115 .hw_value
= 11, .max_power
= 30 },
116 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2467,
117 .hw_value
= 12, .max_power
= 30 },
118 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2472,
119 .hw_value
= 13, .max_power
= 30 },
120 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2484,
121 .hw_value
= 14, .max_power
= 30 }
124 static struct ieee80211_supported_band rtl8xxxu_supported_band
= {
125 .channels
= rtl8xxxu_channels_2g
,
126 .n_channels
= ARRAY_SIZE(rtl8xxxu_channels_2g
),
127 .bitrates
= rtl8xxxu_rates
,
128 .n_bitrates
= ARRAY_SIZE(rtl8xxxu_rates
),
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table
[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table
[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table
[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
282 {0xffff, 0xffffffff},
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table
[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table
[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
481 {0xffff, 0xffffffff},
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table
[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
580 {0xffff, 0xffffffff},
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table
[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table
[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table
[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table
[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table
[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
921 * 0x71 has same package type condition as for register 0x51
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table
[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table
[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table
[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table
[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs
[] = {
1217 .hssiparm1
= REG_FPGA0_XA_HSSI_PARM1
,
1218 .hssiparm2
= REG_FPGA0_XA_HSSI_PARM2
,
1219 .lssiparm
= REG_FPGA0_XA_LSSI_PARM
,
1220 .hspiread
= REG_HSPI_XA_READBACK
,
1221 .lssiread
= REG_FPGA0_XA_LSSI_READBACK
,
1222 .rf_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
,
1225 .hssiparm1
= REG_FPGA0_XB_HSSI_PARM1
,
1226 .hssiparm2
= REG_FPGA0_XB_HSSI_PARM2
,
1227 .lssiparm
= REG_FPGA0_XB_LSSI_PARM
,
1228 .hspiread
= REG_HSPI_XB_READBACK
,
1229 .lssiread
= REG_FPGA0_XB_LSSI_READBACK
,
1230 .rf_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
,
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg
[RTL8XXXU_BB_REGS
] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE
,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE
,
1237 REG_OFDM0_ENERGY_CCA_THRES
,
1238 REG_OFDM0_AGCR_SSI_TABLE
,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE
,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE
,
1241 REG_OFDM0_XC_TX_AFE
,
1242 REG_OFDM0_XD_TX_AFE
,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1246 static u8
rtl8xxxu_read8(struct rtl8xxxu_priv
*priv
, u16 addr
)
1248 struct usb_device
*udev
= priv
->udev
;
1252 mutex_lock(&priv
->usb_buf_mutex
);
1253 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1254 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1255 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1256 RTW_USB_CONTROL_MSG_TIMEOUT
);
1257 data
= priv
->usb_buf
.val8
;
1258 mutex_unlock(&priv
->usb_buf_mutex
);
1260 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1261 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__
, addr
, data
, len
);
1266 static u16
rtl8xxxu_read16(struct rtl8xxxu_priv
*priv
, u16 addr
)
1268 struct usb_device
*udev
= priv
->udev
;
1272 mutex_lock(&priv
->usb_buf_mutex
);
1273 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1274 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1275 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1276 RTW_USB_CONTROL_MSG_TIMEOUT
);
1277 data
= le16_to_cpu(priv
->usb_buf
.val16
);
1278 mutex_unlock(&priv
->usb_buf_mutex
);
1280 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1281 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__
, addr
, data
, len
);
1286 static u32
rtl8xxxu_read32(struct rtl8xxxu_priv
*priv
, u16 addr
)
1288 struct usb_device
*udev
= priv
->udev
;
1292 mutex_lock(&priv
->usb_buf_mutex
);
1293 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1294 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1295 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1296 RTW_USB_CONTROL_MSG_TIMEOUT
);
1297 data
= le32_to_cpu(priv
->usb_buf
.val32
);
1298 mutex_unlock(&priv
->usb_buf_mutex
);
1300 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1301 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__
, addr
, data
, len
);
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv
*priv
, u16 addr
, u8 val
)
1308 struct usb_device
*udev
= priv
->udev
;
1311 mutex_lock(&priv
->usb_buf_mutex
);
1312 priv
->usb_buf
.val8
= val
;
1313 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1314 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1315 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1316 RTW_USB_CONTROL_MSG_TIMEOUT
);
1318 mutex_unlock(&priv
->usb_buf_mutex
);
1320 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1321 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x\n",
1322 __func__
, addr
, val
);
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv
*priv
, u16 addr
, u16 val
)
1328 struct usb_device
*udev
= priv
->udev
;
1331 mutex_lock(&priv
->usb_buf_mutex
);
1332 priv
->usb_buf
.val16
= cpu_to_le16(val
);
1333 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1334 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1335 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1336 RTW_USB_CONTROL_MSG_TIMEOUT
);
1337 mutex_unlock(&priv
->usb_buf_mutex
);
1339 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1340 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x\n",
1341 __func__
, addr
, val
);
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv
*priv
, u16 addr
, u32 val
)
1347 struct usb_device
*udev
= priv
->udev
;
1350 mutex_lock(&priv
->usb_buf_mutex
);
1351 priv
->usb_buf
.val32
= cpu_to_le32(val
);
1352 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1353 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1354 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1355 RTW_USB_CONTROL_MSG_TIMEOUT
);
1356 mutex_unlock(&priv
->usb_buf_mutex
);
1358 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1359 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x\n",
1360 __func__
, addr
, val
);
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv
*priv
, u16 addr
, u8
*buf
, u16 len
)
1367 struct usb_device
*udev
= priv
->udev
;
1368 int blocksize
= priv
->fops
->writeN_block_size
;
1369 int ret
, i
, count
, remainder
;
1371 count
= len
/ blocksize
;
1372 remainder
= len
% blocksize
;
1374 for (i
= 0; i
< count
; i
++) {
1375 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1376 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1377 addr
, 0, buf
, blocksize
,
1378 RTW_USB_CONTROL_MSG_TIMEOUT
);
1379 if (ret
!= blocksize
)
1387 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1388 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1389 addr
, 0, buf
, remainder
,
1390 RTW_USB_CONTROL_MSG_TIMEOUT
);
1391 if (ret
!= remainder
)
1398 dev_info(&udev
->dev
,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__
, addr
, blocksize
);
1404 static u32
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv
*priv
,
1405 enum rtl8xxxu_rfpath path
, u8 reg
)
1407 u32 hssia
, val32
, retval
;
1409 hssia
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM2
);
1411 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
);
1415 val32
&= ~FPGA0_HSSI_PARM2_ADDR_MASK
;
1416 val32
|= (reg
<< FPGA0_HSSI_PARM2_ADDR_SHIFT
);
1417 val32
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1418 hssia
&= ~FPGA0_HSSI_PARM2_EDGE_READ
;
1419 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1423 rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
, val32
);
1426 hssia
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1427 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1430 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm1
);
1431 if (val32
& FPGA0_HSSI_PARM1_PI
)
1432 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hspiread
);
1434 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].lssiread
);
1438 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_READ
)
1439 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1440 __func__
, reg
, retval
);
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv
*priv
,
1450 enum rtl8xxxu_rfpath path
, u8 reg
, u32 data
)
1455 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_WRITE
)
1456 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1457 __func__
, reg
, data
);
1459 data
&= FPGA0_LSSI_PARM_DATA_MASK
;
1460 dataaddr
= (reg
<< FPGA0_LSSI_PARM_ADDR_SHIFT
) | data
;
1462 /* Use XB for path B */
1463 ret
= rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].lssiparm
, dataaddr
);
1464 if (ret
!= sizeof(dataaddr
))
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv
*priv
,
1475 struct h2c_cmd
*h2c
, int len
)
1477 struct device
*dev
= &priv
->udev
->dev
;
1478 int mbox_nr
, retry
, retval
= 0;
1479 int mbox_reg
, mbox_ext_reg
;
1482 mutex_lock(&priv
->h2c_mutex
);
1484 mbox_nr
= priv
->next_mbox
;
1485 mbox_reg
= REG_HMBOX_0
+ (mbox_nr
* 4);
1486 mbox_ext_reg
= priv
->fops
->mbox_ext_reg
+
1487 (mbox_nr
* priv
->fops
->mbox_ext_width
);
1494 val8
= rtl8xxxu_read8(priv
, REG_HMTFR
);
1495 if (!(val8
& BIT(mbox_nr
)))
1500 dev_info(dev
, "%s: Mailbox busy\n", __func__
);
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1508 if (len
> sizeof(u32
)) {
1509 if (priv
->fops
->mbox_ext_width
== 4) {
1510 rtl8xxxu_write32(priv
, mbox_ext_reg
,
1511 le32_to_cpu(h2c
->raw_wide
.ext
));
1512 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1513 dev_info(dev
, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c
->raw_wide
.ext
));
1516 rtl8xxxu_write16(priv
, mbox_ext_reg
,
1517 le16_to_cpu(h2c
->raw
.ext
));
1518 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1519 dev_info(dev
, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c
->raw
.ext
));
1523 rtl8xxxu_write32(priv
, mbox_reg
, le32_to_cpu(h2c
->raw
.data
));
1524 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1525 dev_info(dev
, "H2C %08x\n", le32_to_cpu(h2c
->raw
.data
));
1527 priv
->next_mbox
= (mbox_nr
+ 1) % H2C_MAX_MBOX
;
1530 mutex_unlock(&priv
->h2c_mutex
);
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv
*priv
, u8 reg
, u8 data
)
1539 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
1540 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
1541 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
1542 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
1543 h2c
.bt_mp_oper
.data
= data
;
1544 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
1547 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
1548 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
1549 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
1550 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
1551 h2c
.bt_mp_oper
.addr
= reg
;
1552 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv
*priv
)
1560 val8
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
1561 val8
|= BIT(0) | BIT(3);
1562 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, val8
);
1564 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
1565 val32
&= ~(BIT(4) | BIT(5));
1567 if (priv
->rf_paths
== 2) {
1568 val32
&= ~(BIT(20) | BIT(21));
1571 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
1573 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
1574 val32
&= ~OFDM_RF_PATH_TX_MASK
;
1575 if (priv
->tx_paths
== 2)
1576 val32
|= OFDM_RF_PATH_TX_A
| OFDM_RF_PATH_TX_B
;
1577 else if (priv
->rtlchip
== 0x8192c || priv
->rtlchip
== 0x8191c)
1578 val32
|= OFDM_RF_PATH_TX_B
;
1580 val32
|= OFDM_RF_PATH_TX_A
;
1581 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
1583 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1584 val32
&= ~FPGA_RF_MODE_JAPAN
;
1585 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1587 if (priv
->rf_paths
== 2)
1588 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x63db25a0);
1590 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x631b25a0);
1592 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x32d95);
1593 if (priv
->rf_paths
== 2)
1594 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0x32d95);
1596 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
1599 static void rtl8723a_disable_rf(struct rtl8xxxu_priv
*priv
)
1604 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
1606 sps0
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
1608 /* RF RX code for preamble power saving */
1609 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
1610 val32
&= ~(BIT(3) | BIT(4) | BIT(5));
1611 if (priv
->rf_paths
== 2)
1612 val32
&= ~(BIT(19) | BIT(20) | BIT(21));
1613 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
1615 /* Disable TX for four paths */
1616 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
1617 val32
&= ~OFDM_RF_PATH_TX_MASK
;
1618 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
1620 /* Enable power saving */
1621 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1622 val32
|= FPGA_RF_MODE_JAPAN
;
1623 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1625 /* AFE control register to power down bits [30:22] */
1626 if (priv
->rf_paths
== 2)
1627 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x00db25a0);
1629 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x001b25a0);
1631 /* Power down RF module */
1632 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0);
1633 if (priv
->rf_paths
== 2)
1634 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0);
1636 sps0
&= ~(BIT(0) | BIT(3));
1637 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, sps0
);
1641 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv
*priv
)
1645 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
+ 2);
1647 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
+ 2, val8
);
1649 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
1650 val8
= rtl8xxxu_read8(priv
, REG_TBTT_PROHIBIT
+ 2);
1652 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 2, val8
);
1657 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1658 * supports the 2.4GHz band, so channels 1 - 14:
1659 * group 0: channels 1 - 3
1660 * group 1: channels 4 - 9
1661 * group 2: channels 10 - 14
1663 * Note: We index from 0 in the code
1665 static int rtl8723a_channel_to_group(int channel
)
1671 else if (channel
< 10)
1679 static int rtl8723b_channel_to_group(int channel
)
1685 else if (channel
< 6)
1687 else if (channel
< 9)
1689 else if (channel
< 12)
1697 static void rtl8723au_config_channel(struct ieee80211_hw
*hw
)
1699 struct rtl8xxxu_priv
*priv
= hw
->priv
;
1703 int sec_ch_above
, channel
;
1706 opmode
= rtl8xxxu_read8(priv
, REG_BW_OPMODE
);
1707 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
1708 channel
= hw
->conf
.chandef
.chan
->hw_value
;
1710 switch (hw
->conf
.chandef
.width
) {
1711 case NL80211_CHAN_WIDTH_20_NOHT
:
1713 case NL80211_CHAN_WIDTH_20
:
1714 opmode
|= BW_OPMODE_20MHZ
;
1715 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
1717 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1718 val32
&= ~FPGA_RF_MODE
;
1719 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1721 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1722 val32
&= ~FPGA_RF_MODE
;
1723 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1725 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
1726 val32
|= FPGA0_ANALOG2_20MHZ
;
1727 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
1729 case NL80211_CHAN_WIDTH_40
:
1730 if (hw
->conf
.chandef
.center_freq1
>
1731 hw
->conf
.chandef
.chan
->center_freq
) {
1739 opmode
&= ~BW_OPMODE_20MHZ
;
1740 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
1741 rsr
&= ~RSR_RSC_BANDWIDTH_40M
;
1743 rsr
|= RSR_RSC_UPPER_SUB_CHANNEL
;
1745 rsr
|= RSR_RSC_LOWER_SUB_CHANNEL
;
1746 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, rsr
);
1748 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1749 val32
|= FPGA_RF_MODE
;
1750 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1752 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1753 val32
|= FPGA_RF_MODE
;
1754 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1757 * Set Control channel to upper or lower. These settings
1758 * are required only for 40MHz
1760 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
1761 val32
&= ~CCK0_SIDEBAND
;
1763 val32
|= CCK0_SIDEBAND
;
1764 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
1766 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
1767 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
1769 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
1771 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
1772 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
1774 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
1775 val32
&= ~FPGA0_ANALOG2_20MHZ
;
1776 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
1778 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1779 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
1781 val32
|= FPGA0_PS_UPPER_CHANNEL
;
1783 val32
|= FPGA0_PS_LOWER_CHANNEL
;
1784 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1791 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1792 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1793 val32
&= ~MODE_AG_CHANNEL_MASK
;
1795 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1803 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
1804 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
1806 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
1807 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
1809 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1810 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1811 if (hw
->conf
.chandef
.width
== NL80211_CHAN_WIDTH_40
)
1812 val32
&= ~MODE_AG_CHANNEL_20MHZ
;
1814 val32
|= MODE_AG_CHANNEL_20MHZ
;
1815 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1819 static void rtl8723bu_config_channel(struct ieee80211_hw
*hw
)
1821 struct rtl8xxxu_priv
*priv
= hw
->priv
;
1823 u8 val8
, subchannel
;
1826 int sec_ch_above
, channel
;
1829 rf_mode_bw
= rtl8xxxu_read16(priv
, REG_WMAC_TRXPTCL_CTL
);
1830 rf_mode_bw
&= ~WMAC_TRXPTCL_CTL_BW_MASK
;
1831 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
1832 channel
= hw
->conf
.chandef
.chan
->hw_value
;
1837 switch (hw
->conf
.chandef
.width
) {
1838 case NL80211_CHAN_WIDTH_20_NOHT
:
1840 case NL80211_CHAN_WIDTH_20
:
1841 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_20
;
1844 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1845 val32
&= ~FPGA_RF_MODE
;
1846 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1848 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1849 val32
&= ~FPGA_RF_MODE
;
1850 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1852 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
);
1853 val32
&= ~(BIT(30) | BIT(31));
1854 rtl8xxxu_write32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
, val32
);
1857 case NL80211_CHAN_WIDTH_40
:
1858 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_40
;
1860 if (hw
->conf
.chandef
.center_freq1
>
1861 hw
->conf
.chandef
.chan
->center_freq
) {
1869 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1870 val32
|= FPGA_RF_MODE
;
1871 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1873 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1874 val32
|= FPGA_RF_MODE
;
1875 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1878 * Set Control channel to upper or lower. These settings
1879 * are required only for 40MHz
1881 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
1882 val32
&= ~CCK0_SIDEBAND
;
1884 val32
|= CCK0_SIDEBAND
;
1885 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
1887 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
1888 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
1890 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
1892 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
1893 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
1895 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1896 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
1898 val32
|= FPGA0_PS_UPPER_CHANNEL
;
1900 val32
|= FPGA0_PS_LOWER_CHANNEL
;
1901 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1903 case NL80211_CHAN_WIDTH_80
:
1904 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_80
;
1910 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1911 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1912 val32
&= ~MODE_AG_CHANNEL_MASK
;
1914 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1917 rtl8xxxu_write16(priv
, REG_WMAC_TRXPTCL_CTL
, rf_mode_bw
);
1918 rtl8xxxu_write8(priv
, REG_DATA_SUBCHANNEL
, subchannel
);
1925 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
1926 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
1928 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
1929 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
1931 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1932 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1933 val32
&= ~MODE_AG_BW_MASK
;
1934 switch(hw
->conf
.chandef
.width
) {
1935 case NL80211_CHAN_WIDTH_80
:
1936 val32
|= MODE_AG_BW_80MHZ_8723B
;
1938 case NL80211_CHAN_WIDTH_40
:
1939 val32
|= MODE_AG_BW_40MHZ_8723B
;
1942 val32
|= MODE_AG_BW_20MHZ_8723B
;
1945 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1950 rtl8723a_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
1952 u8 cck
[RTL8723A_MAX_RF_PATHS
], ofdm
[RTL8723A_MAX_RF_PATHS
];
1953 u8 ofdmbase
[RTL8723A_MAX_RF_PATHS
], mcsbase
[RTL8723A_MAX_RF_PATHS
];
1954 u32 val32
, ofdm_a
, ofdm_b
, mcs_a
, mcs_b
;
1958 group
= rtl8723a_channel_to_group(channel
);
1960 cck
[0] = priv
->cck_tx_power_index_A
[group
];
1961 cck
[1] = priv
->cck_tx_power_index_B
[group
];
1963 ofdm
[0] = priv
->ht40_1s_tx_power_index_A
[group
];
1964 ofdm
[1] = priv
->ht40_1s_tx_power_index_B
[group
];
1966 ofdmbase
[0] = ofdm
[0] + priv
->ofdm_tx_power_index_diff
[group
].a
;
1967 ofdmbase
[1] = ofdm
[1] + priv
->ofdm_tx_power_index_diff
[group
].b
;
1969 mcsbase
[0] = ofdm
[0];
1970 mcsbase
[1] = ofdm
[1];
1972 mcsbase
[0] += priv
->ht20_tx_power_index_diff
[group
].a
;
1973 mcsbase
[1] += priv
->ht20_tx_power_index_diff
[group
].b
;
1976 if (priv
->tx_paths
> 1) {
1977 if (ofdm
[0] > priv
->ht40_2s_tx_power_index_diff
[group
].a
)
1978 ofdm
[0] -= priv
->ht40_2s_tx_power_index_diff
[group
].a
;
1979 if (ofdm
[1] > priv
->ht40_2s_tx_power_index_diff
[group
].b
)
1980 ofdm
[1] -= priv
->ht40_2s_tx_power_index_diff
[group
].b
;
1983 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
1984 dev_info(&priv
->udev
->dev
,
1985 "%s: Setting TX power CCK A: %02x, "
1986 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1987 __func__
, cck
[0], cck
[1], ofdm
[0], ofdm
[1]);
1989 for (i
= 0; i
< RTL8723A_MAX_RF_PATHS
; i
++) {
1990 if (cck
[i
] > RF6052_MAX_TX_PWR
)
1991 cck
[i
] = RF6052_MAX_TX_PWR
;
1992 if (ofdm
[i
] > RF6052_MAX_TX_PWR
)
1993 ofdm
[i
] = RF6052_MAX_TX_PWR
;
1996 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
1997 val32
&= 0xffff00ff;
1998 val32
|= (cck
[0] << 8);
1999 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2001 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2003 val32
|= ((cck
[0] << 8) | (cck
[0] << 16) | (cck
[0] << 24));
2004 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2006 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2007 val32
&= 0xffffff00;
2009 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2011 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
);
2013 val32
|= ((cck
[1] << 8) | (cck
[1] << 16) | (cck
[1] << 24));
2014 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
, val32
);
2016 ofdm_a
= ofdmbase
[0] | ofdmbase
[0] << 8 |
2017 ofdmbase
[0] << 16 | ofdmbase
[0] << 24;
2018 ofdm_b
= ofdmbase
[1] | ofdmbase
[1] << 8 |
2019 ofdmbase
[1] << 16 | ofdmbase
[1] << 24;
2020 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm_a
);
2021 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE18_06
, ofdm_b
);
2023 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm_a
);
2024 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE54_24
, ofdm_b
);
2026 mcs_a
= mcsbase
[0] | mcsbase
[0] << 8 |
2027 mcsbase
[0] << 16 | mcsbase
[0] << 24;
2028 mcs_b
= mcsbase
[1] | mcsbase
[1] << 8 |
2029 mcsbase
[1] << 16 | mcsbase
[1] << 24;
2031 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs_a
);
2032 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS03_MCS00
, mcs_b
);
2034 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs_a
);
2035 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS07_MCS04
, mcs_b
);
2037 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS11_MCS08
, mcs_a
);
2038 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS11_MCS08
, mcs_b
);
2040 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS15_MCS12
, mcs_a
);
2041 for (i
= 0; i
< 3; i
++) {
2043 val8
= (mcsbase
[0] > 8) ? (mcsbase
[0] - 8) : 0;
2045 val8
= (mcsbase
[0] > 6) ? (mcsbase
[0] - 6) : 0;
2046 rtl8xxxu_write8(priv
, REG_OFDM0_XC_TX_IQ_IMBALANCE
+ i
, val8
);
2048 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS15_MCS12
, mcs_b
);
2049 for (i
= 0; i
< 3; i
++) {
2051 val8
= (mcsbase
[1] > 8) ? (mcsbase
[1] - 8) : 0;
2053 val8
= (mcsbase
[1] > 6) ? (mcsbase
[1] - 6) : 0;
2054 rtl8xxxu_write8(priv
, REG_OFDM0_XD_TX_IQ_IMBALANCE
+ i
, val8
);
2059 rtl8723b_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
2061 u32 val32
, ofdm
, mcs
;
2062 u8 cck
, ofdmbase
, mcsbase
;
2066 group
= rtl8723b_channel_to_group(channel
);
2068 cck
= priv
->cck_tx_power_index_B
[group
];
2069 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2070 val32
&= 0xffff00ff;
2071 val32
|= (cck
<< 8);
2072 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2074 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2076 val32
|= ((cck
<< 8) | (cck
<< 16) | (cck
<< 24));
2077 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2079 ofdmbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2080 ofdmbase
+= priv
->ofdm_tx_power_diff
[tx_idx
].b
;
2081 ofdm
= ofdmbase
| ofdmbase
<< 8 | ofdmbase
<< 16 | ofdmbase
<< 24;
2083 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm
);
2084 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm
);
2086 mcsbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2088 mcsbase
+= priv
->ht40_tx_power_diff
[tx_idx
++].b
;
2090 mcsbase
+= priv
->ht20_tx_power_diff
[tx_idx
++].b
;
2091 mcs
= mcsbase
| mcsbase
<< 8 | mcsbase
<< 16 | mcsbase
<< 24;
2093 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs
);
2094 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs
);
2097 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv
*priv
,
2098 enum nl80211_iftype linktype
)
2102 val8
= rtl8xxxu_read8(priv
, REG_MSR
);
2103 val8
&= ~MSR_LINKTYPE_MASK
;
2106 case NL80211_IFTYPE_UNSPECIFIED
:
2107 val8
|= MSR_LINKTYPE_NONE
;
2109 case NL80211_IFTYPE_ADHOC
:
2110 val8
|= MSR_LINKTYPE_ADHOC
;
2112 case NL80211_IFTYPE_STATION
:
2113 val8
|= MSR_LINKTYPE_STATION
;
2115 case NL80211_IFTYPE_AP
:
2116 val8
|= MSR_LINKTYPE_AP
;
2122 rtl8xxxu_write8(priv
, REG_MSR
, val8
);
2128 rtl8xxxu_set_retry(struct rtl8xxxu_priv
*priv
, u16 short_retry
, u16 long_retry
)
2132 val16
= ((short_retry
<< RETRY_LIMIT_SHORT_SHIFT
) &
2133 RETRY_LIMIT_SHORT_MASK
) |
2134 ((long_retry
<< RETRY_LIMIT_LONG_SHIFT
) &
2135 RETRY_LIMIT_LONG_MASK
);
2137 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
2141 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv
*priv
, u16 cck
, u16 ofdm
)
2145 val16
= ((cck
<< SPEC_SIFS_CCK_SHIFT
) & SPEC_SIFS_CCK_MASK
) |
2146 ((ofdm
<< SPEC_SIFS_OFDM_SHIFT
) & SPEC_SIFS_OFDM_MASK
);
2148 rtl8xxxu_write16(priv
, REG_SPEC_SIFS
, val16
);
2151 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv
*priv
)
2153 struct device
*dev
= &priv
->udev
->dev
;
2156 switch (priv
->chip_cut
) {
2177 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2178 priv
->chip_name
, cut
, priv
->chip_vendor
, priv
->tx_paths
,
2179 priv
->rx_paths
, priv
->ep_tx_count
, priv
->has_wifi
,
2180 priv
->has_bluetooth
, priv
->has_gps
, priv
->hi_pa
);
2182 dev_info(dev
, "RTL%s MAC: %pM\n", priv
->chip_name
, priv
->mac_addr
);
2185 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv
*priv
)
2187 struct device
*dev
= &priv
->udev
->dev
;
2191 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
2192 priv
->chip_cut
= (val32
& SYS_CFG_CHIP_VERSION_MASK
) >>
2193 SYS_CFG_CHIP_VERSION_SHIFT
;
2194 if (val32
& SYS_CFG_TRP_VAUX_EN
) {
2195 dev_info(dev
, "Unsupported test chip\n");
2199 if (val32
& SYS_CFG_BT_FUNC
) {
2200 if (priv
->chip_cut
>= 3) {
2201 sprintf(priv
->chip_name
, "8723BU");
2202 priv
->rtlchip
= 0x8723b;
2204 sprintf(priv
->chip_name
, "8723AU");
2205 priv
->usb_interrupts
= 1;
2206 priv
->rtlchip
= 0x8723a;
2213 val32
= rtl8xxxu_read32(priv
, REG_MULTI_FUNC_CTRL
);
2214 if (val32
& MULTI_WIFI_FUNC_EN
)
2216 if (val32
& MULTI_BT_FUNC_EN
)
2217 priv
->has_bluetooth
= 1;
2218 if (val32
& MULTI_GPS_FUNC_EN
)
2220 priv
->is_multi_func
= 1;
2221 } else if (val32
& SYS_CFG_TYPE_ID
) {
2222 bonding
= rtl8xxxu_read32(priv
, REG_HPON_FSM
);
2223 bonding
&= HPON_FSM_BONDING_MASK
;
2224 if (priv
->chip_cut
>= 3) {
2225 if (bonding
== HPON_FSM_BONDING_1T2R
) {
2226 sprintf(priv
->chip_name
, "8191EU");
2230 priv
->rtlchip
= 0x8191e;
2232 sprintf(priv
->chip_name
, "8192EU");
2236 priv
->rtlchip
= 0x8192e;
2238 } else if (bonding
== HPON_FSM_BONDING_1T2R
) {
2239 sprintf(priv
->chip_name
, "8191CU");
2243 priv
->usb_interrupts
= 1;
2244 priv
->rtlchip
= 0x8191c;
2246 sprintf(priv
->chip_name
, "8192CU");
2250 priv
->usb_interrupts
= 1;
2251 priv
->rtlchip
= 0x8192c;
2255 sprintf(priv
->chip_name
, "8188CU");
2259 priv
->rtlchip
= 0x8188c;
2260 priv
->usb_interrupts
= 1;
2264 switch (priv
->rtlchip
) {
2268 switch (val32
& SYS_CFG_VENDOR_EXT_MASK
) {
2269 case SYS_CFG_VENDOR_ID_TSMC
:
2270 sprintf(priv
->chip_vendor
, "TSMC");
2272 case SYS_CFG_VENDOR_ID_SMIC
:
2273 sprintf(priv
->chip_vendor
, "SMIC");
2274 priv
->vendor_smic
= 1;
2276 case SYS_CFG_VENDOR_ID_UMC
:
2277 sprintf(priv
->chip_vendor
, "UMC");
2278 priv
->vendor_umc
= 1;
2281 sprintf(priv
->chip_vendor
, "unknown");
2285 if (val32
& SYS_CFG_VENDOR_ID
) {
2286 sprintf(priv
->chip_vendor
, "UMC");
2287 priv
->vendor_umc
= 1;
2289 sprintf(priv
->chip_vendor
, "TSMC");
2293 val32
= rtl8xxxu_read32(priv
, REG_GPIO_OUTSTS
);
2294 priv
->rom_rev
= (val32
& GPIO_RF_RL_ID
) >> 28;
2296 val16
= rtl8xxxu_read16(priv
, REG_NORMAL_SIE_EP_TX
);
2297 if (val16
& NORMAL_SIE_EP_TX_HIGH_MASK
) {
2298 priv
->ep_tx_high_queue
= 1;
2299 priv
->ep_tx_count
++;
2302 if (val16
& NORMAL_SIE_EP_TX_NORMAL_MASK
) {
2303 priv
->ep_tx_normal_queue
= 1;
2304 priv
->ep_tx_count
++;
2307 if (val16
& NORMAL_SIE_EP_TX_LOW_MASK
) {
2308 priv
->ep_tx_low_queue
= 1;
2309 priv
->ep_tx_count
++;
2313 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2315 if (!priv
->ep_tx_count
) {
2316 switch (priv
->nr_out_eps
) {
2319 priv
->ep_tx_low_queue
= 1;
2320 priv
->ep_tx_count
++;
2322 priv
->ep_tx_normal_queue
= 1;
2323 priv
->ep_tx_count
++;
2325 priv
->ep_tx_high_queue
= 1;
2326 priv
->ep_tx_count
++;
2329 dev_info(dev
, "Unsupported USB TX end-points\n");
2337 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv
*priv
)
2339 struct rtl8723au_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723
;
2341 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2344 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2346 memcpy(priv
->cck_tx_power_index_A
,
2347 efuse
->cck_tx_power_index_A
,
2348 sizeof(efuse
->cck_tx_power_index_A
));
2349 memcpy(priv
->cck_tx_power_index_B
,
2350 efuse
->cck_tx_power_index_B
,
2351 sizeof(efuse
->cck_tx_power_index_B
));
2353 memcpy(priv
->ht40_1s_tx_power_index_A
,
2354 efuse
->ht40_1s_tx_power_index_A
,
2355 sizeof(efuse
->ht40_1s_tx_power_index_A
));
2356 memcpy(priv
->ht40_1s_tx_power_index_B
,
2357 efuse
->ht40_1s_tx_power_index_B
,
2358 sizeof(efuse
->ht40_1s_tx_power_index_B
));
2360 memcpy(priv
->ht20_tx_power_index_diff
,
2361 efuse
->ht20_tx_power_index_diff
,
2362 sizeof(efuse
->ht20_tx_power_index_diff
));
2363 memcpy(priv
->ofdm_tx_power_index_diff
,
2364 efuse
->ofdm_tx_power_index_diff
,
2365 sizeof(efuse
->ofdm_tx_power_index_diff
));
2367 memcpy(priv
->ht40_max_power_offset
,
2368 efuse
->ht40_max_power_offset
,
2369 sizeof(efuse
->ht40_max_power_offset
));
2370 memcpy(priv
->ht20_max_power_offset
,
2371 efuse
->ht20_max_power_offset
,
2372 sizeof(efuse
->ht20_max_power_offset
));
2374 if (priv
->efuse_wifi
.efuse8723
.version
>= 0x01) {
2375 priv
->has_xtalk
= 1;
2376 priv
->xtalk
= priv
->efuse_wifi
.efuse8723
.xtal_k
& 0x3f;
2378 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
2379 efuse
->vendor_name
);
2380 dev_info(&priv
->udev
->dev
, "Product: %.41s\n",
2381 efuse
->device_name
);
2385 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2387 struct rtl8723bu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723bu
;
2390 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2393 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2395 memcpy(priv
->cck_tx_power_index_A
, efuse
->tx_power_index_A
.cck_base
,
2396 sizeof(efuse
->tx_power_index_A
.cck_base
));
2397 memcpy(priv
->cck_tx_power_index_B
, efuse
->tx_power_index_B
.cck_base
,
2398 sizeof(efuse
->tx_power_index_B
.cck_base
));
2400 memcpy(priv
->ht40_1s_tx_power_index_A
,
2401 efuse
->tx_power_index_A
.ht40_base
,
2402 sizeof(efuse
->tx_power_index_A
.ht40_base
));
2403 memcpy(priv
->ht40_1s_tx_power_index_B
,
2404 efuse
->tx_power_index_B
.ht40_base
,
2405 sizeof(efuse
->tx_power_index_B
.ht40_base
));
2407 priv
->ofdm_tx_power_diff
[0].a
=
2408 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.a
;
2409 priv
->ofdm_tx_power_diff
[0].b
=
2410 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.a
;
2412 priv
->ht20_tx_power_diff
[0].a
=
2413 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.b
;
2414 priv
->ht20_tx_power_diff
[0].b
=
2415 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.b
;
2417 priv
->ht40_tx_power_diff
[0].a
= 0;
2418 priv
->ht40_tx_power_diff
[0].b
= 0;
2420 for (i
= 1; i
< RTL8723B_TX_COUNT
; i
++) {
2421 priv
->ofdm_tx_power_diff
[i
].a
=
2422 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ofdm
;
2423 priv
->ofdm_tx_power_diff
[i
].b
=
2424 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ofdm
;
2426 priv
->ht20_tx_power_diff
[i
].a
=
2427 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht20
;
2428 priv
->ht20_tx_power_diff
[i
].b
=
2429 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht20
;
2431 priv
->ht40_tx_power_diff
[i
].a
=
2432 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht40
;
2433 priv
->ht40_tx_power_diff
[i
].b
=
2434 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht40
;
2437 priv
->has_xtalk
= 1;
2438 priv
->xtalk
= priv
->efuse_wifi
.efuse8723bu
.xtal_k
& 0x3f;
2440 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
2441 dev_info(&priv
->udev
->dev
, "Product: %.41s\n", efuse
->device_name
);
2443 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2445 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2447 dev_info(&priv
->udev
->dev
,
2448 "%s: dumping efuse (0x%02zx bytes):\n",
2449 __func__
, sizeof(struct rtl8723bu_efuse
));
2450 for (i
= 0; i
< sizeof(struct rtl8723bu_efuse
); i
+= 8) {
2451 dev_info(&priv
->udev
->dev
, "%02x: "
2452 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2453 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2454 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2455 raw
[i
+ 6], raw
[i
+ 7]);
2462 #ifdef CONFIG_RTL8XXXU_UNTESTED
2464 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2466 struct rtl8192cu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192
;
2469 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2472 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2474 memcpy(priv
->cck_tx_power_index_A
,
2475 efuse
->cck_tx_power_index_A
,
2476 sizeof(efuse
->cck_tx_power_index_A
));
2477 memcpy(priv
->cck_tx_power_index_B
,
2478 efuse
->cck_tx_power_index_B
,
2479 sizeof(efuse
->cck_tx_power_index_B
));
2481 memcpy(priv
->ht40_1s_tx_power_index_A
,
2482 efuse
->ht40_1s_tx_power_index_A
,
2483 sizeof(efuse
->ht40_1s_tx_power_index_A
));
2484 memcpy(priv
->ht40_1s_tx_power_index_B
,
2485 efuse
->ht40_1s_tx_power_index_B
,
2486 sizeof(efuse
->ht40_1s_tx_power_index_B
));
2487 memcpy(priv
->ht40_2s_tx_power_index_diff
,
2488 efuse
->ht40_2s_tx_power_index_diff
,
2489 sizeof(efuse
->ht40_2s_tx_power_index_diff
));
2491 memcpy(priv
->ht20_tx_power_index_diff
,
2492 efuse
->ht20_tx_power_index_diff
,
2493 sizeof(efuse
->ht20_tx_power_index_diff
));
2494 memcpy(priv
->ofdm_tx_power_index_diff
,
2495 efuse
->ofdm_tx_power_index_diff
,
2496 sizeof(efuse
->ofdm_tx_power_index_diff
));
2498 memcpy(priv
->ht40_max_power_offset
,
2499 efuse
->ht40_max_power_offset
,
2500 sizeof(efuse
->ht40_max_power_offset
));
2501 memcpy(priv
->ht20_max_power_offset
,
2502 efuse
->ht20_max_power_offset
,
2503 sizeof(efuse
->ht20_max_power_offset
));
2505 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
2506 efuse
->vendor_name
);
2507 dev_info(&priv
->udev
->dev
, "Product: %.20s\n",
2508 efuse
->device_name
);
2510 if (efuse
->rf_regulatory
& 0x20) {
2511 sprintf(priv
->chip_name
, "8188RU");
2515 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2516 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2518 dev_info(&priv
->udev
->dev
,
2519 "%s: dumping efuse (0x%02zx bytes):\n",
2520 __func__
, sizeof(struct rtl8192cu_efuse
));
2521 for (i
= 0; i
< sizeof(struct rtl8192cu_efuse
); i
+= 8) {
2522 dev_info(&priv
->udev
->dev
, "%02x: "
2523 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2524 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2525 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2526 raw
[i
+ 6], raw
[i
+ 7]);
2534 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2536 struct rtl8192eu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192eu
;
2539 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2542 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2544 priv
->has_xtalk
= 1;
2545 priv
->xtalk
= priv
->efuse_wifi
.efuse8192eu
.xtal_k
& 0x3f;
2547 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
2548 dev_info(&priv
->udev
->dev
, "Product: %.11s\n", efuse
->device_name
);
2549 dev_info(&priv
->udev
->dev
, "Serial: %.11s\n", efuse
->serial
);
2551 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2552 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2554 dev_info(&priv
->udev
->dev
,
2555 "%s: dumping efuse (0x%02zx bytes):\n",
2556 __func__
, sizeof(struct rtl8192eu_efuse
));
2557 for (i
= 0; i
< sizeof(struct rtl8192eu_efuse
); i
+= 8) {
2558 dev_info(&priv
->udev
->dev
, "%02x: "
2559 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2560 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2561 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2562 raw
[i
+ 6], raw
[i
+ 7]);
2569 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv
*priv
, u16 offset
, u8
*data
)
2576 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 1, offset
& 0xff);
2577 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 2);
2579 val8
|= (offset
>> 8) & 0x03;
2580 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 2, val8
);
2582 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 3);
2583 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 3, val8
& 0x7f);
2585 /* Poll for data read */
2586 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2587 for (i
= 0; i
< RTL8XXXU_MAX_REG_POLL
; i
++) {
2588 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2589 if (val32
& BIT(31))
2593 if (i
== RTL8XXXU_MAX_REG_POLL
)
2597 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2599 *data
= val32
& 0xff;
2603 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv
*priv
)
2605 struct device
*dev
= &priv
->udev
->dev
;
2607 u8 val8
, word_mask
, header
, extheader
;
2608 u16 val16
, efuse_addr
, offset
;
2611 val16
= rtl8xxxu_read16(priv
, REG_9346CR
);
2612 if (val16
& EEPROM_ENABLE
)
2613 priv
->has_eeprom
= 1;
2614 if (val16
& EEPROM_BOOT
)
2615 priv
->boot_eeprom
= 1;
2617 if (priv
->is_multi_func
) {
2618 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_TEST
);
2619 val32
= (val32
& ~EFUSE_SELECT_MASK
) | EFUSE_WIFI_SELECT
;
2620 rtl8xxxu_write32(priv
, REG_EFUSE_TEST
, val32
);
2623 dev_dbg(dev
, "Booting from %s\n",
2624 priv
->boot_eeprom
? "EEPROM" : "EFUSE");
2626 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_ENABLE
);
2628 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2629 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
2630 if (!(val16
& SYS_ISO_PWC_EV12V
)) {
2631 val16
|= SYS_ISO_PWC_EV12V
;
2632 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
2634 /* Reset: 0x0000[28], default valid */
2635 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2636 if (!(val16
& SYS_FUNC_ELDR
)) {
2637 val16
|= SYS_FUNC_ELDR
;
2638 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
2642 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2644 val16
= rtl8xxxu_read16(priv
, REG_SYS_CLKR
);
2645 if (!(val16
& SYS_CLK_LOADER_ENABLE
) || !(val16
& SYS_CLK_ANA8M
)) {
2646 val16
|= (SYS_CLK_LOADER_ENABLE
| SYS_CLK_ANA8M
);
2647 rtl8xxxu_write16(priv
, REG_SYS_CLKR
, val16
);
2650 /* Default value is 0xff */
2651 memset(priv
->efuse_wifi
.raw
, 0xff, EFUSE_MAP_LEN
);
2654 while (efuse_addr
< EFUSE_REAL_CONTENT_LEN_8723A
) {
2657 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &header
);
2658 if (ret
|| header
== 0xff)
2661 if ((header
& 0x1f) == 0x0f) { /* extended header */
2662 offset
= (header
& 0xe0) >> 5;
2664 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++,
2668 /* All words disabled */
2669 if ((extheader
& 0x0f) == 0x0f)
2672 offset
|= ((extheader
& 0xf0) >> 1);
2673 word_mask
= extheader
& 0x0f;
2675 offset
= (header
>> 4) & 0x0f;
2676 word_mask
= header
& 0x0f;
2679 /* Get word enable value from PG header */
2681 /* We have 8 bits to indicate validity */
2682 map_addr
= offset
* 8;
2683 if (map_addr
>= EFUSE_MAP_LEN
) {
2684 dev_warn(dev
, "%s: Illegal map_addr (%04x), "
2686 __func__
, map_addr
);
2690 for (i
= 0; i
< EFUSE_MAX_WORD_UNIT
; i
++) {
2691 /* Check word enable condition in the section */
2692 if (word_mask
& BIT(i
)) {
2697 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
2700 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
2702 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
2705 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
2710 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_DISABLE
);
2715 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv
*priv
)
2720 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2722 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2723 sys_func
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2724 sys_func
&= ~SYS_FUNC_CPU_ENABLE
;
2725 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2726 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2728 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2729 sys_func
|= SYS_FUNC_CPU_ENABLE
;
2730 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2733 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv
*priv
)
2735 struct device
*dev
= &priv
->udev
->dev
;
2739 /* Poll checksum report */
2740 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
2741 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2742 if (val32
& MCU_FW_DL_CSUM_REPORT
)
2746 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
2747 dev_warn(dev
, "Firmware checksum poll timed out\n");
2752 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2753 val32
|= MCU_FW_DL_READY
;
2754 val32
&= ~MCU_WINT_INIT_READY
;
2755 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
2758 * Reset the 8051 in order for the firmware to start running,
2759 * otherwise it won't come up on the 8192eu
2761 rtl8xxxu_reset_8051(priv
);
2763 /* Wait for firmware to become ready */
2764 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
2765 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2766 if (val32
& MCU_WINT_INIT_READY
)
2772 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
2773 dev_warn(dev
, "Firmware failed to start\n");
2781 if (priv
->rtlchip
== 0x8723b)
2782 rtl8xxxu_write8(priv
, REG_HMTFR
, 0x0f);
2787 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv
*priv
)
2789 int pages
, remainder
, i
, ret
;
2795 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
+ 1);
2797 rtl8xxxu_write8(priv
, REG_SYS_FUNC
+ 1, val8
);
2800 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2801 val16
|= SYS_FUNC_CPU_ENABLE
;
2802 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
2804 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2805 if (val8
& MCU_FW_RAM_SEL
) {
2806 pr_info("do the RAM reset\n");
2807 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
2808 rtl8xxxu_reset_8051(priv
);
2811 /* MCU firmware download enable */
2812 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2813 val8
|= MCU_FW_DL_ENABLE
;
2814 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
2817 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2819 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
2821 /* Reset firmware download checksum */
2822 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2823 val8
|= MCU_FW_DL_CSUM_REPORT
;
2824 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
2826 pages
= priv
->fw_size
/ RTL_FW_PAGE_SIZE
;
2827 remainder
= priv
->fw_size
% RTL_FW_PAGE_SIZE
;
2829 fwptr
= priv
->fw_data
->data
;
2831 for (i
= 0; i
< pages
; i
++) {
2832 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
2834 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
2836 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
2837 fwptr
, RTL_FW_PAGE_SIZE
);
2838 if (ret
!= RTL_FW_PAGE_SIZE
) {
2843 fwptr
+= RTL_FW_PAGE_SIZE
;
2847 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
2849 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
2850 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
2852 if (ret
!= remainder
) {
2860 /* MCU firmware download disable */
2861 val16
= rtl8xxxu_read16(priv
, REG_MCU_FW_DL
);
2862 val16
&= ~MCU_FW_DL_ENABLE
;
2863 rtl8xxxu_write16(priv
, REG_MCU_FW_DL
, val16
);
2868 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv
*priv
, char *fw_name
)
2870 struct device
*dev
= &priv
->udev
->dev
;
2871 const struct firmware
*fw
;
2875 dev_info(dev
, "%s: Loading firmware %s\n", DRIVER_NAME
, fw_name
);
2876 if (request_firmware(&fw
, fw_name
, &priv
->udev
->dev
)) {
2877 dev_warn(dev
, "request_firmware(%s) failed\n", fw_name
);
2882 dev_warn(dev
, "Firmware data not available\n");
2887 priv
->fw_data
= kmemdup(fw
->data
, fw
->size
, GFP_KERNEL
);
2888 if (!priv
->fw_data
) {
2892 priv
->fw_size
= fw
->size
- sizeof(struct rtl8xxxu_firmware_header
);
2894 signature
= le16_to_cpu(priv
->fw_data
->signature
);
2895 switch (signature
& 0xfff0) {
2904 dev_warn(dev
, "%s: Invalid firmware signature: 0x%04x\n",
2905 __func__
, signature
);
2908 dev_info(dev
, "Firmware revision %i.%i (signature 0x%04x)\n",
2909 le16_to_cpu(priv
->fw_data
->major_version
),
2910 priv
->fw_data
->minor_version
, signature
);
2913 release_firmware(fw
);
2917 static int rtl8723au_load_firmware(struct rtl8xxxu_priv
*priv
)
2922 switch (priv
->chip_cut
) {
2924 fw_name
= "rtlwifi/rtl8723aufw_A.bin";
2927 if (priv
->enable_bluetooth
)
2928 fw_name
= "rtlwifi/rtl8723aufw_B.bin";
2930 fw_name
= "rtlwifi/rtl8723aufw_B_NoBT.bin";
2937 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2941 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv
*priv
)
2946 if (priv
->enable_bluetooth
)
2947 fw_name
= "rtlwifi/rtl8723bu_bt.bin";
2949 fw_name
= "rtlwifi/rtl8723bu_nic.bin";
2951 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2955 #ifdef CONFIG_RTL8XXXU_UNTESTED
2957 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv
*priv
)
2962 if (!priv
->vendor_umc
)
2963 fw_name
= "rtlwifi/rtl8192cufw_TMSC.bin";
2964 else if (priv
->chip_cut
|| priv
->rtlchip
== 0x8192c)
2965 fw_name
= "rtlwifi/rtl8192cufw_B.bin";
2967 fw_name
= "rtlwifi/rtl8192cufw_A.bin";
2969 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2976 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv
*priv
)
2981 fw_name
= "rtlwifi/rtl8192eu_nic.bin";
2983 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2988 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv
*priv
)
2993 /* Inform 8051 to perform reset */
2994 rtl8xxxu_write8(priv
, REG_HMTFR
+ 3, 0x20);
2996 for (i
= 100; i
> 0; i
--) {
2997 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2999 if (!(val16
& SYS_FUNC_CPU_ENABLE
)) {
3000 dev_dbg(&priv
->udev
->dev
,
3001 "%s: Firmware self reset success!\n", __func__
);
3008 /* Force firmware reset */
3009 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3010 val16
&= ~SYS_FUNC_CPU_ENABLE
;
3011 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3015 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv
*priv
)
3019 val32
= rtl8xxxu_read32(priv
, 0x64);
3020 val32
&= ~(BIT(20) | BIT(24));
3021 rtl8xxxu_write32(priv
, 0x64, val32
);
3023 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3025 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3027 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3029 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3031 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3033 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3035 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3037 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3039 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
3040 val32
|= (BIT(0) | BIT(1));
3041 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
3043 val32
= rtl8xxxu_read32(priv
, REG_RFE_CTRL_ANTA_SRC
);
3044 val32
&= 0xffffff00;
3046 rtl8xxxu_write32(priv
, REG_RFE_CTRL_ANTA_SRC
, val32
);
3048 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
3049 val32
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
3050 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
3054 rtl8xxxu_init_mac(struct rtl8xxxu_priv
*priv
, struct rtl8xxxu_reg8val
*array
)
3060 for (i
= 0; ; i
++) {
3064 if (reg
== 0xffff && val
== 0xff)
3067 ret
= rtl8xxxu_write8(priv
, reg
, val
);
3069 dev_warn(&priv
->udev
->dev
,
3070 "Failed to initialize MAC\n");
3075 if (priv
->rtlchip
!= 0x8723b)
3076 rtl8xxxu_write8(priv
, REG_MAX_AGGR_NUM
, 0x0a);
3081 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv
*priv
,
3082 struct rtl8xxxu_reg32val
*array
)
3088 for (i
= 0; ; i
++) {
3092 if (reg
== 0xffff && val
== 0xffffffff)
3095 ret
= rtl8xxxu_write32(priv
, reg
, val
);
3096 if (ret
!= sizeof(val
)) {
3097 dev_warn(&priv
->udev
->dev
,
3098 "Failed to initialize PHY\n");
3108 * Most of this is black magic retrieved from the old rtl8723au driver
3110 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv
*priv
)
3112 u8 val8
, ldoa15
, ldov12d
, lpldo
, ldohci12
;
3117 * Todo: The vendor driver maintains a table of PHY register
3118 * addresses, which is initialized here. Do we need this?
3121 if (priv
->rtlchip
== 0x8723b) {
3122 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3123 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
|
3125 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3127 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
3129 val8
= rtl8xxxu_read8(priv
, REG_AFE_PLL_CTRL
);
3131 val8
|= AFE_PLL_320_ENABLE
;
3132 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
, val8
);
3135 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
+ 1, 0xff);
3138 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3139 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
;
3140 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3143 if (priv
->rtlchip
!= 0x8723b) {
3144 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3145 val32
= rtl8xxxu_read32(priv
, REG_AFE_XTAL_CTRL
);
3146 val32
&= ~AFE_XTAL_RF_GATE
;
3147 if (priv
->has_bluetooth
)
3148 val32
&= ~AFE_XTAL_BT_GATE
;
3149 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, val32
);
3152 /* 6. 0x1f[7:0] = 0x07 */
3153 val8
= RF_ENABLE
| RF_RSTB
| RF_SDMRSTB
;
3154 rtl8xxxu_write8(priv
, REG_RF_CTRL
, val8
);
3157 rtl8xxxu_init_phy_regs(priv
, rtl8188ru_phy_1t_highpa_table
);
3158 else if (priv
->tx_paths
== 2)
3159 rtl8xxxu_init_phy_regs(priv
, rtl8192cu_phy_2t_init_table
);
3160 else if (priv
->rtlchip
== 0x8723b) {
3164 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, 0xe3);
3165 rtl8xxxu_write8(priv
, REG_AFE_XTAL_CTRL
+ 1, 0x80);
3166 rtl8xxxu_init_phy_regs(priv
, rtl8723b_phy_1t_init_table
);
3168 rtl8xxxu_init_phy_regs(priv
, rtl8723a_phy_1t_init_table
);
3171 if (priv
->rtlchip
== 0x8188c && priv
->hi_pa
&&
3172 priv
->vendor_umc
&& priv
->chip_cut
== 1)
3173 rtl8xxxu_write8(priv
, REG_OFDM0_AGC_PARM1
+ 2, 0x50);
3175 if (priv
->tx_paths
== 1 && priv
->rx_paths
== 2) {
3177 * For 1T2R boards, patch the registers.
3179 * It looks like 8191/2 1T2R boards use path B for TX
3181 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_TX_INFO
);
3182 val32
&= ~(BIT(0) | BIT(1));
3184 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, val32
);
3186 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_TX_INFO
);
3189 rtl8xxxu_write32(priv
, REG_FPGA1_TX_INFO
, val32
);
3191 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
3192 val32
&= 0xff000000;
3193 val32
|= 0x45000000;
3194 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
3196 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
3197 val32
&= ~(OFDM_RF_PATH_RX_MASK
| OFDM_RF_PATH_TX_MASK
);
3198 val32
|= (OFDM_RF_PATH_RX_A
| OFDM_RF_PATH_RX_B
|
3200 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
3202 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGC_PARM1
);
3203 val32
&= ~(BIT(4) | BIT(5));
3205 rtl8xxxu_write32(priv
, REG_OFDM0_AGC_PARM1
, val32
);
3207 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_RFON
);
3208 val32
&= ~(BIT(27) | BIT(26));
3210 rtl8xxxu_write32(priv
, REG_TX_CCK_RFON
, val32
);
3212 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_BBON
);
3213 val32
&= ~(BIT(27) | BIT(26));
3215 rtl8xxxu_write32(priv
, REG_TX_CCK_BBON
, val32
);
3217 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_RFON
);
3218 val32
&= ~(BIT(27) | BIT(26));
3220 rtl8xxxu_write32(priv
, REG_TX_OFDM_RFON
, val32
);
3222 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_BBON
);
3223 val32
&= ~(BIT(27) | BIT(26));
3225 rtl8xxxu_write32(priv
, REG_TX_OFDM_BBON
, val32
);
3227 val32
= rtl8xxxu_read32(priv
, REG_TX_TO_TX
);
3228 val32
&= ~(BIT(27) | BIT(26));
3230 rtl8xxxu_write32(priv
, REG_TX_TO_TX
, val32
);
3233 if (priv
->rtlchip
== 0x8723b)
3234 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_8723bu_table
);
3235 else if (priv
->hi_pa
)
3236 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_highpa_table
);
3238 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_standard_table
);
3240 if (priv
->has_xtalk
) {
3241 val32
= rtl8xxxu_read32(priv
, REG_MAC_PHY_CTRL
);
3244 val32
&= 0xff000fff;
3245 val32
|= ((val8
| (val8
<< 6)) << 12);
3247 rtl8xxxu_write32(priv
, REG_MAC_PHY_CTRL
, val32
);
3250 if (priv
->rtlchip
!= 0x8723bu
) {
3251 ldoa15
= LDOA15_ENABLE
| LDOA15_OBUF
;
3252 ldov12d
= LDOV12D_ENABLE
| BIT(2) | (2 << LDOV12D_VADJ_SHIFT
);
3255 val32
= (lpldo
<< 24) | (ldohci12
<< 16) |
3256 (ldov12d
<< 8) | ldoa15
;
3258 rtl8xxxu_write32(priv
, REG_LDOA15_CTRL
, val32
);
3264 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv
*priv
,
3265 struct rtl8xxxu_rfregval
*array
,
3266 enum rtl8xxxu_rfpath path
)
3272 for (i
= 0; ; i
++) {
3276 if (reg
== 0xff && val
== 0xffffffff)
3300 ret
= rtl8xxxu_write_rfreg(priv
, path
, reg
, val
);
3302 dev_warn(&priv
->udev
->dev
,
3303 "Failed to initialize RF\n");
3312 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv
*priv
,
3313 struct rtl8xxxu_rfregval
*table
,
3314 enum rtl8xxxu_rfpath path
)
3317 u16 val16
, rfsi_rfenv
;
3318 u16 reg_sw_ctrl
, reg_int_oe
, reg_hssi_parm2
;
3322 reg_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
;
3323 reg_int_oe
= REG_FPGA0_XA_RF_INT_OE
;
3324 reg_hssi_parm2
= REG_FPGA0_XA_HSSI_PARM2
;
3327 reg_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
;
3328 reg_int_oe
= REG_FPGA0_XB_RF_INT_OE
;
3329 reg_hssi_parm2
= REG_FPGA0_XB_HSSI_PARM2
;
3332 dev_err(&priv
->udev
->dev
, "%s:Unsupported RF path %c\n",
3333 __func__
, path
+ 'A');
3336 /* For path B, use XB */
3337 rfsi_rfenv
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
3338 rfsi_rfenv
&= FPGA0_RF_RFENV
;
3341 * These two we might be able to optimize into one
3343 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3344 val32
|= BIT(20); /* 0x10 << 16 */
3345 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3348 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3350 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3354 * These two we might be able to optimize into one
3356 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
3357 val32
&= ~FPGA0_HSSI_3WIRE_ADDR_LEN
;
3358 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
3361 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
3362 val32
&= ~FPGA0_HSSI_3WIRE_DATA_LEN
;
3363 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
3366 rtl8xxxu_init_rf_regs(priv
, table
, path
);
3368 /* For path B, use XB */
3369 val16
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
3370 val16
&= ~FPGA0_RF_RFENV
;
3371 val16
|= rfsi_rfenv
;
3372 rtl8xxxu_write16(priv
, reg_sw_ctrl
, val16
);
3377 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv
*priv
, u8 address
, u8 data
)
3383 value
= LLT_OP_WRITE
| address
<< 8 | data
;
3385 rtl8xxxu_write32(priv
, REG_LLT_INIT
, value
);
3388 value
= rtl8xxxu_read32(priv
, REG_LLT_INIT
);
3389 if ((value
& LLT_OP_MASK
) == LLT_OP_INACTIVE
) {
3393 } while (count
++ < 20);
3398 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
3403 for (i
= 0; i
< last_tx_page
; i
++) {
3404 ret
= rtl8xxxu_llt_write(priv
, i
, i
+ 1);
3409 ret
= rtl8xxxu_llt_write(priv
, last_tx_page
, 0xff);
3413 /* Mark remaining pages as a ring buffer */
3414 for (i
= last_tx_page
+ 1; i
< 0xff; i
++) {
3415 ret
= rtl8xxxu_llt_write(priv
, i
, (i
+ 1));
3420 /* Let last entry point to the start entry of ring buffer */
3421 ret
= rtl8xxxu_llt_write(priv
, 0xff, last_tx_page
+ 1);
3429 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
3435 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
3436 val32
|= AUTO_LLT_INIT_LLT
;
3437 rtl8xxxu_write32(priv
, REG_AUTO_LLT
, val32
);
3439 for (i
= 500; i
; i
--) {
3440 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
3441 if (!(val32
& AUTO_LLT_INIT_LLT
))
3448 dev_warn(&priv
->udev
->dev
, "LLT table init failed\n");
3454 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv
*priv
)
3457 u16 hiq
, mgq
, bkq
, beq
, viq
, voq
;
3458 int hip
, mgp
, bkp
, bep
, vip
, vop
;
3461 switch (priv
->ep_tx_count
) {
3463 if (priv
->ep_tx_high_queue
) {
3464 hi
= TRXDMA_QUEUE_HIGH
;
3465 } else if (priv
->ep_tx_low_queue
) {
3466 hi
= TRXDMA_QUEUE_LOW
;
3467 } else if (priv
->ep_tx_normal_queue
) {
3468 hi
= TRXDMA_QUEUE_NORMAL
;
3489 if (priv
->ep_tx_high_queue
&& priv
->ep_tx_low_queue
) {
3490 hi
= TRXDMA_QUEUE_HIGH
;
3491 lo
= TRXDMA_QUEUE_LOW
;
3492 } else if (priv
->ep_tx_normal_queue
&& priv
->ep_tx_low_queue
) {
3493 hi
= TRXDMA_QUEUE_NORMAL
;
3494 lo
= TRXDMA_QUEUE_LOW
;
3495 } else if (priv
->ep_tx_high_queue
&& priv
->ep_tx_normal_queue
) {
3496 hi
= TRXDMA_QUEUE_HIGH
;
3497 lo
= TRXDMA_QUEUE_NORMAL
;
3519 beq
= TRXDMA_QUEUE_LOW
;
3520 bkq
= TRXDMA_QUEUE_LOW
;
3521 viq
= TRXDMA_QUEUE_NORMAL
;
3522 voq
= TRXDMA_QUEUE_HIGH
;
3523 mgq
= TRXDMA_QUEUE_HIGH
;
3524 hiq
= TRXDMA_QUEUE_HIGH
;
3538 * None of the vendor drivers are configuring the beacon
3539 * queue here .... why?
3542 val16
= rtl8xxxu_read16(priv
, REG_TRXDMA_CTRL
);
3544 val16
|= (voq
<< TRXDMA_CTRL_VOQ_SHIFT
) |
3545 (viq
<< TRXDMA_CTRL_VIQ_SHIFT
) |
3546 (beq
<< TRXDMA_CTRL_BEQ_SHIFT
) |
3547 (bkq
<< TRXDMA_CTRL_BKQ_SHIFT
) |
3548 (mgq
<< TRXDMA_CTRL_MGQ_SHIFT
) |
3549 (hiq
<< TRXDMA_CTRL_HIQ_SHIFT
);
3550 rtl8xxxu_write16(priv
, REG_TRXDMA_CTRL
, val16
);
3552 priv
->pipe_out
[TXDESC_QUEUE_VO
] =
3553 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vop
]);
3554 priv
->pipe_out
[TXDESC_QUEUE_VI
] =
3555 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vip
]);
3556 priv
->pipe_out
[TXDESC_QUEUE_BE
] =
3557 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bep
]);
3558 priv
->pipe_out
[TXDESC_QUEUE_BK
] =
3559 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bkp
]);
3560 priv
->pipe_out
[TXDESC_QUEUE_BEACON
] =
3561 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
3562 priv
->pipe_out
[TXDESC_QUEUE_MGNT
] =
3563 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[mgp
]);
3564 priv
->pipe_out
[TXDESC_QUEUE_HIGH
] =
3565 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[hip
]);
3566 priv
->pipe_out
[TXDESC_QUEUE_CMD
] =
3567 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
3573 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv
*priv
,
3574 bool iqk_ok
, int result
[][8],
3575 int candidate
, bool tx_only
)
3577 u32 oldval
, x
, tx0_a
, reg
;
3584 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3585 oldval
= val32
>> 22;
3587 x
= result
[candidate
][0];
3588 if ((x
& 0x00000200) != 0)
3590 tx0_a
= (x
* oldval
) >> 8;
3592 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3595 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
3597 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3599 if ((x
* oldval
>> 7) & 0x1)
3601 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3603 y
= result
[candidate
][1];
3604 if ((y
& 0x00000200) != 0)
3606 tx0_c
= (y
* oldval
) >> 8;
3608 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XC_TX_AFE
);
3609 val32
&= ~0xf0000000;
3610 val32
|= (((tx0_c
& 0x3c0) >> 6) << 28);
3611 rtl8xxxu_write32(priv
, REG_OFDM0_XC_TX_AFE
, val32
);
3613 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3614 val32
&= ~0x003f0000;
3615 val32
|= ((tx0_c
& 0x3f) << 16);
3616 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
3618 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3620 if ((y
* oldval
>> 7) & 0x1)
3622 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3625 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
3629 reg
= result
[candidate
][2];
3631 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
3633 val32
|= (reg
& 0x3ff);
3634 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
3636 reg
= result
[candidate
][3] & 0x3F;
3638 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
3640 val32
|= ((reg
<< 10) & 0xfc00);
3641 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
3643 reg
= (result
[candidate
][3] >> 6) & 0xF;
3645 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
);
3646 val32
&= ~0xf0000000;
3647 val32
|= (reg
<< 28);
3648 rtl8xxxu_write32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
, val32
);
3651 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv
*priv
,
3652 bool iqk_ok
, int result
[][8],
3653 int candidate
, bool tx_only
)
3655 u32 oldval
, x
, tx1_a
, reg
;
3662 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3663 oldval
= val32
>> 22;
3665 x
= result
[candidate
][4];
3666 if ((x
& 0x00000200) != 0)
3668 tx1_a
= (x
* oldval
) >> 8;
3670 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3673 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
3675 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3677 if ((x
* oldval
>> 7) & 0x1)
3679 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3681 y
= result
[candidate
][5];
3682 if ((y
& 0x00000200) != 0)
3684 tx1_c
= (y
* oldval
) >> 8;
3686 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XD_TX_AFE
);
3687 val32
&= ~0xf0000000;
3688 val32
|= (((tx1_c
& 0x3c0) >> 6) << 28);
3689 rtl8xxxu_write32(priv
, REG_OFDM0_XD_TX_AFE
, val32
);
3691 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3692 val32
&= ~0x003f0000;
3693 val32
|= ((tx1_c
& 0x3f) << 16);
3694 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
3696 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3698 if ((y
* oldval
>> 7) & 0x1)
3700 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3703 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
3707 reg
= result
[candidate
][6];
3709 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
3711 val32
|= (reg
& 0x3ff);
3712 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
3714 reg
= result
[candidate
][7] & 0x3f;
3716 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
3718 val32
|= ((reg
<< 10) & 0xfc00);
3719 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
3721 reg
= (result
[candidate
][7] >> 6) & 0xf;
3723 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGCR_SSI_TABLE
);
3724 val32
&= ~0x0000f000;
3725 val32
|= (reg
<< 12);
3726 rtl8xxxu_write32(priv
, REG_OFDM0_AGCR_SSI_TABLE
, val32
);
3729 #define MAX_TOLERANCE 5
3731 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv
*priv
,
3732 int result
[][8], int c1
, int c2
)
3734 u32 i
, j
, diff
, simubitmap
, bound
= 0;
3735 int candidate
[2] = {-1, -1}; /* for path A and path B */
3738 if (priv
->tx_paths
> 1)
3745 for (i
= 0; i
< bound
; i
++) {
3746 diff
= (result
[c1
][i
] > result
[c2
][i
]) ?
3747 (result
[c1
][i
] - result
[c2
][i
]) :
3748 (result
[c2
][i
] - result
[c1
][i
]);
3749 if (diff
> MAX_TOLERANCE
) {
3750 if ((i
== 2 || i
== 6) && !simubitmap
) {
3751 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
3752 candidate
[(i
/ 4)] = c2
;
3753 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
3754 candidate
[(i
/ 4)] = c1
;
3756 simubitmap
= simubitmap
| (1 << i
);
3758 simubitmap
= simubitmap
| (1 << i
);
3763 if (simubitmap
== 0) {
3764 for (i
= 0; i
< (bound
/ 4); i
++) {
3765 if (candidate
[i
] >= 0) {
3766 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
3767 result
[3][j
] = result
[candidate
[i
]][j
];
3772 } else if (!(simubitmap
& 0x0f)) {
3774 for (i
= 0; i
< 4; i
++)
3775 result
[3][i
] = result
[c1
][i
];
3776 } else if (!(simubitmap
& 0xf0) && priv
->tx_paths
> 1) {
3778 for (i
= 4; i
< 8; i
++)
3779 result
[3][i
] = result
[c1
][i
];
3785 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv
*priv
,
3786 int result
[][8], int c1
, int c2
)
3788 u32 i
, j
, diff
, simubitmap
, bound
= 0;
3789 int candidate
[2] = {-1, -1}; /* for path A and path B */
3793 if (priv
->tx_paths
> 1)
3800 for (i
= 0; i
< bound
; i
++) {
3802 if ((result
[c1
][i
] & 0x00000200))
3803 tmp1
= result
[c1
][i
] | 0xfffffc00;
3805 tmp1
= result
[c1
][i
];
3807 if ((result
[c2
][i
]& 0x00000200))
3808 tmp2
= result
[c2
][i
] | 0xfffffc00;
3810 tmp2
= result
[c2
][i
];
3812 tmp1
= result
[c1
][i
];
3813 tmp2
= result
[c2
][i
];
3816 diff
= (tmp1
> tmp2
) ? (tmp1
- tmp2
) : (tmp2
- tmp1
);
3818 if (diff
> MAX_TOLERANCE
) {
3819 if ((i
== 2 || i
== 6) && !simubitmap
) {
3820 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
3821 candidate
[(i
/ 4)] = c2
;
3822 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
3823 candidate
[(i
/ 4)] = c1
;
3825 simubitmap
= simubitmap
| (1 << i
);
3827 simubitmap
= simubitmap
| (1 << i
);
3832 if (simubitmap
== 0) {
3833 for (i
= 0; i
< (bound
/ 4); i
++) {
3834 if (candidate
[i
] >= 0) {
3835 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
3836 result
[3][j
] = result
[candidate
[i
]][j
];
3842 if (!(simubitmap
& 0x03)) {
3844 for (i
= 0; i
< 2; i
++)
3845 result
[3][i
] = result
[c1
][i
];
3848 if (!(simubitmap
& 0x0c)) {
3850 for (i
= 2; i
< 4; i
++)
3851 result
[3][i
] = result
[c1
][i
];
3854 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
3856 for (i
= 4; i
< 6; i
++)
3857 result
[3][i
] = result
[c1
][i
];
3860 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
3862 for (i
= 6; i
< 8; i
++)
3863 result
[3][i
] = result
[c1
][i
];
3871 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv
*priv
, const u32
*reg
, u32
*backup
)
3875 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3876 backup
[i
] = rtl8xxxu_read8(priv
, reg
[i
]);
3878 backup
[i
] = rtl8xxxu_read32(priv
, reg
[i
]);
3881 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv
*priv
,
3882 const u32
*reg
, u32
*backup
)
3886 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3887 rtl8xxxu_write8(priv
, reg
[i
], backup
[i
]);
3889 rtl8xxxu_write32(priv
, reg
[i
], backup
[i
]);
3892 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3893 u32
*backup
, int count
)
3897 for (i
= 0; i
< count
; i
++)
3898 backup
[i
] = rtl8xxxu_read32(priv
, regs
[i
]);
3901 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3902 u32
*backup
, int count
)
3906 for (i
= 0; i
< count
; i
++)
3907 rtl8xxxu_write32(priv
, regs
[i
], backup
[i
]);
3911 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3917 if (priv
->tx_paths
== 1) {
3918 path_on
= priv
->fops
->adda_1t_path_on
;
3919 rtl8xxxu_write32(priv
, regs
[0], priv
->fops
->adda_1t_init
);
3921 path_on
= path_a_on
? priv
->fops
->adda_2t_path_on_a
:
3922 priv
->fops
->adda_2t_path_on_b
;
3924 rtl8xxxu_write32(priv
, regs
[0], path_on
);
3927 for (i
= 1 ; i
< RTL8XXXU_ADDA_REGS
; i
++)
3928 rtl8xxxu_write32(priv
, regs
[i
], path_on
);
3931 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv
*priv
,
3932 const u32
*regs
, u32
*backup
)
3936 rtl8xxxu_write8(priv
, regs
[i
], 0x3f);
3938 for (i
= 1 ; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3939 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(3)));
3941 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(5)));
3944 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
3946 u32 reg_eac
, reg_e94
, reg_e9c
, reg_ea4
, val32
;
3949 /* path-A IQK setting */
3950 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x10008c1f);
3951 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x10008c1f);
3952 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82140102);
3954 val32
= (priv
->rf_paths
> 1) ? 0x28160202 :
3955 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3957 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, val32
);
3959 /* path-B IQK setting */
3960 if (priv
->rf_paths
> 1) {
3961 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x10008c22);
3962 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x10008c22);
3963 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82140102);
3964 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28160202);
3967 /* LO calibration setting */
3968 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x001028d1);
3970 /* One shot, path A LOK & IQK */
3971 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
3972 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
3977 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
3978 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
3979 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
3980 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
3982 if (!(reg_eac
& BIT(28)) &&
3983 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
3984 ((reg_e9c
& 0x03ff0000) != 0x00420000))
3986 else /* If TX not OK, ignore RX */
3989 /* If TX is OK, check whether RX is OK */
3990 if (!(reg_eac
& BIT(27)) &&
3991 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
3992 ((reg_eac
& 0x03ff0000) != 0x00360000))
3995 dev_warn(&priv
->udev
->dev
, "%s: Path A RX IQK failed!\n",
4001 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
4003 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4006 /* One shot, path B LOK & IQK */
4007 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000002);
4008 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000000);
4013 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4014 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4015 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4016 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4017 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4019 if (!(reg_eac
& BIT(31)) &&
4020 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
4021 ((reg_ebc
& 0x03ff0000) != 0x00420000))
4026 if (!(reg_eac
& BIT(30)) &&
4027 (((reg_ec4
& 0x03ff0000) >> 16) != 0x132) &&
4028 (((reg_ecc
& 0x03ff0000) >> 16) != 0x36))
4031 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
4037 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4039 u32 reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4042 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4047 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4048 val32
&= 0x000000ff;
4049 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4052 * Enable path A PA in TX IQK mode
4054 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4056 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4057 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x20000);
4058 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0003f);
4059 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xc7f87);
4064 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4065 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4067 /* path-A IQK setting */
4068 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4069 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4070 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4071 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4073 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x821403ea);
4074 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4075 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4076 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4078 /* LO calibration setting */
4079 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x00462911);
4084 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4085 val32
&= 0x000000ff;
4086 val32
|= 0x80800000;
4087 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4090 * The vendor driver indicates the USB module is always using
4091 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4093 if (priv
->rf_paths
> 1)
4094 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4096 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4099 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4100 * No trace of this in the 8192eu or 8188eu vendor drivers.
4102 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4104 /* One shot, path A LOK & IQK */
4105 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4106 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4110 /* Restore Ant Path */
4111 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4114 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4120 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4121 val32
&= 0x000000ff;
4122 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4125 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4126 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4127 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4129 val32
= (reg_e9c
>> 16) & 0x3ff;
4131 val32
= 0x400 - val32
;
4133 if (!(reg_eac
& BIT(28)) &&
4134 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4135 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4136 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4137 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4140 else /* If TX not OK, ignore RX */
4147 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4149 u32 reg_ea4
, reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4152 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4157 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4158 val32
&= 0x000000ff;
4159 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4162 * Enable path A PA in TX IQK mode
4164 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4166 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4167 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4168 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4169 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
4174 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4175 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4177 /* path-A IQK setting */
4178 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4179 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4180 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4181 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4183 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82160ff0);
4184 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4185 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4186 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4188 /* LO calibration setting */
4189 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a911);
4194 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4195 val32
&= 0x000000ff;
4196 val32
|= 0x80800000;
4197 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4200 * The vendor driver indicates the USB module is always using
4201 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4203 if (priv
->rf_paths
> 1)
4204 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4206 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4209 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4210 * No trace of this in the 8192eu or 8188eu vendor drivers.
4212 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4214 /* One shot, path A LOK & IQK */
4215 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4216 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4220 /* Restore Ant Path */
4221 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4224 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4230 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4231 val32
&= 0x000000ff;
4232 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4235 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4236 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4237 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4239 val32
= (reg_e9c
>> 16) & 0x3ff;
4241 val32
= 0x400 - val32
;
4243 if (!(reg_eac
& BIT(28)) &&
4244 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4245 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4246 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4247 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4250 else /* If TX not OK, ignore RX */
4253 val32
= 0x80007c00 | (reg_e94
&0x3ff0000) |
4254 ((reg_e9c
& 0x3ff0000) >> 16);
4255 rtl8xxxu_write32(priv
, REG_TX_IQK
, val32
);
4258 * Modify RX IQK mode
4260 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4261 val32
&= 0x000000ff;
4262 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4263 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4265 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4266 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4267 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4268 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7d77);
4273 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0xf80);
4274 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_55
, 0x4021f);
4279 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4281 /* path-A IQK setting */
4282 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
4283 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x18008c1c);
4284 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4285 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4287 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82110000);
4288 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x2816001f);
4289 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4290 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4292 /* LO calibration setting */
4293 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a8d1);
4298 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4299 val32
&= 0x000000ff;
4300 val32
|= 0x80800000;
4301 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4303 if (priv
->rf_paths
> 1)
4304 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4306 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4311 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4313 /* One shot, path A LOK & IQK */
4314 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4315 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4319 /* Restore Ant Path */
4320 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4323 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4329 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4330 val32
&= 0x000000ff;
4331 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4334 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4335 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
4337 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x780);
4339 val32
= (reg_eac
>> 16) & 0x3ff;
4341 val32
= 0x400 - val32
;
4343 if (!(reg_eac
& BIT(27)) &&
4344 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
4345 ((reg_eac
& 0x03ff0000) != 0x00360000) &&
4346 ((reg_ea4
& 0x03ff0000) < 0x01100000) &&
4347 ((reg_ea4
& 0x03ff0000) > 0x00f00000) &&
4350 else /* If TX not OK, ignore RX */
4356 #ifdef RTL8723BU_PATH_B
4357 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
4359 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
, path_sel
;
4362 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4364 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4365 val32
&= 0x000000ff;
4366 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4368 /* One shot, path B LOK & IQK */
4369 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000002);
4370 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000000);
4375 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4376 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4377 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4378 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4379 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4381 if (!(reg_eac
& BIT(31)) &&
4382 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
4383 ((reg_ebc
& 0x03ff0000) != 0x00420000))
4388 if (!(reg_eac
& BIT(30)) &&
4389 (((reg_ec4
& 0x03ff0000) >> 16) != 0x132) &&
4390 (((reg_ecc
& 0x03ff0000) >> 16) != 0x36))
4393 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
4400 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
4401 int result
[][8], int t
)
4403 struct device
*dev
= &priv
->udev
->dev
;
4405 int path_a_ok
, path_b_ok
;
4407 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
4408 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
4409 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
4410 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
4411 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
4412 REG_TX_TO_TX
, REG_RX_CCK
,
4413 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
4414 REG_RX_TO_RX
, REG_STANDBY
,
4415 REG_SLEEP
, REG_PMPD_ANAEN
4417 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
4418 REG_TXPAUSE
, REG_BEACON_CTRL
,
4419 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
4421 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
4422 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
4423 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
4424 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
4425 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
4429 * Note: IQ calibration must be performed after loading
4430 * PHY_REG.txt , and radio_a, radio_b.txt
4434 /* Save ADDA parameters, turn Path A ADDA on */
4435 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
4436 RTL8XXXU_ADDA_REGS
);
4437 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4438 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
4439 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4442 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
4445 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM1
);
4446 if (val32
& FPGA0_HSSI_PARM1_PI
)
4447 priv
->pi_enabled
= 1;
4450 if (!priv
->pi_enabled
) {
4451 /* Switch BB to PI mode to do IQ Calibration. */
4452 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, 0x01000100);
4453 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, 0x01000100);
4456 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
4457 val32
&= ~FPGA_RF_MODE_CCK
;
4458 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
4460 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
4461 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
4462 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
4464 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
);
4465 val32
|= (FPGA0_RF_PAPE
| (FPGA0_RF_PAPE
<< FPGA0_RF_BD_CTRL_SHIFT
));
4466 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
4468 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_RF_INT_OE
);
4470 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, val32
);
4471 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XB_RF_INT_OE
);
4473 rtl8xxxu_write32(priv
, REG_FPGA0_XB_RF_INT_OE
, val32
);
4475 if (priv
->tx_paths
> 1) {
4476 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
4477 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
, 0x00010000);
4481 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
4484 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_A
, 0x00080000);
4486 if (priv
->tx_paths
> 1)
4487 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_B
, 0x00080000);
4489 /* IQ calibration setting */
4490 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
4491 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4492 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4494 for (i
= 0; i
< retry
; i
++) {
4495 path_a_ok
= rtl8xxxu_iqk_path_a(priv
);
4496 if (path_a_ok
== 0x03) {
4497 val32
= rtl8xxxu_read32(priv
,
4498 REG_TX_POWER_BEFORE_IQK_A
);
4499 result
[t
][0] = (val32
>> 16) & 0x3ff;
4500 val32
= rtl8xxxu_read32(priv
,
4501 REG_TX_POWER_AFTER_IQK_A
);
4502 result
[t
][1] = (val32
>> 16) & 0x3ff;
4503 val32
= rtl8xxxu_read32(priv
,
4504 REG_RX_POWER_BEFORE_IQK_A_2
);
4505 result
[t
][2] = (val32
>> 16) & 0x3ff;
4506 val32
= rtl8xxxu_read32(priv
,
4507 REG_RX_POWER_AFTER_IQK_A_2
);
4508 result
[t
][3] = (val32
>> 16) & 0x3ff;
4510 } else if (i
== (retry
- 1) && path_a_ok
== 0x01) {
4512 dev_dbg(dev
, "%s: Path A IQK Only Tx Success!!\n",
4515 val32
= rtl8xxxu_read32(priv
,
4516 REG_TX_POWER_BEFORE_IQK_A
);
4517 result
[t
][0] = (val32
>> 16) & 0x3ff;
4518 val32
= rtl8xxxu_read32(priv
,
4519 REG_TX_POWER_AFTER_IQK_A
);
4520 result
[t
][1] = (val32
>> 16) & 0x3ff;
4525 dev_dbg(dev
, "%s: Path A IQK failed!\n", __func__
);
4527 if (priv
->tx_paths
> 1) {
4529 * Path A into standby
4531 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x0);
4532 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
4533 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
4535 /* Turn Path B ADDA on */
4536 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
4538 for (i
= 0; i
< retry
; i
++) {
4539 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
4540 if (path_b_ok
== 0x03) {
4541 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4542 result
[t
][4] = (val32
>> 16) & 0x3ff;
4543 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4544 result
[t
][5] = (val32
>> 16) & 0x3ff;
4545 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4546 result
[t
][6] = (val32
>> 16) & 0x3ff;
4547 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4548 result
[t
][7] = (val32
>> 16) & 0x3ff;
4550 } else if (i
== (retry
- 1) && path_b_ok
== 0x01) {
4552 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4553 result
[t
][4] = (val32
>> 16) & 0x3ff;
4554 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4555 result
[t
][5] = (val32
>> 16) & 0x3ff;
4560 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
4563 /* Back to BB mode, load original value */
4564 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0);
4567 if (!priv
->pi_enabled
) {
4569 * Switch back BB to SI mode after finishing
4573 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, val32
);
4574 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, val32
);
4577 /* Reload ADDA power saving parameters */
4578 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
4579 RTL8XXXU_ADDA_REGS
);
4581 /* Reload MAC parameters */
4582 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4584 /* Reload BB parameters */
4585 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
4586 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4588 /* Restore RX initial gain */
4589 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00032ed3);
4591 if (priv
->tx_paths
> 1) {
4592 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
,
4596 /* Load 0xe30 IQC default value */
4597 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
4598 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
4602 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
4603 int result
[][8], int t
)
4605 struct device
*dev
= &priv
->udev
->dev
;
4607 int path_a_ok
/*, path_b_ok */;
4609 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
4610 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
4611 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
4612 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
4613 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
4614 REG_TX_TO_TX
, REG_RX_CCK
,
4615 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
4616 REG_RX_TO_RX
, REG_STANDBY
,
4617 REG_SLEEP
, REG_PMPD_ANAEN
4619 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
4620 REG_TXPAUSE
, REG_BEACON_CTRL
,
4621 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
4623 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
4624 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
4625 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
4626 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
4627 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
4629 u8 xa_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
) & 0xff;
4630 u8 xb_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
) & 0xff;
4633 * Note: IQ calibration must be performed after loading
4634 * PHY_REG.txt , and radio_a, radio_b.txt
4638 /* Save ADDA parameters, turn Path A ADDA on */
4639 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
4640 RTL8XXXU_ADDA_REGS
);
4641 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4642 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
4643 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4646 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
4649 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
4651 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
4652 val32
|= 0x0f000000;
4653 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
4655 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
4656 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
4657 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
4659 #ifdef RTL8723BU_PATH_B
4660 /* Set RF mode to standby Path B */
4661 if (priv
->tx_paths
> 1)
4662 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0x10000);
4667 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_A
, 0x0f600000);
4669 if (priv
->tx_paths
> 1)
4670 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_B
, 0x0f600000);
4674 * RX IQ calibration setting for 8723B D cut large current issue
4677 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4678 val32
&= 0x000000ff;
4679 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4681 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4683 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4685 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4686 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4687 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
4689 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
4691 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
4693 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_43
, 0x60fbd);
4695 for (i
= 0; i
< retry
; i
++) {
4696 path_a_ok
= rtl8723bu_iqk_path_a(priv
);
4697 if (path_a_ok
== 0x01) {
4698 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4699 val32
&= 0x000000ff;
4700 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4702 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4703 priv
->RFCalibrateInfo
.TxLOK
[RF_A
] =
4704 rtl8xxxu_read_rfreg(priv
, RF_A
,
4705 RF6052_REG_TXM_IDAC
);
4708 val32
= rtl8xxxu_read32(priv
,
4709 REG_TX_POWER_BEFORE_IQK_A
);
4710 result
[t
][0] = (val32
>> 16) & 0x3ff;
4711 val32
= rtl8xxxu_read32(priv
,
4712 REG_TX_POWER_AFTER_IQK_A
);
4713 result
[t
][1] = (val32
>> 16) & 0x3ff;
4720 dev_dbg(dev
, "%s: Path A TX IQK failed!\n", __func__
);
4722 for (i
= 0; i
< retry
; i
++) {
4723 path_a_ok
= rtl8723bu_rx_iqk_path_a(priv
);
4724 if (path_a_ok
== 0x03) {
4725 val32
= rtl8xxxu_read32(priv
,
4726 REG_RX_POWER_BEFORE_IQK_A_2
);
4727 result
[t
][2] = (val32
>> 16) & 0x3ff;
4728 val32
= rtl8xxxu_read32(priv
,
4729 REG_RX_POWER_AFTER_IQK_A_2
);
4730 result
[t
][3] = (val32
>> 16) & 0x3ff;
4737 dev_dbg(dev
, "%s: Path A RX IQK failed!\n", __func__
);
4739 if (priv
->tx_paths
> 1) {
4741 dev_warn(dev
, "%s: Path B not supported\n", __func__
);
4745 * Path A into standby
4747 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4748 val32
&= 0x000000ff;
4749 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4750 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x10000);
4752 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4753 val32
&= 0x000000ff;
4754 val32
|= 0x80800000;
4755 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4757 /* Turn Path B ADDA on */
4758 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
4760 for (i
= 0; i
< retry
; i
++) {
4761 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
4762 if (path_b_ok
== 0x03) {
4763 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4764 result
[t
][4] = (val32
>> 16) & 0x3ff;
4765 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4766 result
[t
][5] = (val32
>> 16) & 0x3ff;
4772 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
4774 for (i
= 0; i
< retry
; i
++) {
4775 path_b_ok
= rtl8723bu_rx_iqk_path_b(priv
);
4776 if (path_a_ok
== 0x03) {
4777 val32
= rtl8xxxu_read32(priv
,
4778 REG_RX_POWER_BEFORE_IQK_B_2
);
4779 result
[t
][6] = (val32
>> 16) & 0x3ff;
4780 val32
= rtl8xxxu_read32(priv
,
4781 REG_RX_POWER_AFTER_IQK_B_2
);
4782 result
[t
][7] = (val32
>> 16) & 0x3ff;
4788 dev_dbg(dev
, "%s: Path B RX IQK failed!\n", __func__
);
4792 /* Back to BB mode, load original value */
4793 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4794 val32
&= 0x000000ff;
4795 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4798 /* Reload ADDA power saving parameters */
4799 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
4800 RTL8XXXU_ADDA_REGS
);
4802 /* Reload MAC parameters */
4803 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4805 /* Reload BB parameters */
4806 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
4807 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4809 /* Restore RX initial gain */
4810 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
);
4811 val32
&= 0xffffff00;
4812 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| 0x50);
4813 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| xa_agc
);
4815 if (priv
->tx_paths
> 1) {
4816 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
);
4817 val32
&= 0xffffff00;
4818 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
4820 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
4824 /* Load 0xe30 IQC default value */
4825 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
4826 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
4830 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv
*priv
, u8 start
)
4834 if (priv
->fops
->mbox_ext_width
< 4)
4837 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
4838 h2c
.bt_wlan_calibration
.cmd
= H2C_8723B_BT_WLAN_CALIBRATION
;
4839 h2c
.bt_wlan_calibration
.data
= start
;
4841 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_wlan_calibration
));
4844 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
4846 struct device
*dev
= &priv
->udev
->dev
;
4847 int result
[4][8]; /* last is final result */
4849 bool path_a_ok
, path_b_ok
;
4850 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
4851 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4855 rtl8xxxu_prepare_calibrate(priv
, 1);
4857 memset(result
, 0, sizeof(result
));
4863 rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
4865 for (i
= 0; i
< 3; i
++) {
4866 rtl8xxxu_phy_iqcalibrate(priv
, result
, i
);
4869 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 1);
4877 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 2);
4883 simu
= rtl8xxxu_simularity_compare(priv
, result
, 1, 2);
4887 for (i
= 0; i
< 8; i
++)
4888 reg_tmp
+= result
[3][i
];
4898 for (i
= 0; i
< 4; i
++) {
4899 reg_e94
= result
[i
][0];
4900 reg_e9c
= result
[i
][1];
4901 reg_ea4
= result
[i
][2];
4902 reg_eac
= result
[i
][3];
4903 reg_eb4
= result
[i
][4];
4904 reg_ebc
= result
[i
][5];
4905 reg_ec4
= result
[i
][6];
4906 reg_ecc
= result
[i
][7];
4909 if (candidate
>= 0) {
4910 reg_e94
= result
[candidate
][0];
4911 priv
->rege94
= reg_e94
;
4912 reg_e9c
= result
[candidate
][1];
4913 priv
->rege9c
= reg_e9c
;
4914 reg_ea4
= result
[candidate
][2];
4915 reg_eac
= result
[candidate
][3];
4916 reg_eb4
= result
[candidate
][4];
4917 priv
->regeb4
= reg_eb4
;
4918 reg_ebc
= result
[candidate
][5];
4919 priv
->regebc
= reg_ebc
;
4920 reg_ec4
= result
[candidate
][6];
4921 reg_ecc
= result
[candidate
][7];
4922 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
4924 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4925 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
4926 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
4930 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
4931 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
4934 if (reg_e94
&& candidate
>= 0)
4935 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
4936 candidate
, (reg_ea4
== 0));
4938 if (priv
->tx_paths
> 1 && reg_eb4
)
4939 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
4940 candidate
, (reg_ec4
== 0));
4942 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
4943 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
4945 rtl8xxxu_prepare_calibrate(priv
, 0);
4948 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
4950 struct device
*dev
= &priv
->udev
->dev
;
4951 int result
[4][8]; /* last is final result */
4953 bool path_a_ok
, path_b_ok
;
4954 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
4955 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4956 u32 val32
, bt_control
;
4960 rtl8xxxu_prepare_calibrate(priv
, 1);
4962 memset(result
, 0, sizeof(result
));
4968 bt_control
= rtl8xxxu_read32(priv
, REG_BT_CONTROL_8723BU
);
4970 for (i
= 0; i
< 3; i
++) {
4971 rtl8723bu_phy_iqcalibrate(priv
, result
, i
);
4974 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 1);
4982 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 2);
4988 simu
= rtl8723bu_simularity_compare(priv
, result
, 1, 2);
4992 for (i
= 0; i
< 8; i
++)
4993 reg_tmp
+= result
[3][i
];
5003 for (i
= 0; i
< 4; i
++) {
5004 reg_e94
= result
[i
][0];
5005 reg_e9c
= result
[i
][1];
5006 reg_ea4
= result
[i
][2];
5007 reg_eac
= result
[i
][3];
5008 reg_eb4
= result
[i
][4];
5009 reg_ebc
= result
[i
][5];
5010 reg_ec4
= result
[i
][6];
5011 reg_ecc
= result
[i
][7];
5014 if (candidate
>= 0) {
5015 reg_e94
= result
[candidate
][0];
5016 priv
->rege94
= reg_e94
;
5017 reg_e9c
= result
[candidate
][1];
5018 priv
->rege9c
= reg_e9c
;
5019 reg_ea4
= result
[candidate
][2];
5020 reg_eac
= result
[candidate
][3];
5021 reg_eb4
= result
[candidate
][4];
5022 priv
->regeb4
= reg_eb4
;
5023 reg_ebc
= result
[candidate
][5];
5024 priv
->regebc
= reg_ebc
;
5025 reg_ec4
= result
[candidate
][6];
5026 reg_ecc
= result
[candidate
][7];
5027 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
5029 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5030 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
5031 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
5035 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
5036 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
5039 if (reg_e94
&& candidate
>= 0)
5040 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
5041 candidate
, (reg_ea4
== 0));
5043 if (priv
->tx_paths
> 1 && reg_eb4
)
5044 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
5045 candidate
, (reg_ec4
== 0));
5047 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
5048 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
5050 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, bt_control
);
5052 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
5054 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
5055 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x18000);
5056 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
5057 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xe6177);
5058 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
5060 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
5061 rtl8xxxu_write_rfreg(priv
, RF_A
, 0x43, 0x300bd);
5063 if (priv
->rf_paths
> 1) {
5064 dev_dbg(dev
, "%s: beware 2T not yet supported\n", __func__
);
5065 #ifdef RTL8723BU_PATH_B
5066 if (RF_Path
== 0x0) //S1
5067 ODM_SetIQCbyRFpath(pDM_Odm
, 0);
5069 ODM_SetIQCbyRFpath(pDM_Odm
, 1);
5072 rtl8xxxu_prepare_calibrate(priv
, 0);
5075 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv
*priv
)
5078 u32 rf_amode
, rf_bmode
= 0, lstf
;
5080 /* Check continuous TX and Packet TX */
5081 lstf
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
5083 if (lstf
& OFDM_LSTF_MASK
) {
5084 /* Disable all continuous TX */
5085 val32
= lstf
& ~OFDM_LSTF_MASK
;
5086 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
5088 /* Read original RF mode Path A */
5089 rf_amode
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_AC
);
5091 /* Set RF mode to standby Path A */
5092 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
,
5093 (rf_amode
& 0x8ffff) | 0x10000);
5096 if (priv
->tx_paths
> 1) {
5097 rf_bmode
= rtl8xxxu_read_rfreg(priv
, RF_B
,
5100 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
5101 (rf_bmode
& 0x8ffff) | 0x10000);
5104 /* Deal with Packet TX case */
5105 /* block all queues */
5106 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5109 /* Start LC calibration */
5110 if (priv
->fops
->has_s0s1
)
5111 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdfbe0);
5112 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
);
5114 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, val32
);
5118 if (priv
->fops
->has_s0s1
)
5119 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdffe0);
5121 /* Restore original parameters */
5122 if (lstf
& OFDM_LSTF_MASK
) {
5124 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, lstf
);
5125 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, rf_amode
);
5128 if (priv
->tx_paths
> 1)
5129 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
5131 } else /* Deal with Packet TX case */
5132 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
5135 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv
*priv
)
5142 for (i
= 0; i
< ETH_ALEN
; i
++)
5143 rtl8xxxu_write8(priv
, reg
+ i
, priv
->mac_addr
[i
]);
5148 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv
*priv
, const u8
*bssid
)
5153 dev_dbg(&priv
->udev
->dev
, "%s: (%pM)\n", __func__
, bssid
);
5157 for (i
= 0; i
< ETH_ALEN
; i
++)
5158 rtl8xxxu_write8(priv
, reg
+ i
, bssid
[i
]);
5164 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv
*priv
, u8 ampdu_factor
)
5166 u8 vals
[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5170 ampdu_factor
= 1 << (ampdu_factor
+ 2);
5171 if (ampdu_factor
> max_agg
)
5172 ampdu_factor
= max_agg
;
5174 for (i
= 0; i
< 4; i
++) {
5175 if ((vals
[i
] & 0xf0) > (ampdu_factor
<< 4))
5176 vals
[i
] = (vals
[i
] & 0x0f) | (ampdu_factor
<< 4);
5178 if ((vals
[i
] & 0x0f) > ampdu_factor
)
5179 vals
[i
] = (vals
[i
] & 0xf0) | ampdu_factor
;
5181 rtl8xxxu_write8(priv
, REG_AGGLEN_LMT
+ i
, vals
[i
]);
5185 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv
*priv
, u8 density
)
5189 val8
= rtl8xxxu_read8(priv
, REG_AMPDU_MIN_SPACE
);
5192 rtl8xxxu_write8(priv
, REG_AMPDU_MIN_SPACE
, val8
);
5195 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv
*priv
)
5200 /* Start of rtl8723AU_card_enable_flow */
5201 /* Act to Cardemu sequence*/
5203 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0);
5205 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5206 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
5207 val8
&= ~LEDCFG2_DPDT_SELECT
;
5208 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
5210 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5211 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5213 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5215 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5216 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5217 if ((val8
& BIT(1)) == 0)
5223 dev_warn(&priv
->udev
->dev
, "%s: Disabling MAC timed out\n",
5229 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5230 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5231 val8
|= SYS_ISO_ANALOG_IPS
;
5232 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5234 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5235 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5236 val8
&= ~LDOA15_ENABLE
;
5237 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5243 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv
*priv
)
5251 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0);
5253 /* Enable rising edge triggering interrupt */
5254 val16
= rtl8xxxu_read16(priv
, REG_GPIO_INTM
);
5255 val16
&= ~GPIO_INTM_EDGE_TRIG_IRQ
;
5256 rtl8xxxu_write16(priv
, REG_GPIO_INTM
, val16
);
5258 /* Release WLON reset 0x04[16]= 1*/
5259 val32
= rtl8xxxu_read32(priv
, REG_GPIO_INTM
);
5260 val32
|= APS_FSMCO_WLON_RESET
;
5261 rtl8xxxu_write32(priv
, REG_GPIO_INTM
, val32
);
5263 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5264 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5266 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5268 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5269 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5270 if ((val8
& BIT(1)) == 0)
5276 dev_warn(&priv
->udev
->dev
, "%s: Disabling MAC timed out\n",
5282 /* Enable BT control XTAL setting */
5283 val8
= rtl8xxxu_read8(priv
, REG_AFE_MISC
);
5284 val8
&= ~AFE_MISC_WL_XTAL_CTRL
;
5285 rtl8xxxu_write8(priv
, REG_AFE_MISC
, val8
);
5287 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5288 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5289 val8
|= SYS_ISO_ANALOG_IPS
;
5290 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5292 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5293 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5294 val8
&= ~LDOA15_ENABLE
;
5295 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5301 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv
*priv
)
5307 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5310 * Poll - wait for RX packet to complete
5312 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5313 val32
= rtl8xxxu_read32(priv
, 0x5f8);
5320 dev_warn(&priv
->udev
->dev
,
5321 "%s: RX poll timed out (0x05f8)\n", __func__
);
5326 /* Disable CCK and OFDM, clock gated */
5327 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
5328 val8
&= ~SYS_FUNC_BBRSTB
;
5329 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
5333 /* Reset baseband */
5334 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
5335 val8
&= ~SYS_FUNC_BB_GLB_RSTN
;
5336 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
5339 val8
= rtl8xxxu_read8(priv
, REG_CR
);
5340 val8
= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
;
5341 rtl8xxxu_write8(priv
, REG_CR
, val8
);
5344 val8
= rtl8xxxu_read8(priv
, REG_CR
+ 1);
5345 val8
&= ~BIT(1); /* CR_SECURITY_ENABLE */
5346 rtl8xxxu_write8(priv
, REG_CR
+ 1, val8
);
5348 /* Respond TX OK to scheduler */
5349 val8
= rtl8xxxu_read8(priv
, REG_DUAL_TSF_RST
);
5350 val8
|= DUAL_TSF_TX_OK
;
5351 rtl8xxxu_write8(priv
, REG_DUAL_TSF_RST
, val8
);
5357 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
5361 /* Clear suspend enable and power down enable*/
5362 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5363 val8
&= ~(BIT(3) | BIT(7));
5364 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5366 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5367 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
5369 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
5371 /* 0x04[12:11] = 11 enable WL suspend*/
5372 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5373 val8
&= ~(BIT(3) | BIT(4));
5374 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5377 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
5381 /* Clear suspend enable and power down enable*/
5382 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5383 val8
&= ~(BIT(3) | BIT(4));
5384 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5387 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv
*priv
)
5393 /* disable HWPDN 0x04[15]=0*/
5394 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5396 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5398 /* disable SW LPS 0x04[10]= 0 */
5399 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5401 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5403 /* disable WL suspend*/
5404 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5405 val8
&= ~(BIT(3) | BIT(4));
5406 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5408 /* wait till 0x04[17] = 1 power ready*/
5409 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5410 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5411 if (val32
& BIT(17))
5422 /* We should be able to optimize the following three entries into one */
5424 /* release WLON reset 0x04[16]= 1*/
5425 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5427 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5429 /* set, then poll until 0 */
5430 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5431 val32
|= APS_FSMCO_MAC_ENABLE
;
5432 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5434 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5435 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5436 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5452 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv
*priv
)
5458 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5459 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5460 val8
|= LDOA15_ENABLE
;
5461 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5463 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5464 val8
= rtl8xxxu_read8(priv
, 0x0067);
5466 rtl8xxxu_write8(priv
, 0x0067, val8
);
5470 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5471 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5472 val8
&= ~SYS_ISO_ANALOG_IPS
;
5473 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5475 /* disable SW LPS 0x04[10]= 0 */
5476 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5478 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5480 /* wait till 0x04[17] = 1 power ready*/
5481 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5482 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5483 if (val32
& BIT(17))
5494 /* We should be able to optimize the following three entries into one */
5496 /* release WLON reset 0x04[16]= 1*/
5497 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5499 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5501 /* disable HWPDN 0x04[15]= 0*/
5502 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5504 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5506 /* disable WL suspend*/
5507 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5508 val8
&= ~(BIT(3) | BIT(4));
5509 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5511 /* set, then poll until 0 */
5512 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5513 val32
|= APS_FSMCO_MAC_ENABLE
;
5514 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5516 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5517 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5518 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5530 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5532 * Note: Vendor driver actually clears this bit, despite the
5533 * documentation claims it's being set!
5535 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
5536 val8
|= LEDCFG2_DPDT_SELECT
;
5537 val8
&= ~LEDCFG2_DPDT_SELECT
;
5538 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
5544 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv
*priv
)
5550 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5551 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5552 val8
|= LDOA15_ENABLE
;
5553 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5555 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5556 val8
= rtl8xxxu_read8(priv
, 0x0067);
5558 rtl8xxxu_write8(priv
, 0x0067, val8
);
5562 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5563 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5564 val8
&= ~SYS_ISO_ANALOG_IPS
;
5565 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5567 /* Disable SW LPS 0x04[10]= 0 */
5568 val32
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
5569 val32
&= ~APS_FSMCO_SW_LPS
;
5570 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5572 /* Wait until 0x04[17] = 1 power ready */
5573 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5574 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5575 if (val32
& BIT(17))
5586 /* We should be able to optimize the following three entries into one */
5588 /* Release WLON reset 0x04[16]= 1*/
5589 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5590 val32
|= APS_FSMCO_WLON_RESET
;
5591 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5593 /* Disable HWPDN 0x04[15]= 0*/
5594 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5595 val32
&= ~APS_FSMCO_HW_POWERDOWN
;
5596 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5598 /* Disable WL suspend*/
5599 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5600 val32
&= ~(APS_FSMCO_HW_SUSPEND
| APS_FSMCO_PCIE
);
5601 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5603 /* Set, then poll until 0 */
5604 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5605 val32
|= APS_FSMCO_MAC_ENABLE
;
5606 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5608 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5609 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5610 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5622 /* Enable WL control XTAL setting */
5623 val8
= rtl8xxxu_read8(priv
, REG_AFE_MISC
);
5624 val8
|= AFE_MISC_WL_XTAL_CTRL
;
5625 rtl8xxxu_write8(priv
, REG_AFE_MISC
, val8
);
5627 /* Enable falling edge triggering interrupt */
5628 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 1);
5630 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 1, val8
);
5632 /* Enable GPIO9 interrupt mode */
5633 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
+ 1);
5635 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
+ 1, val8
);
5637 /* Enable GPIO9 input mode */
5638 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
);
5640 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
, val8
);
5642 /* Enable HSISR GPIO[C:0] interrupt */
5643 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
);
5645 rtl8xxxu_write8(priv
, REG_HSIMR
, val8
);
5647 /* Enable HSISR GPIO9 interrupt */
5648 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
+ 2);
5650 rtl8xxxu_write8(priv
, REG_HSIMR
+ 2, val8
);
5652 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
);
5653 val8
|= MULTI_WIFI_HW_ROF_EN
;
5654 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
, val8
);
5656 /* For GPIO9 internal pull high setting BIT(14) */
5657 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
+ 1);
5659 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
+ 1, val8
);
5665 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv
*priv
)
5669 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5670 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 3, 0x20);
5672 /* 0x04[12:11] = 01 enable WL suspend */
5673 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5676 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5678 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5680 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5682 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5683 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
5685 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
5690 static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv
*priv
)
5695 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5697 val32
= rtl8xxxu_read32(priv
, REG_RXPKT_NUM
);
5698 val32
|= RXPKT_NUM_RW_RELEASE_EN
;
5699 rtl8xxxu_write32(priv
, REG_RXPKT_NUM
, val32
);
5705 val32
= rtl8xxxu_read32(priv
, REG_RXPKT_NUM
);
5706 if (val32
& RXPKT_NUM_RXDMA_IDLE
) {
5712 rtl8xxxu_write16(priv
, REG_RQPN_NPQ
, 0);
5713 rtl8xxxu_write32(priv
, REG_RQPN
, 0x80000000);
5715 pr_info("%s: retry %i\n", __func__
, retry
);
5720 static int rtl8723au_power_on(struct rtl8xxxu_priv
*priv
)
5728 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5730 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
5732 rtl8723a_disabled_to_emu(priv
);
5734 ret
= rtl8723a_emu_to_active(priv
);
5739 * 0x0004[19] = 1, reset 8051
5741 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5743 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5746 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5747 * Set CR bit10 to enable 32k calibration.
5749 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5750 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5751 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5752 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5753 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5754 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5755 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5758 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
5759 val32
&= ~(BIT(28) | BIT(29) | BIT(30));
5760 val32
|= (0x06 << 28);
5761 rtl8xxxu_write32(priv
, REG_EFUSE_CTRL
, val32
);
5766 static int rtl8723bu_power_on(struct rtl8xxxu_priv
*priv
)
5773 rtl8723a_disabled_to_emu(priv
);
5775 ret
= rtl8723b_emu_to_active(priv
);
5780 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5781 * Set CR bit10 to enable 32k calibration.
5783 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5784 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5785 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5786 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5787 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5788 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5789 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5792 * BT coexist power on settings. This is identical for 1 and 2
5795 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
+ 3, 0x20);
5797 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
5798 val16
|= SYS_FUNC_BBRSTB
| SYS_FUNC_BB_GLB_RSTN
;
5799 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
5801 rtl8xxxu_write8(priv
, REG_BT_CONTROL_8723BU
+ 1, 0x18);
5802 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
5803 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
5804 /* Antenna inverse */
5805 rtl8xxxu_write8(priv
, 0xfe08, 0x01);
5807 val16
= rtl8xxxu_read16(priv
, REG_PWR_DATA
);
5808 val16
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
5809 rtl8xxxu_write16(priv
, REG_PWR_DATA
, val16
);
5811 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
5812 val32
|= LEDCFG0_DPDT_SELECT
;
5813 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
5815 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
5816 val8
&= ~PAD_CTRL1_SW_DPDT_SEL_DATA
;
5817 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
5822 #ifdef CONFIG_RTL8XXXU_UNTESTED
5824 static int rtl8192cu_power_on(struct rtl8xxxu_priv
*priv
)
5831 for (i
= 100; i
; i
--) {
5832 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
5833 if (val8
& APS_FSMCO_PFM_ALDN
)
5838 pr_info("%s: Poll failed\n", __func__
);
5843 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5845 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
5846 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, 0x2b);
5849 val8
= rtl8xxxu_read8(priv
, REG_LDOV12D_CTRL
);
5850 if (!(val8
& LDOV12D_ENABLE
)) {
5851 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__
, val8
);
5852 val8
|= LDOV12D_ENABLE
;
5853 rtl8xxxu_write8(priv
, REG_LDOV12D_CTRL
, val8
);
5857 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5858 val8
&= ~SYS_ISO_MD2PP
;
5859 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5865 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
5866 val16
|= APS_FSMCO_MAC_ENABLE
;
5867 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
5869 for (i
= 1000; i
; i
--) {
5870 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
5871 if (!(val16
& APS_FSMCO_MAC_ENABLE
))
5875 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__
);
5880 * Enable radio, GPIO, LED
5882 val16
= APS_FSMCO_HW_SUSPEND
| APS_FSMCO_ENABLE_POWERDOWN
|
5884 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
5887 * Release RF digital isolation
5889 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
5890 val16
&= ~SYS_ISO_DIOR
;
5891 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
5893 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
5894 val8
&= ~APSD_CTRL_OFF
;
5895 rtl8xxxu_write8(priv
, REG_APSD_CTRL
, val8
);
5896 for (i
= 200; i
; i
--) {
5897 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
5898 if (!(val8
& APSD_CTRL_OFF_STATUS
))
5903 pr_info("%s: APSD_CTRL poll failed\n", __func__
);
5908 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5910 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5911 val16
|= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5912 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
| CR_PROTOCOL_ENABLE
|
5913 CR_SCHEDULE_ENABLE
| CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
;
5914 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5917 * Workaround for 8188RU LNA power leakage problem.
5919 if (priv
->rtlchip
== 0x8188c && priv
->hi_pa
) {
5920 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
5922 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
5929 static int rtl8192eu_power_on(struct rtl8xxxu_priv
*priv
)
5937 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
5938 if (val32
& SYS_CFG_SPS_LDO_SEL
) {
5939 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0xc3);
5942 * Raise 1.2V voltage
5944 val32
= rtl8xxxu_read32(priv
, REG_8192E_LDOV12_CTRL
);
5945 val32
&= 0xff0fffff;
5946 val32
|= 0x00500000;
5947 rtl8xxxu_write32(priv
, REG_8192E_LDOV12_CTRL
, val32
);
5948 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0x83);
5951 rtl8192e_disabled_to_emu(priv
);
5953 ret
= rtl8192e_emu_to_active(priv
);
5957 rtl8xxxu_write16(priv
, REG_CR
, 0x0000);
5960 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5961 * Set CR bit10 to enable 32k calibration.
5963 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5964 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5965 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5966 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5967 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5968 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5969 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5975 static void rtl8xxxu_power_off(struct rtl8xxxu_priv
*priv
)
5982 * Workaround for 8188RU LNA power leakage problem.
5984 if (priv
->rtlchip
== 0x8188c && priv
->hi_pa
) {
5985 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
5987 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
5990 rtl8xxxu_flush_fifo(priv
);
5992 rtl8xxxu_active_to_lps(priv
);
5995 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0x00);
5997 /* Reset Firmware if running in RAM */
5998 if (rtl8xxxu_read8(priv
, REG_MCU_FW_DL
) & MCU_FW_RAM_SEL
)
5999 rtl8xxxu_firmware_self_reset(priv
);
6002 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
6003 val16
&= ~SYS_FUNC_CPU_ENABLE
;
6004 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
6006 /* Reset MCU ready status */
6007 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
6009 rtl8xxxu_active_to_emu(priv
);
6010 rtl8xxxu_emu_to_disabled(priv
);
6012 /* Reset MCU IO Wrapper */
6013 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
6015 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
6017 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
6019 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
6021 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
6022 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0e);
6025 static void rtl8723bu_power_off(struct rtl8xxxu_priv
*priv
)
6030 rtl8xxxu_flush_fifo(priv
);
6033 * Disable TX report timer
6035 val8
= rtl8xxxu_read8(priv
, REG_TX_REPORT_CTRL
);
6036 val8
&= ~TX_REPORT_CTRL_TIMER_ENABLE
;
6037 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
, val8
);
6039 rtl8xxxu_write16(priv
, REG_CR
, 0x0000);
6041 rtl8xxxu_active_to_lps(priv
);
6043 /* Reset Firmware if running in RAM */
6044 if (rtl8xxxu_read8(priv
, REG_MCU_FW_DL
) & MCU_FW_RAM_SEL
)
6045 rtl8xxxu_firmware_self_reset(priv
);
6048 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
6049 val16
&= ~SYS_FUNC_CPU_ENABLE
;
6050 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
6052 /* Reset MCU ready status */
6053 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
6055 rtl8723bu_active_to_emu(priv
);
6056 rtl8xxxu_emu_to_disabled(priv
);
6060 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv
*priv
,
6061 u8 arg1
, u8 arg2
, u8 arg3
, u8 arg4
, u8 arg5
)
6065 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6066 h2c
.b_type_dma
.cmd
= H2C_8723B_B_TYPE_TDMA
;
6067 h2c
.b_type_dma
.data1
= arg1
;
6068 h2c
.b_type_dma
.data2
= arg2
;
6069 h2c
.b_type_dma
.data3
= arg3
;
6070 h2c
.b_type_dma
.data4
= arg4
;
6071 h2c
.b_type_dma
.data5
= arg5
;
6072 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.b_type_dma
));
6076 static void rtl8723b_enable_rf(struct rtl8xxxu_priv
*priv
)
6083 * No indication anywhere as to what 0x0790 does. The 2 antenna
6084 * vendor code preserves bits 6-7 here.
6086 rtl8xxxu_write8(priv
, 0x0790, 0x05);
6088 * 0x0778 seems to be related to enabling the number of antennas
6089 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
6090 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
6092 rtl8xxxu_write8(priv
, 0x0778, 0x01);
6094 val8
= rtl8xxxu_read8(priv
, REG_GPIO_MUXCFG
);
6096 rtl8xxxu_write8(priv
, REG_GPIO_MUXCFG
, val8
);
6098 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_IQADJ_G1
, 0x780);
6100 rtl8723bu_write_btreg(priv
, 0x3c, 0x15); /* BT TRx Mask on */
6103 * Set BT grant to low
6105 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6106 h2c
.bt_grant
.cmd
= H2C_8723B_BT_GRANT
;
6107 h2c
.bt_grant
.data
= 0;
6108 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_grant
));
6111 * WLAN action by PTA
6113 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
6116 * BT select S0/S1 controlled by WiFi
6118 val8
= rtl8xxxu_read8(priv
, 0x0067);
6120 rtl8xxxu_write8(priv
, 0x0067, val8
);
6122 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
6123 val32
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
6124 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
6127 * Bits 6/7 are marked in/out ... but for what?
6129 rtl8xxxu_write8(priv
, 0x0974, 0xff);
6131 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
6132 val32
|= (BIT(0) | BIT(1));
6133 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
6135 rtl8xxxu_write8(priv
, REG_RFE_CTRL_ANTA_SRC
, 0x77);
6137 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
6140 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
6143 * Fix external switch Main->S1, Aux->S0
6145 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
6147 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
6149 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6150 h2c
.ant_sel_rsv
.cmd
= H2C_8723B_ANT_SEL_RSV
;
6151 h2c
.ant_sel_rsv
.ant_inverse
= 1;
6152 h2c
.ant_sel_rsv
.int_switch_type
= 0;
6153 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ant_sel_rsv
));
6156 * 0x280, 0x00, 0x200, 0x80 - not clear
6158 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
6161 * Software control, antenna at WiFi side
6164 rtl8723bu_set_ps_tdma(priv
, 0x08, 0x00, 0x00, 0x00, 0x00);
6167 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE1
, 0x55555555);
6168 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE2
, 0x55555555);
6169 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE3
, 0x00ffffff);
6170 rtl8xxxu_write8(priv
, REG_BT_COEX_TABLE4
, 0x03);
6172 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6173 h2c
.bt_info
.cmd
= H2C_8723B_BT_INFO
;
6174 h2c
.bt_info
.data
= BIT(0);
6175 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_info
));
6177 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6178 h2c
.ignore_wlan
.cmd
= H2C_8723B_BT_IGNORE_WLANACT
;
6179 h2c
.ignore_wlan
.data
= 0;
6180 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ignore_wlan
));
6183 static void rtl8723b_disable_rf(struct rtl8xxxu_priv
*priv
)
6187 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
6189 val32
= rtl8xxxu_read32(priv
, REG_RX_WAIT_CCA
);
6190 val32
&= ~(BIT(22) | BIT(23));
6191 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, val32
);
6194 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv
*priv
)
6200 * For now simply disable RX aggregation
6202 agg_ctrl
= rtl8xxxu_read8(priv
, REG_TRXDMA_CTRL
);
6203 agg_ctrl
&= ~TRXDMA_CTRL_RXDMA_AGG_EN
;
6205 agg_rx
= rtl8xxxu_read32(priv
, REG_RXDMA_AGG_PG_TH
);
6206 agg_rx
&= ~RXDMA_USB_AGG_ENABLE
;
6209 rtl8xxxu_write8(priv
, REG_TRXDMA_CTRL
, agg_ctrl
);
6210 rtl8xxxu_write32(priv
, REG_RXDMA_AGG_PG_TH
, agg_rx
);
6213 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv
*priv
)
6217 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6218 rtl8xxxu_write16(priv
, REG_NHM_TIMER_8723B
+ 2, 0x2710);
6219 rtl8xxxu_write16(priv
, REG_NHM_TH9_TH10_8723B
+ 2, 0xffff);
6220 rtl8xxxu_write32(priv
, REG_NHM_TH3_TO_TH0_8723B
, 0xffffff52);
6221 rtl8xxxu_write32(priv
, REG_NHM_TH7_TO_TH4_8723B
, 0xffffffff);
6223 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
6225 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
6227 val32
= rtl8xxxu_read32(priv
, REG_NHM_TH9_TH10_8723B
);
6228 val32
|= BIT(8) | BIT(9) | BIT(10);
6229 rtl8xxxu_write32(priv
, REG_NHM_TH9_TH10_8723B
, val32
);
6230 /* Max power amongst all RX antennas */
6231 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_FA_RSTC
);
6233 rtl8xxxu_write32(priv
, REG_OFDM0_FA_RSTC
, val32
);
6236 static int rtl8xxxu_init_device(struct ieee80211_hw
*hw
)
6238 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6239 struct device
*dev
= &priv
->udev
->dev
;
6240 struct rtl8xxxu_rfregval
*rftable
;
6247 /* Check if MAC is already powered on */
6248 val8
= rtl8xxxu_read8(priv
, REG_CR
);
6251 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6252 * initialized. First MAC returns 0xea, second MAC returns 0x00
6259 ret
= priv
->fops
->power_on(priv
);
6261 dev_warn(dev
, "%s: Failed power on\n", __func__
);
6265 dev_dbg(dev
, "%s: macpower %i\n", __func__
, macpower
);
6267 ret
= priv
->fops
->llt_init(priv
, TX_TOTAL_PAGE_NUM
);
6269 dev_warn(dev
, "%s: LLT table init failed\n", __func__
);
6274 * Presumably this is for 8188EU as well
6275 * Enable TX report and TX report timer
6277 if (priv
->rtlchip
== 0x8723bu
) {
6278 val8
= rtl8xxxu_read8(priv
, REG_TX_REPORT_CTRL
);
6279 val8
|= TX_REPORT_CTRL_TIMER_ENABLE
;
6280 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
, val8
);
6281 /* Set MAX RPT MACID */
6282 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
+ 1, 0x02);
6283 /* TX report Timer. Unit: 32us */
6284 rtl8xxxu_write16(priv
, REG_TX_REPORT_TIME
, 0xcdf0);
6287 val8
= rtl8xxxu_read8(priv
, 0xa3);
6289 rtl8xxxu_write8(priv
, 0xa3, val8
);
6293 ret
= rtl8xxxu_download_firmware(priv
);
6294 dev_dbg(dev
, "%s: download_fiwmare %i\n", __func__
, ret
);
6297 ret
= rtl8xxxu_start_firmware(priv
);
6298 dev_dbg(dev
, "%s: start_fiwmare %i\n", __func__
, ret
);
6302 /* Solve too many protocol error on USB bus */
6303 /* Can't do this for 8188/8192 UMC A cut parts */
6304 if (priv
->rtlchip
== 0x8723a ||
6305 ((priv
->rtlchip
== 0x8192c || priv
->rtlchip
== 0x8191c ||
6306 priv
->rtlchip
== 0x8188c) &&
6307 (priv
->chip_cut
|| !priv
->vendor_umc
))) {
6308 rtl8xxxu_write8(priv
, 0xfe40, 0xe6);
6309 rtl8xxxu_write8(priv
, 0xfe41, 0x94);
6310 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6312 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6313 rtl8xxxu_write8(priv
, 0xfe41, 0x19);
6314 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6316 rtl8xxxu_write8(priv
, 0xfe40, 0xe5);
6317 rtl8xxxu_write8(priv
, 0xfe41, 0x91);
6318 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6320 rtl8xxxu_write8(priv
, 0xfe40, 0xe2);
6321 rtl8xxxu_write8(priv
, 0xfe41, 0x81);
6322 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6325 if (priv
->rtlchip
== 0x8192e) {
6326 rtl8xxxu_write32(priv
, REG_HIMR0
, 0x00);
6327 rtl8xxxu_write32(priv
, REG_HIMR1
, 0x00);
6330 if (priv
->fops
->phy_init_antenna_selection
)
6331 priv
->fops
->phy_init_antenna_selection(priv
);
6333 if (priv
->rtlchip
== 0x8723b)
6334 ret
= rtl8xxxu_init_mac(priv
, rtl8723b_mac_init_table
);
6336 ret
= rtl8xxxu_init_mac(priv
, rtl8723a_mac_init_table
);
6338 dev_dbg(dev
, "%s: init_mac %i\n", __func__
, ret
);
6342 ret
= rtl8xxxu_init_phy_bb(priv
);
6343 dev_dbg(dev
, "%s: init_phy_bb %i\n", __func__
, ret
);
6347 switch(priv
->rtlchip
) {
6349 rftable
= rtl8723au_radioa_1t_init_table
;
6350 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6353 rftable
= rtl8723bu_radioa_1t_init_table
;
6354 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6358 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdfbe0);
6359 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, 0x8c01);
6361 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdffe0);
6365 rftable
= rtl8188ru_radioa_1t_highpa_table
;
6367 rftable
= rtl8192cu_radioa_1t_init_table
;
6368 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6371 rftable
= rtl8192cu_radioa_1t_init_table
;
6372 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6375 rftable
= rtl8192cu_radioa_2t_init_table
;
6376 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6379 rftable
= rtl8192cu_radiob_2t_init_table
;
6380 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_B
);
6390 * Chip specific quirks
6392 if (priv
->rtlchip
== 0x8723a) {
6393 /* Fix USB interface interference issue */
6394 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6395 rtl8xxxu_write8(priv
, 0xfe41, 0x8d);
6396 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6397 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, 0xfd0320);
6399 /* Reduce 80M spur */
6400 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, 0x0381808d);
6401 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
6402 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff82);
6403 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
6405 val32
= rtl8xxxu_read32(priv
, REG_TXDMA_OFFSET_CHK
);
6406 val32
|= TXDMA_OFFSET_DROP_DATA_EN
;
6407 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, val32
);
6411 if (priv
->ep_tx_normal_queue
)
6412 val8
= TX_PAGE_NUM_NORM_PQ
;
6416 rtl8xxxu_write8(priv
, REG_RQPN_NPQ
, val8
);
6418 val32
= (TX_PAGE_NUM_PUBQ
<< RQPN_NORM_PQ_SHIFT
) | RQPN_LOAD
;
6420 if (priv
->ep_tx_high_queue
)
6421 val32
|= (TX_PAGE_NUM_HI_PQ
<< RQPN_HI_PQ_SHIFT
);
6422 if (priv
->ep_tx_low_queue
)
6423 val32
|= (TX_PAGE_NUM_LO_PQ
<< RQPN_LO_PQ_SHIFT
);
6425 rtl8xxxu_write32(priv
, REG_RQPN
, val32
);
6428 * Set TX buffer boundary
6430 val8
= TX_TOTAL_PAGE_NUM
+ 1;
6432 if (priv
->rtlchip
== 0x8723b)
6435 rtl8xxxu_write8(priv
, REG_TXPKTBUF_BCNQ_BDNY
, val8
);
6436 rtl8xxxu_write8(priv
, REG_TXPKTBUF_MGQ_BDNY
, val8
);
6437 rtl8xxxu_write8(priv
, REG_TXPKTBUF_WMAC_LBK_BF_HD
, val8
);
6438 rtl8xxxu_write8(priv
, REG_TRXFF_BNDY
, val8
);
6439 rtl8xxxu_write8(priv
, REG_TDECTRL
+ 1, val8
);
6442 ret
= rtl8xxxu_init_queue_priority(priv
);
6443 dev_dbg(dev
, "%s: init_queue_priority %i\n", __func__
, ret
);
6447 /* RFSW Control - clear bit 14 ?? */
6448 if (priv
->rtlchip
!= 0x8723b)
6449 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, 0x00000003);
6451 val32
= FPGA0_RF_TRSW
| FPGA0_RF_TRSWB
| FPGA0_RF_ANTSW
|
6452 FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
|
6453 ((FPGA0_RF_ANTSW
| FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
) <<
6454 FPGA0_RF_BD_CTRL_SHIFT
);
6455 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
6456 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6457 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, 0x66F60210);
6459 priv
->rf_mode_ag
[0] = rtl8xxxu_read_rfreg(priv
, RF_A
,
6460 RF6052_REG_MODE_AG
);
6463 * Set RX page boundary
6465 if (priv
->rtlchip
== 0x8723b)
6466 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, 0x3f7f);
6468 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, 0x27ff);
6470 * Transfer page size is always 128
6472 if (priv
->rtlchip
== 0x8723b)
6473 val8
= (PBP_PAGE_SIZE_256
<< PBP_PAGE_SIZE_RX_SHIFT
) |
6474 (PBP_PAGE_SIZE_256
<< PBP_PAGE_SIZE_TX_SHIFT
);
6476 val8
= (PBP_PAGE_SIZE_128
<< PBP_PAGE_SIZE_RX_SHIFT
) |
6477 (PBP_PAGE_SIZE_128
<< PBP_PAGE_SIZE_TX_SHIFT
);
6478 rtl8xxxu_write8(priv
, REG_PBP
, val8
);
6481 * Unit in 8 bytes, not obvious what it is used for
6483 rtl8xxxu_write8(priv
, REG_RX_DRVINFO_SZ
, 4);
6486 * Enable all interrupts - not obvious USB needs to do this
6488 rtl8xxxu_write32(priv
, REG_HISR
, 0xffffffff);
6489 rtl8xxxu_write32(priv
, REG_HIMR
, 0xffffffff);
6491 rtl8xxxu_set_mac(priv
);
6492 rtl8xxxu_set_linktype(priv
, NL80211_IFTYPE_STATION
);
6495 * Configure initial WMAC settings
6497 val32
= RCR_ACCEPT_PHYS_MATCH
| RCR_ACCEPT_MCAST
| RCR_ACCEPT_BCAST
|
6498 RCR_ACCEPT_MGMT_FRAME
| RCR_HTC_LOC_CTRL
|
6499 RCR_APPEND_PHYSTAT
| RCR_APPEND_ICV
| RCR_APPEND_MIC
;
6500 rtl8xxxu_write32(priv
, REG_RCR
, val32
);
6503 * Accept all multicast
6505 rtl8xxxu_write32(priv
, REG_MAR
, 0xffffffff);
6506 rtl8xxxu_write32(priv
, REG_MAR
+ 4, 0xffffffff);
6509 * Init adaptive controls
6511 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6512 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
6513 val32
|= RESPONSE_RATE_RRSR_CCK_ONLY_1M
;
6514 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6516 /* CCK = 0x0a, OFDM = 0x10 */
6517 rtl8xxxu_set_spec_sifs(priv
, 0x10, 0x10);
6518 rtl8xxxu_set_retry(priv
, 0x30, 0x30);
6519 rtl8xxxu_set_spec_sifs(priv
, 0x0a, 0x10);
6524 rtl8xxxu_write16(priv
, REG_MAC_SPEC_SIFS
, 0x100a);
6527 rtl8xxxu_write16(priv
, REG_SIFS_CCK
, 0x100a);
6530 rtl8xxxu_write16(priv
, REG_SIFS_OFDM
, 0x100a);
6533 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, 0x005ea42b);
6534 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, 0x0000a44f);
6535 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, 0x005ea324);
6536 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, 0x002fa226);
6538 /* Set data auto rate fallback retry count */
6539 rtl8xxxu_write32(priv
, REG_DARFRC
, 0x00000000);
6540 rtl8xxxu_write32(priv
, REG_DARFRC
+ 4, 0x10080404);
6541 rtl8xxxu_write32(priv
, REG_RARFRC
, 0x04030201);
6542 rtl8xxxu_write32(priv
, REG_RARFRC
+ 4, 0x08070605);
6544 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
);
6545 val8
|= FWHW_TXQ_CTRL_AMPDU_RETRY
;
6546 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
, val8
);
6548 /* Set ACK timeout */
6549 rtl8xxxu_write8(priv
, REG_ACKTO
, 0x40);
6552 * Initialize beacon parameters
6554 val16
= BEACON_DISABLE_TSF_UPDATE
| (BEACON_DISABLE_TSF_UPDATE
<< 8);
6555 rtl8xxxu_write16(priv
, REG_BEACON_CTRL
, val16
);
6556 rtl8xxxu_write16(priv
, REG_TBTT_PROHIBIT
, 0x6404);
6557 rtl8xxxu_write8(priv
, REG_DRIVER_EARLY_INT
, DRIVER_EARLY_INT_TIME
);
6558 rtl8xxxu_write8(priv
, REG_BEACON_DMA_TIME
, BEACON_DMA_ATIME_INT_TIME
);
6559 rtl8xxxu_write16(priv
, REG_BEACON_TCFG
, 0x660F);
6562 * Initialize burst parameters
6564 if (priv
->rtlchip
== 0x8723b) {
6566 * For USB high speed set 512B packets
6568 val8
= rtl8xxxu_read8(priv
, REG_RXDMA_PRO_8723B
);
6569 val8
&= ~(BIT(4) | BIT(5));
6571 val8
|= BIT(1) | BIT(2) | BIT(3);
6572 rtl8xxxu_write8(priv
, REG_RXDMA_PRO_8723B
, val8
);
6575 * For USB high speed set 512B packets
6577 val8
= rtl8xxxu_read8(priv
, REG_HT_SINGLE_AMPDU_8723B
);
6579 rtl8xxxu_write8(priv
, REG_HT_SINGLE_AMPDU_8723B
, val8
);
6581 rtl8xxxu_write16(priv
, REG_MAX_AGGR_NUM
, 0x0c14);
6582 rtl8xxxu_write8(priv
, REG_AMPDU_MAX_TIME_8723B
, 0x5e);
6583 rtl8xxxu_write32(priv
, REG_AGGLEN_LMT
, 0xffffffff);
6584 rtl8xxxu_write8(priv
, REG_RX_PKT_LIMIT
, 0x18);
6585 rtl8xxxu_write8(priv
, REG_PIFS
, 0x00);
6586 rtl8xxxu_write8(priv
, REG_USTIME_TSF_8723B
, 0x50);
6587 rtl8xxxu_write8(priv
, REG_USTIME_EDCA
, 0x50);
6589 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
6590 val8
|= BIT(5) | BIT(6);
6591 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
6594 if (priv
->fops
->init_aggregation
)
6595 priv
->fops
->init_aggregation(priv
);
6598 * Enable CCK and OFDM block
6600 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
6601 val32
|= (FPGA_RF_MODE_CCK
| FPGA_RF_MODE_OFDM
);
6602 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
6605 * Invalidate all CAM entries - bit 30 is undocumented
6607 rtl8xxxu_write32(priv
, REG_CAM_CMD
, CAM_CMD_POLLING
| BIT(30));
6610 * Start out with default power levels for channel 6, 20MHz
6612 priv
->fops
->set_tx_power(priv
, 1, false);
6614 /* Let the 8051 take control of antenna setting */
6615 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
6616 val8
|= LEDCFG2_DPDT_SELECT
;
6617 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
6619 rtl8xxxu_write8(priv
, REG_HWSEQ_CTRL
, 0xff);
6621 /* Disable BAR - not sure if this has any effect on USB */
6622 rtl8xxxu_write32(priv
, REG_BAR_MODE_CTRL
, 0x0201ffff);
6624 rtl8xxxu_write16(priv
, REG_FAST_EDCA_CTRL
, 0);
6626 if (priv
->fops
->init_statistics
)
6627 priv
->fops
->init_statistics(priv
);
6629 rtl8723a_phy_lc_calibrate(priv
);
6631 priv
->fops
->phy_iq_calibrate(priv
);
6634 * This should enable thermal meter
6636 if (priv
->fops
->has_s0s1
)
6637 rtl8xxxu_write_rfreg(priv
,
6638 RF_A
, RF6052_REG_T_METER_8723B
, 0x37cf8);
6640 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_T_METER
, 0x60);
6642 /* Set NAV_UPPER to 30000us */
6643 val8
= ((30000 + NAV_UPPER_UNIT
- 1) / NAV_UPPER_UNIT
);
6644 rtl8xxxu_write8(priv
, REG_NAV_UPPER
, val8
);
6646 if (priv
->rtlchip
== 0x8723a) {
6648 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6649 * but we need to find root cause.
6650 * This is 8723au only.
6652 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
6653 if ((val32
& 0xff000000) != 0x83000000) {
6654 val32
|= FPGA_RF_MODE_CCK
;
6655 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
6659 val32
= rtl8xxxu_read32(priv
, REG_FWHW_TXQ_CTRL
);
6660 val32
|= FWHW_TXQ_CTRL_XMIT_MGMT_ACK
;
6661 /* ack for xmit mgmt frames. */
6662 rtl8xxxu_write32(priv
, REG_FWHW_TXQ_CTRL
, val32
);
6668 static void rtl8xxxu_disable_device(struct ieee80211_hw
*hw
)
6670 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6672 priv
->fops
->power_off(priv
);
6675 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv
*priv
,
6676 struct ieee80211_key_conf
*key
, const u8
*mac
)
6678 u32 cmd
, val32
, addr
, ctrl
;
6679 int j
, i
, tmp_debug
;
6681 tmp_debug
= rtl8xxxu_debug
;
6682 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_KEY
)
6683 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_REG_WRITE
;
6686 * This is a bit of a hack - the lower bits of the cipher
6687 * suite selector happens to match the cipher index in the CAM
6689 addr
= key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
6690 ctrl
= (key
->cipher
& 0x0f) << 2 | key
->keyidx
| CAM_WRITE_VALID
;
6692 for (j
= 5; j
>= 0; j
--) {
6695 val32
= ctrl
| (mac
[0] << 16) | (mac
[1] << 24);
6698 val32
= mac
[2] | (mac
[3] << 8) |
6699 (mac
[4] << 16) | (mac
[5] << 24);
6703 val32
= key
->key
[i
] | (key
->key
[i
+ 1] << 8) |
6704 key
->key
[i
+ 2] << 16 | key
->key
[i
+ 3] << 24;
6708 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, val32
);
6709 cmd
= CAM_CMD_POLLING
| CAM_CMD_WRITE
| (addr
+ j
);
6710 rtl8xxxu_write32(priv
, REG_CAM_CMD
, cmd
);
6714 rtl8xxxu_debug
= tmp_debug
;
6717 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw
*hw
,
6718 struct ieee80211_vif
*vif
, const u8
*mac
)
6720 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6723 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6724 val8
|= BEACON_DISABLE_TSF_UPDATE
;
6725 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6728 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw
*hw
,
6729 struct ieee80211_vif
*vif
)
6731 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6734 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6735 val8
&= ~BEACON_DISABLE_TSF_UPDATE
;
6736 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6739 static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv
*priv
,
6740 u32 ramask
, int sgi
)
6744 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6746 h2c
.ramask
.cmd
= H2C_SET_RATE_MASK
;
6747 h2c
.ramask
.mask_lo
= cpu_to_le16(ramask
& 0xffff);
6748 h2c
.ramask
.mask_hi
= cpu_to_le16(ramask
>> 16);
6750 h2c
.ramask
.arg
= 0x80;
6752 h2c
.ramask
.arg
|= 0x20;
6754 dev_dbg(&priv
->udev
->dev
, "%s: rate mask %08x, arg %02x, size %zi\n",
6755 __func__
, ramask
, h2c
.ramask
.arg
, sizeof(h2c
.ramask
));
6756 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ramask
));
6759 static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv
*priv
,
6760 u32 ramask
, int sgi
)
6765 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6767 h2c
.b_macid_cfg
.cmd
= H2C_8723B_MACID_CFG_RAID
;
6768 h2c
.b_macid_cfg
.ramask0
= ramask
& 0xff;
6769 h2c
.b_macid_cfg
.ramask1
= (ramask
>> 8) & 0xff;
6770 h2c
.b_macid_cfg
.ramask2
= (ramask
>> 16) & 0xff;
6771 h2c
.b_macid_cfg
.ramask3
= (ramask
>> 24) & 0xff;
6773 h2c
.ramask
.arg
= 0x80;
6774 h2c
.b_macid_cfg
.data1
= 0;
6776 h2c
.b_macid_cfg
.data1
|= BIT(7);
6778 h2c
.b_macid_cfg
.data2
= bw
;
6780 dev_dbg(&priv
->udev
->dev
, "%s: rate mask %08x, arg %02x, size %zi\n",
6781 __func__
, ramask
, h2c
.ramask
.arg
, sizeof(h2c
.b_macid_cfg
));
6782 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.b_macid_cfg
));
6785 static void rtl8723au_report_connect(struct rtl8xxxu_priv
*priv
,
6786 u8 macid
, bool connect
)
6790 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6792 h2c
.joinbss
.cmd
= H2C_JOIN_BSS_REPORT
;
6795 h2c
.joinbss
.data
= H2C_JOIN_BSS_CONNECT
;
6797 h2c
.joinbss
.data
= H2C_JOIN_BSS_DISCONNECT
;
6799 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.joinbss
));
6802 static void rtl8723bu_report_connect(struct rtl8xxxu_priv
*priv
,
6803 u8 macid
, bool connect
)
6807 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6809 h2c
.media_status_rpt
.cmd
= H2C_8723B_MEDIA_STATUS_RPT
;
6811 h2c
.media_status_rpt
.parm
|= BIT(0);
6813 h2c
.media_status_rpt
.parm
&= ~BIT(0);
6815 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.media_status_rpt
));
6818 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv
*priv
, u32 rate_cfg
)
6823 rate_cfg
&= RESPONSE_RATE_BITMAP_ALL
;
6825 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6826 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
6828 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6830 dev_dbg(&priv
->udev
->dev
, "%s: rates %08x\n", __func__
, rate_cfg
);
6833 rate_cfg
= (rate_cfg
>> 1);
6836 rtl8xxxu_write8(priv
, REG_INIRTS_RATE_SEL
, rate_idx
);
6840 rtl8xxxu_bss_info_changed(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
6841 struct ieee80211_bss_conf
*bss_conf
, u32 changed
)
6843 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6844 struct device
*dev
= &priv
->udev
->dev
;
6845 struct ieee80211_sta
*sta
;
6849 if (changed
& BSS_CHANGED_ASSOC
) {
6850 dev_dbg(dev
, "Changed ASSOC: %i!\n", bss_conf
->assoc
);
6852 rtl8xxxu_set_linktype(priv
, vif
->type
);
6854 if (bss_conf
->assoc
) {
6859 sta
= ieee80211_find_sta(vif
, bss_conf
->bssid
);
6861 dev_info(dev
, "%s: ASSOC no sta found\n",
6867 if (sta
->ht_cap
.ht_supported
)
6868 dev_info(dev
, "%s: HT supported\n", __func__
);
6869 if (sta
->vht_cap
.vht_supported
)
6870 dev_info(dev
, "%s: VHT supported\n", __func__
);
6872 /* TODO: Set bits 28-31 for rate adaptive id */
6873 ramask
= (sta
->supp_rates
[0] & 0xfff) |
6874 sta
->ht_cap
.mcs
.rx_mask
[0] << 12 |
6875 sta
->ht_cap
.mcs
.rx_mask
[1] << 20;
6876 if (sta
->ht_cap
.cap
&
6877 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))
6881 priv
->fops
->update_rate_mask(priv
, ramask
, sgi
);
6883 rtl8xxxu_write8(priv
, REG_BCN_MAX_ERR
, 0xff);
6885 rtl8723a_stop_tx_beacon(priv
);
6887 /* joinbss sequence */
6888 rtl8xxxu_write16(priv
, REG_BCN_PSR_RPT
,
6889 0xc000 | bss_conf
->aid
);
6891 priv
->fops
->report_connect(priv
, 0, true);
6893 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6894 val8
|= BEACON_DISABLE_TSF_UPDATE
;
6895 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6897 priv
->fops
->report_connect(priv
, 0, false);
6901 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
6902 dev_dbg(dev
, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6903 bss_conf
->use_short_preamble
);
6904 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6905 if (bss_conf
->use_short_preamble
)
6906 val32
|= RSR_ACK_SHORT_PREAMBLE
;
6908 val32
&= ~RSR_ACK_SHORT_PREAMBLE
;
6909 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6912 if (changed
& BSS_CHANGED_ERP_SLOT
) {
6913 dev_dbg(dev
, "Changed ERP_SLOT: short_slot_time %i\n",
6914 bss_conf
->use_short_slot
);
6916 if (bss_conf
->use_short_slot
)
6920 rtl8xxxu_write8(priv
, REG_SLOT
, val8
);
6923 if (changed
& BSS_CHANGED_BSSID
) {
6924 dev_dbg(dev
, "Changed BSSID!\n");
6925 rtl8xxxu_set_bssid(priv
, bss_conf
->bssid
);
6928 if (changed
& BSS_CHANGED_BASIC_RATES
) {
6929 dev_dbg(dev
, "Changed BASIC_RATES!\n");
6930 rtl8xxxu_set_basic_rates(priv
, bss_conf
->basic_rates
);
6936 static u32
rtl8xxxu_80211_to_rtl_queue(u32 queue
)
6941 case IEEE80211_AC_VO
:
6942 rtlqueue
= TXDESC_QUEUE_VO
;
6944 case IEEE80211_AC_VI
:
6945 rtlqueue
= TXDESC_QUEUE_VI
;
6947 case IEEE80211_AC_BE
:
6948 rtlqueue
= TXDESC_QUEUE_BE
;
6950 case IEEE80211_AC_BK
:
6951 rtlqueue
= TXDESC_QUEUE_BK
;
6954 rtlqueue
= TXDESC_QUEUE_BE
;
6960 static u32
rtl8xxxu_queue_select(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
6962 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
6965 if (ieee80211_is_mgmt(hdr
->frame_control
))
6966 queue
= TXDESC_QUEUE_MGNT
;
6968 queue
= rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb
));
6974 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
6975 * format. The descriptor checksum is still only calculated over the
6976 * initial 32 bytes of the descriptor!
6978 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8723au_tx_desc
*tx_desc
)
6980 __le16
*ptr
= (__le16
*)tx_desc
;
6985 * Clear csum field before calculation, as the csum field is
6986 * in the middle of the struct.
6988 tx_desc
->csum
= cpu_to_le16(0);
6990 for (i
= 0; i
< (sizeof(struct rtl8723au_tx_desc
) / sizeof(u16
)); i
++)
6991 csum
= csum
^ le16_to_cpu(ptr
[i
]);
6993 tx_desc
->csum
|= cpu_to_le16(csum
);
6996 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv
*priv
)
6998 struct rtl8xxxu_tx_urb
*tx_urb
, *tmp
;
6999 unsigned long flags
;
7001 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
7002 list_for_each_entry_safe(tx_urb
, tmp
, &priv
->tx_urb_free_list
, list
) {
7003 list_del(&tx_urb
->list
);
7004 priv
->tx_urb_free_count
--;
7005 usb_free_urb(&tx_urb
->urb
);
7007 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
7010 static struct rtl8xxxu_tx_urb
*
7011 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv
*priv
)
7013 struct rtl8xxxu_tx_urb
*tx_urb
;
7014 unsigned long flags
;
7016 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
7017 tx_urb
= list_first_entry_or_null(&priv
->tx_urb_free_list
,
7018 struct rtl8xxxu_tx_urb
, list
);
7020 list_del(&tx_urb
->list
);
7021 priv
->tx_urb_free_count
--;
7022 if (priv
->tx_urb_free_count
< RTL8XXXU_TX_URB_LOW_WATER
&&
7023 !priv
->tx_stopped
) {
7024 priv
->tx_stopped
= true;
7025 ieee80211_stop_queues(priv
->hw
);
7029 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
7034 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv
*priv
,
7035 struct rtl8xxxu_tx_urb
*tx_urb
)
7037 unsigned long flags
;
7039 INIT_LIST_HEAD(&tx_urb
->list
);
7041 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
7043 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
7044 priv
->tx_urb_free_count
++;
7045 if (priv
->tx_urb_free_count
> RTL8XXXU_TX_URB_HIGH_WATER
&&
7047 priv
->tx_stopped
= false;
7048 ieee80211_wake_queues(priv
->hw
);
7051 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
7054 static void rtl8xxxu_tx_complete(struct urb
*urb
)
7056 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
7057 struct ieee80211_tx_info
*tx_info
;
7058 struct ieee80211_hw
*hw
;
7059 struct rtl8xxxu_priv
*priv
;
7060 struct rtl8xxxu_tx_urb
*tx_urb
=
7061 container_of(urb
, struct rtl8xxxu_tx_urb
, urb
);
7063 tx_info
= IEEE80211_SKB_CB(skb
);
7064 hw
= tx_info
->rate_driver_data
[0];
7067 skb_pull(skb
, priv
->fops
->tx_desc_size
);
7069 ieee80211_tx_info_clear_status(tx_info
);
7070 tx_info
->status
.rates
[0].idx
= -1;
7071 tx_info
->status
.rates
[0].count
= 0;
7074 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
7076 ieee80211_tx_status_irqsafe(hw
, skb
);
7078 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
7081 static void rtl8xxxu_dump_action(struct device
*dev
,
7082 struct ieee80211_hdr
*hdr
)
7084 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)hdr
;
7087 if (!(rtl8xxxu_debug
& RTL8XXXU_DEBUG_ACTION
))
7090 switch (mgmt
->u
.action
.u
.addba_resp
.action_code
) {
7091 case WLAN_ACTION_ADDBA_RESP
:
7092 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.capab
);
7093 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.timeout
);
7094 dev_info(dev
, "WLAN_ACTION_ADDBA_RESP: "
7095 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
7098 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
7099 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
7101 le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.status
));
7103 case WLAN_ACTION_ADDBA_REQ
:
7104 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.capab
);
7105 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.timeout
);
7106 dev_info(dev
, "WLAN_ACTION_ADDBA_REQ: "
7107 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
7109 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
7110 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
7114 dev_info(dev
, "action frame %02x\n",
7115 mgmt
->u
.action
.u
.addba_resp
.action_code
);
7120 static void rtl8xxxu_tx(struct ieee80211_hw
*hw
,
7121 struct ieee80211_tx_control
*control
,
7122 struct sk_buff
*skb
)
7124 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
7125 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
7126 struct ieee80211_rate
*tx_rate
= ieee80211_get_tx_rate(hw
, tx_info
);
7127 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7128 struct rtl8723au_tx_desc
*tx_desc
;
7129 struct rtl8723bu_tx_desc
*tx_desc40
;
7130 struct rtl8xxxu_tx_urb
*tx_urb
;
7131 struct ieee80211_sta
*sta
= NULL
;
7132 struct ieee80211_vif
*vif
= tx_info
->control
.vif
;
7133 struct device
*dev
= &priv
->udev
->dev
;
7135 u16 pktlen
= skb
->len
;
7137 u16 rate_flag
= tx_info
->control
.rates
[0].flags
;
7138 int tx_desc_size
= priv
->fops
->tx_desc_size
;
7140 bool usedesc40
, ampdu_enable
;
7142 if (skb_headroom(skb
) < tx_desc_size
) {
7144 "%s: Not enough headroom (%i) for tx descriptor\n",
7145 __func__
, skb_headroom(skb
));
7149 if (unlikely(skb
->len
> (65535 - tx_desc_size
))) {
7150 dev_warn(dev
, "%s: Trying to send over-sized skb (%i)\n",
7151 __func__
, skb
->len
);
7155 tx_urb
= rtl8xxxu_alloc_tx_urb(priv
);
7157 dev_warn(dev
, "%s: Unable to allocate tx urb\n", __func__
);
7161 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_TX
)
7162 dev_info(dev
, "%s: TX rate: %d (%d), pkt size %d\n",
7163 __func__
, tx_rate
->bitrate
, tx_rate
->hw_value
, pktlen
);
7165 if (ieee80211_is_action(hdr
->frame_control
))
7166 rtl8xxxu_dump_action(dev
, hdr
);
7168 usedesc40
= (tx_desc_size
== 40);
7169 tx_info
->rate_driver_data
[0] = hw
;
7171 if (control
&& control
->sta
)
7174 tx_desc
= (struct rtl8723au_tx_desc
*)skb_push(skb
, tx_desc_size
);
7176 memset(tx_desc
, 0, tx_desc_size
);
7177 tx_desc
->pkt_size
= cpu_to_le16(pktlen
);
7178 tx_desc
->pkt_offset
= tx_desc_size
;
7181 TXDESC_OWN
| TXDESC_FIRST_SEGMENT
| TXDESC_LAST_SEGMENT
;
7182 if (is_multicast_ether_addr(ieee80211_get_DA(hdr
)) ||
7183 is_broadcast_ether_addr(ieee80211_get_DA(hdr
)))
7184 tx_desc
->txdw0
|= TXDESC_BROADMULTICAST
;
7186 queue
= rtl8xxxu_queue_select(hw
, skb
);
7187 tx_desc
->txdw1
= cpu_to_le32(queue
<< TXDESC_QUEUE_SHIFT
);
7189 if (tx_info
->control
.hw_key
) {
7190 switch (tx_info
->control
.hw_key
->cipher
) {
7191 case WLAN_CIPHER_SUITE_WEP40
:
7192 case WLAN_CIPHER_SUITE_WEP104
:
7193 case WLAN_CIPHER_SUITE_TKIP
:
7194 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_RC4
);
7196 case WLAN_CIPHER_SUITE_CCMP
:
7197 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_AES
);
7204 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7205 ampdu_enable
= false;
7206 if (ieee80211_is_data_qos(hdr
->frame_control
) && sta
) {
7207 if (sta
->ht_cap
.ht_supported
) {
7210 ampdu
= (u32
)sta
->ht_cap
.ampdu_density
;
7211 val32
= ampdu
<< TXDESC_AMPDU_DENSITY_SHIFT
;
7212 tx_desc
->txdw2
|= cpu_to_le32(val32
);
7214 ampdu_enable
= true;
7218 if (rate_flag
& IEEE80211_TX_RC_MCS
)
7219 rate
= tx_info
->control
.rates
[0].idx
+ DESC_RATE_MCS0
;
7221 rate
= tx_rate
->hw_value
;
7223 seq_number
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
7225 tx_desc
->txdw5
= cpu_to_le32(rate
);
7227 if (ieee80211_is_data(hdr
->frame_control
))
7228 tx_desc
->txdw5
|= cpu_to_le32(0x0001ff00);
7231 cpu_to_le32((u32
)seq_number
<< TXDESC_SEQ_SHIFT_8723A
);
7234 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_AGG_ENABLE_8723A
);
7236 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_AGG_BREAK_8723A
);
7238 if (ieee80211_is_mgmt(hdr
->frame_control
)) {
7239 tx_desc
->txdw5
= cpu_to_le32(tx_rate
->hw_value
);
7241 cpu_to_le32(TXDESC_USE_DRIVER_RATE_8723A
);
7244 TXDESC_RETRY_LIMIT_SHIFT_8723A
);
7246 cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE_8723A
);
7249 if (ieee80211_is_data_qos(hdr
->frame_control
))
7250 tx_desc
->txdw4
|= cpu_to_le32(TXDESC_QOS_8723A
);
7252 if (rate_flag
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
||
7253 (sta
&& vif
&& vif
->bss_conf
.use_short_preamble
))
7255 cpu_to_le32(TXDESC_SHORT_PREAMBLE_8723A
);
7257 if (rate_flag
& IEEE80211_TX_RC_SHORT_GI
||
7258 (ieee80211_is_data_qos(hdr
->frame_control
) &&
7259 sta
&& sta
->ht_cap
.cap
&
7260 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))) {
7261 tx_desc
->txdw5
|= cpu_to_le32(TXDESC_SHORT_GI
);
7264 if (rate_flag
& IEEE80211_TX_RC_USE_RTS_CTS
) {
7266 * Use RTS rate 24M - does the mac80211 tell
7270 cpu_to_le32(DESC_RATE_24M
<<
7271 TXDESC_RTS_RATE_SHIFT_8723A
);
7273 cpu_to_le32(TXDESC_RTS_CTS_ENABLE_8723A
);
7275 cpu_to_le32(TXDESC_HW_RTS_ENABLE_8723A
);
7278 tx_desc40
= (struct rtl8723bu_tx_desc
*)tx_desc
;
7280 tx_desc40
->txdw4
= cpu_to_le32(rate
);
7281 if (ieee80211_is_data(hdr
->frame_control
)) {
7284 TXDESC_DATA_RATE_FB_SHIFT_8723B
);
7288 cpu_to_le32((u32
)seq_number
<< TXDESC_SEQ_SHIFT_8723B
);
7292 cpu_to_le32(TXDESC_AGG_ENABLE_8723B
);
7294 tx_desc40
->txdw2
|= cpu_to_le32(TXDESC_AGG_BREAK_8723B
);
7296 if (ieee80211_is_mgmt(hdr
->frame_control
)) {
7297 tx_desc40
->txdw4
= cpu_to_le32(tx_rate
->hw_value
);
7299 cpu_to_le32(TXDESC_USE_DRIVER_RATE_8723B
);
7302 TXDESC_RETRY_LIMIT_SHIFT_8723B
);
7304 cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE_8723B
);
7307 if (rate_flag
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
||
7308 (sta
&& vif
&& vif
->bss_conf
.use_short_preamble
))
7310 cpu_to_le32(TXDESC_SHORT_PREAMBLE_8723B
);
7312 if (rate_flag
& IEEE80211_TX_RC_USE_RTS_CTS
) {
7314 * Use RTS rate 24M - does the mac80211 tell
7318 cpu_to_le32(DESC_RATE_24M
<<
7319 TXDESC_RTS_RATE_SHIFT_8723B
);
7321 cpu_to_le32(TXDESC_RTS_CTS_ENABLE_8723B
);
7323 cpu_to_le32(TXDESC_HW_RTS_ENABLE_8723B
);
7327 rtl8xxxu_calc_tx_desc_csum(tx_desc
);
7329 usb_fill_bulk_urb(&tx_urb
->urb
, priv
->udev
, priv
->pipe_out
[queue
],
7330 skb
->data
, skb
->len
, rtl8xxxu_tx_complete
, skb
);
7332 usb_anchor_urb(&tx_urb
->urb
, &priv
->tx_anchor
);
7333 ret
= usb_submit_urb(&tx_urb
->urb
, GFP_ATOMIC
);
7335 usb_unanchor_urb(&tx_urb
->urb
);
7336 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
7344 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv
*priv
,
7345 struct ieee80211_rx_status
*rx_status
,
7346 struct rtl8723au_phy_stats
*phy_stats
,
7349 if (phy_stats
->sgi_en
)
7350 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
7352 if (rxmcs
< DESC_RATE_6M
) {
7354 * Handle PHY stats for CCK rates
7356 u8 cck_agc_rpt
= phy_stats
->cck_agc_rpt_ofdm_cfosho_a
;
7358 switch (cck_agc_rpt
& 0xc0) {
7360 rx_status
->signal
= -46 - (cck_agc_rpt
& 0x3e);
7363 rx_status
->signal
= -26 - (cck_agc_rpt
& 0x3e);
7366 rx_status
->signal
= -12 - (cck_agc_rpt
& 0x3e);
7369 rx_status
->signal
= 16 - (cck_agc_rpt
& 0x3e);
7374 (phy_stats
->cck_sig_qual_ofdm_pwdb_all
>> 1) - 110;
7378 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv
*priv
)
7380 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
7381 unsigned long flags
;
7383 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7385 list_for_each_entry_safe(rx_urb
, tmp
,
7386 &priv
->rx_urb_pending_list
, list
) {
7387 list_del(&rx_urb
->list
);
7388 priv
->rx_urb_pending_count
--;
7389 usb_free_urb(&rx_urb
->urb
);
7392 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7395 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv
*priv
,
7396 struct rtl8xxxu_rx_urb
*rx_urb
)
7398 struct sk_buff
*skb
;
7399 unsigned long flags
;
7402 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7404 if (!priv
->shutdown
) {
7405 list_add_tail(&rx_urb
->list
, &priv
->rx_urb_pending_list
);
7406 priv
->rx_urb_pending_count
++;
7407 pending
= priv
->rx_urb_pending_count
;
7409 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
7411 usb_free_urb(&rx_urb
->urb
);
7414 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7416 if (pending
> RTL8XXXU_RX_URB_PENDING_WATER
)
7417 schedule_work(&priv
->rx_urb_wq
);
7420 static void rtl8xxxu_rx_urb_work(struct work_struct
*work
)
7422 struct rtl8xxxu_priv
*priv
;
7423 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
7424 struct list_head local
;
7425 struct sk_buff
*skb
;
7426 unsigned long flags
;
7429 priv
= container_of(work
, struct rtl8xxxu_priv
, rx_urb_wq
);
7430 INIT_LIST_HEAD(&local
);
7432 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7434 list_splice_init(&priv
->rx_urb_pending_list
, &local
);
7435 priv
->rx_urb_pending_count
= 0;
7437 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7439 list_for_each_entry_safe(rx_urb
, tmp
, &local
, list
) {
7440 list_del_init(&rx_urb
->list
);
7441 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
7443 * If out of memory or temporary error, put it back on the
7444 * queue and try again. Otherwise the device is dead/gone
7445 * and we should drop it.
7452 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
7455 pr_info("failed to requeue urb %i\n", ret
);
7456 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
7458 usb_free_urb(&rx_urb
->urb
);
7463 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv
*priv
,
7464 struct sk_buff
*skb
,
7465 struct ieee80211_rx_status
*rx_status
)
7467 struct rtl8xxxu_rx_desc
*rx_desc
= (struct rtl8xxxu_rx_desc
*)skb
->data
;
7468 struct rtl8723au_phy_stats
*phy_stats
;
7469 int drvinfo_sz
, desc_shift
;
7471 skb_pull(skb
, sizeof(struct rtl8xxxu_rx_desc
));
7473 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
7475 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
7476 desc_shift
= rx_desc
->shift
;
7477 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
7479 if (rx_desc
->phy_stats
)
7480 rtl8xxxu_rx_parse_phystats(priv
, rx_status
, phy_stats
,
7483 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
7484 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
7486 if (!rx_desc
->swdec
)
7487 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
7489 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7491 rx_status
->flag
|= RX_FLAG_40MHZ
;
7493 if (rx_desc
->rxht
) {
7494 rx_status
->flag
|= RX_FLAG_HT
;
7495 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
7497 rx_status
->rate_idx
= rx_desc
->rxmcs
;
7500 return RX_TYPE_DATA_PKT
;
7503 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv
*priv
,
7504 struct sk_buff
*skb
,
7505 struct ieee80211_rx_status
*rx_status
)
7507 struct rtl8723bu_rx_desc
*rx_desc
=
7508 (struct rtl8723bu_rx_desc
*)skb
->data
;
7509 struct rtl8723au_phy_stats
*phy_stats
;
7510 int drvinfo_sz
, desc_shift
;
7512 skb_pull(skb
, sizeof(struct rtl8723bu_rx_desc
));
7514 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
7516 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
7517 desc_shift
= rx_desc
->shift
;
7518 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
7520 if (rx_desc
->rpt_sel
) {
7521 struct device
*dev
= &priv
->udev
->dev
;
7522 dev_dbg(dev
, "%s: C2H packet\n", __func__
);
7526 if (rx_desc
->phy_stats
)
7527 rtl8xxxu_rx_parse_phystats(priv
, rx_status
, phy_stats
,
7530 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
7531 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
7533 if (!rx_desc
->swdec
)
7534 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
7536 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7538 rx_status
->flag
|= RX_FLAG_40MHZ
;
7540 if (rx_desc
->rxmcs
>= DESC_RATE_MCS0
) {
7541 rx_status
->flag
|= RX_FLAG_HT
;
7542 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
7544 rx_status
->rate_idx
= rx_desc
->rxmcs
;
7547 return RX_TYPE_DATA_PKT
;
7550 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv
*priv
,
7551 struct sk_buff
*skb
)
7553 struct rtl8723bu_c2h
*c2h
= (struct rtl8723bu_c2h
*)skb
->data
;
7554 struct device
*dev
= &priv
->udev
->dev
;
7559 dev_dbg(dev
, "C2H ID %02x seq %02x, len %02x source %02x\n",
7560 c2h
->id
, c2h
->seq
, len
, c2h
->bt_info
.response_source
);
7563 case C2H_8723B_BT_INFO
:
7564 if (c2h
->bt_info
.response_source
>
7565 BT_INFO_SRC_8723B_BT_ACTIVE_SEND
)
7566 dev_dbg(dev
, "C2H_BT_INFO WiFi only firmware\n");
7568 dev_dbg(dev
, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7570 if (c2h
->bt_info
.bt_has_reset
)
7571 dev_dbg(dev
, "BT has been reset\n");
7572 if (c2h
->bt_info
.tx_rx_mask
)
7573 dev_dbg(dev
, "BT TRx mask\n");
7576 case C2H_8723B_BT_MP_INFO
:
7577 dev_dbg(dev
, "C2H_MP_INFO ext ID %02x, status %02x\n",
7578 c2h
->bt_mp_info
.ext_id
, c2h
->bt_mp_info
.status
);
7580 case C2H_8723B_RA_REPORT
:
7582 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
7583 c2h
->ra_report
.rate
, c2h
->ra_report
.dummy0_0
,
7584 c2h
->ra_report
.macid
, c2h
->ra_report
.noisy_state
);
7587 dev_info(dev
, "Unhandled C2H event %02x seq %02x\n",
7589 print_hex_dump(KERN_INFO
, "C2H content: ", DUMP_PREFIX_NONE
,
7590 16, 1, c2h
->raw
.payload
, len
, false);
7595 static void rtl8xxxu_rx_complete(struct urb
*urb
)
7597 struct rtl8xxxu_rx_urb
*rx_urb
=
7598 container_of(urb
, struct rtl8xxxu_rx_urb
, urb
);
7599 struct ieee80211_hw
*hw
= rx_urb
->hw
;
7600 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7601 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
7602 struct ieee80211_rx_status
*rx_status
= IEEE80211_SKB_RXCB(skb
);
7603 struct device
*dev
= &priv
->udev
->dev
;
7604 __le32
*_rx_desc_le
= (__le32
*)skb
->data
;
7605 u32
*_rx_desc
= (u32
*)skb
->data
;
7608 for (i
= 0; i
< (sizeof(struct rtl8xxxu_rx_desc
) / sizeof(u32
)); i
++)
7609 _rx_desc
[i
] = le32_to_cpu(_rx_desc_le
[i
]);
7611 skb_put(skb
, urb
->actual_length
);
7613 if (urb
->status
== 0) {
7614 memset(rx_status
, 0, sizeof(struct ieee80211_rx_status
));
7616 rx_type
= priv
->fops
->parse_rx_desc(priv
, skb
, rx_status
);
7618 rx_status
->freq
= hw
->conf
.chandef
.chan
->center_freq
;
7619 rx_status
->band
= hw
->conf
.chandef
.chan
->band
;
7621 if (rx_type
== RX_TYPE_DATA_PKT
)
7622 ieee80211_rx_irqsafe(hw
, skb
);
7624 rtl8723bu_handle_c2h(priv
, skb
);
7629 rx_urb
->urb
.context
= NULL
;
7630 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
7632 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
7643 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
7644 struct rtl8xxxu_rx_urb
*rx_urb
)
7646 struct sk_buff
*skb
;
7650 skb_size
= sizeof(struct rtl8xxxu_rx_desc
) + RTL_RX_BUFFER_SIZE
;
7651 skb
= __netdev_alloc_skb(NULL
, skb_size
, GFP_KERNEL
);
7655 memset(skb
->data
, 0, sizeof(struct rtl8xxxu_rx_desc
));
7656 usb_fill_bulk_urb(&rx_urb
->urb
, priv
->udev
, priv
->pipe_in
, skb
->data
,
7657 skb_size
, rtl8xxxu_rx_complete
, skb
);
7658 usb_anchor_urb(&rx_urb
->urb
, &priv
->rx_anchor
);
7659 ret
= usb_submit_urb(&rx_urb
->urb
, GFP_ATOMIC
);
7661 usb_unanchor_urb(&rx_urb
->urb
);
7665 static void rtl8xxxu_int_complete(struct urb
*urb
)
7667 struct rtl8xxxu_priv
*priv
= (struct rtl8xxxu_priv
*)urb
->context
;
7668 struct device
*dev
= &priv
->udev
->dev
;
7671 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
7672 if (urb
->status
== 0) {
7673 usb_anchor_urb(urb
, &priv
->int_anchor
);
7674 ret
= usb_submit_urb(urb
, GFP_ATOMIC
);
7676 usb_unanchor_urb(urb
);
7678 dev_info(dev
, "%s: Error %i\n", __func__
, urb
->status
);
7683 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw
*hw
)
7685 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7690 urb
= usb_alloc_urb(0, GFP_KERNEL
);
7694 usb_fill_int_urb(urb
, priv
->udev
, priv
->pipe_interrupt
,
7695 priv
->int_buf
, USB_INTR_CONTENT_LENGTH
,
7696 rtl8xxxu_int_complete
, priv
, 1);
7697 usb_anchor_urb(urb
, &priv
->int_anchor
);
7698 ret
= usb_submit_urb(urb
, GFP_KERNEL
);
7700 usb_unanchor_urb(urb
);
7704 val32
= rtl8xxxu_read32(priv
, REG_USB_HIMR
);
7705 val32
|= USB_HIMR_CPWM
;
7706 rtl8xxxu_write32(priv
, REG_USB_HIMR
, val32
);
7712 static int rtl8xxxu_add_interface(struct ieee80211_hw
*hw
,
7713 struct ieee80211_vif
*vif
)
7715 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7719 switch (vif
->type
) {
7720 case NL80211_IFTYPE_STATION
:
7721 rtl8723a_stop_tx_beacon(priv
);
7723 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
7724 val8
|= BEACON_ATIM
| BEACON_FUNCTION_ENABLE
|
7725 BEACON_DISABLE_TSF_UPDATE
;
7726 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
7733 rtl8xxxu_set_linktype(priv
, vif
->type
);
7738 static void rtl8xxxu_remove_interface(struct ieee80211_hw
*hw
,
7739 struct ieee80211_vif
*vif
)
7741 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7743 dev_dbg(&priv
->udev
->dev
, "%s\n", __func__
);
7746 static int rtl8xxxu_config(struct ieee80211_hw
*hw
, u32 changed
)
7748 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7749 struct device
*dev
= &priv
->udev
->dev
;
7751 int ret
= 0, channel
;
7754 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
7756 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7757 __func__
, hw
->conf
.chandef
.chan
->hw_value
,
7758 changed
, hw
->conf
.chandef
.width
);
7760 if (changed
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
) {
7761 val16
= ((hw
->conf
.long_frame_max_tx_count
<<
7762 RETRY_LIMIT_LONG_SHIFT
) & RETRY_LIMIT_LONG_MASK
) |
7763 ((hw
->conf
.short_frame_max_tx_count
<<
7764 RETRY_LIMIT_SHORT_SHIFT
) & RETRY_LIMIT_SHORT_MASK
);
7765 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
7768 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
7769 switch (hw
->conf
.chandef
.width
) {
7770 case NL80211_CHAN_WIDTH_20_NOHT
:
7771 case NL80211_CHAN_WIDTH_20
:
7774 case NL80211_CHAN_WIDTH_40
:
7782 channel
= hw
->conf
.chandef
.chan
->hw_value
;
7784 priv
->fops
->set_tx_power(priv
, channel
, ht40
);
7786 priv
->fops
->config_channel(hw
);
7793 static int rtl8xxxu_conf_tx(struct ieee80211_hw
*hw
,
7794 struct ieee80211_vif
*vif
, u16 queue
,
7795 const struct ieee80211_tx_queue_params
*param
)
7797 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7798 struct device
*dev
= &priv
->udev
->dev
;
7800 u8 aifs
, acm_ctrl
, acm_bit
;
7805 fls(param
->cw_min
) << EDCA_PARAM_ECW_MIN_SHIFT
|
7806 fls(param
->cw_max
) << EDCA_PARAM_ECW_MAX_SHIFT
|
7807 (u32
)param
->txop
<< EDCA_PARAM_TXOP_SHIFT
;
7809 acm_ctrl
= rtl8xxxu_read8(priv
, REG_ACM_HW_CTRL
);
7811 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7812 __func__
, queue
, val32
, param
->acm
, acm_ctrl
);
7815 case IEEE80211_AC_VO
:
7816 acm_bit
= ACM_HW_CTRL_VO
;
7817 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, val32
);
7819 case IEEE80211_AC_VI
:
7820 acm_bit
= ACM_HW_CTRL_VI
;
7821 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, val32
);
7823 case IEEE80211_AC_BE
:
7824 acm_bit
= ACM_HW_CTRL_BE
;
7825 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, val32
);
7827 case IEEE80211_AC_BK
:
7828 acm_bit
= ACM_HW_CTRL_BK
;
7829 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, val32
);
7837 acm_ctrl
|= acm_bit
;
7839 acm_ctrl
&= ~acm_bit
;
7840 rtl8xxxu_write8(priv
, REG_ACM_HW_CTRL
, acm_ctrl
);
7845 static void rtl8xxxu_configure_filter(struct ieee80211_hw
*hw
,
7846 unsigned int changed_flags
,
7847 unsigned int *total_flags
, u64 multicast
)
7849 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7850 u32 rcr
= rtl8xxxu_read32(priv
, REG_RCR
);
7852 dev_dbg(&priv
->udev
->dev
, "%s: changed_flags %08x, total_flags %08x\n",
7853 __func__
, changed_flags
, *total_flags
);
7856 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7859 if (*total_flags
& FIF_FCSFAIL
)
7860 rcr
|= RCR_ACCEPT_CRC32
;
7862 rcr
&= ~RCR_ACCEPT_CRC32
;
7865 * FIF_PLCPFAIL not supported?
7868 if (*total_flags
& FIF_BCN_PRBRESP_PROMISC
)
7869 rcr
&= ~RCR_CHECK_BSSID_BEACON
;
7871 rcr
|= RCR_CHECK_BSSID_BEACON
;
7873 if (*total_flags
& FIF_CONTROL
)
7874 rcr
|= RCR_ACCEPT_CTRL_FRAME
;
7876 rcr
&= ~RCR_ACCEPT_CTRL_FRAME
;
7878 if (*total_flags
& FIF_OTHER_BSS
) {
7879 rcr
|= RCR_ACCEPT_AP
;
7880 rcr
&= ~RCR_CHECK_BSSID_MATCH
;
7882 rcr
&= ~RCR_ACCEPT_AP
;
7883 rcr
|= RCR_CHECK_BSSID_MATCH
;
7886 if (*total_flags
& FIF_PSPOLL
)
7887 rcr
|= RCR_ACCEPT_PM
;
7889 rcr
&= ~RCR_ACCEPT_PM
;
7892 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7895 rtl8xxxu_write32(priv
, REG_RCR
, rcr
);
7897 *total_flags
&= (FIF_ALLMULTI
| FIF_FCSFAIL
| FIF_BCN_PRBRESP_PROMISC
|
7898 FIF_CONTROL
| FIF_OTHER_BSS
| FIF_PSPOLL
|
7902 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw
*hw
, u32 rts
)
7910 static int rtl8xxxu_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
7911 struct ieee80211_vif
*vif
,
7912 struct ieee80211_sta
*sta
,
7913 struct ieee80211_key_conf
*key
)
7915 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7916 struct device
*dev
= &priv
->udev
->dev
;
7917 u8 mac_addr
[ETH_ALEN
];
7921 int retval
= -EOPNOTSUPP
;
7923 dev_dbg(dev
, "%s: cmd %02x, cipher %08x, index %i\n",
7924 __func__
, cmd
, key
->cipher
, key
->keyidx
);
7926 if (vif
->type
!= NL80211_IFTYPE_STATION
)
7929 if (key
->keyidx
> 3)
7932 switch (key
->cipher
) {
7933 case WLAN_CIPHER_SUITE_WEP40
:
7934 case WLAN_CIPHER_SUITE_WEP104
:
7937 case WLAN_CIPHER_SUITE_CCMP
:
7938 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT_TX
;
7940 case WLAN_CIPHER_SUITE_TKIP
:
7941 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
7946 if (key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) {
7947 dev_dbg(dev
, "%s: pairwise key\n", __func__
);
7948 ether_addr_copy(mac_addr
, sta
->addr
);
7950 dev_dbg(dev
, "%s: group key\n", __func__
);
7951 eth_broadcast_addr(mac_addr
);
7954 val16
= rtl8xxxu_read16(priv
, REG_CR
);
7955 val16
|= CR_SECURITY_ENABLE
;
7956 rtl8xxxu_write16(priv
, REG_CR
, val16
);
7958 val8
= SEC_CFG_TX_SEC_ENABLE
| SEC_CFG_TXBC_USE_DEFKEY
|
7959 SEC_CFG_RX_SEC_ENABLE
| SEC_CFG_RXBC_USE_DEFKEY
;
7960 val8
|= SEC_CFG_TX_USE_DEFKEY
| SEC_CFG_RX_USE_DEFKEY
;
7961 rtl8xxxu_write8(priv
, REG_SECURITY_CFG
, val8
);
7965 key
->hw_key_idx
= key
->keyidx
;
7966 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
7967 rtl8xxxu_cam_write(priv
, key
, mac_addr
);
7971 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, 0x00000000);
7972 val32
= CAM_CMD_POLLING
| CAM_CMD_WRITE
|
7973 key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
7974 rtl8xxxu_write32(priv
, REG_CAM_CMD
, val32
);
7978 dev_warn(dev
, "%s: Unsupported command %02x\n", __func__
, cmd
);
7985 rtl8xxxu_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
7986 struct ieee80211_ampdu_params
*params
)
7988 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7989 struct device
*dev
= &priv
->udev
->dev
;
7990 u8 ampdu_factor
, ampdu_density
;
7991 struct ieee80211_sta
*sta
= params
->sta
;
7992 enum ieee80211_ampdu_mlme_action action
= params
->action
;
7995 case IEEE80211_AMPDU_TX_START
:
7996 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_START\n", __func__
);
7997 ampdu_factor
= sta
->ht_cap
.ampdu_factor
;
7998 ampdu_density
= sta
->ht_cap
.ampdu_density
;
7999 rtl8xxxu_set_ampdu_factor(priv
, ampdu_factor
);
8000 rtl8xxxu_set_ampdu_min_space(priv
, ampdu_density
);
8002 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
8003 ampdu_factor
, ampdu_density
);
8005 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
8006 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__
);
8007 rtl8xxxu_set_ampdu_factor(priv
, 0);
8008 rtl8xxxu_set_ampdu_min_space(priv
, 0);
8010 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
8011 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
8013 rtl8xxxu_set_ampdu_factor(priv
, 0);
8014 rtl8xxxu_set_ampdu_min_space(priv
, 0);
8016 case IEEE80211_AMPDU_RX_START
:
8017 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_START\n", __func__
);
8019 case IEEE80211_AMPDU_RX_STOP
:
8020 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__
);
8028 static int rtl8xxxu_start(struct ieee80211_hw
*hw
)
8030 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8031 struct rtl8xxxu_rx_urb
*rx_urb
;
8032 struct rtl8xxxu_tx_urb
*tx_urb
;
8033 unsigned long flags
;
8038 init_usb_anchor(&priv
->rx_anchor
);
8039 init_usb_anchor(&priv
->tx_anchor
);
8040 init_usb_anchor(&priv
->int_anchor
);
8042 priv
->fops
->enable_rf(priv
);
8043 if (priv
->usb_interrupts
) {
8044 ret
= rtl8xxxu_submit_int_urb(hw
);
8049 for (i
= 0; i
< RTL8XXXU_TX_URBS
; i
++) {
8050 tx_urb
= kmalloc(sizeof(struct rtl8xxxu_tx_urb
), GFP_KERNEL
);
8057 usb_init_urb(&tx_urb
->urb
);
8058 INIT_LIST_HEAD(&tx_urb
->list
);
8060 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
8061 priv
->tx_urb_free_count
++;
8064 priv
->tx_stopped
= false;
8066 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
8067 priv
->shutdown
= false;
8068 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
8070 for (i
= 0; i
< RTL8XXXU_RX_URBS
; i
++) {
8071 rx_urb
= kmalloc(sizeof(struct rtl8xxxu_rx_urb
), GFP_KERNEL
);
8078 usb_init_urb(&rx_urb
->urb
);
8079 INIT_LIST_HEAD(&rx_urb
->list
);
8082 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
8086 * Accept all data and mgmt frames
8088 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0xffff);
8089 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0xffff);
8091 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, 0x6954341e);
8096 rtl8xxxu_free_tx_resources(priv
);
8098 * Disable all data and mgmt frames
8100 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
8101 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
8106 static void rtl8xxxu_stop(struct ieee80211_hw
*hw
)
8108 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8109 unsigned long flags
;
8111 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
8113 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
8114 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
8116 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
8117 priv
->shutdown
= true;
8118 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
8120 usb_kill_anchored_urbs(&priv
->rx_anchor
);
8121 usb_kill_anchored_urbs(&priv
->tx_anchor
);
8122 if (priv
->usb_interrupts
)
8123 usb_kill_anchored_urbs(&priv
->int_anchor
);
8125 priv
->fops
->disable_rf(priv
);
8128 * Disable interrupts
8130 if (priv
->usb_interrupts
)
8131 rtl8xxxu_write32(priv
, REG_USB_HIMR
, 0);
8133 rtl8xxxu_free_rx_resources(priv
);
8134 rtl8xxxu_free_tx_resources(priv
);
8137 static const struct ieee80211_ops rtl8xxxu_ops
= {
8139 .add_interface
= rtl8xxxu_add_interface
,
8140 .remove_interface
= rtl8xxxu_remove_interface
,
8141 .config
= rtl8xxxu_config
,
8142 .conf_tx
= rtl8xxxu_conf_tx
,
8143 .bss_info_changed
= rtl8xxxu_bss_info_changed
,
8144 .configure_filter
= rtl8xxxu_configure_filter
,
8145 .set_rts_threshold
= rtl8xxxu_set_rts_threshold
,
8146 .start
= rtl8xxxu_start
,
8147 .stop
= rtl8xxxu_stop
,
8148 .sw_scan_start
= rtl8xxxu_sw_scan_start
,
8149 .sw_scan_complete
= rtl8xxxu_sw_scan_complete
,
8150 .set_key
= rtl8xxxu_set_key
,
8151 .ampdu_action
= rtl8xxxu_ampdu_action
,
8154 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv
*priv
,
8155 struct usb_interface
*interface
)
8157 struct usb_interface_descriptor
*interface_desc
;
8158 struct usb_host_interface
*host_interface
;
8159 struct usb_endpoint_descriptor
*endpoint
;
8160 struct device
*dev
= &priv
->udev
->dev
;
8161 int i
, j
= 0, endpoints
;
8165 host_interface
= &interface
->altsetting
[0];
8166 interface_desc
= &host_interface
->desc
;
8167 endpoints
= interface_desc
->bNumEndpoints
;
8169 for (i
= 0; i
< endpoints
; i
++) {
8170 endpoint
= &host_interface
->endpoint
[i
].desc
;
8172 dir
= endpoint
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
;
8173 num
= usb_endpoint_num(endpoint
);
8174 xtype
= usb_endpoint_type(endpoint
);
8175 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8177 "%s: endpoint: dir %02x, # %02x, type %02x\n",
8178 __func__
, dir
, num
, xtype
);
8179 if (usb_endpoint_dir_in(endpoint
) &&
8180 usb_endpoint_xfer_bulk(endpoint
)) {
8181 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8182 dev_dbg(dev
, "%s: in endpoint num %i\n",
8185 if (priv
->pipe_in
) {
8187 "%s: Too many IN pipes\n", __func__
);
8192 priv
->pipe_in
= usb_rcvbulkpipe(priv
->udev
, num
);
8195 if (usb_endpoint_dir_in(endpoint
) &&
8196 usb_endpoint_xfer_int(endpoint
)) {
8197 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8198 dev_dbg(dev
, "%s: interrupt endpoint num %i\n",
8201 if (priv
->pipe_interrupt
) {
8202 dev_warn(dev
, "%s: Too many INTERRUPT pipes\n",
8208 priv
->pipe_interrupt
= usb_rcvintpipe(priv
->udev
, num
);
8211 if (usb_endpoint_dir_out(endpoint
) &&
8212 usb_endpoint_xfer_bulk(endpoint
)) {
8213 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8214 dev_dbg(dev
, "%s: out endpoint num %i\n",
8216 if (j
>= RTL8XXXU_OUT_ENDPOINTS
) {
8218 "%s: Too many OUT pipes\n", __func__
);
8222 priv
->out_ep
[j
++] = num
;
8226 priv
->nr_out_eps
= j
;
8230 static int rtl8xxxu_probe(struct usb_interface
*interface
,
8231 const struct usb_device_id
*id
)
8233 struct rtl8xxxu_priv
*priv
;
8234 struct ieee80211_hw
*hw
;
8235 struct usb_device
*udev
;
8236 struct ieee80211_supported_band
*sband
;
8240 udev
= usb_get_dev(interface_to_usbdev(interface
));
8242 switch (id
->idVendor
) {
8243 case USB_VENDOR_ID_REALTEK
:
8244 switch(id
->idProduct
) {
8254 if (id
->idProduct
== 0x7811)
8262 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_EFUSE
;
8263 dev_info(&udev
->dev
,
8264 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8265 id
->idVendor
, id
->idProduct
);
8266 dev_info(&udev
->dev
,
8267 "Please report results to Jes.Sorensen@gmail.com\n");
8270 hw
= ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv
), &rtl8xxxu_ops
);
8279 priv
->fops
= (struct rtl8xxxu_fileops
*)id
->driver_info
;
8280 mutex_init(&priv
->usb_buf_mutex
);
8281 mutex_init(&priv
->h2c_mutex
);
8282 INIT_LIST_HEAD(&priv
->tx_urb_free_list
);
8283 spin_lock_init(&priv
->tx_urb_lock
);
8284 INIT_LIST_HEAD(&priv
->rx_urb_pending_list
);
8285 spin_lock_init(&priv
->rx_urb_lock
);
8286 INIT_WORK(&priv
->rx_urb_wq
, rtl8xxxu_rx_urb_work
);
8288 usb_set_intfdata(interface
, hw
);
8290 ret
= rtl8xxxu_parse_usb(priv
, interface
);
8294 ret
= rtl8xxxu_identify_chip(priv
);
8296 dev_err(&udev
->dev
, "Fatal - failed to identify chip\n");
8300 ret
= rtl8xxxu_read_efuse(priv
);
8302 dev_err(&udev
->dev
, "Fatal - failed to read EFuse\n");
8306 ret
= priv
->fops
->parse_efuse(priv
);
8308 dev_err(&udev
->dev
, "Fatal - failed to parse EFuse\n");
8312 rtl8xxxu_print_chipinfo(priv
);
8314 ret
= priv
->fops
->load_firmware(priv
);
8316 dev_err(&udev
->dev
, "Fatal - failed to load firmware\n");
8320 ret
= rtl8xxxu_init_device(hw
);
8322 hw
->wiphy
->max_scan_ssids
= 1;
8323 hw
->wiphy
->max_scan_ie_len
= IEEE80211_MAX_DATA_LEN
;
8324 hw
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
);
8327 sband
= &rtl8xxxu_supported_band
;
8328 sband
->ht_cap
.ht_supported
= true;
8329 sband
->ht_cap
.ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
8330 sband
->ht_cap
.ampdu_density
= IEEE80211_HT_MPDU_DENSITY_16
;
8331 sband
->ht_cap
.cap
= IEEE80211_HT_CAP_SGI_20
| IEEE80211_HT_CAP_SGI_40
;
8332 memset(&sband
->ht_cap
.mcs
, 0, sizeof(sband
->ht_cap
.mcs
));
8333 sband
->ht_cap
.mcs
.rx_mask
[0] = 0xff;
8334 sband
->ht_cap
.mcs
.rx_mask
[4] = 0x01;
8335 if (priv
->rf_paths
> 1) {
8336 sband
->ht_cap
.mcs
.rx_mask
[1] = 0xff;
8337 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SGI_40
;
8339 sband
->ht_cap
.mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
8341 * Some APs will negotiate HT20_40 in a noisy environment leading
8342 * to miserable performance. Rather than defaulting to this, only
8343 * enable it if explicitly requested at module load time.
8345 if (rtl8xxxu_ht40_2g
) {
8346 dev_info(&udev
->dev
, "Enabling HT_20_40 on the 2.4GHz band\n");
8347 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SUP_WIDTH_20_40
;
8349 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
8351 hw
->wiphy
->rts_threshold
= 2347;
8353 SET_IEEE80211_DEV(priv
->hw
, &interface
->dev
);
8354 SET_IEEE80211_PERM_ADDR(hw
, priv
->mac_addr
);
8356 hw
->extra_tx_headroom
= priv
->fops
->tx_desc_size
;
8357 ieee80211_hw_set(hw
, SIGNAL_DBM
);
8359 * The firmware handles rate control
8361 ieee80211_hw_set(hw
, HAS_RATE_CONTROL
);
8362 ieee80211_hw_set(hw
, AMPDU_AGGREGATION
);
8364 ret
= ieee80211_register_hw(priv
->hw
);
8366 dev_err(&udev
->dev
, "%s: Failed to register: %i\n",
8377 static void rtl8xxxu_disconnect(struct usb_interface
*interface
)
8379 struct rtl8xxxu_priv
*priv
;
8380 struct ieee80211_hw
*hw
;
8382 hw
= usb_get_intfdata(interface
);
8385 rtl8xxxu_disable_device(hw
);
8386 usb_set_intfdata(interface
, NULL
);
8388 dev_info(&priv
->udev
->dev
, "disconnecting\n");
8390 ieee80211_unregister_hw(hw
);
8392 kfree(priv
->fw_data
);
8393 mutex_destroy(&priv
->usb_buf_mutex
);
8394 mutex_destroy(&priv
->h2c_mutex
);
8396 usb_put_dev(priv
->udev
);
8397 ieee80211_free_hw(hw
);
8400 static struct rtl8xxxu_fileops rtl8723au_fops
= {
8401 .parse_efuse
= rtl8723au_parse_efuse
,
8402 .load_firmware
= rtl8723au_load_firmware
,
8403 .power_on
= rtl8723au_power_on
,
8404 .power_off
= rtl8xxxu_power_off
,
8405 .llt_init
= rtl8xxxu_init_llt_table
,
8406 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
8407 .config_channel
= rtl8723au_config_channel
,
8408 .parse_rx_desc
= rtl8723au_parse_rx_desc
,
8409 .enable_rf
= rtl8723a_enable_rf
,
8410 .disable_rf
= rtl8723a_disable_rf
,
8411 .set_tx_power
= rtl8723a_set_tx_power
,
8412 .update_rate_mask
= rtl8723au_update_rate_mask
,
8413 .report_connect
= rtl8723au_report_connect
,
8414 .writeN_block_size
= 1024,
8415 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
8416 .mbox_ext_width
= 2,
8417 .tx_desc_size
= sizeof(struct rtl8723au_tx_desc
),
8418 .adda_1t_init
= 0x0b1b25a0,
8419 .adda_1t_path_on
= 0x0bdb25a0,
8420 .adda_2t_path_on_a
= 0x04db25a4,
8421 .adda_2t_path_on_b
= 0x0b1b25a4,
8424 static struct rtl8xxxu_fileops rtl8723bu_fops
= {
8425 .parse_efuse
= rtl8723bu_parse_efuse
,
8426 .load_firmware
= rtl8723bu_load_firmware
,
8427 .power_on
= rtl8723bu_power_on
,
8428 .power_off
= rtl8723bu_power_off
,
8429 .llt_init
= rtl8xxxu_auto_llt_table
,
8430 .phy_init_antenna_selection
= rtl8723bu_phy_init_antenna_selection
,
8431 .phy_iq_calibrate
= rtl8723bu_phy_iq_calibrate
,
8432 .config_channel
= rtl8723bu_config_channel
,
8433 .parse_rx_desc
= rtl8723bu_parse_rx_desc
,
8434 .init_aggregation
= rtl8723bu_init_aggregation
,
8435 .init_statistics
= rtl8723bu_init_statistics
,
8436 .enable_rf
= rtl8723b_enable_rf
,
8437 .disable_rf
= rtl8723b_disable_rf
,
8438 .set_tx_power
= rtl8723b_set_tx_power
,
8439 .update_rate_mask
= rtl8723bu_update_rate_mask
,
8440 .report_connect
= rtl8723bu_report_connect
,
8441 .writeN_block_size
= 1024,
8442 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
8443 .mbox_ext_width
= 4,
8444 .tx_desc_size
= sizeof(struct rtl8723bu_tx_desc
),
8446 .adda_1t_init
= 0x01c00014,
8447 .adda_1t_path_on
= 0x01c00014,
8448 .adda_2t_path_on_a
= 0x01c00014,
8449 .adda_2t_path_on_b
= 0x01c00014,
8452 #ifdef CONFIG_RTL8XXXU_UNTESTED
8454 static struct rtl8xxxu_fileops rtl8192cu_fops
= {
8455 .parse_efuse
= rtl8192cu_parse_efuse
,
8456 .load_firmware
= rtl8192cu_load_firmware
,
8457 .power_on
= rtl8192cu_power_on
,
8458 .power_off
= rtl8xxxu_power_off
,
8459 .llt_init
= rtl8xxxu_init_llt_table
,
8460 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
8461 .config_channel
= rtl8723au_config_channel
,
8462 .parse_rx_desc
= rtl8723au_parse_rx_desc
,
8463 .enable_rf
= rtl8723a_enable_rf
,
8464 .disable_rf
= rtl8723a_disable_rf
,
8465 .set_tx_power
= rtl8723a_set_tx_power
,
8466 .update_rate_mask
= rtl8723au_update_rate_mask
,
8467 .report_connect
= rtl8723au_report_connect
,
8468 .writeN_block_size
= 128,
8469 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
8470 .mbox_ext_width
= 2,
8471 .tx_desc_size
= sizeof(struct rtl8723au_tx_desc
),
8472 .adda_1t_init
= 0x0b1b25a0,
8473 .adda_1t_path_on
= 0x0bdb25a0,
8474 .adda_2t_path_on_a
= 0x04db25a4,
8475 .adda_2t_path_on_b
= 0x0b1b25a4,
8480 static struct rtl8xxxu_fileops rtl8192eu_fops
= {
8481 .parse_efuse
= rtl8192eu_parse_efuse
,
8482 .load_firmware
= rtl8192eu_load_firmware
,
8483 .power_on
= rtl8192eu_power_on
,
8484 .power_off
= rtl8xxxu_power_off
,
8485 .llt_init
= rtl8xxxu_auto_llt_table
,
8486 .phy_iq_calibrate
= rtl8723bu_phy_iq_calibrate
,
8487 .config_channel
= rtl8723bu_config_channel
,
8488 .parse_rx_desc
= rtl8723bu_parse_rx_desc
,
8489 .enable_rf
= rtl8723b_enable_rf
,
8490 .disable_rf
= rtl8723b_disable_rf
,
8491 .set_tx_power
= rtl8723b_set_tx_power
,
8492 .update_rate_mask
= rtl8723au_update_rate_mask
,
8493 .report_connect
= rtl8723au_report_connect
,
8494 .writeN_block_size
= 128,
8495 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
8496 .mbox_ext_width
= 4,
8497 .tx_desc_size
= sizeof(struct rtl8723au_tx_desc
),
8499 .adda_1t_init
= 0x0fc01616,
8500 .adda_1t_path_on
= 0x0fc01616,
8501 .adda_2t_path_on_a
= 0x0fc01616,
8502 .adda_2t_path_on_b
= 0x0fc01616,
8505 static struct usb_device_id dev_table
[] = {
8506 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8724, 0xff, 0xff, 0xff),
8507 .driver_info
= (unsigned long)&rtl8723au_fops
},
8508 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1724, 0xff, 0xff, 0xff),
8509 .driver_info
= (unsigned long)&rtl8723au_fops
},
8510 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x0724, 0xff, 0xff, 0xff),
8511 .driver_info
= (unsigned long)&rtl8723au_fops
},
8512 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818b, 0xff, 0xff, 0xff),
8513 .driver_info
= (unsigned long)&rtl8192eu_fops
},
8514 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0xb720, 0xff, 0xff, 0xff),
8515 .driver_info
= (unsigned long)&rtl8723bu_fops
},
8516 #ifdef CONFIG_RTL8XXXU_UNTESTED
8517 /* Still supported by rtlwifi */
8518 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8176, 0xff, 0xff, 0xff),
8519 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8520 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8178, 0xff, 0xff, 0xff),
8521 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8522 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817f, 0xff, 0xff, 0xff),
8523 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8524 /* Tested by Larry Finger */
8525 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8526 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8527 /* Currently untested 8188 series devices */
8528 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8191, 0xff, 0xff, 0xff),
8529 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8530 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8170, 0xff, 0xff, 0xff),
8531 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8532 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8177, 0xff, 0xff, 0xff),
8533 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8534 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817a, 0xff, 0xff, 0xff),
8535 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8536 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817b, 0xff, 0xff, 0xff),
8537 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8538 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817d, 0xff, 0xff, 0xff),
8539 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8540 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817e, 0xff, 0xff, 0xff),
8541 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8542 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818a, 0xff, 0xff, 0xff),
8543 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8544 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x317f, 0xff, 0xff, 0xff),
8545 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8546 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8547 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8548 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8549 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8550 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8551 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8552 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8553 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8554 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8555 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8556 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8557 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8558 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8559 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8560 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1e1e, 0xff, 0xff, 0xff),
8561 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8562 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x5088, 0xff, 0xff, 0xff),
8563 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8564 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8565 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8566 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8567 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8568 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8569 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8570 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8571 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8572 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8573 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8574 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8575 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8576 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8577 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8578 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8579 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8580 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8581 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8582 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8583 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8584 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8585 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8586 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8587 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8588 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8589 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8590 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8591 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8592 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8593 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8594 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8595 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8596 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8597 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8598 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8599 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8600 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8601 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8602 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8603 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8604 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8605 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8606 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8607 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8608 /* Currently untested 8192 series devices */
8609 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8610 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8611 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8612 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8613 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8614 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8615 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8616 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8617 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8618 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8619 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8620 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8621 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8622 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8623 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8624 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8625 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8626 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8627 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8628 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8629 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8630 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8631 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8632 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8633 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8634 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8635 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8636 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8637 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x2e2e, 0xff, 0xff, 0xff),
8638 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8639 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8640 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8641 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8642 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8643 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8644 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8645 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8646 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8647 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8648 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8649 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8650 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8651 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8652 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8653 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8654 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8655 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8656 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8657 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8658 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8663 static struct usb_driver rtl8xxxu_driver
= {
8664 .name
= DRIVER_NAME
,
8665 .probe
= rtl8xxxu_probe
,
8666 .disconnect
= rtl8xxxu_disconnect
,
8667 .id_table
= dev_table
,
8668 .disable_hub_initiated_lpm
= 1,
8671 static int __init
rtl8xxxu_module_init(void)
8675 res
= usb_register(&rtl8xxxu_driver
);
8677 pr_err(DRIVER_NAME
": usb_register() failed (%i)\n", res
);
8682 static void __exit
rtl8xxxu_module_exit(void)
8684 usb_deregister(&rtl8xxxu_driver
);
8688 MODULE_DEVICE_TABLE(usb
, dev_table
);
8690 module_init(rtl8xxxu_module_init
);
8691 module_exit(rtl8xxxu_module_exit
);