3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
32 #include "rtl8225se.h"
34 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
35 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
36 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
37 MODULE_LICENSE("GPL");
39 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table
) = {
41 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8185) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x700f) },
43 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x701f) },
46 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8180) },
47 { PCI_DEVICE(0x1799, 0x6001) },
48 { PCI_DEVICE(0x1799, 0x6020) },
49 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x3300) },
50 { PCI_DEVICE(0x1186, 0x3301) },
51 { PCI_DEVICE(0x1432, 0x7106) },
55 MODULE_DEVICE_TABLE(pci
, rtl8180_table
);
57 static const struct ieee80211_rate rtl818x_rates
[] = {
58 { .bitrate
= 10, .hw_value
= 0, },
59 { .bitrate
= 20, .hw_value
= 1, },
60 { .bitrate
= 55, .hw_value
= 2, },
61 { .bitrate
= 110, .hw_value
= 3, },
62 { .bitrate
= 60, .hw_value
= 4, },
63 { .bitrate
= 90, .hw_value
= 5, },
64 { .bitrate
= 120, .hw_value
= 6, },
65 { .bitrate
= 180, .hw_value
= 7, },
66 { .bitrate
= 240, .hw_value
= 8, },
67 { .bitrate
= 360, .hw_value
= 9, },
68 { .bitrate
= 480, .hw_value
= 10, },
69 { .bitrate
= 540, .hw_value
= 11, },
72 static const struct ieee80211_channel rtl818x_channels
[] = {
73 { .center_freq
= 2412 },
74 { .center_freq
= 2417 },
75 { .center_freq
= 2422 },
76 { .center_freq
= 2427 },
77 { .center_freq
= 2432 },
78 { .center_freq
= 2437 },
79 { .center_freq
= 2442 },
80 { .center_freq
= 2447 },
81 { .center_freq
= 2452 },
82 { .center_freq
= 2457 },
83 { .center_freq
= 2462 },
84 { .center_freq
= 2467 },
85 { .center_freq
= 2472 },
86 { .center_freq
= 2484 },
89 /* Queues for rtl8187se card
100 * The complete map for DMA kick reg using use all queue is:
101 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
102 * {1, 6, 5, 4, 3, 2, 7};
104 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
107 * BC | 7 | 4 <- currently not used yet
108 * MG | 1 | x <- Not used
109 * HI | 6 | x <- Not used
115 * Beacon queue could be used, but this is not finished yet.
117 * I thougth about using the other two queues but I decided not to do this:
119 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
122 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
123 * queue but since mac80211 will do not know about it, I will probably gain
124 * some HW priority whenever the VO queue is not empty, but this gain is
125 * limited by the fact that I had to stop the mac80211 queue whenever one of
126 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
129 * - I don't know how to set in the HW the contention window params for MGMT
130 * and HI-prio queues.
133 static const int rtl8187se_queues_map
[RTL8187SE_NR_TX_QUEUES
] = {5, 4, 3, 2, 7};
135 /* Queues for rtl8180/rtl8185 cards
143 * The complete map for DMA kick reg using all queue is:
144 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
146 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
147 * otherwise QoS can't be done, we use just one.
148 * Beacon queue could be used, but this is not finished yet.
152 * BC | 7 | 1 <- currently not used yet.
153 * HI | 6 | x <- not used
154 * NO | 5 | x <- not used
158 static const int rtl8180_queues_map
[RTL8180_NR_TX_QUEUES
] = {4, 7};
160 void rtl8180_write_phy(struct ieee80211_hw
*dev
, u8 addr
, u32 data
)
162 struct rtl8180_priv
*priv
= dev
->priv
;
166 buf
= (data
<< 8) | addr
;
168 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
| 0x80);
170 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
);
171 if (rtl818x_ioread8(priv
, &priv
->map
->PHY
[2]) == (data
& 0xFF))
176 static void rtl8180_handle_rx(struct ieee80211_hw
*dev
)
178 struct rtl8180_priv
*priv
= dev
->priv
;
179 struct rtl818x_rx_cmd_desc
*cmd_desc
;
180 unsigned int count
= 32;
185 void *entry
= priv
->rx_ring
+ priv
->rx_idx
* priv
->rx_ring_sz
;
186 struct sk_buff
*skb
= priv
->rx_buf
[priv
->rx_idx
];
190 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
191 struct rtl8187se_rx_desc
*desc
= entry
;
193 flags
= le32_to_cpu(desc
->flags
);
194 flags2
= le32_to_cpu(desc
->flags2
);
195 tsft
= le64_to_cpu(desc
->tsft
);
197 struct rtl8180_rx_desc
*desc
= entry
;
199 flags
= le32_to_cpu(desc
->flags
);
200 flags2
= le32_to_cpu(desc
->flags2
);
201 tsft
= le64_to_cpu(desc
->tsft
);
204 if (flags
& RTL818X_RX_DESC_FLAG_OWN
)
207 if (unlikely(flags
& (RTL818X_RX_DESC_FLAG_DMA_FAIL
|
208 RTL818X_RX_DESC_FLAG_FOF
|
209 RTL818X_RX_DESC_FLAG_RX_ERR
)))
212 struct ieee80211_rx_status rx_status
= {0};
213 struct sk_buff
*new_skb
= dev_alloc_skb(MAX_RX_SIZE
);
215 if (unlikely(!new_skb
))
218 mapping
= pci_map_single(priv
->pdev
,
219 skb_tail_pointer(new_skb
),
220 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
222 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
224 dev_err(&priv
->pdev
->dev
, "RX DMA map error\n");
229 pci_unmap_single(priv
->pdev
,
230 *((dma_addr_t
*)skb
->cb
),
231 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
232 skb_put(skb
, flags
& 0xFFF);
234 rx_status
.antenna
= (flags2
>> 15) & 1;
235 rx_status
.rate_idx
= (flags
>> 20) & 0xF;
236 agc
= (flags2
>> 17) & 0x7F;
238 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
239 if (rx_status
.rate_idx
> 3)
240 signal
= 90 - clamp_t(u8
, agc
, 25, 90);
242 signal
= 95 - clamp_t(u8
, agc
, 30, 95);
243 } else if (priv
->chip_family
==
244 RTL818X_CHIP_FAMILY_RTL8180
) {
246 signal
= priv
->rf
->calc_rssi(agc
, sq
);
248 /* TODO: rtl8187se rssi */
251 rx_status
.signal
= signal
;
252 rx_status
.freq
= dev
->conf
.chandef
.chan
->center_freq
;
253 rx_status
.band
= dev
->conf
.chandef
.chan
->band
;
254 rx_status
.mactime
= tsft
;
255 rx_status
.flag
|= RX_FLAG_MACTIME_START
;
256 if (flags
& RTL818X_RX_DESC_FLAG_CRC32_ERR
)
257 rx_status
.flag
|= RX_FLAG_FAILED_FCS_CRC
;
259 memcpy(IEEE80211_SKB_RXCB(skb
), &rx_status
, sizeof(rx_status
));
260 ieee80211_rx_irqsafe(dev
, skb
);
263 priv
->rx_buf
[priv
->rx_idx
] = skb
;
264 *((dma_addr_t
*) skb
->cb
) = mapping
;
269 cmd_desc
->rx_buf
= cpu_to_le32(*((dma_addr_t
*)skb
->cb
));
270 cmd_desc
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
272 if (priv
->rx_idx
== 31)
274 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
275 priv
->rx_idx
= (priv
->rx_idx
+ 1) % 32;
279 static void rtl8180_handle_tx(struct ieee80211_hw
*dev
, unsigned int prio
)
281 struct rtl8180_priv
*priv
= dev
->priv
;
282 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
284 while (skb_queue_len(&ring
->queue
)) {
285 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
287 struct ieee80211_tx_info
*info
;
288 u32 flags
= le32_to_cpu(entry
->flags
);
290 if (flags
& RTL818X_TX_DESC_FLAG_OWN
)
293 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
294 skb
= __skb_dequeue(&ring
->queue
);
295 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
296 skb
->len
, PCI_DMA_TODEVICE
);
298 info
= IEEE80211_SKB_CB(skb
);
299 ieee80211_tx_info_clear_status(info
);
301 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
) &&
302 (flags
& RTL818X_TX_DESC_FLAG_TX_OK
))
303 info
->flags
|= IEEE80211_TX_STAT_ACK
;
305 info
->status
.rates
[0].count
= (flags
& 0xFF) + 1;
306 info
->status
.rates
[1].idx
= -1;
308 ieee80211_tx_status_irqsafe(dev
, skb
);
309 if (ring
->entries
- skb_queue_len(&ring
->queue
) == 2)
310 ieee80211_wake_queue(dev
, prio
);
314 static irqreturn_t
rtl8187se_interrupt(int irq
, void *dev_id
)
316 struct ieee80211_hw
*dev
= dev_id
;
317 struct rtl8180_priv
*priv
= dev
->priv
;
322 spin_lock_irqsave(&priv
->lock
, flags
);
323 /* Note: 32-bit interrupt status */
324 reg
= rtl818x_ioread32(priv
, &priv
->map
->INT_STATUS_SE
);
325 if (unlikely(reg
== 0xFFFFFFFF)) {
326 spin_unlock_irqrestore(&priv
->lock
, flags
);
330 rtl818x_iowrite32(priv
, &priv
->map
->INT_STATUS_SE
, reg
);
332 if (reg
& IMR_TIMEOUT1
)
333 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
335 if (reg
& (IMR_TBDOK
| IMR_TBDER
))
336 rtl8180_handle_tx(dev
, 4);
338 if (reg
& (IMR_TVODOK
| IMR_TVODER
))
339 rtl8180_handle_tx(dev
, 0);
341 if (reg
& (IMR_TVIDOK
| IMR_TVIDER
))
342 rtl8180_handle_tx(dev
, 1);
344 if (reg
& (IMR_TBEDOK
| IMR_TBEDER
))
345 rtl8180_handle_tx(dev
, 2);
347 if (reg
& (IMR_TBKDOK
| IMR_TBKDER
))
348 rtl8180_handle_tx(dev
, 3);
350 if (reg
& (IMR_ROK
| IMR_RER
| RTL818X_INT_SE_RX_DU
| IMR_RQOSOK
))
351 rtl8180_handle_rx(dev
);
352 /* The interface sometimes generates several RX DMA descriptor errors
353 * at startup. Do not report these.
355 if ((reg
& RTL818X_INT_SE_RX_DU
) && desc_err
++ > 2)
357 wiphy_err(dev
->wiphy
, "No RX DMA Descriptor avail\n");
359 spin_unlock_irqrestore(&priv
->lock
, flags
);
363 static irqreturn_t
rtl8180_interrupt(int irq
, void *dev_id
)
365 struct ieee80211_hw
*dev
= dev_id
;
366 struct rtl8180_priv
*priv
= dev
->priv
;
369 spin_lock(&priv
->lock
);
370 reg
= rtl818x_ioread16(priv
, &priv
->map
->INT_STATUS
);
371 if (unlikely(reg
== 0xFFFF)) {
372 spin_unlock(&priv
->lock
);
376 rtl818x_iowrite16(priv
, &priv
->map
->INT_STATUS
, reg
);
378 if (reg
& (RTL818X_INT_TXB_OK
| RTL818X_INT_TXB_ERR
))
379 rtl8180_handle_tx(dev
, 1);
381 if (reg
& (RTL818X_INT_TXL_OK
| RTL818X_INT_TXL_ERR
))
382 rtl8180_handle_tx(dev
, 0);
384 if (reg
& (RTL818X_INT_RX_OK
| RTL818X_INT_RX_ERR
))
385 rtl8180_handle_rx(dev
);
387 spin_unlock(&priv
->lock
);
392 static void rtl8180_tx(struct ieee80211_hw
*dev
,
393 struct ieee80211_tx_control
*control
,
396 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
397 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
398 struct rtl8180_priv
*priv
= dev
->priv
;
399 struct rtl8180_tx_ring
*ring
;
400 struct rtl8180_tx_desc
*entry
;
402 unsigned int idx
, prio
, hw_prio
;
407 __le16 rts_duration
= 0;
408 /* do arithmetic and then convert to le16 */
409 u16 frame_duration
= 0;
411 prio
= skb_get_queue_mapping(skb
);
412 ring
= &priv
->tx_ring
[prio
];
414 mapping
= pci_map_single(priv
->pdev
, skb
->data
,
415 skb
->len
, PCI_DMA_TODEVICE
);
417 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
419 dev_err(&priv
->pdev
->dev
, "TX DMA mapping error\n");
423 tx_flags
= RTL818X_TX_DESC_FLAG_OWN
| RTL818X_TX_DESC_FLAG_FS
|
424 RTL818X_TX_DESC_FLAG_LS
|
425 (ieee80211_get_tx_rate(dev
, info
)->hw_value
<< 24) |
428 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
429 tx_flags
|= RTL818X_TX_DESC_FLAG_DMA
|
430 RTL818X_TX_DESC_FLAG_NO_ENC
;
432 rc_flags
= info
->control
.rates
[0].flags
;
433 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
434 tx_flags
|= RTL818X_TX_DESC_FLAG_RTS
;
435 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
436 } else if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
437 tx_flags
|= RTL818X_TX_DESC_FLAG_CTS
;
438 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
441 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
442 rts_duration
= ieee80211_rts_duration(dev
, priv
->vif
, skb
->len
,
445 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
446 unsigned int remainder
;
448 plcp_len
= DIV_ROUND_UP(16 * (skb
->len
+ 4),
449 (ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
450 remainder
= (16 * (skb
->len
+ 4)) %
451 ((ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
456 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
458 /* SIFS time (required by HW) is already included by
459 * ieee80211_generic_frame_duration
461 duration
= ieee80211_generic_frame_duration(dev
, priv
->vif
,
462 IEEE80211_BAND_2GHZ
, skb
->len
,
463 ieee80211_get_tx_rate(dev
, info
));
465 frame_duration
= priv
->ack_time
+ le16_to_cpu(duration
);
468 spin_lock_irqsave(&priv
->lock
, flags
);
470 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
471 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
473 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
474 hdr
->seq_ctrl
|= cpu_to_le16(priv
->seqno
);
477 idx
= (ring
->idx
+ skb_queue_len(&ring
->queue
)) % ring
->entries
;
478 entry
= &ring
->desc
[idx
];
480 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
481 entry
->frame_duration
= cpu_to_le16(frame_duration
);
482 entry
->frame_len_se
= cpu_to_le16(skb
->len
);
485 entry
->flags3
= cpu_to_le16(1<<4);
487 entry
->frame_len
= cpu_to_le32(skb
->len
);
489 entry
->rts_duration
= rts_duration
;
490 entry
->plcp_len
= cpu_to_le16(plcp_len
);
491 entry
->tx_buf
= cpu_to_le32(mapping
);
493 entry
->flags2
= info
->control
.rates
[1].idx
>= 0 ?
494 ieee80211_get_alt_retry_rate(dev
, info
, 0)->bitrate
<< 4 : 0;
495 entry
->retry_limit
= info
->control
.rates
[0].count
;
497 /* We must be sure that tx_flags is written last because the HW
498 * looks at it to check if the rest of data is valid or not
501 entry
->flags
= cpu_to_le32(tx_flags
);
502 /* We must be sure this has been written before followings HW
503 * register write, because this write will made the HW attempts
504 * to DMA the just-written data
508 __skb_queue_tail(&ring
->queue
, skb
);
509 if (ring
->entries
- skb_queue_len(&ring
->queue
) < 2)
510 ieee80211_stop_queue(dev
, prio
);
512 spin_unlock_irqrestore(&priv
->lock
, flags
);
514 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
515 /* just poll: rings are stopped with TPPollStop reg */
516 hw_prio
= rtl8187se_queues_map
[prio
];
517 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
520 hw_prio
= rtl8180_queues_map
[prio
];
521 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
522 (1 << hw_prio
) | /* ring to poll */
523 (1<<1) | (1<<2));/* stopped rings */
527 static void rtl8180_set_anaparam3(struct rtl8180_priv
*priv
, u16 anaparam3
)
531 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
532 RTL818X_EEPROM_CMD_CONFIG
);
534 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
535 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
536 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
538 rtl818x_iowrite16(priv
, &priv
->map
->ANAPARAM3
, anaparam3
);
540 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
541 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
543 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
544 RTL818X_EEPROM_CMD_NORMAL
);
547 void rtl8180_set_anaparam2(struct rtl8180_priv
*priv
, u32 anaparam2
)
551 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
552 RTL818X_EEPROM_CMD_CONFIG
);
554 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
555 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
556 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
558 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM2
, anaparam2
);
560 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
561 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
563 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
564 RTL818X_EEPROM_CMD_NORMAL
);
567 void rtl8180_set_anaparam(struct rtl8180_priv
*priv
, u32 anaparam
)
571 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
572 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
573 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
574 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
575 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM
, anaparam
);
576 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
577 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
578 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
581 static void rtl8180_int_enable(struct ieee80211_hw
*dev
)
583 struct rtl8180_priv
*priv
= dev
->priv
;
585 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
586 rtl818x_iowrite32(priv
, &priv
->map
->IMR
, IMR_TMGDOK
|
587 IMR_TBDER
| IMR_THPDER
|
588 IMR_THPDER
| IMR_THPDOK
|
589 IMR_TVODER
| IMR_TVODOK
|
590 IMR_TVIDER
| IMR_TVIDOK
|
591 IMR_TBEDER
| IMR_TBEDOK
|
592 IMR_TBKDER
| IMR_TBKDOK
|
594 IMR_ROK
| IMR_RQOSOK
);
596 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0xFFFF);
600 static void rtl8180_int_disable(struct ieee80211_hw
*dev
)
602 struct rtl8180_priv
*priv
= dev
->priv
;
604 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
605 rtl818x_iowrite32(priv
, &priv
->map
->IMR
, 0);
607 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
611 static void rtl8180_conf_basic_rates(struct ieee80211_hw
*dev
,
614 struct rtl8180_priv
*priv
= dev
->priv
;
619 max
= fls(rates_mask
) - 1;
620 min
= ffs(rates_mask
) - 1;
622 switch (priv
->chip_family
) {
624 case RTL818X_CHIP_FAMILY_RTL8180
:
625 /* in 8180 this is NOT a BITMAP */
626 reg
= rtl818x_ioread16(priv
, &priv
->map
->BRSR
);
629 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, reg
);
632 case RTL818X_CHIP_FAMILY_RTL8185
:
633 /* in 8185 this is a BITMAP */
634 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, rates_mask
);
635 rtl818x_iowrite8(priv
, &priv
->map
->RESP_RATE
, (max
<< 4) | min
);
638 case RTL818X_CHIP_FAMILY_RTL8187SE
:
639 /* in 8187se this is a BITMAP */
640 rtl818x_iowrite16(priv
, &priv
->map
->BRSR_8187SE
, rates_mask
);
645 static void rtl8180_config_cardbus(struct ieee80211_hw
*dev
)
647 struct rtl8180_priv
*priv
= dev
->priv
;
651 reg8
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
653 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg8
);
655 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
656 rtl818x_iowrite16(priv
, FEMR_SE
, 0xffff);
658 reg16
= rtl818x_ioread16(priv
, &priv
->map
->FEMR
);
659 reg16
|= (1 << 15) | (1 << 14) | (1 << 4);
660 rtl818x_iowrite16(priv
, &priv
->map
->FEMR
, reg16
);
665 static int rtl8180_init_hw(struct ieee80211_hw
*dev
)
667 struct rtl8180_priv
*priv
= dev
->priv
;
670 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, 0);
671 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
675 rtl8180_int_disable(dev
);
676 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
678 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
680 reg
|= RTL818X_CMD_RESET
;
681 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, RTL818X_CMD_RESET
);
682 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
685 /* check success of reset */
686 if (rtl818x_ioread8(priv
, &priv
->map
->CMD
) & RTL818X_CMD_RESET
) {
687 wiphy_err(dev
->wiphy
, "reset timeout!\n");
691 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_LOAD
);
692 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
695 if (rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
) & (1 << 3)) {
696 rtl8180_config_cardbus(dev
);
699 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, 0);
701 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
702 rtl8180_set_anaparam(priv
, priv
->anaparam
);
704 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
705 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
, priv
->tx_ring
[1].dma
);
706 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
, priv
->tx_ring
[0].dma
);
708 /* TODO: necessary? specs indicate not */
709 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
710 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
711 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
& ~(1 << 3));
712 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
713 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
714 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
| (1 << 4));
716 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
718 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
720 /* TODO: turn off hw wep on rtl8180 */
722 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
724 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
725 rtl818x_iowrite8(priv
, &priv
->map
->WPA_CONF
, 0);
726 rtl818x_iowrite8(priv
, &priv
->map
->RATE_FALLBACK
, 0x81);
728 /* TODO: set ClkRun enable? necessary? */
729 reg
= rtl818x_ioread8(priv
, &priv
->map
->GP_ENABLE
);
730 rtl818x_iowrite8(priv
, &priv
->map
->GP_ENABLE
, reg
& ~(1 << 6));
731 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
732 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
733 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
| (1 << 2));
734 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
736 rtl818x_iowrite8(priv
, &priv
->map
->SECURITY
, 0);
738 rtl818x_iowrite8(priv
, &priv
->map
->PHY_DELAY
, 0x6);
739 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, 0x4C);
744 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
745 * otherwise. bitmask 0x3 and 0x01f3 respectively.
746 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
747 * this after rf init.
748 * TODO: try to find out whether RF code really needs to do this..
750 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
751 rtl8180_conf_basic_rates(dev
, 0x3);
753 rtl8180_conf_basic_rates(dev
, 0x1f3);
758 static int rtl8180_init_rx_ring(struct ieee80211_hw
*dev
)
760 struct rtl8180_priv
*priv
= dev
->priv
;
761 struct rtl818x_rx_cmd_desc
*entry
;
764 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
765 priv
->rx_ring_sz
= sizeof(struct rtl8187se_rx_desc
);
767 priv
->rx_ring_sz
= sizeof(struct rtl8180_rx_desc
);
769 priv
->rx_ring
= pci_alloc_consistent(priv
->pdev
,
770 priv
->rx_ring_sz
* 32,
773 if (!priv
->rx_ring
|| (unsigned long)priv
->rx_ring
& 0xFF) {
774 wiphy_err(dev
->wiphy
, "Cannot allocate RX ring\n");
778 memset(priv
->rx_ring
, 0, priv
->rx_ring_sz
* 32);
781 for (i
= 0; i
< 32; i
++) {
782 struct sk_buff
*skb
= dev_alloc_skb(MAX_RX_SIZE
);
784 entry
= priv
->rx_ring
+ priv
->rx_ring_sz
*i
;
786 wiphy_err(dev
->wiphy
, "Cannot allocate RX skb\n");
789 priv
->rx_buf
[i
] = skb
;
790 mapping
= (dma_addr_t
*)skb
->cb
;
791 *mapping
= pci_map_single(priv
->pdev
, skb_tail_pointer(skb
),
792 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
794 if (pci_dma_mapping_error(priv
->pdev
, *mapping
)) {
796 wiphy_err(dev
->wiphy
, "Cannot map DMA for RX skb\n");
800 entry
->rx_buf
= cpu_to_le32(*mapping
);
801 entry
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
804 entry
->flags
|= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
808 static void rtl8180_free_rx_ring(struct ieee80211_hw
*dev
)
810 struct rtl8180_priv
*priv
= dev
->priv
;
813 for (i
= 0; i
< 32; i
++) {
814 struct sk_buff
*skb
= priv
->rx_buf
[i
];
818 pci_unmap_single(priv
->pdev
,
819 *((dma_addr_t
*)skb
->cb
),
820 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
824 pci_free_consistent(priv
->pdev
, priv
->rx_ring_sz
* 32,
825 priv
->rx_ring
, priv
->rx_ring_dma
);
826 priv
->rx_ring
= NULL
;
829 static int rtl8180_init_tx_ring(struct ieee80211_hw
*dev
,
830 unsigned int prio
, unsigned int entries
)
832 struct rtl8180_priv
*priv
= dev
->priv
;
833 struct rtl8180_tx_desc
*ring
;
837 ring
= pci_alloc_consistent(priv
->pdev
, sizeof(*ring
) * entries
, &dma
);
838 if (!ring
|| (unsigned long)ring
& 0xFF) {
839 wiphy_err(dev
->wiphy
, "Cannot allocate TX ring (prio = %d)\n",
844 memset(ring
, 0, sizeof(*ring
)*entries
);
845 priv
->tx_ring
[prio
].desc
= ring
;
846 priv
->tx_ring
[prio
].dma
= dma
;
847 priv
->tx_ring
[prio
].idx
= 0;
848 priv
->tx_ring
[prio
].entries
= entries
;
849 skb_queue_head_init(&priv
->tx_ring
[prio
].queue
);
851 for (i
= 0; i
< entries
; i
++)
852 ring
[i
].next_tx_desc
=
853 cpu_to_le32((u32
)dma
+ ((i
+ 1) % entries
) * sizeof(*ring
));
858 static void rtl8180_free_tx_ring(struct ieee80211_hw
*dev
, unsigned int prio
)
860 struct rtl8180_priv
*priv
= dev
->priv
;
861 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
863 while (skb_queue_len(&ring
->queue
)) {
864 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
865 struct sk_buff
*skb
= __skb_dequeue(&ring
->queue
);
867 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
868 skb
->len
, PCI_DMA_TODEVICE
);
870 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
873 pci_free_consistent(priv
->pdev
, sizeof(*ring
->desc
)*ring
->entries
,
874 ring
->desc
, ring
->dma
);
878 static int rtl8180_start(struct ieee80211_hw
*dev
)
880 struct rtl8180_priv
*priv
= dev
->priv
;
884 ret
= rtl8180_init_rx_ring(dev
);
888 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
889 if ((ret
= rtl8180_init_tx_ring(dev
, i
, 16)))
892 ret
= rtl8180_init_hw(dev
);
896 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
897 ret
= request_irq(priv
->pdev
->irq
, rtl8187se_interrupt
,
898 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
900 ret
= request_irq(priv
->pdev
->irq
, rtl8180_interrupt
,
901 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
905 wiphy_err(dev
->wiphy
, "failed to register IRQ handler\n");
909 rtl8180_int_enable(dev
);
911 /* in rtl8187se at MAR regs offset there is the management
912 * TX descriptor DMA addres..
914 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8187SE
) {
915 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[0], ~0);
916 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[1], ~0);
919 reg
= RTL818X_RX_CONF_ONLYERLPKT
|
920 RTL818X_RX_CONF_RX_AUTORESETPHY
|
921 RTL818X_RX_CONF_MGMT
|
922 RTL818X_RX_CONF_DATA
|
923 (7 << 8 /* MAX RX DMA */) |
924 RTL818X_RX_CONF_BROADCAST
|
925 RTL818X_RX_CONF_NICMAC
;
927 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
)
928 reg
|= RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
;
930 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE1
)
931 ? RTL818X_RX_CONF_CSDM1
: 0;
932 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE2
)
933 ? RTL818X_RX_CONF_CSDM2
: 0;
937 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, reg
);
939 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
940 reg
= rtl818x_ioread8(priv
, &priv
->map
->CW_CONF
);
942 /* CW is not on per-packet basis.
943 * in rtl8185 the CW_VALUE reg is used.
945 reg
&= ~RTL818X_CW_CONF_PERPACKET_CW
;
946 /* retry limit IS on per-packet basis.
947 * the short and long retry limit in TX_CONF
950 reg
|= RTL818X_CW_CONF_PERPACKET_RETRY
;
951 rtl818x_iowrite8(priv
, &priv
->map
->CW_CONF
, reg
);
953 reg
= rtl818x_ioread8(priv
, &priv
->map
->TX_AGC_CTL
);
954 /* TX antenna and TX gain are not on per-packet basis.
955 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
956 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
958 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN
;
959 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL
;
960 reg
|= RTL818X_TX_AGC_CTL_FEEDBACK_ANT
;
961 rtl818x_iowrite8(priv
, &priv
->map
->TX_AGC_CTL
, reg
);
963 /* disable early TX */
964 rtl818x_iowrite8(priv
, (u8 __iomem
*)priv
->map
+ 0xec, 0x3f);
967 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
968 reg
|= (6 << 21 /* MAX TX DMA */) |
969 RTL818X_TX_CONF_NO_ICV
;
973 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
974 reg
&= ~RTL818X_TX_CONF_PROBE_DTS
;
976 reg
&= ~RTL818X_TX_CONF_HW_SEQNUM
;
978 reg
&= ~RTL818X_TX_CONF_DISCW
;
980 /* different meaning, same value on both rtl8185 and rtl8180 */
981 reg
&= ~RTL818X_TX_CONF_SAT_HWPLCP
;
983 rtl818x_iowrite32(priv
, &priv
->map
->TX_CONF
, reg
);
985 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
986 reg
|= RTL818X_CMD_RX_ENABLE
;
987 reg
|= RTL818X_CMD_TX_ENABLE
;
988 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
993 rtl8180_free_rx_ring(dev
);
994 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
995 if (priv
->tx_ring
[i
].desc
)
996 rtl8180_free_tx_ring(dev
, i
);
1001 static void rtl8180_stop(struct ieee80211_hw
*dev
)
1003 struct rtl8180_priv
*priv
= dev
->priv
;
1007 rtl8180_int_disable(dev
);
1009 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
1010 reg
&= ~RTL818X_CMD_TX_ENABLE
;
1011 reg
&= ~RTL818X_CMD_RX_ENABLE
;
1012 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
1014 priv
->rf
->stop(dev
);
1016 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1017 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG4
);
1018 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG4
, reg
| RTL818X_CONFIG4_VCOOFF
);
1019 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1021 free_irq(priv
->pdev
->irq
, dev
);
1023 rtl8180_free_rx_ring(dev
);
1024 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1025 rtl8180_free_tx_ring(dev
, i
);
1028 static u64
rtl8180_get_tsf(struct ieee80211_hw
*dev
,
1029 struct ieee80211_vif
*vif
)
1031 struct rtl8180_priv
*priv
= dev
->priv
;
1033 return rtl818x_ioread32(priv
, &priv
->map
->TSFT
[0]) |
1034 (u64
)(rtl818x_ioread32(priv
, &priv
->map
->TSFT
[1])) << 32;
1037 static void rtl8180_beacon_work(struct work_struct
*work
)
1039 struct rtl8180_vif
*vif_priv
=
1040 container_of(work
, struct rtl8180_vif
, beacon_work
.work
);
1041 struct ieee80211_vif
*vif
=
1042 container_of((void *)vif_priv
, struct ieee80211_vif
, drv_priv
);
1043 struct ieee80211_hw
*dev
= vif_priv
->dev
;
1044 struct ieee80211_mgmt
*mgmt
;
1045 struct sk_buff
*skb
;
1047 /* don't overflow the tx ring */
1048 if (ieee80211_queue_stopped(dev
, 0))
1051 /* grab a fresh beacon */
1052 skb
= ieee80211_beacon_get(dev
, vif
);
1057 * update beacon timestamp w/ TSF value
1058 * TODO: make hardware update beacon timestamp
1060 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1061 mgmt
->u
.beacon
.timestamp
= cpu_to_le64(rtl8180_get_tsf(dev
, vif
));
1063 /* TODO: use actual beacon queue */
1064 skb_set_queue_mapping(skb
, 0);
1066 rtl8180_tx(dev
, NULL
, skb
);
1070 * schedule next beacon
1071 * TODO: use hardware support for beacon timing
1073 schedule_delayed_work(&vif_priv
->beacon_work
,
1074 usecs_to_jiffies(1024 * vif
->bss_conf
.beacon_int
));
1077 static int rtl8180_add_interface(struct ieee80211_hw
*dev
,
1078 struct ieee80211_vif
*vif
)
1080 struct rtl8180_priv
*priv
= dev
->priv
;
1081 struct rtl8180_vif
*vif_priv
;
1084 * We only support one active interface at a time.
1089 switch (vif
->type
) {
1090 case NL80211_IFTYPE_STATION
:
1091 case NL80211_IFTYPE_ADHOC
:
1099 /* Initialize driver private area */
1100 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1101 vif_priv
->dev
= dev
;
1102 INIT_DELAYED_WORK(&vif_priv
->beacon_work
, rtl8180_beacon_work
);
1103 vif_priv
->enable_beacon
= false;
1105 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1106 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->MAC
[0],
1107 le32_to_cpu(*(__le32
*)vif
->addr
));
1108 rtl818x_iowrite16(priv
, (__le16 __iomem
*)&priv
->map
->MAC
[4],
1109 le16_to_cpu(*(__le16
*)(vif
->addr
+ 4)));
1110 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1115 static void rtl8180_remove_interface(struct ieee80211_hw
*dev
,
1116 struct ieee80211_vif
*vif
)
1118 struct rtl8180_priv
*priv
= dev
->priv
;
1122 static int rtl8180_config(struct ieee80211_hw
*dev
, u32 changed
)
1124 struct rtl8180_priv
*priv
= dev
->priv
;
1125 struct ieee80211_conf
*conf
= &dev
->conf
;
1127 priv
->rf
->set_chan(dev
, conf
);
1132 static int rtl8180_conf_tx(struct ieee80211_hw
*dev
,
1133 struct ieee80211_vif
*vif
, u16 queue
,
1134 const struct ieee80211_tx_queue_params
*params
)
1136 struct rtl8180_priv
*priv
= dev
->priv
;
1139 /* nothing to do ? */
1140 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1143 cw_min
= fls(params
->cw_min
);
1144 cw_max
= fls(params
->cw_max
);
1146 rtl818x_iowrite8(priv
, &priv
->map
->CW_VAL
, (cw_max
<< 4) | cw_min
);
1151 static void rtl8180_conf_erp(struct ieee80211_hw
*dev
,
1152 struct ieee80211_bss_conf
*info
)
1154 struct rtl8180_priv
*priv
= dev
->priv
;
1159 /* TODO: should we do something ? */
1160 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1163 /* I _hope_ this means 10uS for the HW.
1164 * In reference code it is 0x22 for
1165 * both rtl8187L and rtl8187SE
1169 if (info
->use_short_slot
)
1170 priv
->slot_time
= 9;
1172 priv
->slot_time
= 20;
1174 /* 10 is SIFS time in uS */
1175 difs
= 10 + 2 * priv
->slot_time
;
1176 eifs
= 10 + difs
+ priv
->ack_time
;
1178 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1179 hw_eifs
= DIV_ROUND_UP(eifs
, 4);
1182 rtl818x_iowrite8(priv
, &priv
->map
->SLOT
, priv
->slot_time
);
1183 rtl818x_iowrite8(priv
, &priv
->map
->SIFS
, sifs
);
1184 rtl818x_iowrite8(priv
, &priv
->map
->DIFS
, difs
);
1186 /* from reference code. set ack timeout reg = eifs reg */
1187 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, hw_eifs
);
1189 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1190 * the HW still wait for DIFS.
1191 * HW uses 4uS units for EIFS.
1193 hw_eifs
= DIV_ROUND_UP(eifs
- difs
, 4);
1195 rtl818x_iowrite8(priv
, &priv
->map
->EIFS
, hw_eifs
);
1198 static void rtl8180_bss_info_changed(struct ieee80211_hw
*dev
,
1199 struct ieee80211_vif
*vif
,
1200 struct ieee80211_bss_conf
*info
,
1203 struct rtl8180_priv
*priv
= dev
->priv
;
1204 struct rtl8180_vif
*vif_priv
;
1208 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1210 if (changed
& BSS_CHANGED_BSSID
) {
1211 for (i
= 0; i
< ETH_ALEN
; i
++)
1212 rtl818x_iowrite8(priv
, &priv
->map
->BSSID
[i
],
1215 if (is_valid_ether_addr(info
->bssid
)) {
1216 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
1217 reg
= RTL818X_MSR_ADHOC
;
1219 reg
= RTL818X_MSR_INFRA
;
1221 reg
= RTL818X_MSR_NO_LINK
;
1222 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, reg
);
1225 if (changed
& BSS_CHANGED_BASIC_RATES
)
1226 rtl8180_conf_basic_rates(dev
, info
->basic_rates
);
1228 if (changed
& (BSS_CHANGED_ERP_SLOT
| BSS_CHANGED_ERP_PREAMBLE
)) {
1230 /* when preamble changes, acktime duration changes, and erp must
1231 * be recalculated. ACK time is calculated at lowest rate.
1232 * Since mac80211 include SIFS time we remove it (-10)
1235 le16_to_cpu(ieee80211_generic_frame_duration(dev
,
1237 IEEE80211_BAND_2GHZ
, 10,
1238 &priv
->rates
[0])) - 10;
1240 rtl8180_conf_erp(dev
, info
);
1243 if (changed
& BSS_CHANGED_BEACON_ENABLED
)
1244 vif_priv
->enable_beacon
= info
->enable_beacon
;
1246 if (changed
& (BSS_CHANGED_BEACON_ENABLED
| BSS_CHANGED_BEACON
)) {
1247 cancel_delayed_work_sync(&vif_priv
->beacon_work
);
1248 if (vif_priv
->enable_beacon
)
1249 schedule_work(&vif_priv
->beacon_work
.work
);
1253 static u64
rtl8180_prepare_multicast(struct ieee80211_hw
*dev
,
1254 struct netdev_hw_addr_list
*mc_list
)
1256 return netdev_hw_addr_list_count(mc_list
);
1259 static void rtl8180_configure_filter(struct ieee80211_hw
*dev
,
1260 unsigned int changed_flags
,
1261 unsigned int *total_flags
,
1264 struct rtl8180_priv
*priv
= dev
->priv
;
1266 if (changed_flags
& FIF_FCSFAIL
)
1267 priv
->rx_conf
^= RTL818X_RX_CONF_FCS
;
1268 if (changed_flags
& FIF_CONTROL
)
1269 priv
->rx_conf
^= RTL818X_RX_CONF_CTRL
;
1270 if (changed_flags
& FIF_OTHER_BSS
)
1271 priv
->rx_conf
^= RTL818X_RX_CONF_MONITOR
;
1272 if (*total_flags
& FIF_ALLMULTI
|| multicast
> 0)
1273 priv
->rx_conf
|= RTL818X_RX_CONF_MULTICAST
;
1275 priv
->rx_conf
&= ~RTL818X_RX_CONF_MULTICAST
;
1279 if (priv
->rx_conf
& RTL818X_RX_CONF_FCS
)
1280 *total_flags
|= FIF_FCSFAIL
;
1281 if (priv
->rx_conf
& RTL818X_RX_CONF_CTRL
)
1282 *total_flags
|= FIF_CONTROL
;
1283 if (priv
->rx_conf
& RTL818X_RX_CONF_MONITOR
)
1284 *total_flags
|= FIF_OTHER_BSS
;
1285 if (priv
->rx_conf
& RTL818X_RX_CONF_MULTICAST
)
1286 *total_flags
|= FIF_ALLMULTI
;
1288 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, priv
->rx_conf
);
1291 static const struct ieee80211_ops rtl8180_ops
= {
1293 .start
= rtl8180_start
,
1294 .stop
= rtl8180_stop
,
1295 .add_interface
= rtl8180_add_interface
,
1296 .remove_interface
= rtl8180_remove_interface
,
1297 .config
= rtl8180_config
,
1298 .bss_info_changed
= rtl8180_bss_info_changed
,
1299 .conf_tx
= rtl8180_conf_tx
,
1300 .prepare_multicast
= rtl8180_prepare_multicast
,
1301 .configure_filter
= rtl8180_configure_filter
,
1302 .get_tsf
= rtl8180_get_tsf
,
1305 static void rtl8180_eeprom_register_read(struct eeprom_93cx6
*eeprom
)
1307 struct rtl8180_priv
*priv
= eeprom
->data
;
1308 u8 reg
= rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1310 eeprom
->reg_data_in
= reg
& RTL818X_EEPROM_CMD_WRITE
;
1311 eeprom
->reg_data_out
= reg
& RTL818X_EEPROM_CMD_READ
;
1312 eeprom
->reg_data_clock
= reg
& RTL818X_EEPROM_CMD_CK
;
1313 eeprom
->reg_chip_select
= reg
& RTL818X_EEPROM_CMD_CS
;
1316 static void rtl8180_eeprom_register_write(struct eeprom_93cx6
*eeprom
)
1318 struct rtl8180_priv
*priv
= eeprom
->data
;
1321 if (eeprom
->reg_data_in
)
1322 reg
|= RTL818X_EEPROM_CMD_WRITE
;
1323 if (eeprom
->reg_data_out
)
1324 reg
|= RTL818X_EEPROM_CMD_READ
;
1325 if (eeprom
->reg_data_clock
)
1326 reg
|= RTL818X_EEPROM_CMD_CK
;
1327 if (eeprom
->reg_chip_select
)
1328 reg
|= RTL818X_EEPROM_CMD_CS
;
1330 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, reg
);
1331 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1335 static void rtl8180_eeprom_read(struct rtl8180_priv
*priv
)
1337 struct eeprom_93cx6 eeprom
;
1338 int eeprom_cck_table_adr
;
1343 eeprom
.register_read
= rtl8180_eeprom_register_read
;
1344 eeprom
.register_write
= rtl8180_eeprom_register_write
;
1345 if (rtl818x_ioread32(priv
, &priv
->map
->RX_CONF
) & (1 << 6))
1346 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
1348 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
1350 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1351 RTL818X_EEPROM_CMD_PROGRAM
);
1352 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1355 eeprom_93cx6_read(&eeprom
, 0x06, &eeprom_val
);
1357 priv
->rf_type
= eeprom_val
;
1359 eeprom_93cx6_read(&eeprom
, 0x17, &eeprom_val
);
1360 priv
->csthreshold
= eeprom_val
>> 8;
1362 eeprom_93cx6_multiread(&eeprom
, 0x7, (__le16
*)priv
->mac_addr
, 3);
1364 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1365 eeprom_cck_table_adr
= 0x30;
1367 eeprom_cck_table_adr
= 0x10;
1370 for (i
= 0; i
< 14; i
+= 2) {
1372 eeprom_93cx6_read(&eeprom
, eeprom_cck_table_adr
+ (i
>> 1),
1374 priv
->channels
[i
].hw_value
= txpwr
& 0xFF;
1375 priv
->channels
[i
+ 1].hw_value
= txpwr
>> 8;
1379 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1380 for (i
= 0; i
< 14; i
+= 2) {
1382 eeprom_93cx6_read(&eeprom
, 0x20 + (i
>> 1), &txpwr
);
1383 priv
->channels
[i
].hw_value
|= (txpwr
& 0xFF) << 8;
1384 priv
->channels
[i
+ 1].hw_value
|= txpwr
& 0xFF00;
1388 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
1390 eeprom_93cx6_multiread(&eeprom
, 0xD, (__le16
*)&anaparam
, 2);
1391 priv
->anaparam
= le32_to_cpu(anaparam
);
1392 eeprom_93cx6_read(&eeprom
, 0x19, &priv
->rfparam
);
1395 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1396 eeprom_93cx6_read(&eeprom
, 0x3F, &eeprom_val
);
1397 priv
->antenna_diversity_en
= !!(eeprom_val
& 0x100);
1398 priv
->antenna_diversity_default
= (eeprom_val
& 0xC00) == 0x400;
1400 eeprom_93cx6_read(&eeprom
, 0x7C, &eeprom_val
);
1401 priv
->xtal_out
= eeprom_val
& 0xF;
1402 priv
->xtal_in
= (eeprom_val
& 0xF0) >> 4;
1403 priv
->xtal_cal
= !!(eeprom_val
& 0x1000);
1404 priv
->thermal_meter_val
= (eeprom_val
& 0xF00) >> 8;
1405 priv
->thermal_meter_en
= !!(eeprom_val
& 0x2000);
1408 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1409 RTL818X_EEPROM_CMD_NORMAL
);
1412 static int rtl8180_probe(struct pci_dev
*pdev
,
1413 const struct pci_device_id
*id
)
1415 struct ieee80211_hw
*dev
;
1416 struct rtl8180_priv
*priv
;
1417 unsigned long mem_addr
, mem_len
;
1418 unsigned int io_addr
, io_len
;
1420 const char *chip_name
, *rf_name
= NULL
;
1423 err
= pci_enable_device(pdev
);
1425 printk(KERN_ERR
"%s (rtl8180): Cannot enable new PCI device\n",
1430 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
1432 printk(KERN_ERR
"%s (rtl8180): Cannot obtain PCI resources\n",
1437 io_addr
= pci_resource_start(pdev
, 0);
1438 io_len
= pci_resource_len(pdev
, 0);
1439 mem_addr
= pci_resource_start(pdev
, 1);
1440 mem_len
= pci_resource_len(pdev
, 1);
1442 if (mem_len
< sizeof(struct rtl818x_csr
) ||
1443 io_len
< sizeof(struct rtl818x_csr
)) {
1444 printk(KERN_ERR
"%s (rtl8180): Too short PCI resources\n",
1450 if ((err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) ||
1451 (err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))) {
1452 printk(KERN_ERR
"%s (rtl8180): No suitable DMA available\n",
1457 pci_set_master(pdev
);
1459 dev
= ieee80211_alloc_hw(sizeof(*priv
), &rtl8180_ops
);
1461 printk(KERN_ERR
"%s (rtl8180): ieee80211 alloc failed\n",
1471 SET_IEEE80211_DEV(dev
, &pdev
->dev
);
1472 pci_set_drvdata(pdev
, dev
);
1474 priv
->map
= pci_iomap(pdev
, 1, mem_len
);
1476 priv
->map
= pci_iomap(pdev
, 0, io_len
);
1479 printk(KERN_ERR
"%s (rtl8180): Cannot map device memory\n",
1484 BUILD_BUG_ON(sizeof(priv
->channels
) != sizeof(rtl818x_channels
));
1485 BUILD_BUG_ON(sizeof(priv
->rates
) != sizeof(rtl818x_rates
));
1487 memcpy(priv
->channels
, rtl818x_channels
, sizeof(rtl818x_channels
));
1488 memcpy(priv
->rates
, rtl818x_rates
, sizeof(rtl818x_rates
));
1490 priv
->band
.band
= IEEE80211_BAND_2GHZ
;
1491 priv
->band
.channels
= priv
->channels
;
1492 priv
->band
.n_channels
= ARRAY_SIZE(rtl818x_channels
);
1493 priv
->band
.bitrates
= priv
->rates
;
1494 priv
->band
.n_bitrates
= 4;
1495 dev
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &priv
->band
;
1497 dev
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1498 IEEE80211_HW_RX_INCLUDES_FCS
|
1499 IEEE80211_HW_SIGNAL_UNSPEC
;
1500 dev
->vif_data_size
= sizeof(struct rtl8180_vif
);
1501 dev
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
) |
1502 BIT(NL80211_IFTYPE_ADHOC
);
1503 dev
->max_signal
= 65;
1505 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
1506 reg
&= RTL818X_TX_CONF_HWVER_MASK
;
1508 case RTL818X_TX_CONF_R8180_ABCD
:
1509 chip_name
= "RTL8180";
1510 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1513 case RTL818X_TX_CONF_R8180_F
:
1514 chip_name
= "RTL8180vF";
1515 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1518 case RTL818X_TX_CONF_R8185_ABC
:
1519 chip_name
= "RTL8185";
1520 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1523 case RTL818X_TX_CONF_R8185_D
:
1524 chip_name
= "RTL8185vD";
1525 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1528 printk(KERN_ERR
"%s (rtl8180): Unknown chip! (0x%x)\n",
1529 pci_name(pdev
), reg
>> 25);
1533 /* we declare to MAC80211 all the queues except for beacon queue
1534 * that will be eventually handled by DRV.
1535 * TX rings are arranged in such a way that lower is the IDX,
1536 * higher is the priority, in order to achieve direct mapping
1537 * with mac80211, however the beacon queue is an exception and it
1538 * is mapped on the highst tx ring IDX.
1540 dev
->queues
= RTL8180_NR_TX_QUEUES
- 1;
1542 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1543 priv
->band
.n_bitrates
= ARRAY_SIZE(rtl818x_rates
);
1544 pci_try_set_mwi(pdev
);
1547 rtl8180_eeprom_read(priv
);
1549 switch (priv
->rf_type
) {
1550 case 1: rf_name
= "Intersil";
1552 case 2: rf_name
= "RFMD";
1554 case 3: priv
->rf
= &sa2400_rf_ops
;
1556 case 4: priv
->rf
= &max2820_rf_ops
;
1558 case 5: priv
->rf
= &grf5101_rf_ops
;
1560 case 9: priv
->rf
= rtl8180_detect_rf(dev
);
1563 rf_name
= "RTL8255";
1566 printk(KERN_ERR
"%s (rtl8180): Unknown RF! (0x%x)\n",
1567 pci_name(pdev
), priv
->rf_type
);
1572 printk(KERN_ERR
"%s (rtl8180): %s RF frontend not supported!\n",
1573 pci_name(pdev
), rf_name
);
1577 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1578 printk(KERN_WARNING
"%s (rtl8180): Invalid hwaddr! Using"
1579 " randomly generated MAC addr\n", pci_name(pdev
));
1580 eth_random_addr(priv
->mac_addr
);
1582 SET_IEEE80211_PERM_ADDR(dev
, priv
->mac_addr
);
1584 spin_lock_init(&priv
->lock
);
1586 err
= ieee80211_register_hw(dev
);
1588 printk(KERN_ERR
"%s (rtl8180): Cannot register device\n",
1593 wiphy_info(dev
->wiphy
, "hwaddr %pm, %s + %s\n",
1594 priv
->mac_addr
, chip_name
, priv
->rf
->name
);
1599 pci_iounmap(pdev
, priv
->map
);
1602 ieee80211_free_hw(dev
);
1605 pci_release_regions(pdev
);
1606 pci_disable_device(pdev
);
1610 static void rtl8180_remove(struct pci_dev
*pdev
)
1612 struct ieee80211_hw
*dev
= pci_get_drvdata(pdev
);
1613 struct rtl8180_priv
*priv
;
1618 ieee80211_unregister_hw(dev
);
1622 pci_iounmap(pdev
, priv
->map
);
1623 pci_release_regions(pdev
);
1624 pci_disable_device(pdev
);
1625 ieee80211_free_hw(dev
);
1629 static int rtl8180_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1631 pci_save_state(pdev
);
1632 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1636 static int rtl8180_resume(struct pci_dev
*pdev
)
1638 pci_set_power_state(pdev
, PCI_D0
);
1639 pci_restore_state(pdev
);
1643 #endif /* CONFIG_PM */
1645 static struct pci_driver rtl8180_driver
= {
1646 .name
= KBUILD_MODNAME
,
1647 .id_table
= rtl8180_table
,
1648 .probe
= rtl8180_probe
,
1649 .remove
= rtl8180_remove
,
1651 .suspend
= rtl8180_suspend
,
1652 .resume
= rtl8180_resume
,
1653 #endif /* CONFIG_PM */
1656 module_pci_driver(rtl8180_driver
);