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[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
1
2 /*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
26
27 #include "rtl8180.h"
28 #include "rtl8225.h"
29 #include "sa2400.h"
30 #include "max2820.h"
31 #include "grf5101.h"
32
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
37
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
39 /* rtl8185 */
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
43
44 /* rtl8180 */
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
51 { }
52 };
53
54 MODULE_DEVICE_TABLE(pci, rtl8180_table);
55
56 static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
69 };
70
71 static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
86 };
87
88 /* Queues for rtl8180/rtl8185 cards
89 *
90 * name | reg | prio
91 * BC | 7 | 3
92 * HI | 6 | 0
93 * NO | 5 | 1
94 * LO | 4 | 2
95 *
96 * The complete map for DMA kick reg using all queue is:
97 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
98 *
99 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
100 * otherwise QoS can't be done, we use just one.
101 * Beacon queue could be used, but this is not finished yet.
102 * Actual map is:
103 *
104 * name | reg | prio
105 * BC | 7 | 1 <- currently not used yet.
106 * HI | 6 | x <- not used
107 * NO | 5 | x <- not used
108 * LO | 4 | 0 <- used
109 */
110
111 static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
112
113 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
114 {
115 struct rtl8180_priv *priv = dev->priv;
116 int i = 10;
117 u32 buf;
118
119 buf = (data << 8) | addr;
120
121 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
122 while (i--) {
123 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
124 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
125 return;
126 }
127 }
128
129 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
130 {
131 struct rtl8180_priv *priv = dev->priv;
132 struct rtl818x_rx_cmd_desc *cmd_desc;
133 unsigned int count = 32;
134 u8 signal, agc, sq;
135 dma_addr_t mapping;
136
137 while (count--) {
138 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz;
139 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
140 u32 flags, flags2;
141 u64 tsft;
142
143 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
144 struct rtl8187se_rx_desc *desc = entry;
145
146 flags = le32_to_cpu(desc->flags);
147 flags2 = le32_to_cpu(desc->flags2);
148 tsft = le64_to_cpu(desc->tsft);
149 } else {
150 struct rtl8180_rx_desc *desc = entry;
151
152 flags = le32_to_cpu(desc->flags);
153 flags2 = le32_to_cpu(desc->flags2);
154 tsft = le64_to_cpu(desc->tsft);
155 }
156
157 if (flags & RTL818X_RX_DESC_FLAG_OWN)
158 return;
159
160 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
161 RTL818X_RX_DESC_FLAG_FOF |
162 RTL818X_RX_DESC_FLAG_RX_ERR)))
163 goto done;
164 else {
165 struct ieee80211_rx_status rx_status = {0};
166 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
167
168 if (unlikely(!new_skb))
169 goto done;
170
171 mapping = pci_map_single(priv->pdev,
172 skb_tail_pointer(new_skb),
173 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
174
175 if (pci_dma_mapping_error(priv->pdev, mapping)) {
176 kfree_skb(new_skb);
177 dev_err(&priv->pdev->dev, "RX DMA map error\n");
178
179 goto done;
180 }
181
182 pci_unmap_single(priv->pdev,
183 *((dma_addr_t *)skb->cb),
184 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
185 skb_put(skb, flags & 0xFFF);
186
187 rx_status.antenna = (flags2 >> 15) & 1;
188 rx_status.rate_idx = (flags >> 20) & 0xF;
189 agc = (flags2 >> 17) & 0x7F;
190
191 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
192 if (rx_status.rate_idx > 3)
193 signal = 90 - clamp_t(u8, agc, 25, 90);
194 else
195 signal = 95 - clamp_t(u8, agc, 30, 95);
196 } else if (priv->chip_family ==
197 RTL818X_CHIP_FAMILY_RTL8180) {
198 sq = flags2 & 0xff;
199 signal = priv->rf->calc_rssi(agc, sq);
200 } else {
201 /* TODO: rtl8187se rssi */
202 signal = 10;
203 }
204 rx_status.signal = signal;
205 rx_status.freq = dev->conf.chandef.chan->center_freq;
206 rx_status.band = dev->conf.chandef.chan->band;
207 rx_status.mactime = tsft;
208 rx_status.flag |= RX_FLAG_MACTIME_START;
209 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
210 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
211
212 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
213 ieee80211_rx_irqsafe(dev, skb);
214
215 skb = new_skb;
216 priv->rx_buf[priv->rx_idx] = skb;
217 *((dma_addr_t *) skb->cb) = mapping;
218 }
219
220 done:
221 cmd_desc = entry;
222 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
223 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
224 MAX_RX_SIZE);
225 if (priv->rx_idx == 31)
226 cmd_desc->flags |=
227 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
228 priv->rx_idx = (priv->rx_idx + 1) % 32;
229 }
230 }
231
232 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
233 {
234 struct rtl8180_priv *priv = dev->priv;
235 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
236
237 while (skb_queue_len(&ring->queue)) {
238 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
239 struct sk_buff *skb;
240 struct ieee80211_tx_info *info;
241 u32 flags = le32_to_cpu(entry->flags);
242
243 if (flags & RTL818X_TX_DESC_FLAG_OWN)
244 return;
245
246 ring->idx = (ring->idx + 1) % ring->entries;
247 skb = __skb_dequeue(&ring->queue);
248 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
249 skb->len, PCI_DMA_TODEVICE);
250
251 info = IEEE80211_SKB_CB(skb);
252 ieee80211_tx_info_clear_status(info);
253
254 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
255 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
256 info->flags |= IEEE80211_TX_STAT_ACK;
257
258 info->status.rates[0].count = (flags & 0xFF) + 1;
259 info->status.rates[1].idx = -1;
260
261 ieee80211_tx_status_irqsafe(dev, skb);
262 if (ring->entries - skb_queue_len(&ring->queue) == 2)
263 ieee80211_wake_queue(dev, prio);
264 }
265 }
266
267 static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id)
268 {
269 struct ieee80211_hw *dev = dev_id;
270 struct rtl8180_priv *priv = dev->priv;
271 u32 reg;
272 unsigned long flags;
273 static int desc_err;
274
275 spin_lock_irqsave(&priv->lock, flags);
276 /* Note: 32-bit interrupt status */
277 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE);
278 if (unlikely(reg == 0xFFFFFFFF)) {
279 spin_unlock_irqrestore(&priv->lock, flags);
280 return IRQ_HANDLED;
281 }
282
283 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg);
284
285 if (reg & IMR_TIMEOUT1)
286 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
287
288 if (reg & (IMR_TBDOK | IMR_TBDER))
289 rtl8180_handle_tx(dev, 4);
290
291 if (reg & (IMR_TVODOK | IMR_TVODER))
292 rtl8180_handle_tx(dev, 0);
293
294 if (reg & (IMR_TVIDOK | IMR_TVIDER))
295 rtl8180_handle_tx(dev, 1);
296
297 if (reg & (IMR_TBEDOK | IMR_TBEDER))
298 rtl8180_handle_tx(dev, 2);
299
300 if (reg & (IMR_TBKDOK | IMR_TBKDER))
301 rtl8180_handle_tx(dev, 3);
302
303 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK))
304 rtl8180_handle_rx(dev);
305 /* The interface sometimes generates several RX DMA descriptor errors
306 * at startup. Do not report these.
307 */
308 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2)
309 if (net_ratelimit())
310 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n");
311
312 spin_unlock_irqrestore(&priv->lock, flags);
313 return IRQ_HANDLED;
314 }
315
316 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
317 {
318 struct ieee80211_hw *dev = dev_id;
319 struct rtl8180_priv *priv = dev->priv;
320 u16 reg;
321
322 spin_lock(&priv->lock);
323 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
324 if (unlikely(reg == 0xFFFF)) {
325 spin_unlock(&priv->lock);
326 return IRQ_HANDLED;
327 }
328
329 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
330
331 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
332 rtl8180_handle_tx(dev, 1);
333
334 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
335 rtl8180_handle_tx(dev, 0);
336
337 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
338 rtl8180_handle_rx(dev);
339
340 spin_unlock(&priv->lock);
341
342 return IRQ_HANDLED;
343 }
344
345 static void rtl8180_tx(struct ieee80211_hw *dev,
346 struct ieee80211_tx_control *control,
347 struct sk_buff *skb)
348 {
349 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
350 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
351 struct rtl8180_priv *priv = dev->priv;
352 struct rtl8180_tx_ring *ring;
353 struct rtl8180_tx_desc *entry;
354 unsigned long flags;
355 unsigned int idx, prio, hw_prio;
356 dma_addr_t mapping;
357 u32 tx_flags;
358 u8 rc_flags;
359 u16 plcp_len = 0;
360 __le16 rts_duration = 0;
361
362 prio = skb_get_queue_mapping(skb);
363 ring = &priv->tx_ring[prio];
364
365 mapping = pci_map_single(priv->pdev, skb->data,
366 skb->len, PCI_DMA_TODEVICE);
367
368 if (pci_dma_mapping_error(priv->pdev, mapping)) {
369 kfree_skb(skb);
370 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
371 return;
372
373 }
374
375 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
376 RTL818X_TX_DESC_FLAG_LS |
377 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
378 skb->len;
379
380 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
381 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
382 RTL818X_TX_DESC_FLAG_NO_ENC;
383
384 rc_flags = info->control.rates[0].flags;
385 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
386 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
387 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
388 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
389 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
390 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
391 }
392
393 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
394 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
395 info);
396
397 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
398 unsigned int remainder;
399
400 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
401 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
402 remainder = (16 * (skb->len + 4)) %
403 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
404 if (remainder <= 6)
405 plcp_len |= 1 << 15;
406 }
407
408 spin_lock_irqsave(&priv->lock, flags);
409
410 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
411 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
412 priv->seqno += 0x10;
413 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
414 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
415 }
416
417 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
418 entry = &ring->desc[idx];
419
420 entry->rts_duration = rts_duration;
421 entry->plcp_len = cpu_to_le16(plcp_len);
422 entry->tx_buf = cpu_to_le32(mapping);
423 entry->frame_len = cpu_to_le32(skb->len);
424 entry->flags2 = info->control.rates[1].idx >= 0 ?
425 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
426 entry->retry_limit = info->control.rates[0].count;
427
428 /* We must be sure that tx_flags is written last because the HW
429 * looks at it to check if the rest of data is valid or not
430 */
431 wmb();
432 entry->flags = cpu_to_le32(tx_flags);
433 /* We must be sure this has been written before followings HW
434 * register write, because this write will made the HW attempts
435 * to DMA the just-written data
436 */
437 wmb();
438
439 __skb_queue_tail(&ring->queue, skb);
440 if (ring->entries - skb_queue_len(&ring->queue) < 2)
441 ieee80211_stop_queue(dev, prio);
442
443 spin_unlock_irqrestore(&priv->lock, flags);
444
445 hw_prio = rtl8180_queues_map[prio];
446
447 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
448 (1 << hw_prio) | /* ring to poll */
449 (1<<1) | (1<<2));/* stopped rings */
450 }
451
452 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
453 {
454 u8 reg;
455
456 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
457 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
458 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
459 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
460 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
461 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
462 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
463 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
464 }
465
466 static void rtl8180_int_enable(struct ieee80211_hw *dev)
467 {
468 struct rtl8180_priv *priv = dev->priv;
469
470 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
471 rtl818x_iowrite32(priv, &priv->map->IMR, IMR_TMGDOK |
472 IMR_TBDER | IMR_THPDER |
473 IMR_THPDER | IMR_THPDOK |
474 IMR_TVODER | IMR_TVODOK |
475 IMR_TVIDER | IMR_TVIDOK |
476 IMR_TBEDER | IMR_TBEDOK |
477 IMR_TBKDER | IMR_TBKDOK |
478 IMR_RDU | IMR_RER |
479 IMR_ROK | IMR_RQOSOK);
480 } else {
481 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
482 }
483 }
484
485 static void rtl8180_int_disable(struct ieee80211_hw *dev)
486 {
487 struct rtl8180_priv *priv = dev->priv;
488
489 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
490 rtl818x_iowrite32(priv, &priv->map->IMR, 0);
491 } else {
492 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
493 }
494 }
495
496 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
497 u32 rates_mask)
498 {
499 struct rtl8180_priv *priv = dev->priv;
500
501 u8 max, min;
502 u16 reg;
503
504 max = fls(rates_mask) - 1;
505 min = ffs(rates_mask) - 1;
506
507 switch (priv->chip_family) {
508
509 case RTL818X_CHIP_FAMILY_RTL8180:
510 /* in 8180 this is NOT a BITMAP */
511 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
512 reg &= ~3;
513 reg |= max;
514 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
515 break;
516
517 case RTL818X_CHIP_FAMILY_RTL8185:
518 /* in 8185 this is a BITMAP */
519 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
520 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
521 break;
522
523 case RTL818X_CHIP_FAMILY_RTL8187SE:
524 /* in 8187se this is a BITMAP */
525 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, rates_mask);
526 break;
527 }
528 }
529
530 static int rtl8180_init_hw(struct ieee80211_hw *dev)
531 {
532 struct rtl8180_priv *priv = dev->priv;
533 u16 reg;
534
535 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
536 rtl818x_ioread8(priv, &priv->map->CMD);
537 msleep(10);
538
539 /* reset */
540 rtl8180_int_disable(dev);
541 rtl818x_ioread8(priv, &priv->map->CMD);
542
543 reg = rtl818x_ioread8(priv, &priv->map->CMD);
544 reg &= (1 << 1);
545 reg |= RTL818X_CMD_RESET;
546 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
547 rtl818x_ioread8(priv, &priv->map->CMD);
548 msleep(200);
549
550 /* check success of reset */
551 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
552 wiphy_err(dev->wiphy, "reset timeout!\n");
553 return -ETIMEDOUT;
554 }
555
556 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
557 rtl818x_ioread8(priv, &priv->map->CMD);
558 msleep(200);
559
560 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
561 /* For cardbus */
562 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
563 reg |= 1 << 1;
564 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
565 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
566 reg |= (1 << 15) | (1 << 14) | (1 << 4);
567 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
568 }
569
570 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
571
572 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
573 rtl8180_set_anaparam(priv, priv->anaparam);
574
575 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
576 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[1].dma);
577 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
578
579 /* TODO: necessary? specs indicate not */
580 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
581 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
582 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
583 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
584 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
585 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
586 }
587 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
588
589 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
590
591 /* TODO: turn off hw wep on rtl8180 */
592
593 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
594
595 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
596 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
597 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
598
599 /* TODO: set ClkRun enable? necessary? */
600 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
601 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
602 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
603 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
604 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
605 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
606 } else {
607 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
608
609 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
610 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
611 }
612
613 priv->rf->init(dev);
614
615 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
616 * otherwise. bitmask 0x3 and 0x01f3 respectively.
617 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
618 * this after rf init.
619 * TODO: try to find out whether RF code really needs to do this..
620 */
621 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
622 rtl8180_conf_basic_rates(dev, 0x3);
623 else
624 rtl8180_conf_basic_rates(dev, 0x1f3);
625
626 return 0;
627 }
628
629 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
630 {
631 struct rtl8180_priv *priv = dev->priv;
632 struct rtl818x_rx_cmd_desc *entry;
633 int i;
634
635 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
636 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc);
637 else
638 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc);
639
640 priv->rx_ring = pci_alloc_consistent(priv->pdev,
641 priv->rx_ring_sz * 32,
642 &priv->rx_ring_dma);
643
644 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
645 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
646 return -ENOMEM;
647 }
648
649 memset(priv->rx_ring, 0, priv->rx_ring_sz * 32);
650 priv->rx_idx = 0;
651
652 for (i = 0; i < 32; i++) {
653 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
654 dma_addr_t *mapping;
655 entry = priv->rx_ring + priv->rx_ring_sz*i;
656 if (!skb) {
657 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
658 return -ENOMEM;
659 }
660 priv->rx_buf[i] = skb;
661 mapping = (dma_addr_t *)skb->cb;
662 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
663 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
664
665 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
666 kfree_skb(skb);
667 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
668 return -ENOMEM;
669 }
670
671 entry->rx_buf = cpu_to_le32(*mapping);
672 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
673 MAX_RX_SIZE);
674 }
675 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
676 return 0;
677 }
678
679 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
680 {
681 struct rtl8180_priv *priv = dev->priv;
682 int i;
683
684 for (i = 0; i < 32; i++) {
685 struct sk_buff *skb = priv->rx_buf[i];
686 if (!skb)
687 continue;
688
689 pci_unmap_single(priv->pdev,
690 *((dma_addr_t *)skb->cb),
691 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
692 kfree_skb(skb);
693 }
694
695 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
696 priv->rx_ring, priv->rx_ring_dma);
697 priv->rx_ring = NULL;
698 }
699
700 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
701 unsigned int prio, unsigned int entries)
702 {
703 struct rtl8180_priv *priv = dev->priv;
704 struct rtl8180_tx_desc *ring;
705 dma_addr_t dma;
706 int i;
707
708 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
709 if (!ring || (unsigned long)ring & 0xFF) {
710 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
711 prio);
712 return -ENOMEM;
713 }
714
715 memset(ring, 0, sizeof(*ring)*entries);
716 priv->tx_ring[prio].desc = ring;
717 priv->tx_ring[prio].dma = dma;
718 priv->tx_ring[prio].idx = 0;
719 priv->tx_ring[prio].entries = entries;
720 skb_queue_head_init(&priv->tx_ring[prio].queue);
721
722 for (i = 0; i < entries; i++)
723 ring[i].next_tx_desc =
724 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
725
726 return 0;
727 }
728
729 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
730 {
731 struct rtl8180_priv *priv = dev->priv;
732 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
733
734 while (skb_queue_len(&ring->queue)) {
735 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
736 struct sk_buff *skb = __skb_dequeue(&ring->queue);
737
738 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
739 skb->len, PCI_DMA_TODEVICE);
740 kfree_skb(skb);
741 ring->idx = (ring->idx + 1) % ring->entries;
742 }
743
744 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
745 ring->desc, ring->dma);
746 ring->desc = NULL;
747 }
748
749 static int rtl8180_start(struct ieee80211_hw *dev)
750 {
751 struct rtl8180_priv *priv = dev->priv;
752 int ret, i;
753 u32 reg;
754
755 ret = rtl8180_init_rx_ring(dev);
756 if (ret)
757 return ret;
758
759 for (i = 0; i < (dev->queues + 1); i++)
760 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
761 goto err_free_rings;
762
763 ret = rtl8180_init_hw(dev);
764 if (ret)
765 goto err_free_rings;
766
767 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
768 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt,
769 IRQF_SHARED, KBUILD_MODNAME, dev);
770 } else {
771 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
772 IRQF_SHARED, KBUILD_MODNAME, dev);
773 }
774
775 if (ret) {
776 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
777 goto err_free_rings;
778 }
779
780 rtl8180_int_enable(dev);
781
782 /* in rtl8187se at MAR regs offset there is the management
783 * TX descriptor DMA addres..
784 */
785 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
786 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
787 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
788 }
789
790 reg = RTL818X_RX_CONF_ONLYERLPKT |
791 RTL818X_RX_CONF_RX_AUTORESETPHY |
792 RTL818X_RX_CONF_MGMT |
793 RTL818X_RX_CONF_DATA |
794 (7 << 8 /* MAX RX DMA */) |
795 RTL818X_RX_CONF_BROADCAST |
796 RTL818X_RX_CONF_NICMAC;
797
798 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
799 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
800 else {
801 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
802 ? RTL818X_RX_CONF_CSDM1 : 0;
803 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
804 ? RTL818X_RX_CONF_CSDM2 : 0;
805 }
806
807 priv->rx_conf = reg;
808 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
809
810 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
811 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
812
813 /* CW is not on per-packet basis.
814 * in rtl8185 the CW_VALUE reg is used.
815 */
816 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
817 /* retry limit IS on per-packet basis.
818 * the short and long retry limit in TX_CONF
819 * reg are ignored
820 */
821 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
822 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
823
824 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
825 /* TX antenna and TX gain are not on per-packet basis.
826 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
827 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
828 */
829 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
830 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
831 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
832 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
833
834 /* disable early TX */
835 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
836 }
837
838 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
839 reg |= (6 << 21 /* MAX TX DMA */) |
840 RTL818X_TX_CONF_NO_ICV;
841
842
843
844 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
845 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
846 else
847 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
848
849 reg &= ~RTL818X_TX_CONF_DISCW;
850
851 /* different meaning, same value on both rtl8185 and rtl8180 */
852 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
853
854 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
855
856 reg = rtl818x_ioread8(priv, &priv->map->CMD);
857 reg |= RTL818X_CMD_RX_ENABLE;
858 reg |= RTL818X_CMD_TX_ENABLE;
859 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
860
861 return 0;
862
863 err_free_rings:
864 rtl8180_free_rx_ring(dev);
865 for (i = 0; i < (dev->queues + 1); i++)
866 if (priv->tx_ring[i].desc)
867 rtl8180_free_tx_ring(dev, i);
868
869 return ret;
870 }
871
872 static void rtl8180_stop(struct ieee80211_hw *dev)
873 {
874 struct rtl8180_priv *priv = dev->priv;
875 u8 reg;
876 int i;
877
878 rtl8180_int_disable(dev);
879
880 reg = rtl818x_ioread8(priv, &priv->map->CMD);
881 reg &= ~RTL818X_CMD_TX_ENABLE;
882 reg &= ~RTL818X_CMD_RX_ENABLE;
883 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
884
885 priv->rf->stop(dev);
886
887 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
888 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
889 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
890 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
891
892 free_irq(priv->pdev->irq, dev);
893
894 rtl8180_free_rx_ring(dev);
895 for (i = 0; i < (dev->queues + 1); i++)
896 rtl8180_free_tx_ring(dev, i);
897 }
898
899 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
900 struct ieee80211_vif *vif)
901 {
902 struct rtl8180_priv *priv = dev->priv;
903
904 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
905 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
906 }
907
908 static void rtl8180_beacon_work(struct work_struct *work)
909 {
910 struct rtl8180_vif *vif_priv =
911 container_of(work, struct rtl8180_vif, beacon_work.work);
912 struct ieee80211_vif *vif =
913 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
914 struct ieee80211_hw *dev = vif_priv->dev;
915 struct ieee80211_mgmt *mgmt;
916 struct sk_buff *skb;
917
918 /* don't overflow the tx ring */
919 if (ieee80211_queue_stopped(dev, 0))
920 goto resched;
921
922 /* grab a fresh beacon */
923 skb = ieee80211_beacon_get(dev, vif);
924 if (!skb)
925 goto resched;
926
927 /*
928 * update beacon timestamp w/ TSF value
929 * TODO: make hardware update beacon timestamp
930 */
931 mgmt = (struct ieee80211_mgmt *)skb->data;
932 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
933
934 /* TODO: use actual beacon queue */
935 skb_set_queue_mapping(skb, 0);
936
937 rtl8180_tx(dev, NULL, skb);
938
939 resched:
940 /*
941 * schedule next beacon
942 * TODO: use hardware support for beacon timing
943 */
944 schedule_delayed_work(&vif_priv->beacon_work,
945 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
946 }
947
948 static int rtl8180_add_interface(struct ieee80211_hw *dev,
949 struct ieee80211_vif *vif)
950 {
951 struct rtl8180_priv *priv = dev->priv;
952 struct rtl8180_vif *vif_priv;
953
954 /*
955 * We only support one active interface at a time.
956 */
957 if (priv->vif)
958 return -EBUSY;
959
960 switch (vif->type) {
961 case NL80211_IFTYPE_STATION:
962 case NL80211_IFTYPE_ADHOC:
963 break;
964 default:
965 return -EOPNOTSUPP;
966 }
967
968 priv->vif = vif;
969
970 /* Initialize driver private area */
971 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
972 vif_priv->dev = dev;
973 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
974 vif_priv->enable_beacon = false;
975
976 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
977 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
978 le32_to_cpu(*(__le32 *)vif->addr));
979 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
980 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
981 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
982
983 return 0;
984 }
985
986 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
987 struct ieee80211_vif *vif)
988 {
989 struct rtl8180_priv *priv = dev->priv;
990 priv->vif = NULL;
991 }
992
993 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
994 {
995 struct rtl8180_priv *priv = dev->priv;
996 struct ieee80211_conf *conf = &dev->conf;
997
998 priv->rf->set_chan(dev, conf);
999
1000 return 0;
1001 }
1002
1003 static int rtl8180_conf_tx(struct ieee80211_hw *dev,
1004 struct ieee80211_vif *vif, u16 queue,
1005 const struct ieee80211_tx_queue_params *params)
1006 {
1007 struct rtl8180_priv *priv = dev->priv;
1008 u8 cw_min, cw_max;
1009
1010 /* nothing to do ? */
1011 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1012 return 0;
1013
1014 cw_min = fls(params->cw_min);
1015 cw_max = fls(params->cw_max);
1016
1017 rtl818x_iowrite8(priv, &priv->map->CW_VAL, (cw_max << 4) | cw_min);
1018
1019 return 0;
1020 }
1021
1022 static void rtl8180_conf_erp(struct ieee80211_hw *dev,
1023 struct ieee80211_bss_conf *info)
1024 {
1025 struct rtl8180_priv *priv = dev->priv;
1026 u8 sifs, difs;
1027 int eifs;
1028 u8 hw_eifs;
1029
1030 /* TODO: should we do something ? */
1031 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1032 return;
1033
1034 /* I _hope_ this means 10uS for the HW.
1035 * In reference code it is 0x22 for
1036 * both rtl8187L and rtl8187SE
1037 */
1038 sifs = 0x22;
1039
1040 if (info->use_short_slot)
1041 priv->slot_time = 9;
1042 else
1043 priv->slot_time = 20;
1044
1045 /* 10 is SIFS time in uS */
1046 difs = 10 + 2 * priv->slot_time;
1047 eifs = 10 + difs + priv->ack_time;
1048
1049 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1050 hw_eifs = DIV_ROUND_UP(eifs, 4);
1051
1052
1053 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1054 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
1055 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1056
1057 /* from reference code. set ack timeout reg = eifs reg */
1058 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
1059
1060 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1061 * the HW still wait for DIFS.
1062 * HW uses 4uS units for EIFS.
1063 */
1064 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
1065
1066 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
1067 }
1068
1069 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
1070 struct ieee80211_vif *vif,
1071 struct ieee80211_bss_conf *info,
1072 u32 changed)
1073 {
1074 struct rtl8180_priv *priv = dev->priv;
1075 struct rtl8180_vif *vif_priv;
1076 int i;
1077 u8 reg;
1078
1079 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1080
1081 if (changed & BSS_CHANGED_BSSID) {
1082 for (i = 0; i < ETH_ALEN; i++)
1083 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1084 info->bssid[i]);
1085
1086 if (is_valid_ether_addr(info->bssid)) {
1087 if (vif->type == NL80211_IFTYPE_ADHOC)
1088 reg = RTL818X_MSR_ADHOC;
1089 else
1090 reg = RTL818X_MSR_INFRA;
1091 } else
1092 reg = RTL818X_MSR_NO_LINK;
1093 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1094 }
1095
1096 if (changed & BSS_CHANGED_BASIC_RATES)
1097 rtl8180_conf_basic_rates(dev, info->basic_rates);
1098
1099 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
1100
1101 /* when preamble changes, acktime duration changes, and erp must
1102 * be recalculated. ACK time is calculated at lowest rate.
1103 * Since mac80211 include SIFS time we remove it (-10)
1104 */
1105 priv->ack_time =
1106 le16_to_cpu(ieee80211_generic_frame_duration(dev,
1107 priv->vif,
1108 IEEE80211_BAND_2GHZ, 10,
1109 &priv->rates[0])) - 10;
1110
1111 rtl8180_conf_erp(dev, info);
1112 }
1113
1114 if (changed & BSS_CHANGED_BEACON_ENABLED)
1115 vif_priv->enable_beacon = info->enable_beacon;
1116
1117 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1118 cancel_delayed_work_sync(&vif_priv->beacon_work);
1119 if (vif_priv->enable_beacon)
1120 schedule_work(&vif_priv->beacon_work.work);
1121 }
1122 }
1123
1124 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1125 struct netdev_hw_addr_list *mc_list)
1126 {
1127 return netdev_hw_addr_list_count(mc_list);
1128 }
1129
1130 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1131 unsigned int changed_flags,
1132 unsigned int *total_flags,
1133 u64 multicast)
1134 {
1135 struct rtl8180_priv *priv = dev->priv;
1136
1137 if (changed_flags & FIF_FCSFAIL)
1138 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1139 if (changed_flags & FIF_CONTROL)
1140 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1141 if (changed_flags & FIF_OTHER_BSS)
1142 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1143 if (*total_flags & FIF_ALLMULTI || multicast > 0)
1144 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1145 else
1146 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1147
1148 *total_flags = 0;
1149
1150 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1151 *total_flags |= FIF_FCSFAIL;
1152 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1153 *total_flags |= FIF_CONTROL;
1154 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1155 *total_flags |= FIF_OTHER_BSS;
1156 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1157 *total_flags |= FIF_ALLMULTI;
1158
1159 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1160 }
1161
1162 static const struct ieee80211_ops rtl8180_ops = {
1163 .tx = rtl8180_tx,
1164 .start = rtl8180_start,
1165 .stop = rtl8180_stop,
1166 .add_interface = rtl8180_add_interface,
1167 .remove_interface = rtl8180_remove_interface,
1168 .config = rtl8180_config,
1169 .bss_info_changed = rtl8180_bss_info_changed,
1170 .conf_tx = rtl8180_conf_tx,
1171 .prepare_multicast = rtl8180_prepare_multicast,
1172 .configure_filter = rtl8180_configure_filter,
1173 .get_tsf = rtl8180_get_tsf,
1174 };
1175
1176 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1177 {
1178 struct rtl8180_priv *priv = eeprom->data;
1179 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1180
1181 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1182 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1183 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1184 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1185 }
1186
1187 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1188 {
1189 struct rtl8180_priv *priv = eeprom->data;
1190 u8 reg = 2 << 6;
1191
1192 if (eeprom->reg_data_in)
1193 reg |= RTL818X_EEPROM_CMD_WRITE;
1194 if (eeprom->reg_data_out)
1195 reg |= RTL818X_EEPROM_CMD_READ;
1196 if (eeprom->reg_data_clock)
1197 reg |= RTL818X_EEPROM_CMD_CK;
1198 if (eeprom->reg_chip_select)
1199 reg |= RTL818X_EEPROM_CMD_CS;
1200
1201 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1202 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1203 udelay(10);
1204 }
1205
1206 static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1207 {
1208 struct eeprom_93cx6 eeprom;
1209 int eeprom_cck_table_adr;
1210 u16 eeprom_val;
1211 int i;
1212
1213 eeprom.data = priv;
1214 eeprom.register_read = rtl8180_eeprom_register_read;
1215 eeprom.register_write = rtl8180_eeprom_register_write;
1216 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1217 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1218 else
1219 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1220
1221 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1222 RTL818X_EEPROM_CMD_PROGRAM);
1223 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1224 udelay(10);
1225
1226 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1227 eeprom_val &= 0xFF;
1228 priv->rf_type = eeprom_val;
1229
1230 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1231 priv->csthreshold = eeprom_val >> 8;
1232
1233 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1234
1235 eeprom_cck_table_adr = 0x10;
1236
1237 /* CCK TX power */
1238 for (i = 0; i < 14; i += 2) {
1239 u16 txpwr;
1240 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1241 &txpwr);
1242 priv->channels[i].hw_value = txpwr & 0xFF;
1243 priv->channels[i + 1].hw_value = txpwr >> 8;
1244 }
1245
1246 /* OFDM TX power */
1247 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1248 for (i = 0; i < 14; i += 2) {
1249 u16 txpwr;
1250 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1251 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1252 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1253 }
1254 }
1255
1256 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1257 __le32 anaparam;
1258 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1259 priv->anaparam = le32_to_cpu(anaparam);
1260 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1261 }
1262
1263 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1264 RTL818X_EEPROM_CMD_NORMAL);
1265 }
1266
1267 static int rtl8180_probe(struct pci_dev *pdev,
1268 const struct pci_device_id *id)
1269 {
1270 struct ieee80211_hw *dev;
1271 struct rtl8180_priv *priv;
1272 unsigned long mem_addr, mem_len;
1273 unsigned int io_addr, io_len;
1274 int err;
1275 const char *chip_name, *rf_name = NULL;
1276 u32 reg;
1277
1278 err = pci_enable_device(pdev);
1279 if (err) {
1280 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1281 pci_name(pdev));
1282 return err;
1283 }
1284
1285 err = pci_request_regions(pdev, KBUILD_MODNAME);
1286 if (err) {
1287 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1288 pci_name(pdev));
1289 return err;
1290 }
1291
1292 io_addr = pci_resource_start(pdev, 0);
1293 io_len = pci_resource_len(pdev, 0);
1294 mem_addr = pci_resource_start(pdev, 1);
1295 mem_len = pci_resource_len(pdev, 1);
1296
1297 if (mem_len < sizeof(struct rtl818x_csr) ||
1298 io_len < sizeof(struct rtl818x_csr)) {
1299 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1300 pci_name(pdev));
1301 err = -ENOMEM;
1302 goto err_free_reg;
1303 }
1304
1305 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1306 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1307 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1308 pci_name(pdev));
1309 goto err_free_reg;
1310 }
1311
1312 pci_set_master(pdev);
1313
1314 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1315 if (!dev) {
1316 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1317 pci_name(pdev));
1318 err = -ENOMEM;
1319 goto err_free_reg;
1320 }
1321
1322 priv = dev->priv;
1323 priv->pdev = pdev;
1324
1325 dev->max_rates = 2;
1326 SET_IEEE80211_DEV(dev, &pdev->dev);
1327 pci_set_drvdata(pdev, dev);
1328
1329 priv->map = pci_iomap(pdev, 1, mem_len);
1330 if (!priv->map)
1331 priv->map = pci_iomap(pdev, 0, io_len);
1332
1333 if (!priv->map) {
1334 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1335 pci_name(pdev));
1336 goto err_free_dev;
1337 }
1338
1339 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1340 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1341
1342 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1343 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1344
1345 priv->band.band = IEEE80211_BAND_2GHZ;
1346 priv->band.channels = priv->channels;
1347 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1348 priv->band.bitrates = priv->rates;
1349 priv->band.n_bitrates = 4;
1350 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1351
1352 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1353 IEEE80211_HW_RX_INCLUDES_FCS |
1354 IEEE80211_HW_SIGNAL_UNSPEC;
1355 dev->vif_data_size = sizeof(struct rtl8180_vif);
1356 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1357 BIT(NL80211_IFTYPE_ADHOC);
1358 dev->max_signal = 65;
1359
1360 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1361 reg &= RTL818X_TX_CONF_HWVER_MASK;
1362 switch (reg) {
1363 case RTL818X_TX_CONF_R8180_ABCD:
1364 chip_name = "RTL8180";
1365 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1366 break;
1367
1368 case RTL818X_TX_CONF_R8180_F:
1369 chip_name = "RTL8180vF";
1370 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1371 break;
1372
1373 case RTL818X_TX_CONF_R8185_ABC:
1374 chip_name = "RTL8185";
1375 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1376 break;
1377
1378 case RTL818X_TX_CONF_R8185_D:
1379 chip_name = "RTL8185vD";
1380 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1381 break;
1382 default:
1383 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1384 pci_name(pdev), reg >> 25);
1385 goto err_iounmap;
1386 }
1387
1388 /* we declare to MAC80211 all the queues except for beacon queue
1389 * that will be eventually handled by DRV.
1390 * TX rings are arranged in such a way that lower is the IDX,
1391 * higher is the priority, in order to achieve direct mapping
1392 * with mac80211, however the beacon queue is an exception and it
1393 * is mapped on the highst tx ring IDX.
1394 */
1395 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1396
1397 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1398 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1399 pci_try_set_mwi(pdev);
1400 }
1401
1402 rtl8180_eeprom_read(priv);
1403
1404 switch (priv->rf_type) {
1405 case 1: rf_name = "Intersil";
1406 break;
1407 case 2: rf_name = "RFMD";
1408 break;
1409 case 3: priv->rf = &sa2400_rf_ops;
1410 break;
1411 case 4: priv->rf = &max2820_rf_ops;
1412 break;
1413 case 5: priv->rf = &grf5101_rf_ops;
1414 break;
1415 case 9: priv->rf = rtl8180_detect_rf(dev);
1416 break;
1417 case 10:
1418 rf_name = "RTL8255";
1419 break;
1420 default:
1421 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1422 pci_name(pdev), priv->rf_type);
1423 goto err_iounmap;
1424 }
1425
1426 if (!priv->rf) {
1427 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1428 pci_name(pdev), rf_name);
1429 goto err_iounmap;
1430 }
1431
1432 if (!is_valid_ether_addr(priv->mac_addr)) {
1433 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1434 " randomly generated MAC addr\n", pci_name(pdev));
1435 eth_random_addr(priv->mac_addr);
1436 }
1437 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
1438
1439 spin_lock_init(&priv->lock);
1440
1441 err = ieee80211_register_hw(dev);
1442 if (err) {
1443 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1444 pci_name(pdev));
1445 goto err_iounmap;
1446 }
1447
1448 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1449 priv->mac_addr, chip_name, priv->rf->name);
1450
1451 return 0;
1452
1453 err_iounmap:
1454 pci_iounmap(pdev, priv->map);
1455
1456 err_free_dev:
1457 ieee80211_free_hw(dev);
1458
1459 err_free_reg:
1460 pci_release_regions(pdev);
1461 pci_disable_device(pdev);
1462 return err;
1463 }
1464
1465 static void rtl8180_remove(struct pci_dev *pdev)
1466 {
1467 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1468 struct rtl8180_priv *priv;
1469
1470 if (!dev)
1471 return;
1472
1473 ieee80211_unregister_hw(dev);
1474
1475 priv = dev->priv;
1476
1477 pci_iounmap(pdev, priv->map);
1478 pci_release_regions(pdev);
1479 pci_disable_device(pdev);
1480 ieee80211_free_hw(dev);
1481 }
1482
1483 #ifdef CONFIG_PM
1484 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1485 {
1486 pci_save_state(pdev);
1487 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1488 return 0;
1489 }
1490
1491 static int rtl8180_resume(struct pci_dev *pdev)
1492 {
1493 pci_set_power_state(pdev, PCI_D0);
1494 pci_restore_state(pdev);
1495 return 0;
1496 }
1497
1498 #endif /* CONFIG_PM */
1499
1500 static struct pci_driver rtl8180_driver = {
1501 .name = KBUILD_MODNAME,
1502 .id_table = rtl8180_table,
1503 .probe = rtl8180_probe,
1504 .remove = rtl8180_remove,
1505 #ifdef CONFIG_PM
1506 .suspend = rtl8180_suspend,
1507 .resume = rtl8180_resume,
1508 #endif /* CONFIG_PM */
1509 };
1510
1511 module_pci_driver(rtl8180_driver);
Linux kernel - Deliverables
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