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Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
1
2 /*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
26
27 #include "rtl8180.h"
28 #include "rtl8225.h"
29 #include "sa2400.h"
30 #include "max2820.h"
31 #include "grf5101.h"
32
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
37
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
39 /* rtl8185 */
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
43
44 /* rtl8180 */
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
51 { }
52 };
53
54 MODULE_DEVICE_TABLE(pci, rtl8180_table);
55
56 static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
69 };
70
71 static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
86 };
87
88
89 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
90 {
91 struct rtl8180_priv *priv = dev->priv;
92 int i = 10;
93 u32 buf;
94
95 buf = (data << 8) | addr;
96
97 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
98 while (i--) {
99 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
100 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
101 return;
102 }
103 }
104
105 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
106 {
107 struct rtl8180_priv *priv = dev->priv;
108 unsigned int count = 32;
109 u8 signal, agc, sq;
110
111 while (count--) {
112 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
113 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
114 u32 flags = le32_to_cpu(entry->flags);
115
116 if (flags & RTL818X_RX_DESC_FLAG_OWN)
117 return;
118
119 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
120 RTL818X_RX_DESC_FLAG_FOF |
121 RTL818X_RX_DESC_FLAG_RX_ERR)))
122 goto done;
123 else {
124 u32 flags2 = le32_to_cpu(entry->flags2);
125 struct ieee80211_rx_status rx_status = {0};
126 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
127
128 if (unlikely(!new_skb))
129 goto done;
130
131 pci_unmap_single(priv->pdev,
132 *((dma_addr_t *)skb->cb),
133 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
134 skb_put(skb, flags & 0xFFF);
135
136 rx_status.antenna = (flags2 >> 15) & 1;
137 rx_status.rate_idx = (flags >> 20) & 0xF;
138 agc = (flags2 >> 17) & 0x7F;
139 if (priv->r8185) {
140 if (rx_status.rate_idx > 3)
141 signal = 90 - clamp_t(u8, agc, 25, 90);
142 else
143 signal = 95 - clamp_t(u8, agc, 30, 95);
144 } else {
145 sq = flags2 & 0xff;
146 signal = priv->rf->calc_rssi(agc, sq);
147 }
148 rx_status.signal = signal;
149 rx_status.freq = dev->conf.chandef.chan->center_freq;
150 rx_status.band = dev->conf.chandef.chan->band;
151 rx_status.mactime = le64_to_cpu(entry->tsft);
152 rx_status.flag |= RX_FLAG_MACTIME_START;
153 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
154 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
155
156 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
157 ieee80211_rx_irqsafe(dev, skb);
158
159 skb = new_skb;
160 priv->rx_buf[priv->rx_idx] = skb;
161 *((dma_addr_t *) skb->cb) =
162 pci_map_single(priv->pdev, skb_tail_pointer(skb),
163 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
164 }
165
166 done:
167 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
168 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
169 MAX_RX_SIZE);
170 if (priv->rx_idx == 31)
171 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
172 priv->rx_idx = (priv->rx_idx + 1) % 32;
173 }
174 }
175
176 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
177 {
178 struct rtl8180_priv *priv = dev->priv;
179 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
180
181 while (skb_queue_len(&ring->queue)) {
182 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
183 struct sk_buff *skb;
184 struct ieee80211_tx_info *info;
185 u32 flags = le32_to_cpu(entry->flags);
186
187 if (flags & RTL818X_TX_DESC_FLAG_OWN)
188 return;
189
190 ring->idx = (ring->idx + 1) % ring->entries;
191 skb = __skb_dequeue(&ring->queue);
192 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
193 skb->len, PCI_DMA_TODEVICE);
194
195 info = IEEE80211_SKB_CB(skb);
196 ieee80211_tx_info_clear_status(info);
197
198 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
199 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
200 info->flags |= IEEE80211_TX_STAT_ACK;
201
202 info->status.rates[0].count = (flags & 0xFF) + 1;
203 info->status.rates[1].idx = -1;
204
205 ieee80211_tx_status_irqsafe(dev, skb);
206 if (ring->entries - skb_queue_len(&ring->queue) == 2)
207 ieee80211_wake_queue(dev, prio);
208 }
209 }
210
211 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
212 {
213 struct ieee80211_hw *dev = dev_id;
214 struct rtl8180_priv *priv = dev->priv;
215 u16 reg;
216
217 spin_lock(&priv->lock);
218 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
219 if (unlikely(reg == 0xFFFF)) {
220 spin_unlock(&priv->lock);
221 return IRQ_HANDLED;
222 }
223
224 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
225
226 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
227 rtl8180_handle_tx(dev, 3);
228
229 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
230 rtl8180_handle_tx(dev, 2);
231
232 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
233 rtl8180_handle_tx(dev, 1);
234
235 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
236 rtl8180_handle_tx(dev, 0);
237
238 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
239 rtl8180_handle_rx(dev);
240
241 spin_unlock(&priv->lock);
242
243 return IRQ_HANDLED;
244 }
245
246 static void rtl8180_tx(struct ieee80211_hw *dev,
247 struct ieee80211_tx_control *control,
248 struct sk_buff *skb)
249 {
250 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
251 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
252 struct rtl8180_priv *priv = dev->priv;
253 struct rtl8180_tx_ring *ring;
254 struct rtl8180_tx_desc *entry;
255 unsigned long flags;
256 unsigned int idx, prio;
257 dma_addr_t mapping;
258 u32 tx_flags;
259 u8 rc_flags;
260 u16 plcp_len = 0;
261 __le16 rts_duration = 0;
262
263 prio = skb_get_queue_mapping(skb);
264 ring = &priv->tx_ring[prio];
265
266 mapping = pci_map_single(priv->pdev, skb->data,
267 skb->len, PCI_DMA_TODEVICE);
268
269 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
270 RTL818X_TX_DESC_FLAG_LS |
271 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
272 skb->len;
273
274 if (priv->r8185)
275 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
276 RTL818X_TX_DESC_FLAG_NO_ENC;
277
278 rc_flags = info->control.rates[0].flags;
279 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
280 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
281 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
282 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
283 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
284 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
285 }
286
287 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
288 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
289 info);
290
291 if (!priv->r8185) {
292 unsigned int remainder;
293
294 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
295 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
296 remainder = (16 * (skb->len + 4)) %
297 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
298 if (remainder <= 6)
299 plcp_len |= 1 << 15;
300 }
301
302 spin_lock_irqsave(&priv->lock, flags);
303
304 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
305 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
306 priv->seqno += 0x10;
307 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
308 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
309 }
310
311 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
312 entry = &ring->desc[idx];
313
314 entry->rts_duration = rts_duration;
315 entry->plcp_len = cpu_to_le16(plcp_len);
316 entry->tx_buf = cpu_to_le32(mapping);
317 entry->frame_len = cpu_to_le32(skb->len);
318 entry->flags2 = info->control.rates[1].idx >= 0 ?
319 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
320 entry->retry_limit = info->control.rates[0].count;
321 entry->flags = cpu_to_le32(tx_flags);
322 __skb_queue_tail(&ring->queue, skb);
323 if (ring->entries - skb_queue_len(&ring->queue) < 2)
324 ieee80211_stop_queue(dev, prio);
325
326 spin_unlock_irqrestore(&priv->lock, flags);
327
328 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
329 }
330
331 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
332 {
333 u8 reg;
334
335 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
336 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
337 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
338 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
339 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
340 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
341 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
342 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
343 }
344
345 static int rtl8180_init_hw(struct ieee80211_hw *dev)
346 {
347 struct rtl8180_priv *priv = dev->priv;
348 u16 reg;
349
350 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
351 rtl818x_ioread8(priv, &priv->map->CMD);
352 msleep(10);
353
354 /* reset */
355 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
356 rtl818x_ioread8(priv, &priv->map->CMD);
357
358 reg = rtl818x_ioread8(priv, &priv->map->CMD);
359 reg &= (1 << 1);
360 reg |= RTL818X_CMD_RESET;
361 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
362 rtl818x_ioread8(priv, &priv->map->CMD);
363 msleep(200);
364
365 /* check success of reset */
366 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
367 wiphy_err(dev->wiphy, "reset timeout!\n");
368 return -ETIMEDOUT;
369 }
370
371 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
372 rtl818x_ioread8(priv, &priv->map->CMD);
373 msleep(200);
374
375 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
376 /* For cardbus */
377 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
378 reg |= 1 << 1;
379 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
380 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
381 reg |= (1 << 15) | (1 << 14) | (1 << 4);
382 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
383 }
384
385 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
386
387 if (!priv->r8185)
388 rtl8180_set_anaparam(priv, priv->anaparam);
389
390 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
391 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
392 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
393 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
394 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
395
396 /* TODO: necessary? specs indicate not */
397 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
398 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
399 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
400 if (priv->r8185) {
401 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
402 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
403 }
404 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
405
406 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
407
408 /* TODO: turn off hw wep on rtl8180 */
409
410 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
411
412 if (priv->r8185) {
413 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
414 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
415 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
416
417 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
418
419 /* TODO: set ClkRun enable? necessary? */
420 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
421 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
422 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
423 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
424 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
425 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
426 } else {
427 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
428 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
429
430 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
431 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
432 }
433
434 priv->rf->init(dev);
435 if (priv->r8185)
436 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
437 return 0;
438 }
439
440 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
441 {
442 struct rtl8180_priv *priv = dev->priv;
443 struct rtl8180_rx_desc *entry;
444 int i;
445
446 priv->rx_ring = pci_alloc_consistent(priv->pdev,
447 sizeof(*priv->rx_ring) * 32,
448 &priv->rx_ring_dma);
449
450 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
451 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
452 return -ENOMEM;
453 }
454
455 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
456 priv->rx_idx = 0;
457
458 for (i = 0; i < 32; i++) {
459 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
460 dma_addr_t *mapping;
461 entry = &priv->rx_ring[i];
462 if (!skb)
463 return 0;
464
465 priv->rx_buf[i] = skb;
466 mapping = (dma_addr_t *)skb->cb;
467 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
468 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
469 entry->rx_buf = cpu_to_le32(*mapping);
470 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
471 MAX_RX_SIZE);
472 }
473 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
474 return 0;
475 }
476
477 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
478 {
479 struct rtl8180_priv *priv = dev->priv;
480 int i;
481
482 for (i = 0; i < 32; i++) {
483 struct sk_buff *skb = priv->rx_buf[i];
484 if (!skb)
485 continue;
486
487 pci_unmap_single(priv->pdev,
488 *((dma_addr_t *)skb->cb),
489 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
490 kfree_skb(skb);
491 }
492
493 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
494 priv->rx_ring, priv->rx_ring_dma);
495 priv->rx_ring = NULL;
496 }
497
498 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
499 unsigned int prio, unsigned int entries)
500 {
501 struct rtl8180_priv *priv = dev->priv;
502 struct rtl8180_tx_desc *ring;
503 dma_addr_t dma;
504 int i;
505
506 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
507 if (!ring || (unsigned long)ring & 0xFF) {
508 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
509 prio);
510 return -ENOMEM;
511 }
512
513 memset(ring, 0, sizeof(*ring)*entries);
514 priv->tx_ring[prio].desc = ring;
515 priv->tx_ring[prio].dma = dma;
516 priv->tx_ring[prio].idx = 0;
517 priv->tx_ring[prio].entries = entries;
518 skb_queue_head_init(&priv->tx_ring[prio].queue);
519
520 for (i = 0; i < entries; i++)
521 ring[i].next_tx_desc =
522 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
523
524 return 0;
525 }
526
527 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
528 {
529 struct rtl8180_priv *priv = dev->priv;
530 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
531
532 while (skb_queue_len(&ring->queue)) {
533 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
534 struct sk_buff *skb = __skb_dequeue(&ring->queue);
535
536 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
537 skb->len, PCI_DMA_TODEVICE);
538 kfree_skb(skb);
539 ring->idx = (ring->idx + 1) % ring->entries;
540 }
541
542 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
543 ring->desc, ring->dma);
544 ring->desc = NULL;
545 }
546
547 static int rtl8180_start(struct ieee80211_hw *dev)
548 {
549 struct rtl8180_priv *priv = dev->priv;
550 int ret, i;
551 u32 reg;
552
553 ret = rtl8180_init_rx_ring(dev);
554 if (ret)
555 return ret;
556
557 for (i = 0; i < 4; i++)
558 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
559 goto err_free_rings;
560
561 ret = rtl8180_init_hw(dev);
562 if (ret)
563 goto err_free_rings;
564
565 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
566 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
567 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
568 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
569 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
570
571 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
572 IRQF_SHARED, KBUILD_MODNAME, dev);
573 if (ret) {
574 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
575 goto err_free_rings;
576 }
577
578 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
579
580 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
581 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
582
583 reg = RTL818X_RX_CONF_ONLYERLPKT |
584 RTL818X_RX_CONF_RX_AUTORESETPHY |
585 RTL818X_RX_CONF_MGMT |
586 RTL818X_RX_CONF_DATA |
587 (7 << 8 /* MAX RX DMA */) |
588 RTL818X_RX_CONF_BROADCAST |
589 RTL818X_RX_CONF_NICMAC;
590
591 if (priv->r8185)
592 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
593 else {
594 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
595 ? RTL818X_RX_CONF_CSDM1 : 0;
596 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
597 ? RTL818X_RX_CONF_CSDM2 : 0;
598 }
599
600 priv->rx_conf = reg;
601 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
602
603 if (priv->r8185) {
604 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
605 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
606 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
607 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
608
609 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
610 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
611 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
612 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
613 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
614
615 /* disable early TX */
616 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
617 }
618
619 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
620 reg |= (6 << 21 /* MAX TX DMA */) |
621 RTL818X_TX_CONF_NO_ICV;
622
623 if (priv->r8185)
624 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
625 else
626 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
627
628 /* different meaning, same value on both rtl8185 and rtl8180 */
629 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
630
631 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
632
633 reg = rtl818x_ioread8(priv, &priv->map->CMD);
634 reg |= RTL818X_CMD_RX_ENABLE;
635 reg |= RTL818X_CMD_TX_ENABLE;
636 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
637
638 return 0;
639
640 err_free_rings:
641 rtl8180_free_rx_ring(dev);
642 for (i = 0; i < 4; i++)
643 if (priv->tx_ring[i].desc)
644 rtl8180_free_tx_ring(dev, i);
645
646 return ret;
647 }
648
649 static void rtl8180_stop(struct ieee80211_hw *dev)
650 {
651 struct rtl8180_priv *priv = dev->priv;
652 u8 reg;
653 int i;
654
655 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
656
657 reg = rtl818x_ioread8(priv, &priv->map->CMD);
658 reg &= ~RTL818X_CMD_TX_ENABLE;
659 reg &= ~RTL818X_CMD_RX_ENABLE;
660 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
661
662 priv->rf->stop(dev);
663
664 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
665 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
666 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
667 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
668
669 free_irq(priv->pdev->irq, dev);
670
671 rtl8180_free_rx_ring(dev);
672 for (i = 0; i < 4; i++)
673 rtl8180_free_tx_ring(dev, i);
674 }
675
676 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
677 struct ieee80211_vif *vif)
678 {
679 struct rtl8180_priv *priv = dev->priv;
680
681 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
682 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
683 }
684
685 static void rtl8180_beacon_work(struct work_struct *work)
686 {
687 struct rtl8180_vif *vif_priv =
688 container_of(work, struct rtl8180_vif, beacon_work.work);
689 struct ieee80211_vif *vif =
690 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
691 struct ieee80211_hw *dev = vif_priv->dev;
692 struct ieee80211_mgmt *mgmt;
693 struct sk_buff *skb;
694
695 /* don't overflow the tx ring */
696 if (ieee80211_queue_stopped(dev, 0))
697 goto resched;
698
699 /* grab a fresh beacon */
700 skb = ieee80211_beacon_get(dev, vif);
701 if (!skb)
702 goto resched;
703
704 /*
705 * update beacon timestamp w/ TSF value
706 * TODO: make hardware update beacon timestamp
707 */
708 mgmt = (struct ieee80211_mgmt *)skb->data;
709 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
710
711 /* TODO: use actual beacon queue */
712 skb_set_queue_mapping(skb, 0);
713
714 rtl8180_tx(dev, NULL, skb);
715
716 resched:
717 /*
718 * schedule next beacon
719 * TODO: use hardware support for beacon timing
720 */
721 schedule_delayed_work(&vif_priv->beacon_work,
722 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
723 }
724
725 static int rtl8180_add_interface(struct ieee80211_hw *dev,
726 struct ieee80211_vif *vif)
727 {
728 struct rtl8180_priv *priv = dev->priv;
729 struct rtl8180_vif *vif_priv;
730
731 /*
732 * We only support one active interface at a time.
733 */
734 if (priv->vif)
735 return -EBUSY;
736
737 switch (vif->type) {
738 case NL80211_IFTYPE_STATION:
739 case NL80211_IFTYPE_ADHOC:
740 break;
741 default:
742 return -EOPNOTSUPP;
743 }
744
745 priv->vif = vif;
746
747 /* Initialize driver private area */
748 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
749 vif_priv->dev = dev;
750 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
751 vif_priv->enable_beacon = false;
752
753 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
754 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
755 le32_to_cpu(*(__le32 *)vif->addr));
756 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
757 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
758 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
759
760 return 0;
761 }
762
763 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
764 struct ieee80211_vif *vif)
765 {
766 struct rtl8180_priv *priv = dev->priv;
767 priv->vif = NULL;
768 }
769
770 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
771 {
772 struct rtl8180_priv *priv = dev->priv;
773 struct ieee80211_conf *conf = &dev->conf;
774
775 priv->rf->set_chan(dev, conf);
776
777 return 0;
778 }
779
780 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
781 struct ieee80211_vif *vif,
782 struct ieee80211_bss_conf *info,
783 u32 changed)
784 {
785 struct rtl8180_priv *priv = dev->priv;
786 struct rtl8180_vif *vif_priv;
787 int i;
788 u8 reg;
789
790 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
791
792 if (changed & BSS_CHANGED_BSSID) {
793 for (i = 0; i < ETH_ALEN; i++)
794 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
795 info->bssid[i]);
796
797 if (is_valid_ether_addr(info->bssid)) {
798 if (vif->type == NL80211_IFTYPE_ADHOC)
799 reg = RTL818X_MSR_ADHOC;
800 else
801 reg = RTL818X_MSR_INFRA;
802 } else
803 reg = RTL818X_MSR_NO_LINK;
804 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
805 }
806
807 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
808 priv->rf->conf_erp(dev, info);
809
810 if (changed & BSS_CHANGED_BEACON_ENABLED)
811 vif_priv->enable_beacon = info->enable_beacon;
812
813 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
814 cancel_delayed_work_sync(&vif_priv->beacon_work);
815 if (vif_priv->enable_beacon)
816 schedule_work(&vif_priv->beacon_work.work);
817 }
818 }
819
820 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
821 struct netdev_hw_addr_list *mc_list)
822 {
823 return netdev_hw_addr_list_count(mc_list);
824 }
825
826 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
827 unsigned int changed_flags,
828 unsigned int *total_flags,
829 u64 multicast)
830 {
831 struct rtl8180_priv *priv = dev->priv;
832
833 if (changed_flags & FIF_FCSFAIL)
834 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
835 if (changed_flags & FIF_CONTROL)
836 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
837 if (changed_flags & FIF_OTHER_BSS)
838 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
839 if (*total_flags & FIF_ALLMULTI || multicast > 0)
840 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
841 else
842 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
843
844 *total_flags = 0;
845
846 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
847 *total_flags |= FIF_FCSFAIL;
848 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
849 *total_flags |= FIF_CONTROL;
850 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
851 *total_flags |= FIF_OTHER_BSS;
852 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
853 *total_flags |= FIF_ALLMULTI;
854
855 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
856 }
857
858 static const struct ieee80211_ops rtl8180_ops = {
859 .tx = rtl8180_tx,
860 .start = rtl8180_start,
861 .stop = rtl8180_stop,
862 .add_interface = rtl8180_add_interface,
863 .remove_interface = rtl8180_remove_interface,
864 .config = rtl8180_config,
865 .bss_info_changed = rtl8180_bss_info_changed,
866 .prepare_multicast = rtl8180_prepare_multicast,
867 .configure_filter = rtl8180_configure_filter,
868 .get_tsf = rtl8180_get_tsf,
869 };
870
871 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
872 {
873 struct ieee80211_hw *dev = eeprom->data;
874 struct rtl8180_priv *priv = dev->priv;
875 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
876
877 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
878 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
879 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
880 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
881 }
882
883 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
884 {
885 struct ieee80211_hw *dev = eeprom->data;
886 struct rtl8180_priv *priv = dev->priv;
887 u8 reg = 2 << 6;
888
889 if (eeprom->reg_data_in)
890 reg |= RTL818X_EEPROM_CMD_WRITE;
891 if (eeprom->reg_data_out)
892 reg |= RTL818X_EEPROM_CMD_READ;
893 if (eeprom->reg_data_clock)
894 reg |= RTL818X_EEPROM_CMD_CK;
895 if (eeprom->reg_chip_select)
896 reg |= RTL818X_EEPROM_CMD_CS;
897
898 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
899 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
900 udelay(10);
901 }
902
903 static int rtl8180_probe(struct pci_dev *pdev,
904 const struct pci_device_id *id)
905 {
906 struct ieee80211_hw *dev;
907 struct rtl8180_priv *priv;
908 unsigned long mem_addr, mem_len;
909 unsigned int io_addr, io_len;
910 int err, i;
911 struct eeprom_93cx6 eeprom;
912 const char *chip_name, *rf_name = NULL;
913 u32 reg;
914 u16 eeprom_val;
915 u8 mac_addr[ETH_ALEN];
916
917 err = pci_enable_device(pdev);
918 if (err) {
919 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
920 pci_name(pdev));
921 return err;
922 }
923
924 err = pci_request_regions(pdev, KBUILD_MODNAME);
925 if (err) {
926 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
927 pci_name(pdev));
928 return err;
929 }
930
931 io_addr = pci_resource_start(pdev, 0);
932 io_len = pci_resource_len(pdev, 0);
933 mem_addr = pci_resource_start(pdev, 1);
934 mem_len = pci_resource_len(pdev, 1);
935
936 if (mem_len < sizeof(struct rtl818x_csr) ||
937 io_len < sizeof(struct rtl818x_csr)) {
938 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
939 pci_name(pdev));
940 err = -ENOMEM;
941 goto err_free_reg;
942 }
943
944 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
945 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
946 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
947 pci_name(pdev));
948 goto err_free_reg;
949 }
950
951 pci_set_master(pdev);
952
953 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
954 if (!dev) {
955 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
956 pci_name(pdev));
957 err = -ENOMEM;
958 goto err_free_reg;
959 }
960
961 priv = dev->priv;
962 priv->pdev = pdev;
963
964 dev->max_rates = 2;
965 SET_IEEE80211_DEV(dev, &pdev->dev);
966 pci_set_drvdata(pdev, dev);
967
968 priv->map = pci_iomap(pdev, 1, mem_len);
969 if (!priv->map)
970 priv->map = pci_iomap(pdev, 0, io_len);
971
972 if (!priv->map) {
973 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
974 pci_name(pdev));
975 goto err_free_dev;
976 }
977
978 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
979 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
980
981 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
982 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
983
984 priv->band.band = IEEE80211_BAND_2GHZ;
985 priv->band.channels = priv->channels;
986 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
987 priv->band.bitrates = priv->rates;
988 priv->band.n_bitrates = 4;
989 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
990
991 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
992 IEEE80211_HW_RX_INCLUDES_FCS |
993 IEEE80211_HW_SIGNAL_UNSPEC;
994 dev->vif_data_size = sizeof(struct rtl8180_vif);
995 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
996 BIT(NL80211_IFTYPE_ADHOC);
997 dev->queues = 1;
998 dev->max_signal = 65;
999
1000 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1001 reg &= RTL818X_TX_CONF_HWVER_MASK;
1002 switch (reg) {
1003 case RTL818X_TX_CONF_R8180_ABCD:
1004 chip_name = "RTL8180";
1005 break;
1006 case RTL818X_TX_CONF_R8180_F:
1007 chip_name = "RTL8180vF";
1008 break;
1009 case RTL818X_TX_CONF_R8185_ABC:
1010 chip_name = "RTL8185";
1011 break;
1012 case RTL818X_TX_CONF_R8185_D:
1013 chip_name = "RTL8185vD";
1014 break;
1015 default:
1016 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1017 pci_name(pdev), reg >> 25);
1018 goto err_iounmap;
1019 }
1020
1021 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1022 if (priv->r8185) {
1023 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1024 pci_try_set_mwi(pdev);
1025 }
1026
1027 eeprom.data = dev;
1028 eeprom.register_read = rtl8180_eeprom_register_read;
1029 eeprom.register_write = rtl8180_eeprom_register_write;
1030 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1031 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1032 else
1033 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1034
1035 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1036 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1037 udelay(10);
1038
1039 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1040 eeprom_val &= 0xFF;
1041 switch (eeprom_val) {
1042 case 1: rf_name = "Intersil";
1043 break;
1044 case 2: rf_name = "RFMD";
1045 break;
1046 case 3: priv->rf = &sa2400_rf_ops;
1047 break;
1048 case 4: priv->rf = &max2820_rf_ops;
1049 break;
1050 case 5: priv->rf = &grf5101_rf_ops;
1051 break;
1052 case 9: priv->rf = rtl8180_detect_rf(dev);
1053 break;
1054 case 10:
1055 rf_name = "RTL8255";
1056 break;
1057 default:
1058 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1059 pci_name(pdev), eeprom_val);
1060 goto err_iounmap;
1061 }
1062
1063 if (!priv->rf) {
1064 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1065 pci_name(pdev), rf_name);
1066 goto err_iounmap;
1067 }
1068
1069 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1070 priv->csthreshold = eeprom_val >> 8;
1071 if (!priv->r8185) {
1072 __le32 anaparam;
1073 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1074 priv->anaparam = le32_to_cpu(anaparam);
1075 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1076 }
1077
1078 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1079 if (!is_valid_ether_addr(mac_addr)) {
1080 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1081 " randomly generated MAC addr\n", pci_name(pdev));
1082 eth_random_addr(mac_addr);
1083 }
1084 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1085
1086 /* CCK TX power */
1087 for (i = 0; i < 14; i += 2) {
1088 u16 txpwr;
1089 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1090 priv->channels[i].hw_value = txpwr & 0xFF;
1091 priv->channels[i + 1].hw_value = txpwr >> 8;
1092 }
1093
1094 /* OFDM TX power */
1095 if (priv->r8185) {
1096 for (i = 0; i < 14; i += 2) {
1097 u16 txpwr;
1098 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1099 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1100 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1101 }
1102 }
1103
1104 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1105
1106 spin_lock_init(&priv->lock);
1107
1108 err = ieee80211_register_hw(dev);
1109 if (err) {
1110 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1111 pci_name(pdev));
1112 goto err_iounmap;
1113 }
1114
1115 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1116 mac_addr, chip_name, priv->rf->name);
1117
1118 return 0;
1119
1120 err_iounmap:
1121 iounmap(priv->map);
1122
1123 err_free_dev:
1124 ieee80211_free_hw(dev);
1125
1126 err_free_reg:
1127 pci_release_regions(pdev);
1128 pci_disable_device(pdev);
1129 return err;
1130 }
1131
1132 static void rtl8180_remove(struct pci_dev *pdev)
1133 {
1134 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1135 struct rtl8180_priv *priv;
1136
1137 if (!dev)
1138 return;
1139
1140 ieee80211_unregister_hw(dev);
1141
1142 priv = dev->priv;
1143
1144 pci_iounmap(pdev, priv->map);
1145 pci_release_regions(pdev);
1146 pci_disable_device(pdev);
1147 ieee80211_free_hw(dev);
1148 }
1149
1150 #ifdef CONFIG_PM
1151 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1152 {
1153 pci_save_state(pdev);
1154 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1155 return 0;
1156 }
1157
1158 static int rtl8180_resume(struct pci_dev *pdev)
1159 {
1160 pci_set_power_state(pdev, PCI_D0);
1161 pci_restore_state(pdev);
1162 return 0;
1163 }
1164
1165 #endif /* CONFIG_PM */
1166
1167 static struct pci_driver rtl8180_driver = {
1168 .name = KBUILD_MODNAME,
1169 .id_table = rtl8180_table,
1170 .probe = rtl8180_probe,
1171 .remove = rtl8180_remove,
1172 #ifdef CONFIG_PM
1173 .suspend = rtl8180_suspend,
1174 .resume = rtl8180_resume,
1175 #endif /* CONFIG_PM */
1176 };
1177
1178 module_pci_driver(rtl8180_driver);
Linux kernel - Deliverables
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