3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table
) = {
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x701f) },
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x3300) },
49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
54 MODULE_DEVICE_TABLE(pci
, rtl8180_table
);
56 static const struct ieee80211_rate rtl818x_rates
[] = {
57 { .bitrate
= 10, .hw_value
= 0, },
58 { .bitrate
= 20, .hw_value
= 1, },
59 { .bitrate
= 55, .hw_value
= 2, },
60 { .bitrate
= 110, .hw_value
= 3, },
61 { .bitrate
= 60, .hw_value
= 4, },
62 { .bitrate
= 90, .hw_value
= 5, },
63 { .bitrate
= 120, .hw_value
= 6, },
64 { .bitrate
= 180, .hw_value
= 7, },
65 { .bitrate
= 240, .hw_value
= 8, },
66 { .bitrate
= 360, .hw_value
= 9, },
67 { .bitrate
= 480, .hw_value
= 10, },
68 { .bitrate
= 540, .hw_value
= 11, },
71 static const struct ieee80211_channel rtl818x_channels
[] = {
72 { .center_freq
= 2412 },
73 { .center_freq
= 2417 },
74 { .center_freq
= 2422 },
75 { .center_freq
= 2427 },
76 { .center_freq
= 2432 },
77 { .center_freq
= 2437 },
78 { .center_freq
= 2442 },
79 { .center_freq
= 2447 },
80 { .center_freq
= 2452 },
81 { .center_freq
= 2457 },
82 { .center_freq
= 2462 },
83 { .center_freq
= 2467 },
84 { .center_freq
= 2472 },
85 { .center_freq
= 2484 },
89 void rtl8180_write_phy(struct ieee80211_hw
*dev
, u8 addr
, u32 data
)
91 struct rtl8180_priv
*priv
= dev
->priv
;
95 buf
= (data
<< 8) | addr
;
97 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
| 0x80);
99 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
);
100 if (rtl818x_ioread8(priv
, &priv
->map
->PHY
[2]) == (data
& 0xFF))
105 static void rtl8180_handle_rx(struct ieee80211_hw
*dev
)
107 struct rtl8180_priv
*priv
= dev
->priv
;
108 unsigned int count
= 32;
113 struct rtl8180_rx_desc
*entry
= &priv
->rx_ring
[priv
->rx_idx
];
114 struct sk_buff
*skb
= priv
->rx_buf
[priv
->rx_idx
];
115 u32 flags
= le32_to_cpu(entry
->flags
);
117 if (flags
& RTL818X_RX_DESC_FLAG_OWN
)
120 if (unlikely(flags
& (RTL818X_RX_DESC_FLAG_DMA_FAIL
|
121 RTL818X_RX_DESC_FLAG_FOF
|
122 RTL818X_RX_DESC_FLAG_RX_ERR
)))
125 u32 flags2
= le32_to_cpu(entry
->flags2
);
126 struct ieee80211_rx_status rx_status
= {0};
127 struct sk_buff
*new_skb
= dev_alloc_skb(MAX_RX_SIZE
);
129 if (unlikely(!new_skb
))
132 mapping
= pci_map_single(priv
->pdev
,
133 skb_tail_pointer(new_skb
),
134 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
136 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
138 dev_err(&priv
->pdev
->dev
, "RX DMA map error\n");
143 pci_unmap_single(priv
->pdev
,
144 *((dma_addr_t
*)skb
->cb
),
145 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
146 skb_put(skb
, flags
& 0xFFF);
148 rx_status
.antenna
= (flags2
>> 15) & 1;
149 rx_status
.rate_idx
= (flags
>> 20) & 0xF;
150 agc
= (flags2
>> 17) & 0x7F;
152 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
153 if (rx_status
.rate_idx
> 3)
154 signal
= 90 - clamp_t(u8
, agc
, 25, 90);
156 signal
= 95 - clamp_t(u8
, agc
, 30, 95);
159 signal
= priv
->rf
->calc_rssi(agc
, sq
);
161 rx_status
.signal
= signal
;
162 rx_status
.freq
= dev
->conf
.chandef
.chan
->center_freq
;
163 rx_status
.band
= dev
->conf
.chandef
.chan
->band
;
164 rx_status
.mactime
= le64_to_cpu(entry
->tsft
);
165 rx_status
.flag
|= RX_FLAG_MACTIME_START
;
166 if (flags
& RTL818X_RX_DESC_FLAG_CRC32_ERR
)
167 rx_status
.flag
|= RX_FLAG_FAILED_FCS_CRC
;
169 memcpy(IEEE80211_SKB_RXCB(skb
), &rx_status
, sizeof(rx_status
));
170 ieee80211_rx_irqsafe(dev
, skb
);
173 priv
->rx_buf
[priv
->rx_idx
] = skb
;
174 *((dma_addr_t
*) skb
->cb
) = mapping
;
178 entry
->rx_buf
= cpu_to_le32(*((dma_addr_t
*)skb
->cb
));
179 entry
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
181 if (priv
->rx_idx
== 31)
182 entry
->flags
|= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
183 priv
->rx_idx
= (priv
->rx_idx
+ 1) % 32;
187 static void rtl8180_handle_tx(struct ieee80211_hw
*dev
, unsigned int prio
)
189 struct rtl8180_priv
*priv
= dev
->priv
;
190 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
192 while (skb_queue_len(&ring
->queue
)) {
193 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
195 struct ieee80211_tx_info
*info
;
196 u32 flags
= le32_to_cpu(entry
->flags
);
198 if (flags
& RTL818X_TX_DESC_FLAG_OWN
)
201 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
202 skb
= __skb_dequeue(&ring
->queue
);
203 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
204 skb
->len
, PCI_DMA_TODEVICE
);
206 info
= IEEE80211_SKB_CB(skb
);
207 ieee80211_tx_info_clear_status(info
);
209 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
) &&
210 (flags
& RTL818X_TX_DESC_FLAG_TX_OK
))
211 info
->flags
|= IEEE80211_TX_STAT_ACK
;
213 info
->status
.rates
[0].count
= (flags
& 0xFF) + 1;
214 info
->status
.rates
[1].idx
= -1;
216 ieee80211_tx_status_irqsafe(dev
, skb
);
217 if (ring
->entries
- skb_queue_len(&ring
->queue
) == 2)
218 ieee80211_wake_queue(dev
, prio
);
222 static irqreturn_t
rtl8180_interrupt(int irq
, void *dev_id
)
224 struct ieee80211_hw
*dev
= dev_id
;
225 struct rtl8180_priv
*priv
= dev
->priv
;
228 spin_lock(&priv
->lock
);
229 reg
= rtl818x_ioread16(priv
, &priv
->map
->INT_STATUS
);
230 if (unlikely(reg
== 0xFFFF)) {
231 spin_unlock(&priv
->lock
);
235 rtl818x_iowrite16(priv
, &priv
->map
->INT_STATUS
, reg
);
237 if (reg
& (RTL818X_INT_TXB_OK
| RTL818X_INT_TXB_ERR
))
238 rtl8180_handle_tx(dev
, 3);
240 if (reg
& (RTL818X_INT_TXH_OK
| RTL818X_INT_TXH_ERR
))
241 rtl8180_handle_tx(dev
, 2);
243 if (reg
& (RTL818X_INT_TXN_OK
| RTL818X_INT_TXN_ERR
))
244 rtl8180_handle_tx(dev
, 1);
246 if (reg
& (RTL818X_INT_TXL_OK
| RTL818X_INT_TXL_ERR
))
247 rtl8180_handle_tx(dev
, 0);
249 if (reg
& (RTL818X_INT_RX_OK
| RTL818X_INT_RX_ERR
))
250 rtl8180_handle_rx(dev
);
252 spin_unlock(&priv
->lock
);
257 static void rtl8180_tx(struct ieee80211_hw
*dev
,
258 struct ieee80211_tx_control
*control
,
261 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
262 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
263 struct rtl8180_priv
*priv
= dev
->priv
;
264 struct rtl8180_tx_ring
*ring
;
265 struct rtl8180_tx_desc
*entry
;
267 unsigned int idx
, prio
;
272 __le16 rts_duration
= 0;
274 prio
= skb_get_queue_mapping(skb
);
275 ring
= &priv
->tx_ring
[prio
];
277 mapping
= pci_map_single(priv
->pdev
, skb
->data
,
278 skb
->len
, PCI_DMA_TODEVICE
);
280 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
282 dev_err(&priv
->pdev
->dev
, "TX DMA mapping error\n");
287 tx_flags
= RTL818X_TX_DESC_FLAG_OWN
| RTL818X_TX_DESC_FLAG_FS
|
288 RTL818X_TX_DESC_FLAG_LS
|
289 (ieee80211_get_tx_rate(dev
, info
)->hw_value
<< 24) |
292 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
293 tx_flags
|= RTL818X_TX_DESC_FLAG_DMA
|
294 RTL818X_TX_DESC_FLAG_NO_ENC
;
296 rc_flags
= info
->control
.rates
[0].flags
;
297 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
298 tx_flags
|= RTL818X_TX_DESC_FLAG_RTS
;
299 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
300 } else if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
301 tx_flags
|= RTL818X_TX_DESC_FLAG_CTS
;
302 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
305 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
306 rts_duration
= ieee80211_rts_duration(dev
, priv
->vif
, skb
->len
,
309 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
310 unsigned int remainder
;
312 plcp_len
= DIV_ROUND_UP(16 * (skb
->len
+ 4),
313 (ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
314 remainder
= (16 * (skb
->len
+ 4)) %
315 ((ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
320 spin_lock_irqsave(&priv
->lock
, flags
);
322 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
323 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
325 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
326 hdr
->seq_ctrl
|= cpu_to_le16(priv
->seqno
);
329 idx
= (ring
->idx
+ skb_queue_len(&ring
->queue
)) % ring
->entries
;
330 entry
= &ring
->desc
[idx
];
332 entry
->rts_duration
= rts_duration
;
333 entry
->plcp_len
= cpu_to_le16(plcp_len
);
334 entry
->tx_buf
= cpu_to_le32(mapping
);
335 entry
->frame_len
= cpu_to_le32(skb
->len
);
336 entry
->flags2
= info
->control
.rates
[1].idx
>= 0 ?
337 ieee80211_get_alt_retry_rate(dev
, info
, 0)->bitrate
<< 4 : 0;
338 entry
->retry_limit
= info
->control
.rates
[0].count
;
340 /* We must be sure that tx_flags is written last because the HW
341 * looks at it to check if the rest of data is valid or not
344 entry
->flags
= cpu_to_le32(tx_flags
);
345 /* We must be sure this has been written before followings HW
346 * register write, because this write will made the HW attempts
347 * to DMA the just-written data
351 __skb_queue_tail(&ring
->queue
, skb
);
352 if (ring
->entries
- skb_queue_len(&ring
->queue
) < 2)
353 ieee80211_stop_queue(dev
, prio
);
355 spin_unlock_irqrestore(&priv
->lock
, flags
);
357 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
, (1 << (prio
+ 4)));
360 void rtl8180_set_anaparam(struct rtl8180_priv
*priv
, u32 anaparam
)
364 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
365 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
366 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
367 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
368 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM
, anaparam
);
369 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
370 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
371 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
374 static void rtl8180_conf_basic_rates(struct ieee80211_hw
*dev
,
377 struct rtl8180_priv
*priv
= dev
->priv
;
382 max
= fls(rates_mask
) - 1;
383 min
= ffs(rates_mask
) - 1;
385 switch (priv
->chip_family
) {
387 case RTL818X_CHIP_FAMILY_RTL8180
:
388 /* in 8180 this is NOT a BITMAP */
389 reg
= rtl818x_ioread16(priv
, &priv
->map
->BRSR
);
392 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, reg
);
396 case RTL818X_CHIP_FAMILY_RTL8185
:
397 /* in 8185 this is a BITMAP */
398 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, rates_mask
);
399 rtl818x_iowrite8(priv
, &priv
->map
->RESP_RATE
, (max
<< 4) | min
);
404 static int rtl8180_init_hw(struct ieee80211_hw
*dev
)
406 struct rtl8180_priv
*priv
= dev
->priv
;
409 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, 0);
410 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
414 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
415 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
417 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
419 reg
|= RTL818X_CMD_RESET
;
420 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, RTL818X_CMD_RESET
);
421 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
424 /* check success of reset */
425 if (rtl818x_ioread8(priv
, &priv
->map
->CMD
) & RTL818X_CMD_RESET
) {
426 wiphy_err(dev
->wiphy
, "reset timeout!\n");
430 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_LOAD
);
431 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
434 if (rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
) & (1 << 3)) {
436 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
438 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
);
439 reg
= rtl818x_ioread16(priv
, &priv
->map
->FEMR
);
440 reg
|= (1 << 15) | (1 << 14) | (1 << 4);
441 rtl818x_iowrite16(priv
, &priv
->map
->FEMR
, reg
);
444 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, 0);
446 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
447 rtl8180_set_anaparam(priv
, priv
->anaparam
);
449 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
450 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
, priv
->tx_ring
[3].dma
);
451 rtl818x_iowrite32(priv
, &priv
->map
->THPDA
, priv
->tx_ring
[2].dma
);
452 rtl818x_iowrite32(priv
, &priv
->map
->TNPDA
, priv
->tx_ring
[1].dma
);
453 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
, priv
->tx_ring
[0].dma
);
455 /* TODO: necessary? specs indicate not */
456 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
457 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
458 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
& ~(1 << 3));
459 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
460 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
461 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
| (1 << 4));
463 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
465 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
467 /* TODO: turn off hw wep on rtl8180 */
469 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
471 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
472 rtl818x_iowrite8(priv
, &priv
->map
->WPA_CONF
, 0);
473 rtl818x_iowrite8(priv
, &priv
->map
->RATE_FALLBACK
, 0x81);
475 /* TODO: set ClkRun enable? necessary? */
476 reg
= rtl818x_ioread8(priv
, &priv
->map
->GP_ENABLE
);
477 rtl818x_iowrite8(priv
, &priv
->map
->GP_ENABLE
, reg
& ~(1 << 6));
478 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
479 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
480 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
| (1 << 2));
481 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
483 rtl818x_iowrite8(priv
, &priv
->map
->SECURITY
, 0);
485 rtl818x_iowrite8(priv
, &priv
->map
->PHY_DELAY
, 0x6);
486 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, 0x4C);
491 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
492 * otherwise. bitmask 0x3 and 0x01f3 respectively.
493 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
494 * this after rf init.
495 * TODO: try to find out whether RF code really needs to do this..
497 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
498 rtl8180_conf_basic_rates(dev
, 0x3);
500 rtl8180_conf_basic_rates(dev
, 0x1f3);
505 static int rtl8180_init_rx_ring(struct ieee80211_hw
*dev
)
507 struct rtl8180_priv
*priv
= dev
->priv
;
508 struct rtl8180_rx_desc
*entry
;
511 priv
->rx_ring
= pci_alloc_consistent(priv
->pdev
,
512 sizeof(*priv
->rx_ring
) * 32,
515 if (!priv
->rx_ring
|| (unsigned long)priv
->rx_ring
& 0xFF) {
516 wiphy_err(dev
->wiphy
, "Cannot allocate RX ring\n");
520 memset(priv
->rx_ring
, 0, sizeof(*priv
->rx_ring
) * 32);
523 for (i
= 0; i
< 32; i
++) {
524 struct sk_buff
*skb
= dev_alloc_skb(MAX_RX_SIZE
);
526 entry
= &priv
->rx_ring
[i
];
528 wiphy_err(dev
->wiphy
, "Cannot allocate RX skb\n");
531 priv
->rx_buf
[i
] = skb
;
532 mapping
= (dma_addr_t
*)skb
->cb
;
533 *mapping
= pci_map_single(priv
->pdev
, skb_tail_pointer(skb
),
534 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
536 if (pci_dma_mapping_error(priv
->pdev
, *mapping
)) {
538 wiphy_err(dev
->wiphy
, "Cannot map DMA for RX skb\n");
542 entry
->rx_buf
= cpu_to_le32(*mapping
);
543 entry
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
546 entry
->flags
|= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
550 static void rtl8180_free_rx_ring(struct ieee80211_hw
*dev
)
552 struct rtl8180_priv
*priv
= dev
->priv
;
555 for (i
= 0; i
< 32; i
++) {
556 struct sk_buff
*skb
= priv
->rx_buf
[i
];
560 pci_unmap_single(priv
->pdev
,
561 *((dma_addr_t
*)skb
->cb
),
562 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
566 pci_free_consistent(priv
->pdev
, sizeof(*priv
->rx_ring
) * 32,
567 priv
->rx_ring
, priv
->rx_ring_dma
);
568 priv
->rx_ring
= NULL
;
571 static int rtl8180_init_tx_ring(struct ieee80211_hw
*dev
,
572 unsigned int prio
, unsigned int entries
)
574 struct rtl8180_priv
*priv
= dev
->priv
;
575 struct rtl8180_tx_desc
*ring
;
579 ring
= pci_alloc_consistent(priv
->pdev
, sizeof(*ring
) * entries
, &dma
);
580 if (!ring
|| (unsigned long)ring
& 0xFF) {
581 wiphy_err(dev
->wiphy
, "Cannot allocate TX ring (prio = %d)\n",
586 memset(ring
, 0, sizeof(*ring
)*entries
);
587 priv
->tx_ring
[prio
].desc
= ring
;
588 priv
->tx_ring
[prio
].dma
= dma
;
589 priv
->tx_ring
[prio
].idx
= 0;
590 priv
->tx_ring
[prio
].entries
= entries
;
591 skb_queue_head_init(&priv
->tx_ring
[prio
].queue
);
593 for (i
= 0; i
< entries
; i
++)
594 ring
[i
].next_tx_desc
=
595 cpu_to_le32((u32
)dma
+ ((i
+ 1) % entries
) * sizeof(*ring
));
600 static void rtl8180_free_tx_ring(struct ieee80211_hw
*dev
, unsigned int prio
)
602 struct rtl8180_priv
*priv
= dev
->priv
;
603 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
605 while (skb_queue_len(&ring
->queue
)) {
606 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
607 struct sk_buff
*skb
= __skb_dequeue(&ring
->queue
);
609 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
610 skb
->len
, PCI_DMA_TODEVICE
);
612 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
615 pci_free_consistent(priv
->pdev
, sizeof(*ring
->desc
)*ring
->entries
,
616 ring
->desc
, ring
->dma
);
620 static int rtl8180_start(struct ieee80211_hw
*dev
)
622 struct rtl8180_priv
*priv
= dev
->priv
;
626 ret
= rtl8180_init_rx_ring(dev
);
630 for (i
= 0; i
< 4; i
++)
631 if ((ret
= rtl8180_init_tx_ring(dev
, i
, 16)))
634 ret
= rtl8180_init_hw(dev
);
638 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
639 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
, priv
->tx_ring
[3].dma
);
640 rtl818x_iowrite32(priv
, &priv
->map
->THPDA
, priv
->tx_ring
[2].dma
);
641 rtl818x_iowrite32(priv
, &priv
->map
->TNPDA
, priv
->tx_ring
[1].dma
);
642 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
, priv
->tx_ring
[0].dma
);
644 ret
= request_irq(priv
->pdev
->irq
, rtl8180_interrupt
,
645 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
647 wiphy_err(dev
->wiphy
, "failed to register IRQ handler\n");
651 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0xFFFF);
653 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[0], ~0);
654 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[1], ~0);
656 reg
= RTL818X_RX_CONF_ONLYERLPKT
|
657 RTL818X_RX_CONF_RX_AUTORESETPHY
|
658 RTL818X_RX_CONF_MGMT
|
659 RTL818X_RX_CONF_DATA
|
660 (7 << 8 /* MAX RX DMA */) |
661 RTL818X_RX_CONF_BROADCAST
|
662 RTL818X_RX_CONF_NICMAC
;
664 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
)
665 reg
|= RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
;
667 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE1
)
668 ? RTL818X_RX_CONF_CSDM1
: 0;
669 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE2
)
670 ? RTL818X_RX_CONF_CSDM2
: 0;
674 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, reg
);
676 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
677 reg
= rtl818x_ioread8(priv
, &priv
->map
->CW_CONF
);
679 /* CW is not on per-packet basis.
680 * in rtl8185 the CW_VALUE reg is used.
682 reg
&= ~RTL818X_CW_CONF_PERPACKET_CW
;
683 /* retry limit IS on per-packet basis.
684 * the short and long retry limit in TX_CONF
687 reg
|= RTL818X_CW_CONF_PERPACKET_RETRY
;
688 rtl818x_iowrite8(priv
, &priv
->map
->CW_CONF
, reg
);
690 reg
= rtl818x_ioread8(priv
, &priv
->map
->TX_AGC_CTL
);
691 /* TX antenna and TX gain are not on per-packet basis.
692 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
693 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
695 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN
;
696 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL
;
697 reg
|= RTL818X_TX_AGC_CTL_FEEDBACK_ANT
;
698 rtl818x_iowrite8(priv
, &priv
->map
->TX_AGC_CTL
, reg
);
700 /* disable early TX */
701 rtl818x_iowrite8(priv
, (u8 __iomem
*)priv
->map
+ 0xec, 0x3f);
704 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
705 reg
|= (6 << 21 /* MAX TX DMA */) |
706 RTL818X_TX_CONF_NO_ICV
;
710 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
711 reg
&= ~RTL818X_TX_CONF_PROBE_DTS
;
713 reg
&= ~RTL818X_TX_CONF_HW_SEQNUM
;
715 reg
&= ~RTL818X_TX_CONF_DISCW
;
717 /* different meaning, same value on both rtl8185 and rtl8180 */
718 reg
&= ~RTL818X_TX_CONF_SAT_HWPLCP
;
720 rtl818x_iowrite32(priv
, &priv
->map
->TX_CONF
, reg
);
722 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
723 reg
|= RTL818X_CMD_RX_ENABLE
;
724 reg
|= RTL818X_CMD_TX_ENABLE
;
725 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
730 rtl8180_free_rx_ring(dev
);
731 for (i
= 0; i
< 4; i
++)
732 if (priv
->tx_ring
[i
].desc
)
733 rtl8180_free_tx_ring(dev
, i
);
738 static void rtl8180_stop(struct ieee80211_hw
*dev
)
740 struct rtl8180_priv
*priv
= dev
->priv
;
744 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
746 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
747 reg
&= ~RTL818X_CMD_TX_ENABLE
;
748 reg
&= ~RTL818X_CMD_RX_ENABLE
;
749 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
753 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
754 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG4
);
755 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG4
, reg
| RTL818X_CONFIG4_VCOOFF
);
756 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
758 free_irq(priv
->pdev
->irq
, dev
);
760 rtl8180_free_rx_ring(dev
);
761 for (i
= 0; i
< 4; i
++)
762 rtl8180_free_tx_ring(dev
, i
);
765 static u64
rtl8180_get_tsf(struct ieee80211_hw
*dev
,
766 struct ieee80211_vif
*vif
)
768 struct rtl8180_priv
*priv
= dev
->priv
;
770 return rtl818x_ioread32(priv
, &priv
->map
->TSFT
[0]) |
771 (u64
)(rtl818x_ioread32(priv
, &priv
->map
->TSFT
[1])) << 32;
774 static void rtl8180_beacon_work(struct work_struct
*work
)
776 struct rtl8180_vif
*vif_priv
=
777 container_of(work
, struct rtl8180_vif
, beacon_work
.work
);
778 struct ieee80211_vif
*vif
=
779 container_of((void *)vif_priv
, struct ieee80211_vif
, drv_priv
);
780 struct ieee80211_hw
*dev
= vif_priv
->dev
;
781 struct ieee80211_mgmt
*mgmt
;
784 /* don't overflow the tx ring */
785 if (ieee80211_queue_stopped(dev
, 0))
788 /* grab a fresh beacon */
789 skb
= ieee80211_beacon_get(dev
, vif
);
794 * update beacon timestamp w/ TSF value
795 * TODO: make hardware update beacon timestamp
797 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
798 mgmt
->u
.beacon
.timestamp
= cpu_to_le64(rtl8180_get_tsf(dev
, vif
));
800 /* TODO: use actual beacon queue */
801 skb_set_queue_mapping(skb
, 0);
803 rtl8180_tx(dev
, NULL
, skb
);
807 * schedule next beacon
808 * TODO: use hardware support for beacon timing
810 schedule_delayed_work(&vif_priv
->beacon_work
,
811 usecs_to_jiffies(1024 * vif
->bss_conf
.beacon_int
));
814 static int rtl8180_add_interface(struct ieee80211_hw
*dev
,
815 struct ieee80211_vif
*vif
)
817 struct rtl8180_priv
*priv
= dev
->priv
;
818 struct rtl8180_vif
*vif_priv
;
821 * We only support one active interface at a time.
827 case NL80211_IFTYPE_STATION
:
828 case NL80211_IFTYPE_ADHOC
:
836 /* Initialize driver private area */
837 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
839 INIT_DELAYED_WORK(&vif_priv
->beacon_work
, rtl8180_beacon_work
);
840 vif_priv
->enable_beacon
= false;
842 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
843 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->MAC
[0],
844 le32_to_cpu(*(__le32
*)vif
->addr
));
845 rtl818x_iowrite16(priv
, (__le16 __iomem
*)&priv
->map
->MAC
[4],
846 le16_to_cpu(*(__le16
*)(vif
->addr
+ 4)));
847 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
852 static void rtl8180_remove_interface(struct ieee80211_hw
*dev
,
853 struct ieee80211_vif
*vif
)
855 struct rtl8180_priv
*priv
= dev
->priv
;
859 static int rtl8180_config(struct ieee80211_hw
*dev
, u32 changed
)
861 struct rtl8180_priv
*priv
= dev
->priv
;
862 struct ieee80211_conf
*conf
= &dev
->conf
;
864 priv
->rf
->set_chan(dev
, conf
);
869 static int rtl8180_conf_tx(struct ieee80211_hw
*dev
,
870 struct ieee80211_vif
*vif
, u16 queue
,
871 const struct ieee80211_tx_queue_params
*params
)
873 struct rtl8180_priv
*priv
= dev
->priv
;
876 /* nothing to do ? */
877 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
880 cw_min
= fls(params
->cw_min
);
881 cw_max
= fls(params
->cw_max
);
883 rtl818x_iowrite8(priv
, &priv
->map
->CW_VAL
, (cw_max
<< 4) | cw_min
);
888 static void rtl8180_conf_erp(struct ieee80211_hw
*dev
,
889 struct ieee80211_bss_conf
*info
)
891 struct rtl8180_priv
*priv
= dev
->priv
;
896 /* TODO: should we do something ? */
897 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
900 /* I _hope_ this means 10uS for the HW.
901 * In reference code it is 0x22 for
902 * both rtl8187L and rtl8187SE
906 if (info
->use_short_slot
)
909 priv
->slot_time
= 20;
911 /* 10 is SIFS time in uS */
912 difs
= 10 + 2 * priv
->slot_time
;
913 eifs
= 10 + difs
+ priv
->ack_time
;
915 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
916 hw_eifs
= DIV_ROUND_UP(eifs
, 4);
919 rtl818x_iowrite8(priv
, &priv
->map
->SLOT
, priv
->slot_time
);
920 rtl818x_iowrite8(priv
, &priv
->map
->SIFS
, sifs
);
921 rtl818x_iowrite8(priv
, &priv
->map
->DIFS
, difs
);
923 /* from reference code. set ack timeout reg = eifs reg */
924 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, hw_eifs
);
926 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
927 * the HW still wait for DIFS.
928 * HW uses 4uS units for EIFS.
930 hw_eifs
= DIV_ROUND_UP(eifs
- difs
, 4);
932 rtl818x_iowrite8(priv
, &priv
->map
->EIFS
, hw_eifs
);
935 static void rtl8180_bss_info_changed(struct ieee80211_hw
*dev
,
936 struct ieee80211_vif
*vif
,
937 struct ieee80211_bss_conf
*info
,
940 struct rtl8180_priv
*priv
= dev
->priv
;
941 struct rtl8180_vif
*vif_priv
;
945 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
947 if (changed
& BSS_CHANGED_BSSID
) {
948 for (i
= 0; i
< ETH_ALEN
; i
++)
949 rtl818x_iowrite8(priv
, &priv
->map
->BSSID
[i
],
952 if (is_valid_ether_addr(info
->bssid
)) {
953 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
954 reg
= RTL818X_MSR_ADHOC
;
956 reg
= RTL818X_MSR_INFRA
;
958 reg
= RTL818X_MSR_NO_LINK
;
959 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, reg
);
962 if (changed
& BSS_CHANGED_BASIC_RATES
)
963 rtl8180_conf_basic_rates(dev
, info
->basic_rates
);
965 if (changed
& (BSS_CHANGED_ERP_SLOT
| BSS_CHANGED_ERP_PREAMBLE
)) {
967 /* when preamble changes, acktime duration changes, and erp must
968 * be recalculated. ACK time is calculated at lowest rate.
969 * Since mac80211 include SIFS time we remove it (-10)
972 le16_to_cpu(ieee80211_generic_frame_duration(dev
,
974 IEEE80211_BAND_2GHZ
, 10,
975 &priv
->rates
[0])) - 10;
977 rtl8180_conf_erp(dev
, info
);
980 if (changed
& BSS_CHANGED_BEACON_ENABLED
)
981 vif_priv
->enable_beacon
= info
->enable_beacon
;
983 if (changed
& (BSS_CHANGED_BEACON_ENABLED
| BSS_CHANGED_BEACON
)) {
984 cancel_delayed_work_sync(&vif_priv
->beacon_work
);
985 if (vif_priv
->enable_beacon
)
986 schedule_work(&vif_priv
->beacon_work
.work
);
990 static u64
rtl8180_prepare_multicast(struct ieee80211_hw
*dev
,
991 struct netdev_hw_addr_list
*mc_list
)
993 return netdev_hw_addr_list_count(mc_list
);
996 static void rtl8180_configure_filter(struct ieee80211_hw
*dev
,
997 unsigned int changed_flags
,
998 unsigned int *total_flags
,
1001 struct rtl8180_priv
*priv
= dev
->priv
;
1003 if (changed_flags
& FIF_FCSFAIL
)
1004 priv
->rx_conf
^= RTL818X_RX_CONF_FCS
;
1005 if (changed_flags
& FIF_CONTROL
)
1006 priv
->rx_conf
^= RTL818X_RX_CONF_CTRL
;
1007 if (changed_flags
& FIF_OTHER_BSS
)
1008 priv
->rx_conf
^= RTL818X_RX_CONF_MONITOR
;
1009 if (*total_flags
& FIF_ALLMULTI
|| multicast
> 0)
1010 priv
->rx_conf
|= RTL818X_RX_CONF_MULTICAST
;
1012 priv
->rx_conf
&= ~RTL818X_RX_CONF_MULTICAST
;
1016 if (priv
->rx_conf
& RTL818X_RX_CONF_FCS
)
1017 *total_flags
|= FIF_FCSFAIL
;
1018 if (priv
->rx_conf
& RTL818X_RX_CONF_CTRL
)
1019 *total_flags
|= FIF_CONTROL
;
1020 if (priv
->rx_conf
& RTL818X_RX_CONF_MONITOR
)
1021 *total_flags
|= FIF_OTHER_BSS
;
1022 if (priv
->rx_conf
& RTL818X_RX_CONF_MULTICAST
)
1023 *total_flags
|= FIF_ALLMULTI
;
1025 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, priv
->rx_conf
);
1028 static const struct ieee80211_ops rtl8180_ops
= {
1030 .start
= rtl8180_start
,
1031 .stop
= rtl8180_stop
,
1032 .add_interface
= rtl8180_add_interface
,
1033 .remove_interface
= rtl8180_remove_interface
,
1034 .config
= rtl8180_config
,
1035 .bss_info_changed
= rtl8180_bss_info_changed
,
1036 .conf_tx
= rtl8180_conf_tx
,
1037 .prepare_multicast
= rtl8180_prepare_multicast
,
1038 .configure_filter
= rtl8180_configure_filter
,
1039 .get_tsf
= rtl8180_get_tsf
,
1042 static void rtl8180_eeprom_register_read(struct eeprom_93cx6
*eeprom
)
1044 struct rtl8180_priv
*priv
= eeprom
->data
;
1045 u8 reg
= rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1047 eeprom
->reg_data_in
= reg
& RTL818X_EEPROM_CMD_WRITE
;
1048 eeprom
->reg_data_out
= reg
& RTL818X_EEPROM_CMD_READ
;
1049 eeprom
->reg_data_clock
= reg
& RTL818X_EEPROM_CMD_CK
;
1050 eeprom
->reg_chip_select
= reg
& RTL818X_EEPROM_CMD_CS
;
1053 static void rtl8180_eeprom_register_write(struct eeprom_93cx6
*eeprom
)
1055 struct rtl8180_priv
*priv
= eeprom
->data
;
1058 if (eeprom
->reg_data_in
)
1059 reg
|= RTL818X_EEPROM_CMD_WRITE
;
1060 if (eeprom
->reg_data_out
)
1061 reg
|= RTL818X_EEPROM_CMD_READ
;
1062 if (eeprom
->reg_data_clock
)
1063 reg
|= RTL818X_EEPROM_CMD_CK
;
1064 if (eeprom
->reg_chip_select
)
1065 reg
|= RTL818X_EEPROM_CMD_CS
;
1067 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, reg
);
1068 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1072 static void rtl8180_eeprom_read(struct rtl8180_priv
*priv
)
1074 struct eeprom_93cx6 eeprom
;
1075 int eeprom_cck_table_adr
;
1080 eeprom
.register_read
= rtl8180_eeprom_register_read
;
1081 eeprom
.register_write
= rtl8180_eeprom_register_write
;
1082 if (rtl818x_ioread32(priv
, &priv
->map
->RX_CONF
) & (1 << 6))
1083 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
1085 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
1087 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1088 RTL818X_EEPROM_CMD_PROGRAM
);
1089 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1092 eeprom_93cx6_read(&eeprom
, 0x06, &eeprom_val
);
1094 priv
->rf_type
= eeprom_val
;
1096 eeprom_93cx6_read(&eeprom
, 0x17, &eeprom_val
);
1097 priv
->csthreshold
= eeprom_val
>> 8;
1099 eeprom_93cx6_multiread(&eeprom
, 0x7, (__le16
*)priv
->mac_addr
, 3);
1101 eeprom_cck_table_adr
= 0x10;
1104 for (i
= 0; i
< 14; i
+= 2) {
1106 eeprom_93cx6_read(&eeprom
, eeprom_cck_table_adr
+ (i
>> 1),
1108 priv
->channels
[i
].hw_value
= txpwr
& 0xFF;
1109 priv
->channels
[i
+ 1].hw_value
= txpwr
>> 8;
1113 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1114 for (i
= 0; i
< 14; i
+= 2) {
1116 eeprom_93cx6_read(&eeprom
, 0x20 + (i
>> 1), &txpwr
);
1117 priv
->channels
[i
].hw_value
|= (txpwr
& 0xFF) << 8;
1118 priv
->channels
[i
+ 1].hw_value
|= txpwr
& 0xFF00;
1122 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
1124 eeprom_93cx6_multiread(&eeprom
, 0xD, (__le16
*)&anaparam
, 2);
1125 priv
->anaparam
= le32_to_cpu(anaparam
);
1126 eeprom_93cx6_read(&eeprom
, 0x19, &priv
->rfparam
);
1129 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1130 RTL818X_EEPROM_CMD_NORMAL
);
1133 static int rtl8180_probe(struct pci_dev
*pdev
,
1134 const struct pci_device_id
*id
)
1136 struct ieee80211_hw
*dev
;
1137 struct rtl8180_priv
*priv
;
1138 unsigned long mem_addr
, mem_len
;
1139 unsigned int io_addr
, io_len
;
1141 const char *chip_name
, *rf_name
= NULL
;
1144 err
= pci_enable_device(pdev
);
1146 printk(KERN_ERR
"%s (rtl8180): Cannot enable new PCI device\n",
1151 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
1153 printk(KERN_ERR
"%s (rtl8180): Cannot obtain PCI resources\n",
1158 io_addr
= pci_resource_start(pdev
, 0);
1159 io_len
= pci_resource_len(pdev
, 0);
1160 mem_addr
= pci_resource_start(pdev
, 1);
1161 mem_len
= pci_resource_len(pdev
, 1);
1163 if (mem_len
< sizeof(struct rtl818x_csr
) ||
1164 io_len
< sizeof(struct rtl818x_csr
)) {
1165 printk(KERN_ERR
"%s (rtl8180): Too short PCI resources\n",
1171 if ((err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) ||
1172 (err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))) {
1173 printk(KERN_ERR
"%s (rtl8180): No suitable DMA available\n",
1178 pci_set_master(pdev
);
1180 dev
= ieee80211_alloc_hw(sizeof(*priv
), &rtl8180_ops
);
1182 printk(KERN_ERR
"%s (rtl8180): ieee80211 alloc failed\n",
1192 SET_IEEE80211_DEV(dev
, &pdev
->dev
);
1193 pci_set_drvdata(pdev
, dev
);
1195 priv
->map
= pci_iomap(pdev
, 1, mem_len
);
1197 priv
->map
= pci_iomap(pdev
, 0, io_len
);
1200 printk(KERN_ERR
"%s (rtl8180): Cannot map device memory\n",
1205 BUILD_BUG_ON(sizeof(priv
->channels
) != sizeof(rtl818x_channels
));
1206 BUILD_BUG_ON(sizeof(priv
->rates
) != sizeof(rtl818x_rates
));
1208 memcpy(priv
->channels
, rtl818x_channels
, sizeof(rtl818x_channels
));
1209 memcpy(priv
->rates
, rtl818x_rates
, sizeof(rtl818x_rates
));
1211 priv
->band
.band
= IEEE80211_BAND_2GHZ
;
1212 priv
->band
.channels
= priv
->channels
;
1213 priv
->band
.n_channels
= ARRAY_SIZE(rtl818x_channels
);
1214 priv
->band
.bitrates
= priv
->rates
;
1215 priv
->band
.n_bitrates
= 4;
1216 dev
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &priv
->band
;
1218 dev
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1219 IEEE80211_HW_RX_INCLUDES_FCS
|
1220 IEEE80211_HW_SIGNAL_UNSPEC
;
1221 dev
->vif_data_size
= sizeof(struct rtl8180_vif
);
1222 dev
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
) |
1223 BIT(NL80211_IFTYPE_ADHOC
);
1225 dev
->max_signal
= 65;
1227 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
1228 reg
&= RTL818X_TX_CONF_HWVER_MASK
;
1230 case RTL818X_TX_CONF_R8180_ABCD
:
1231 chip_name
= "RTL8180";
1232 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1235 case RTL818X_TX_CONF_R8180_F
:
1236 chip_name
= "RTL8180vF";
1237 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1240 case RTL818X_TX_CONF_R8185_ABC
:
1241 chip_name
= "RTL8185";
1242 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1245 case RTL818X_TX_CONF_R8185_D
:
1246 chip_name
= "RTL8185vD";
1247 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1250 printk(KERN_ERR
"%s (rtl8180): Unknown chip! (0x%x)\n",
1251 pci_name(pdev
), reg
>> 25);
1255 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1256 priv
->band
.n_bitrates
= ARRAY_SIZE(rtl818x_rates
);
1257 pci_try_set_mwi(pdev
);
1260 rtl8180_eeprom_read(priv
);
1262 switch (priv
->rf_type
) {
1263 case 1: rf_name
= "Intersil";
1265 case 2: rf_name
= "RFMD";
1267 case 3: priv
->rf
= &sa2400_rf_ops
;
1269 case 4: priv
->rf
= &max2820_rf_ops
;
1271 case 5: priv
->rf
= &grf5101_rf_ops
;
1273 case 9: priv
->rf
= rtl8180_detect_rf(dev
);
1276 rf_name
= "RTL8255";
1279 printk(KERN_ERR
"%s (rtl8180): Unknown RF! (0x%x)\n",
1280 pci_name(pdev
), priv
->rf_type
);
1285 printk(KERN_ERR
"%s (rtl8180): %s RF frontend not supported!\n",
1286 pci_name(pdev
), rf_name
);
1290 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1291 printk(KERN_WARNING
"%s (rtl8180): Invalid hwaddr! Using"
1292 " randomly generated MAC addr\n", pci_name(pdev
));
1293 eth_random_addr(priv
->mac_addr
);
1295 SET_IEEE80211_PERM_ADDR(dev
, priv
->mac_addr
);
1297 spin_lock_init(&priv
->lock
);
1299 err
= ieee80211_register_hw(dev
);
1301 printk(KERN_ERR
"%s (rtl8180): Cannot register device\n",
1306 wiphy_info(dev
->wiphy
, "hwaddr %pm, %s + %s\n",
1307 priv
->mac_addr
, chip_name
, priv
->rf
->name
);
1312 pci_iounmap(pdev
, priv
->map
);
1315 ieee80211_free_hw(dev
);
1318 pci_release_regions(pdev
);
1319 pci_disable_device(pdev
);
1323 static void rtl8180_remove(struct pci_dev
*pdev
)
1325 struct ieee80211_hw
*dev
= pci_get_drvdata(pdev
);
1326 struct rtl8180_priv
*priv
;
1331 ieee80211_unregister_hw(dev
);
1335 pci_iounmap(pdev
, priv
->map
);
1336 pci_release_regions(pdev
);
1337 pci_disable_device(pdev
);
1338 ieee80211_free_hw(dev
);
1342 static int rtl8180_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1344 pci_save_state(pdev
);
1345 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1349 static int rtl8180_resume(struct pci_dev
*pdev
)
1351 pci_set_power_state(pdev
, PCI_D0
);
1352 pci_restore_state(pdev
);
1356 #endif /* CONFIG_PM */
1358 static struct pci_driver rtl8180_driver
= {
1359 .name
= KBUILD_MODNAME
,
1360 .id_table
= rtl8180_table
,
1361 .probe
= rtl8180_probe
,
1362 .remove
= rtl8180_remove
,
1364 .suspend
= rtl8180_suspend
,
1365 .resume
= rtl8180_resume
,
1366 #endif /* CONFIG_PM */
1369 module_pci_driver(rtl8180_driver
);