3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table
) = {
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x701f) },
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x3300) },
49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
54 MODULE_DEVICE_TABLE(pci
, rtl8180_table
);
56 static const struct ieee80211_rate rtl818x_rates
[] = {
57 { .bitrate
= 10, .hw_value
= 0, },
58 { .bitrate
= 20, .hw_value
= 1, },
59 { .bitrate
= 55, .hw_value
= 2, },
60 { .bitrate
= 110, .hw_value
= 3, },
61 { .bitrate
= 60, .hw_value
= 4, },
62 { .bitrate
= 90, .hw_value
= 5, },
63 { .bitrate
= 120, .hw_value
= 6, },
64 { .bitrate
= 180, .hw_value
= 7, },
65 { .bitrate
= 240, .hw_value
= 8, },
66 { .bitrate
= 360, .hw_value
= 9, },
67 { .bitrate
= 480, .hw_value
= 10, },
68 { .bitrate
= 540, .hw_value
= 11, },
71 static const struct ieee80211_channel rtl818x_channels
[] = {
72 { .center_freq
= 2412 },
73 { .center_freq
= 2417 },
74 { .center_freq
= 2422 },
75 { .center_freq
= 2427 },
76 { .center_freq
= 2432 },
77 { .center_freq
= 2437 },
78 { .center_freq
= 2442 },
79 { .center_freq
= 2447 },
80 { .center_freq
= 2452 },
81 { .center_freq
= 2457 },
82 { .center_freq
= 2462 },
83 { .center_freq
= 2467 },
84 { .center_freq
= 2472 },
85 { .center_freq
= 2484 },
88 /* Queues for rtl8187se card
99 * The complete map for DMA kick reg using use all queue is:
100 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
101 * {1, 6, 5, 4, 3, 2, 7};
103 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
106 * BC | 7 | 4 <- currently not used yet
107 * MG | 1 | x <- Not used
108 * HI | 6 | x <- Not used
114 * Beacon queue could be used, but this is not finished yet.
116 * I thougth about using the other two queues but I decided not to do this:
118 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
121 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
122 * queue but since mac80211 will do not know about it, I will probably gain
123 * some HW priority whenever the VO queue is not empty, but this gain is
124 * limited by the fact that I had to stop the mac80211 queue whenever one of
125 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
128 * - I don't know how to set in the HW the contention window params for MGMT
129 * and HI-prio queues.
132 static const int rtl8187se_queues_map
[RTL8187SE_NR_TX_QUEUES
] = {5, 4, 3, 2, 7};
134 /* Queues for rtl8180/rtl8185 cards
142 * The complete map for DMA kick reg using all queue is:
143 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
145 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
146 * otherwise QoS can't be done, we use just one.
147 * Beacon queue could be used, but this is not finished yet.
151 * BC | 7 | 1 <- currently not used yet.
152 * HI | 6 | x <- not used
153 * NO | 5 | x <- not used
157 static const int rtl8180_queues_map
[RTL8180_NR_TX_QUEUES
] = {4, 7};
159 void rtl8180_write_phy(struct ieee80211_hw
*dev
, u8 addr
, u32 data
)
161 struct rtl8180_priv
*priv
= dev
->priv
;
165 buf
= (data
<< 8) | addr
;
167 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
| 0x80);
169 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
);
170 if (rtl818x_ioread8(priv
, &priv
->map
->PHY
[2]) == (data
& 0xFF))
175 static void rtl8180_handle_rx(struct ieee80211_hw
*dev
)
177 struct rtl8180_priv
*priv
= dev
->priv
;
178 struct rtl818x_rx_cmd_desc
*cmd_desc
;
179 unsigned int count
= 32;
184 void *entry
= priv
->rx_ring
+ priv
->rx_idx
* priv
->rx_ring_sz
;
185 struct sk_buff
*skb
= priv
->rx_buf
[priv
->rx_idx
];
189 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
190 struct rtl8187se_rx_desc
*desc
= entry
;
192 flags
= le32_to_cpu(desc
->flags
);
193 flags2
= le32_to_cpu(desc
->flags2
);
194 tsft
= le64_to_cpu(desc
->tsft
);
196 struct rtl8180_rx_desc
*desc
= entry
;
198 flags
= le32_to_cpu(desc
->flags
);
199 flags2
= le32_to_cpu(desc
->flags2
);
200 tsft
= le64_to_cpu(desc
->tsft
);
203 if (flags
& RTL818X_RX_DESC_FLAG_OWN
)
206 if (unlikely(flags
& (RTL818X_RX_DESC_FLAG_DMA_FAIL
|
207 RTL818X_RX_DESC_FLAG_FOF
|
208 RTL818X_RX_DESC_FLAG_RX_ERR
)))
211 struct ieee80211_rx_status rx_status
= {0};
212 struct sk_buff
*new_skb
= dev_alloc_skb(MAX_RX_SIZE
);
214 if (unlikely(!new_skb
))
217 mapping
= pci_map_single(priv
->pdev
,
218 skb_tail_pointer(new_skb
),
219 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
221 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
223 dev_err(&priv
->pdev
->dev
, "RX DMA map error\n");
228 pci_unmap_single(priv
->pdev
,
229 *((dma_addr_t
*)skb
->cb
),
230 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
231 skb_put(skb
, flags
& 0xFFF);
233 rx_status
.antenna
= (flags2
>> 15) & 1;
234 rx_status
.rate_idx
= (flags
>> 20) & 0xF;
235 agc
= (flags2
>> 17) & 0x7F;
237 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
238 if (rx_status
.rate_idx
> 3)
239 signal
= 90 - clamp_t(u8
, agc
, 25, 90);
241 signal
= 95 - clamp_t(u8
, agc
, 30, 95);
242 } else if (priv
->chip_family
==
243 RTL818X_CHIP_FAMILY_RTL8180
) {
245 signal
= priv
->rf
->calc_rssi(agc
, sq
);
247 /* TODO: rtl8187se rssi */
250 rx_status
.signal
= signal
;
251 rx_status
.freq
= dev
->conf
.chandef
.chan
->center_freq
;
252 rx_status
.band
= dev
->conf
.chandef
.chan
->band
;
253 rx_status
.mactime
= tsft
;
254 rx_status
.flag
|= RX_FLAG_MACTIME_START
;
255 if (flags
& RTL818X_RX_DESC_FLAG_CRC32_ERR
)
256 rx_status
.flag
|= RX_FLAG_FAILED_FCS_CRC
;
258 memcpy(IEEE80211_SKB_RXCB(skb
), &rx_status
, sizeof(rx_status
));
259 ieee80211_rx_irqsafe(dev
, skb
);
262 priv
->rx_buf
[priv
->rx_idx
] = skb
;
263 *((dma_addr_t
*) skb
->cb
) = mapping
;
268 cmd_desc
->rx_buf
= cpu_to_le32(*((dma_addr_t
*)skb
->cb
));
269 cmd_desc
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
271 if (priv
->rx_idx
== 31)
273 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
274 priv
->rx_idx
= (priv
->rx_idx
+ 1) % 32;
278 static void rtl8180_handle_tx(struct ieee80211_hw
*dev
, unsigned int prio
)
280 struct rtl8180_priv
*priv
= dev
->priv
;
281 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
283 while (skb_queue_len(&ring
->queue
)) {
284 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
286 struct ieee80211_tx_info
*info
;
287 u32 flags
= le32_to_cpu(entry
->flags
);
289 if (flags
& RTL818X_TX_DESC_FLAG_OWN
)
292 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
293 skb
= __skb_dequeue(&ring
->queue
);
294 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
295 skb
->len
, PCI_DMA_TODEVICE
);
297 info
= IEEE80211_SKB_CB(skb
);
298 ieee80211_tx_info_clear_status(info
);
300 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
) &&
301 (flags
& RTL818X_TX_DESC_FLAG_TX_OK
))
302 info
->flags
|= IEEE80211_TX_STAT_ACK
;
304 info
->status
.rates
[0].count
= (flags
& 0xFF) + 1;
305 info
->status
.rates
[1].idx
= -1;
307 ieee80211_tx_status_irqsafe(dev
, skb
);
308 if (ring
->entries
- skb_queue_len(&ring
->queue
) == 2)
309 ieee80211_wake_queue(dev
, prio
);
313 static irqreturn_t
rtl8187se_interrupt(int irq
, void *dev_id
)
315 struct ieee80211_hw
*dev
= dev_id
;
316 struct rtl8180_priv
*priv
= dev
->priv
;
321 spin_lock_irqsave(&priv
->lock
, flags
);
322 /* Note: 32-bit interrupt status */
323 reg
= rtl818x_ioread32(priv
, &priv
->map
->INT_STATUS_SE
);
324 if (unlikely(reg
== 0xFFFFFFFF)) {
325 spin_unlock_irqrestore(&priv
->lock
, flags
);
329 rtl818x_iowrite32(priv
, &priv
->map
->INT_STATUS_SE
, reg
);
331 if (reg
& IMR_TIMEOUT1
)
332 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
334 if (reg
& (IMR_TBDOK
| IMR_TBDER
))
335 rtl8180_handle_tx(dev
, 4);
337 if (reg
& (IMR_TVODOK
| IMR_TVODER
))
338 rtl8180_handle_tx(dev
, 0);
340 if (reg
& (IMR_TVIDOK
| IMR_TVIDER
))
341 rtl8180_handle_tx(dev
, 1);
343 if (reg
& (IMR_TBEDOK
| IMR_TBEDER
))
344 rtl8180_handle_tx(dev
, 2);
346 if (reg
& (IMR_TBKDOK
| IMR_TBKDER
))
347 rtl8180_handle_tx(dev
, 3);
349 if (reg
& (IMR_ROK
| IMR_RER
| RTL818X_INT_SE_RX_DU
| IMR_RQOSOK
))
350 rtl8180_handle_rx(dev
);
351 /* The interface sometimes generates several RX DMA descriptor errors
352 * at startup. Do not report these.
354 if ((reg
& RTL818X_INT_SE_RX_DU
) && desc_err
++ > 2)
356 wiphy_err(dev
->wiphy
, "No RX DMA Descriptor avail\n");
358 spin_unlock_irqrestore(&priv
->lock
, flags
);
362 static irqreturn_t
rtl8180_interrupt(int irq
, void *dev_id
)
364 struct ieee80211_hw
*dev
= dev_id
;
365 struct rtl8180_priv
*priv
= dev
->priv
;
368 spin_lock(&priv
->lock
);
369 reg
= rtl818x_ioread16(priv
, &priv
->map
->INT_STATUS
);
370 if (unlikely(reg
== 0xFFFF)) {
371 spin_unlock(&priv
->lock
);
375 rtl818x_iowrite16(priv
, &priv
->map
->INT_STATUS
, reg
);
377 if (reg
& (RTL818X_INT_TXB_OK
| RTL818X_INT_TXB_ERR
))
378 rtl8180_handle_tx(dev
, 1);
380 if (reg
& (RTL818X_INT_TXL_OK
| RTL818X_INT_TXL_ERR
))
381 rtl8180_handle_tx(dev
, 0);
383 if (reg
& (RTL818X_INT_RX_OK
| RTL818X_INT_RX_ERR
))
384 rtl8180_handle_rx(dev
);
386 spin_unlock(&priv
->lock
);
391 static void rtl8180_tx(struct ieee80211_hw
*dev
,
392 struct ieee80211_tx_control
*control
,
395 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
396 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
397 struct rtl8180_priv
*priv
= dev
->priv
;
398 struct rtl8180_tx_ring
*ring
;
399 struct rtl8180_tx_desc
*entry
;
401 unsigned int idx
, prio
, hw_prio
;
406 __le16 rts_duration
= 0;
407 /* do arithmetic and then convert to le16 */
408 u16 frame_duration
= 0;
410 prio
= skb_get_queue_mapping(skb
);
411 ring
= &priv
->tx_ring
[prio
];
413 mapping
= pci_map_single(priv
->pdev
, skb
->data
,
414 skb
->len
, PCI_DMA_TODEVICE
);
416 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
418 dev_err(&priv
->pdev
->dev
, "TX DMA mapping error\n");
422 tx_flags
= RTL818X_TX_DESC_FLAG_OWN
| RTL818X_TX_DESC_FLAG_FS
|
423 RTL818X_TX_DESC_FLAG_LS
|
424 (ieee80211_get_tx_rate(dev
, info
)->hw_value
<< 24) |
427 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
428 tx_flags
|= RTL818X_TX_DESC_FLAG_DMA
|
429 RTL818X_TX_DESC_FLAG_NO_ENC
;
431 rc_flags
= info
->control
.rates
[0].flags
;
432 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
433 tx_flags
|= RTL818X_TX_DESC_FLAG_RTS
;
434 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
435 } else if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
436 tx_flags
|= RTL818X_TX_DESC_FLAG_CTS
;
437 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
440 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
441 rts_duration
= ieee80211_rts_duration(dev
, priv
->vif
, skb
->len
,
444 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
445 unsigned int remainder
;
447 plcp_len
= DIV_ROUND_UP(16 * (skb
->len
+ 4),
448 (ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
449 remainder
= (16 * (skb
->len
+ 4)) %
450 ((ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
455 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
457 /* SIFS time (required by HW) is already included by
458 * ieee80211_generic_frame_duration
460 duration
= ieee80211_generic_frame_duration(dev
, priv
->vif
,
461 IEEE80211_BAND_2GHZ
, skb
->len
,
462 ieee80211_get_tx_rate(dev
, info
));
464 frame_duration
= priv
->ack_time
+ le16_to_cpu(duration
);
467 spin_lock_irqsave(&priv
->lock
, flags
);
469 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
470 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
472 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
473 hdr
->seq_ctrl
|= cpu_to_le16(priv
->seqno
);
476 idx
= (ring
->idx
+ skb_queue_len(&ring
->queue
)) % ring
->entries
;
477 entry
= &ring
->desc
[idx
];
479 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
480 entry
->frame_duration
= cpu_to_le16(frame_duration
);
481 entry
->frame_len_se
= cpu_to_le16(skb
->len
);
484 entry
->flags3
= cpu_to_le16(1<<4);
486 entry
->frame_len
= cpu_to_le32(skb
->len
);
488 entry
->rts_duration
= rts_duration
;
489 entry
->plcp_len
= cpu_to_le16(plcp_len
);
490 entry
->tx_buf
= cpu_to_le32(mapping
);
492 entry
->flags2
= info
->control
.rates
[1].idx
>= 0 ?
493 ieee80211_get_alt_retry_rate(dev
, info
, 0)->bitrate
<< 4 : 0;
494 entry
->retry_limit
= info
->control
.rates
[0].count
;
496 /* We must be sure that tx_flags is written last because the HW
497 * looks at it to check if the rest of data is valid or not
500 entry
->flags
= cpu_to_le32(tx_flags
);
501 /* We must be sure this has been written before followings HW
502 * register write, because this write will made the HW attempts
503 * to DMA the just-written data
507 __skb_queue_tail(&ring
->queue
, skb
);
508 if (ring
->entries
- skb_queue_len(&ring
->queue
) < 2)
509 ieee80211_stop_queue(dev
, prio
);
511 spin_unlock_irqrestore(&priv
->lock
, flags
);
513 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
514 /* just poll: rings are stopped with TPPollStop reg */
515 hw_prio
= rtl8187se_queues_map
[prio
];
516 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
519 hw_prio
= rtl8180_queues_map
[prio
];
520 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
521 (1 << hw_prio
) | /* ring to poll */
522 (1<<1) | (1<<2));/* stopped rings */
526 static void rtl8180_set_anaparam3(struct rtl8180_priv
*priv
, u16 anaparam3
)
530 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
531 RTL818X_EEPROM_CMD_CONFIG
);
533 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
534 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
535 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
537 rtl818x_iowrite16(priv
, &priv
->map
->ANAPARAM3
, anaparam3
);
539 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
540 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
542 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
543 RTL818X_EEPROM_CMD_NORMAL
);
546 void rtl8180_set_anaparam2(struct rtl8180_priv
*priv
, u32 anaparam2
)
550 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
551 RTL818X_EEPROM_CMD_CONFIG
);
553 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
554 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
555 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
557 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM2
, anaparam2
);
559 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
560 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
562 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
563 RTL818X_EEPROM_CMD_NORMAL
);
566 void rtl8180_set_anaparam(struct rtl8180_priv
*priv
, u32 anaparam
)
570 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
571 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
572 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
573 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
574 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM
, anaparam
);
575 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
576 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
577 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
580 static void rtl8180_int_enable(struct ieee80211_hw
*dev
)
582 struct rtl8180_priv
*priv
= dev
->priv
;
584 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
585 rtl818x_iowrite32(priv
, &priv
->map
->IMR
, IMR_TMGDOK
|
586 IMR_TBDER
| IMR_THPDER
|
587 IMR_THPDER
| IMR_THPDOK
|
588 IMR_TVODER
| IMR_TVODOK
|
589 IMR_TVIDER
| IMR_TVIDOK
|
590 IMR_TBEDER
| IMR_TBEDOK
|
591 IMR_TBKDER
| IMR_TBKDOK
|
593 IMR_ROK
| IMR_RQOSOK
);
595 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0xFFFF);
599 static void rtl8180_int_disable(struct ieee80211_hw
*dev
)
601 struct rtl8180_priv
*priv
= dev
->priv
;
603 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
604 rtl818x_iowrite32(priv
, &priv
->map
->IMR
, 0);
606 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
610 static void rtl8180_conf_basic_rates(struct ieee80211_hw
*dev
,
613 struct rtl8180_priv
*priv
= dev
->priv
;
618 max
= fls(rates_mask
) - 1;
619 min
= ffs(rates_mask
) - 1;
621 switch (priv
->chip_family
) {
623 case RTL818X_CHIP_FAMILY_RTL8180
:
624 /* in 8180 this is NOT a BITMAP */
625 reg
= rtl818x_ioread16(priv
, &priv
->map
->BRSR
);
628 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, reg
);
631 case RTL818X_CHIP_FAMILY_RTL8185
:
632 /* in 8185 this is a BITMAP */
633 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, rates_mask
);
634 rtl818x_iowrite8(priv
, &priv
->map
->RESP_RATE
, (max
<< 4) | min
);
637 case RTL818X_CHIP_FAMILY_RTL8187SE
:
638 /* in 8187se this is a BITMAP */
639 rtl818x_iowrite16(priv
, &priv
->map
->BRSR_8187SE
, rates_mask
);
644 static void rtl8180_config_cardbus(struct ieee80211_hw
*dev
)
646 struct rtl8180_priv
*priv
= dev
->priv
;
650 reg8
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
652 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg8
);
654 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
655 rtl818x_iowrite16(priv
, FEMR_SE
, 0xffff);
657 reg16
= rtl818x_ioread16(priv
, &priv
->map
->FEMR
);
658 reg16
|= (1 << 15) | (1 << 14) | (1 << 4);
659 rtl818x_iowrite16(priv
, &priv
->map
->FEMR
, reg16
);
664 static int rtl8180_init_hw(struct ieee80211_hw
*dev
)
666 struct rtl8180_priv
*priv
= dev
->priv
;
669 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, 0);
670 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
674 rtl8180_int_disable(dev
);
675 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
677 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
679 reg
|= RTL818X_CMD_RESET
;
680 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, RTL818X_CMD_RESET
);
681 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
684 /* check success of reset */
685 if (rtl818x_ioread8(priv
, &priv
->map
->CMD
) & RTL818X_CMD_RESET
) {
686 wiphy_err(dev
->wiphy
, "reset timeout!\n");
690 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_LOAD
);
691 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
694 if (rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
) & (1 << 3)) {
695 rtl8180_config_cardbus(dev
);
698 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, 0);
700 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
701 rtl8180_set_anaparam(priv
, priv
->anaparam
);
703 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
704 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
, priv
->tx_ring
[1].dma
);
705 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
, priv
->tx_ring
[0].dma
);
707 /* TODO: necessary? specs indicate not */
708 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
709 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
710 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
& ~(1 << 3));
711 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
712 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
713 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
| (1 << 4));
715 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
717 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
719 /* TODO: turn off hw wep on rtl8180 */
721 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
723 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
724 rtl818x_iowrite8(priv
, &priv
->map
->WPA_CONF
, 0);
725 rtl818x_iowrite8(priv
, &priv
->map
->RATE_FALLBACK
, 0x81);
727 /* TODO: set ClkRun enable? necessary? */
728 reg
= rtl818x_ioread8(priv
, &priv
->map
->GP_ENABLE
);
729 rtl818x_iowrite8(priv
, &priv
->map
->GP_ENABLE
, reg
& ~(1 << 6));
730 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
731 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
732 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
| (1 << 2));
733 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
735 rtl818x_iowrite8(priv
, &priv
->map
->SECURITY
, 0);
737 rtl818x_iowrite8(priv
, &priv
->map
->PHY_DELAY
, 0x6);
738 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, 0x4C);
743 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
744 * otherwise. bitmask 0x3 and 0x01f3 respectively.
745 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
746 * this after rf init.
747 * TODO: try to find out whether RF code really needs to do this..
749 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
750 rtl8180_conf_basic_rates(dev
, 0x3);
752 rtl8180_conf_basic_rates(dev
, 0x1f3);
757 static int rtl8180_init_rx_ring(struct ieee80211_hw
*dev
)
759 struct rtl8180_priv
*priv
= dev
->priv
;
760 struct rtl818x_rx_cmd_desc
*entry
;
763 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
764 priv
->rx_ring_sz
= sizeof(struct rtl8187se_rx_desc
);
766 priv
->rx_ring_sz
= sizeof(struct rtl8180_rx_desc
);
768 priv
->rx_ring
= pci_alloc_consistent(priv
->pdev
,
769 priv
->rx_ring_sz
* 32,
772 if (!priv
->rx_ring
|| (unsigned long)priv
->rx_ring
& 0xFF) {
773 wiphy_err(dev
->wiphy
, "Cannot allocate RX ring\n");
777 memset(priv
->rx_ring
, 0, priv
->rx_ring_sz
* 32);
780 for (i
= 0; i
< 32; i
++) {
781 struct sk_buff
*skb
= dev_alloc_skb(MAX_RX_SIZE
);
783 entry
= priv
->rx_ring
+ priv
->rx_ring_sz
*i
;
785 wiphy_err(dev
->wiphy
, "Cannot allocate RX skb\n");
788 priv
->rx_buf
[i
] = skb
;
789 mapping
= (dma_addr_t
*)skb
->cb
;
790 *mapping
= pci_map_single(priv
->pdev
, skb_tail_pointer(skb
),
791 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
793 if (pci_dma_mapping_error(priv
->pdev
, *mapping
)) {
795 wiphy_err(dev
->wiphy
, "Cannot map DMA for RX skb\n");
799 entry
->rx_buf
= cpu_to_le32(*mapping
);
800 entry
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
803 entry
->flags
|= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
807 static void rtl8180_free_rx_ring(struct ieee80211_hw
*dev
)
809 struct rtl8180_priv
*priv
= dev
->priv
;
812 for (i
= 0; i
< 32; i
++) {
813 struct sk_buff
*skb
= priv
->rx_buf
[i
];
817 pci_unmap_single(priv
->pdev
,
818 *((dma_addr_t
*)skb
->cb
),
819 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
823 pci_free_consistent(priv
->pdev
, priv
->rx_ring_sz
* 32,
824 priv
->rx_ring
, priv
->rx_ring_dma
);
825 priv
->rx_ring
= NULL
;
828 static int rtl8180_init_tx_ring(struct ieee80211_hw
*dev
,
829 unsigned int prio
, unsigned int entries
)
831 struct rtl8180_priv
*priv
= dev
->priv
;
832 struct rtl8180_tx_desc
*ring
;
836 ring
= pci_alloc_consistent(priv
->pdev
, sizeof(*ring
) * entries
, &dma
);
837 if (!ring
|| (unsigned long)ring
& 0xFF) {
838 wiphy_err(dev
->wiphy
, "Cannot allocate TX ring (prio = %d)\n",
843 memset(ring
, 0, sizeof(*ring
)*entries
);
844 priv
->tx_ring
[prio
].desc
= ring
;
845 priv
->tx_ring
[prio
].dma
= dma
;
846 priv
->tx_ring
[prio
].idx
= 0;
847 priv
->tx_ring
[prio
].entries
= entries
;
848 skb_queue_head_init(&priv
->tx_ring
[prio
].queue
);
850 for (i
= 0; i
< entries
; i
++)
851 ring
[i
].next_tx_desc
=
852 cpu_to_le32((u32
)dma
+ ((i
+ 1) % entries
) * sizeof(*ring
));
857 static void rtl8180_free_tx_ring(struct ieee80211_hw
*dev
, unsigned int prio
)
859 struct rtl8180_priv
*priv
= dev
->priv
;
860 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
862 while (skb_queue_len(&ring
->queue
)) {
863 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
864 struct sk_buff
*skb
= __skb_dequeue(&ring
->queue
);
866 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
867 skb
->len
, PCI_DMA_TODEVICE
);
869 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
872 pci_free_consistent(priv
->pdev
, sizeof(*ring
->desc
)*ring
->entries
,
873 ring
->desc
, ring
->dma
);
877 static int rtl8180_start(struct ieee80211_hw
*dev
)
879 struct rtl8180_priv
*priv
= dev
->priv
;
883 ret
= rtl8180_init_rx_ring(dev
);
887 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
888 if ((ret
= rtl8180_init_tx_ring(dev
, i
, 16)))
891 ret
= rtl8180_init_hw(dev
);
895 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
896 ret
= request_irq(priv
->pdev
->irq
, rtl8187se_interrupt
,
897 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
899 ret
= request_irq(priv
->pdev
->irq
, rtl8180_interrupt
,
900 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
904 wiphy_err(dev
->wiphy
, "failed to register IRQ handler\n");
908 rtl8180_int_enable(dev
);
910 /* in rtl8187se at MAR regs offset there is the management
911 * TX descriptor DMA addres..
913 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8187SE
) {
914 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[0], ~0);
915 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[1], ~0);
918 reg
= RTL818X_RX_CONF_ONLYERLPKT
|
919 RTL818X_RX_CONF_RX_AUTORESETPHY
|
920 RTL818X_RX_CONF_MGMT
|
921 RTL818X_RX_CONF_DATA
|
922 (7 << 8 /* MAX RX DMA */) |
923 RTL818X_RX_CONF_BROADCAST
|
924 RTL818X_RX_CONF_NICMAC
;
926 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
)
927 reg
|= RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
;
929 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE1
)
930 ? RTL818X_RX_CONF_CSDM1
: 0;
931 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE2
)
932 ? RTL818X_RX_CONF_CSDM2
: 0;
936 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, reg
);
938 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
939 reg
= rtl818x_ioread8(priv
, &priv
->map
->CW_CONF
);
941 /* CW is not on per-packet basis.
942 * in rtl8185 the CW_VALUE reg is used.
944 reg
&= ~RTL818X_CW_CONF_PERPACKET_CW
;
945 /* retry limit IS on per-packet basis.
946 * the short and long retry limit in TX_CONF
949 reg
|= RTL818X_CW_CONF_PERPACKET_RETRY
;
950 rtl818x_iowrite8(priv
, &priv
->map
->CW_CONF
, reg
);
952 reg
= rtl818x_ioread8(priv
, &priv
->map
->TX_AGC_CTL
);
953 /* TX antenna and TX gain are not on per-packet basis.
954 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
955 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
957 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN
;
958 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL
;
959 reg
|= RTL818X_TX_AGC_CTL_FEEDBACK_ANT
;
960 rtl818x_iowrite8(priv
, &priv
->map
->TX_AGC_CTL
, reg
);
962 /* disable early TX */
963 rtl818x_iowrite8(priv
, (u8 __iomem
*)priv
->map
+ 0xec, 0x3f);
966 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
967 reg
|= (6 << 21 /* MAX TX DMA */) |
968 RTL818X_TX_CONF_NO_ICV
;
972 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
973 reg
&= ~RTL818X_TX_CONF_PROBE_DTS
;
975 reg
&= ~RTL818X_TX_CONF_HW_SEQNUM
;
977 reg
&= ~RTL818X_TX_CONF_DISCW
;
979 /* different meaning, same value on both rtl8185 and rtl8180 */
980 reg
&= ~RTL818X_TX_CONF_SAT_HWPLCP
;
982 rtl818x_iowrite32(priv
, &priv
->map
->TX_CONF
, reg
);
984 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
985 reg
|= RTL818X_CMD_RX_ENABLE
;
986 reg
|= RTL818X_CMD_TX_ENABLE
;
987 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
992 rtl8180_free_rx_ring(dev
);
993 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
994 if (priv
->tx_ring
[i
].desc
)
995 rtl8180_free_tx_ring(dev
, i
);
1000 static void rtl8180_stop(struct ieee80211_hw
*dev
)
1002 struct rtl8180_priv
*priv
= dev
->priv
;
1006 rtl8180_int_disable(dev
);
1008 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
1009 reg
&= ~RTL818X_CMD_TX_ENABLE
;
1010 reg
&= ~RTL818X_CMD_RX_ENABLE
;
1011 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
1013 priv
->rf
->stop(dev
);
1015 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1016 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG4
);
1017 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG4
, reg
| RTL818X_CONFIG4_VCOOFF
);
1018 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1020 free_irq(priv
->pdev
->irq
, dev
);
1022 rtl8180_free_rx_ring(dev
);
1023 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1024 rtl8180_free_tx_ring(dev
, i
);
1027 static u64
rtl8180_get_tsf(struct ieee80211_hw
*dev
,
1028 struct ieee80211_vif
*vif
)
1030 struct rtl8180_priv
*priv
= dev
->priv
;
1032 return rtl818x_ioread32(priv
, &priv
->map
->TSFT
[0]) |
1033 (u64
)(rtl818x_ioread32(priv
, &priv
->map
->TSFT
[1])) << 32;
1036 static void rtl8180_beacon_work(struct work_struct
*work
)
1038 struct rtl8180_vif
*vif_priv
=
1039 container_of(work
, struct rtl8180_vif
, beacon_work
.work
);
1040 struct ieee80211_vif
*vif
=
1041 container_of((void *)vif_priv
, struct ieee80211_vif
, drv_priv
);
1042 struct ieee80211_hw
*dev
= vif_priv
->dev
;
1043 struct ieee80211_mgmt
*mgmt
;
1044 struct sk_buff
*skb
;
1046 /* don't overflow the tx ring */
1047 if (ieee80211_queue_stopped(dev
, 0))
1050 /* grab a fresh beacon */
1051 skb
= ieee80211_beacon_get(dev
, vif
);
1056 * update beacon timestamp w/ TSF value
1057 * TODO: make hardware update beacon timestamp
1059 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1060 mgmt
->u
.beacon
.timestamp
= cpu_to_le64(rtl8180_get_tsf(dev
, vif
));
1062 /* TODO: use actual beacon queue */
1063 skb_set_queue_mapping(skb
, 0);
1065 rtl8180_tx(dev
, NULL
, skb
);
1069 * schedule next beacon
1070 * TODO: use hardware support for beacon timing
1072 schedule_delayed_work(&vif_priv
->beacon_work
,
1073 usecs_to_jiffies(1024 * vif
->bss_conf
.beacon_int
));
1076 static int rtl8180_add_interface(struct ieee80211_hw
*dev
,
1077 struct ieee80211_vif
*vif
)
1079 struct rtl8180_priv
*priv
= dev
->priv
;
1080 struct rtl8180_vif
*vif_priv
;
1083 * We only support one active interface at a time.
1088 switch (vif
->type
) {
1089 case NL80211_IFTYPE_STATION
:
1090 case NL80211_IFTYPE_ADHOC
:
1098 /* Initialize driver private area */
1099 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1100 vif_priv
->dev
= dev
;
1101 INIT_DELAYED_WORK(&vif_priv
->beacon_work
, rtl8180_beacon_work
);
1102 vif_priv
->enable_beacon
= false;
1104 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1105 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->MAC
[0],
1106 le32_to_cpu(*(__le32
*)vif
->addr
));
1107 rtl818x_iowrite16(priv
, (__le16 __iomem
*)&priv
->map
->MAC
[4],
1108 le16_to_cpu(*(__le16
*)(vif
->addr
+ 4)));
1109 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1114 static void rtl8180_remove_interface(struct ieee80211_hw
*dev
,
1115 struct ieee80211_vif
*vif
)
1117 struct rtl8180_priv
*priv
= dev
->priv
;
1121 static int rtl8180_config(struct ieee80211_hw
*dev
, u32 changed
)
1123 struct rtl8180_priv
*priv
= dev
->priv
;
1124 struct ieee80211_conf
*conf
= &dev
->conf
;
1126 priv
->rf
->set_chan(dev
, conf
);
1131 static int rtl8180_conf_tx(struct ieee80211_hw
*dev
,
1132 struct ieee80211_vif
*vif
, u16 queue
,
1133 const struct ieee80211_tx_queue_params
*params
)
1135 struct rtl8180_priv
*priv
= dev
->priv
;
1138 /* nothing to do ? */
1139 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1142 cw_min
= fls(params
->cw_min
);
1143 cw_max
= fls(params
->cw_max
);
1145 rtl818x_iowrite8(priv
, &priv
->map
->CW_VAL
, (cw_max
<< 4) | cw_min
);
1150 static void rtl8180_conf_erp(struct ieee80211_hw
*dev
,
1151 struct ieee80211_bss_conf
*info
)
1153 struct rtl8180_priv
*priv
= dev
->priv
;
1158 /* TODO: should we do something ? */
1159 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1162 /* I _hope_ this means 10uS for the HW.
1163 * In reference code it is 0x22 for
1164 * both rtl8187L and rtl8187SE
1168 if (info
->use_short_slot
)
1169 priv
->slot_time
= 9;
1171 priv
->slot_time
= 20;
1173 /* 10 is SIFS time in uS */
1174 difs
= 10 + 2 * priv
->slot_time
;
1175 eifs
= 10 + difs
+ priv
->ack_time
;
1177 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1178 hw_eifs
= DIV_ROUND_UP(eifs
, 4);
1181 rtl818x_iowrite8(priv
, &priv
->map
->SLOT
, priv
->slot_time
);
1182 rtl818x_iowrite8(priv
, &priv
->map
->SIFS
, sifs
);
1183 rtl818x_iowrite8(priv
, &priv
->map
->DIFS
, difs
);
1185 /* from reference code. set ack timeout reg = eifs reg */
1186 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, hw_eifs
);
1188 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1189 * the HW still wait for DIFS.
1190 * HW uses 4uS units for EIFS.
1192 hw_eifs
= DIV_ROUND_UP(eifs
- difs
, 4);
1194 rtl818x_iowrite8(priv
, &priv
->map
->EIFS
, hw_eifs
);
1197 static void rtl8180_bss_info_changed(struct ieee80211_hw
*dev
,
1198 struct ieee80211_vif
*vif
,
1199 struct ieee80211_bss_conf
*info
,
1202 struct rtl8180_priv
*priv
= dev
->priv
;
1203 struct rtl8180_vif
*vif_priv
;
1207 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1209 if (changed
& BSS_CHANGED_BSSID
) {
1210 for (i
= 0; i
< ETH_ALEN
; i
++)
1211 rtl818x_iowrite8(priv
, &priv
->map
->BSSID
[i
],
1214 if (is_valid_ether_addr(info
->bssid
)) {
1215 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
1216 reg
= RTL818X_MSR_ADHOC
;
1218 reg
= RTL818X_MSR_INFRA
;
1220 reg
= RTL818X_MSR_NO_LINK
;
1221 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, reg
);
1224 if (changed
& BSS_CHANGED_BASIC_RATES
)
1225 rtl8180_conf_basic_rates(dev
, info
->basic_rates
);
1227 if (changed
& (BSS_CHANGED_ERP_SLOT
| BSS_CHANGED_ERP_PREAMBLE
)) {
1229 /* when preamble changes, acktime duration changes, and erp must
1230 * be recalculated. ACK time is calculated at lowest rate.
1231 * Since mac80211 include SIFS time we remove it (-10)
1234 le16_to_cpu(ieee80211_generic_frame_duration(dev
,
1236 IEEE80211_BAND_2GHZ
, 10,
1237 &priv
->rates
[0])) - 10;
1239 rtl8180_conf_erp(dev
, info
);
1242 if (changed
& BSS_CHANGED_BEACON_ENABLED
)
1243 vif_priv
->enable_beacon
= info
->enable_beacon
;
1245 if (changed
& (BSS_CHANGED_BEACON_ENABLED
| BSS_CHANGED_BEACON
)) {
1246 cancel_delayed_work_sync(&vif_priv
->beacon_work
);
1247 if (vif_priv
->enable_beacon
)
1248 schedule_work(&vif_priv
->beacon_work
.work
);
1252 static u64
rtl8180_prepare_multicast(struct ieee80211_hw
*dev
,
1253 struct netdev_hw_addr_list
*mc_list
)
1255 return netdev_hw_addr_list_count(mc_list
);
1258 static void rtl8180_configure_filter(struct ieee80211_hw
*dev
,
1259 unsigned int changed_flags
,
1260 unsigned int *total_flags
,
1263 struct rtl8180_priv
*priv
= dev
->priv
;
1265 if (changed_flags
& FIF_FCSFAIL
)
1266 priv
->rx_conf
^= RTL818X_RX_CONF_FCS
;
1267 if (changed_flags
& FIF_CONTROL
)
1268 priv
->rx_conf
^= RTL818X_RX_CONF_CTRL
;
1269 if (changed_flags
& FIF_OTHER_BSS
)
1270 priv
->rx_conf
^= RTL818X_RX_CONF_MONITOR
;
1271 if (*total_flags
& FIF_ALLMULTI
|| multicast
> 0)
1272 priv
->rx_conf
|= RTL818X_RX_CONF_MULTICAST
;
1274 priv
->rx_conf
&= ~RTL818X_RX_CONF_MULTICAST
;
1278 if (priv
->rx_conf
& RTL818X_RX_CONF_FCS
)
1279 *total_flags
|= FIF_FCSFAIL
;
1280 if (priv
->rx_conf
& RTL818X_RX_CONF_CTRL
)
1281 *total_flags
|= FIF_CONTROL
;
1282 if (priv
->rx_conf
& RTL818X_RX_CONF_MONITOR
)
1283 *total_flags
|= FIF_OTHER_BSS
;
1284 if (priv
->rx_conf
& RTL818X_RX_CONF_MULTICAST
)
1285 *total_flags
|= FIF_ALLMULTI
;
1287 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, priv
->rx_conf
);
1290 static const struct ieee80211_ops rtl8180_ops
= {
1292 .start
= rtl8180_start
,
1293 .stop
= rtl8180_stop
,
1294 .add_interface
= rtl8180_add_interface
,
1295 .remove_interface
= rtl8180_remove_interface
,
1296 .config
= rtl8180_config
,
1297 .bss_info_changed
= rtl8180_bss_info_changed
,
1298 .conf_tx
= rtl8180_conf_tx
,
1299 .prepare_multicast
= rtl8180_prepare_multicast
,
1300 .configure_filter
= rtl8180_configure_filter
,
1301 .get_tsf
= rtl8180_get_tsf
,
1304 static void rtl8180_eeprom_register_read(struct eeprom_93cx6
*eeprom
)
1306 struct rtl8180_priv
*priv
= eeprom
->data
;
1307 u8 reg
= rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1309 eeprom
->reg_data_in
= reg
& RTL818X_EEPROM_CMD_WRITE
;
1310 eeprom
->reg_data_out
= reg
& RTL818X_EEPROM_CMD_READ
;
1311 eeprom
->reg_data_clock
= reg
& RTL818X_EEPROM_CMD_CK
;
1312 eeprom
->reg_chip_select
= reg
& RTL818X_EEPROM_CMD_CS
;
1315 static void rtl8180_eeprom_register_write(struct eeprom_93cx6
*eeprom
)
1317 struct rtl8180_priv
*priv
= eeprom
->data
;
1320 if (eeprom
->reg_data_in
)
1321 reg
|= RTL818X_EEPROM_CMD_WRITE
;
1322 if (eeprom
->reg_data_out
)
1323 reg
|= RTL818X_EEPROM_CMD_READ
;
1324 if (eeprom
->reg_data_clock
)
1325 reg
|= RTL818X_EEPROM_CMD_CK
;
1326 if (eeprom
->reg_chip_select
)
1327 reg
|= RTL818X_EEPROM_CMD_CS
;
1329 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, reg
);
1330 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1334 static void rtl8180_eeprom_read(struct rtl8180_priv
*priv
)
1336 struct eeprom_93cx6 eeprom
;
1337 int eeprom_cck_table_adr
;
1342 eeprom
.register_read
= rtl8180_eeprom_register_read
;
1343 eeprom
.register_write
= rtl8180_eeprom_register_write
;
1344 if (rtl818x_ioread32(priv
, &priv
->map
->RX_CONF
) & (1 << 6))
1345 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
1347 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
1349 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1350 RTL818X_EEPROM_CMD_PROGRAM
);
1351 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1354 eeprom_93cx6_read(&eeprom
, 0x06, &eeprom_val
);
1356 priv
->rf_type
= eeprom_val
;
1358 eeprom_93cx6_read(&eeprom
, 0x17, &eeprom_val
);
1359 priv
->csthreshold
= eeprom_val
>> 8;
1361 eeprom_93cx6_multiread(&eeprom
, 0x7, (__le16
*)priv
->mac_addr
, 3);
1363 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1364 eeprom_cck_table_adr
= 0x30;
1366 eeprom_cck_table_adr
= 0x10;
1369 for (i
= 0; i
< 14; i
+= 2) {
1371 eeprom_93cx6_read(&eeprom
, eeprom_cck_table_adr
+ (i
>> 1),
1373 priv
->channels
[i
].hw_value
= txpwr
& 0xFF;
1374 priv
->channels
[i
+ 1].hw_value
= txpwr
>> 8;
1378 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1379 for (i
= 0; i
< 14; i
+= 2) {
1381 eeprom_93cx6_read(&eeprom
, 0x20 + (i
>> 1), &txpwr
);
1382 priv
->channels
[i
].hw_value
|= (txpwr
& 0xFF) << 8;
1383 priv
->channels
[i
+ 1].hw_value
|= txpwr
& 0xFF00;
1387 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
1389 eeprom_93cx6_multiread(&eeprom
, 0xD, (__le16
*)&anaparam
, 2);
1390 priv
->anaparam
= le32_to_cpu(anaparam
);
1391 eeprom_93cx6_read(&eeprom
, 0x19, &priv
->rfparam
);
1394 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1395 eeprom_93cx6_read(&eeprom
, 0x3F, &eeprom_val
);
1396 priv
->antenna_diversity_en
= !!(eeprom_val
& 0x100);
1397 priv
->antenna_diversity_default
= (eeprom_val
& 0xC00) == 0x400;
1399 eeprom_93cx6_read(&eeprom
, 0x7C, &eeprom_val
);
1400 priv
->xtal_out
= eeprom_val
& 0xF;
1401 priv
->xtal_in
= (eeprom_val
& 0xF0) >> 4;
1402 priv
->xtal_cal
= !!(eeprom_val
& 0x1000);
1403 priv
->thermal_meter_val
= (eeprom_val
& 0xF00) >> 8;
1404 priv
->thermal_meter_en
= !!(eeprom_val
& 0x2000);
1407 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1408 RTL818X_EEPROM_CMD_NORMAL
);
1411 static int rtl8180_probe(struct pci_dev
*pdev
,
1412 const struct pci_device_id
*id
)
1414 struct ieee80211_hw
*dev
;
1415 struct rtl8180_priv
*priv
;
1416 unsigned long mem_addr
, mem_len
;
1417 unsigned int io_addr
, io_len
;
1419 const char *chip_name
, *rf_name
= NULL
;
1422 err
= pci_enable_device(pdev
);
1424 printk(KERN_ERR
"%s (rtl8180): Cannot enable new PCI device\n",
1429 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
1431 printk(KERN_ERR
"%s (rtl8180): Cannot obtain PCI resources\n",
1436 io_addr
= pci_resource_start(pdev
, 0);
1437 io_len
= pci_resource_len(pdev
, 0);
1438 mem_addr
= pci_resource_start(pdev
, 1);
1439 mem_len
= pci_resource_len(pdev
, 1);
1441 if (mem_len
< sizeof(struct rtl818x_csr
) ||
1442 io_len
< sizeof(struct rtl818x_csr
)) {
1443 printk(KERN_ERR
"%s (rtl8180): Too short PCI resources\n",
1449 if ((err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) ||
1450 (err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))) {
1451 printk(KERN_ERR
"%s (rtl8180): No suitable DMA available\n",
1456 pci_set_master(pdev
);
1458 dev
= ieee80211_alloc_hw(sizeof(*priv
), &rtl8180_ops
);
1460 printk(KERN_ERR
"%s (rtl8180): ieee80211 alloc failed\n",
1470 SET_IEEE80211_DEV(dev
, &pdev
->dev
);
1471 pci_set_drvdata(pdev
, dev
);
1473 priv
->map
= pci_iomap(pdev
, 1, mem_len
);
1475 priv
->map
= pci_iomap(pdev
, 0, io_len
);
1478 printk(KERN_ERR
"%s (rtl8180): Cannot map device memory\n",
1483 BUILD_BUG_ON(sizeof(priv
->channels
) != sizeof(rtl818x_channels
));
1484 BUILD_BUG_ON(sizeof(priv
->rates
) != sizeof(rtl818x_rates
));
1486 memcpy(priv
->channels
, rtl818x_channels
, sizeof(rtl818x_channels
));
1487 memcpy(priv
->rates
, rtl818x_rates
, sizeof(rtl818x_rates
));
1489 priv
->band
.band
= IEEE80211_BAND_2GHZ
;
1490 priv
->band
.channels
= priv
->channels
;
1491 priv
->band
.n_channels
= ARRAY_SIZE(rtl818x_channels
);
1492 priv
->band
.bitrates
= priv
->rates
;
1493 priv
->band
.n_bitrates
= 4;
1494 dev
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &priv
->band
;
1496 dev
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1497 IEEE80211_HW_RX_INCLUDES_FCS
|
1498 IEEE80211_HW_SIGNAL_UNSPEC
;
1499 dev
->vif_data_size
= sizeof(struct rtl8180_vif
);
1500 dev
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
) |
1501 BIT(NL80211_IFTYPE_ADHOC
);
1502 dev
->max_signal
= 65;
1504 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
1505 reg
&= RTL818X_TX_CONF_HWVER_MASK
;
1507 case RTL818X_TX_CONF_R8180_ABCD
:
1508 chip_name
= "RTL8180";
1509 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1512 case RTL818X_TX_CONF_R8180_F
:
1513 chip_name
= "RTL8180vF";
1514 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1517 case RTL818X_TX_CONF_R8185_ABC
:
1518 chip_name
= "RTL8185";
1519 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1522 case RTL818X_TX_CONF_R8185_D
:
1523 chip_name
= "RTL8185vD";
1524 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1527 printk(KERN_ERR
"%s (rtl8180): Unknown chip! (0x%x)\n",
1528 pci_name(pdev
), reg
>> 25);
1532 /* we declare to MAC80211 all the queues except for beacon queue
1533 * that will be eventually handled by DRV.
1534 * TX rings are arranged in such a way that lower is the IDX,
1535 * higher is the priority, in order to achieve direct mapping
1536 * with mac80211, however the beacon queue is an exception and it
1537 * is mapped on the highst tx ring IDX.
1539 dev
->queues
= RTL8180_NR_TX_QUEUES
- 1;
1541 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1542 priv
->band
.n_bitrates
= ARRAY_SIZE(rtl818x_rates
);
1543 pci_try_set_mwi(pdev
);
1546 rtl8180_eeprom_read(priv
);
1548 switch (priv
->rf_type
) {
1549 case 1: rf_name
= "Intersil";
1551 case 2: rf_name
= "RFMD";
1553 case 3: priv
->rf
= &sa2400_rf_ops
;
1555 case 4: priv
->rf
= &max2820_rf_ops
;
1557 case 5: priv
->rf
= &grf5101_rf_ops
;
1559 case 9: priv
->rf
= rtl8180_detect_rf(dev
);
1562 rf_name
= "RTL8255";
1565 printk(KERN_ERR
"%s (rtl8180): Unknown RF! (0x%x)\n",
1566 pci_name(pdev
), priv
->rf_type
);
1571 printk(KERN_ERR
"%s (rtl8180): %s RF frontend not supported!\n",
1572 pci_name(pdev
), rf_name
);
1576 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1577 printk(KERN_WARNING
"%s (rtl8180): Invalid hwaddr! Using"
1578 " randomly generated MAC addr\n", pci_name(pdev
));
1579 eth_random_addr(priv
->mac_addr
);
1581 SET_IEEE80211_PERM_ADDR(dev
, priv
->mac_addr
);
1583 spin_lock_init(&priv
->lock
);
1585 err
= ieee80211_register_hw(dev
);
1587 printk(KERN_ERR
"%s (rtl8180): Cannot register device\n",
1592 wiphy_info(dev
->wiphy
, "hwaddr %pm, %s + %s\n",
1593 priv
->mac_addr
, chip_name
, priv
->rf
->name
);
1598 pci_iounmap(pdev
, priv
->map
);
1601 ieee80211_free_hw(dev
);
1604 pci_release_regions(pdev
);
1605 pci_disable_device(pdev
);
1609 static void rtl8180_remove(struct pci_dev
*pdev
)
1611 struct ieee80211_hw
*dev
= pci_get_drvdata(pdev
);
1612 struct rtl8180_priv
*priv
;
1617 ieee80211_unregister_hw(dev
);
1621 pci_iounmap(pdev
, priv
->map
);
1622 pci_release_regions(pdev
);
1623 pci_disable_device(pdev
);
1624 ieee80211_free_hw(dev
);
1628 static int rtl8180_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1630 pci_save_state(pdev
);
1631 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1635 static int rtl8180_resume(struct pci_dev
*pdev
)
1637 pci_set_power_state(pdev
, PCI_D0
);
1638 pci_restore_state(pdev
);
1642 #endif /* CONFIG_PM */
1644 static struct pci_driver rtl8180_driver
= {
1645 .name
= KBUILD_MODNAME
,
1646 .id_table
= rtl8180_table
,
1647 .probe
= rtl8180_probe
,
1648 .remove
= rtl8180_remove
,
1650 .suspend
= rtl8180_suspend
,
1651 .resume
= rtl8180_resume
,
1652 #endif /* CONFIG_PM */
1655 module_pci_driver(rtl8180_driver
);