1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
41 u32
rtl92ce_phy_query_rf_reg(struct ieee80211_hw
*hw
,
42 enum radio_path rfpath
, u32 regaddr
, u32 bitmask
)
44 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
45 u32 original_value
, readback_value
, bitshift
;
46 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
49 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
, ("regaddr(%#x), "
50 "rfpath(%#x), bitmask(%#x)\n",
51 regaddr
, rfpath
, bitmask
));
53 spin_lock_irqsave(&rtlpriv
->locks
.rf_lock
, flags
);
55 if (rtlphy
->rf_mode
!= RF_OP_BY_FW
) {
56 original_value
= _rtl92c_phy_rf_serial_read(hw
,
59 original_value
= _rtl92c_phy_fw_rf_serial_read(hw
,
63 bitshift
= _rtl92c_phy_calculate_bit_shift(bitmask
);
64 readback_value
= (original_value
& bitmask
) >> bitshift
;
66 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_lock
, flags
);
68 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
69 ("regaddr(%#x), rfpath(%#x), "
70 "bitmask(%#x), original_value(%#x)\n",
71 regaddr
, rfpath
, bitmask
, original_value
));
73 return readback_value
;
76 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw
*hw
,
77 enum radio_path rfpath
,
78 u32 regaddr
, u32 bitmask
, u32 data
)
80 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
81 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
82 u32 original_value
, bitshift
;
85 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
86 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
87 regaddr
, bitmask
, data
, rfpath
));
89 spin_lock_irqsave(&rtlpriv
->locks
.rf_lock
, flags
);
91 if (rtlphy
->rf_mode
!= RF_OP_BY_FW
) {
92 if (bitmask
!= RFREG_OFFSET_MASK
) {
93 original_value
= _rtl92c_phy_rf_serial_read(hw
,
96 bitshift
= _rtl92c_phy_calculate_bit_shift(bitmask
);
98 ((original_value
& (~bitmask
)) |
102 _rtl92c_phy_rf_serial_write(hw
, rfpath
, regaddr
, data
);
104 if (bitmask
!= RFREG_OFFSET_MASK
) {
105 original_value
= _rtl92c_phy_fw_rf_serial_read(hw
,
108 bitshift
= _rtl92c_phy_calculate_bit_shift(bitmask
);
110 ((original_value
& (~bitmask
)) |
113 _rtl92c_phy_fw_rf_serial_write(hw
, rfpath
, regaddr
, data
);
116 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_lock
, flags
);
118 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
, ("regaddr(%#x), "
119 "bitmask(%#x), data(%#x), "
120 "rfpath(%#x)\n", regaddr
,
121 bitmask
, data
, rfpath
));
124 bool rtl92ce_phy_mac_config(struct ieee80211_hw
*hw
)
126 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
127 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
128 bool is92c
= IS_92C_SERIAL(rtlhal
->version
);
129 bool rtstatus
= _rtl92ce_phy_config_mac_with_headerfile(hw
);
132 rtl_write_byte(rtlpriv
, 0x14, 0x71);
136 bool rtl92ce_phy_bb_config(struct ieee80211_hw
*hw
)
138 bool rtstatus
= true;
139 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
142 u8 reg_hwparafile
= 1;
144 _rtl92c_phy_init_bb_rf_register_definition(hw
);
145 regval
= rtl_read_word(rtlpriv
, REG_SYS_FUNC_EN
);
146 rtl_write_word(rtlpriv
, REG_SYS_FUNC_EN
,
147 regval
| BIT(13) | BIT(0) | BIT(1));
148 rtl_write_byte(rtlpriv
, REG_AFE_PLL_CTRL
, 0x83);
149 rtl_write_byte(rtlpriv
, REG_AFE_PLL_CTRL
+ 1, 0xdb);
150 rtl_write_byte(rtlpriv
, REG_RF_CTRL
, RF_EN
| RF_RSTB
| RF_SDMRSTB
);
151 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
,
152 FEN_PPLL
| FEN_PCIEA
| FEN_DIO_PCIE
|
153 FEN_BB_GLB_RSTn
| FEN_BBRSTB
);
154 rtl_write_byte(rtlpriv
, REG_AFE_XTAL_CTRL
+ 1, 0x80);
155 regvaldw
= rtl_read_dword(rtlpriv
, REG_LEDCFG0
);
156 rtl_write_dword(rtlpriv
, REG_LEDCFG0
, regvaldw
| BIT(23));
157 if (reg_hwparafile
== 1)
158 rtstatus
= _rtl92c_phy_bb8192c_config_parafile(hw
);
162 bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw
*hw
)
164 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
169 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, ("Read Rtl819XMACPHY_Array\n"));
170 arraylength
= MAC_2T_ARRAYLENGTH
;
171 ptrarray
= RTL8192CEMAC_2T_ARRAY
;
172 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
173 ("Img:RTL8192CEMAC_2T_ARRAY\n"));
174 for (i
= 0; i
< arraylength
; i
= i
+ 2)
175 rtl_write_byte(rtlpriv
, ptrarray
[i
], (u8
) ptrarray
[i
+ 1]);
179 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw
*hw
,
183 u32
*phy_regarray_table
;
184 u32
*agctab_array_table
;
185 u16 phy_reg_arraylen
, agctab_arraylen
;
186 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
187 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
189 if (IS_92C_SERIAL(rtlhal
->version
)) {
190 agctab_arraylen
= AGCTAB_2TARRAYLENGTH
;
191 agctab_array_table
= RTL8192CEAGCTAB_2TARRAY
;
192 phy_reg_arraylen
= PHY_REG_2TARRAY_LENGTH
;
193 phy_regarray_table
= RTL8192CEPHY_REG_2TARRAY
;
195 agctab_arraylen
= AGCTAB_1TARRAYLENGTH
;
196 agctab_array_table
= RTL8192CEAGCTAB_1TARRAY
;
197 phy_reg_arraylen
= PHY_REG_1TARRAY_LENGTH
;
198 phy_regarray_table
= RTL8192CEPHY_REG_1TARRAY
;
200 if (configtype
== BASEBAND_CONFIG_PHY_REG
) {
201 for (i
= 0; i
< phy_reg_arraylen
; i
= i
+ 2) {
202 if (phy_regarray_table
[i
] == 0xfe)
204 else if (phy_regarray_table
[i
] == 0xfd)
206 else if (phy_regarray_table
[i
] == 0xfc)
208 else if (phy_regarray_table
[i
] == 0xfb)
210 else if (phy_regarray_table
[i
] == 0xfa)
212 else if (phy_regarray_table
[i
] == 0xf9)
214 rtl_set_bbreg(hw
, phy_regarray_table
[i
], MASKDWORD
,
215 phy_regarray_table
[i
+ 1]);
217 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
218 ("The phy_regarray_table[0] is %x"
219 " Rtl819XPHY_REGArray[1] is %x\n",
220 phy_regarray_table
[i
],
221 phy_regarray_table
[i
+ 1]));
223 } else if (configtype
== BASEBAND_CONFIG_AGC_TAB
) {
224 for (i
= 0; i
< agctab_arraylen
; i
= i
+ 2) {
225 rtl_set_bbreg(hw
, agctab_array_table
[i
], MASKDWORD
,
226 agctab_array_table
[i
+ 1]);
228 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
229 ("The agctab_array_table[0] is "
230 "%x Rtl819XPHY_REGArray[1] is %x\n",
231 agctab_array_table
[i
],
232 agctab_array_table
[i
+ 1]));
238 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw
*hw
,
241 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
243 u32
*phy_regarray_table_pg
;
244 u16 phy_regarray_pg_len
;
246 phy_regarray_pg_len
= PHY_REG_ARRAY_PGLENGTH
;
247 phy_regarray_table_pg
= RTL8192CEPHY_REG_ARRAY_PG
;
249 if (configtype
== BASEBAND_CONFIG_PHY_REG
) {
250 for (i
= 0; i
< phy_regarray_pg_len
; i
= i
+ 3) {
251 if (phy_regarray_table_pg
[i
] == 0xfe)
253 else if (phy_regarray_table_pg
[i
] == 0xfd)
255 else if (phy_regarray_table_pg
[i
] == 0xfc)
257 else if (phy_regarray_table_pg
[i
] == 0xfb)
259 else if (phy_regarray_table_pg
[i
] == 0xfa)
261 else if (phy_regarray_table_pg
[i
] == 0xf9)
264 _rtl92c_store_pwrIndex_diffrate_offset(hw
,
265 phy_regarray_table_pg
[i
],
266 phy_regarray_table_pg
[i
+ 1],
267 phy_regarray_table_pg
[i
+ 2]);
271 RT_TRACE(rtlpriv
, COMP_SEND
, DBG_TRACE
,
272 ("configtype != BaseBand_Config_PHY_REG\n"));
277 bool rtl92ce_phy_config_rf_with_headerfile(struct ieee80211_hw
*hw
,
278 enum radio_path rfpath
)
282 bool rtstatus
= true;
283 u32
*radioa_array_table
;
284 u32
*radiob_array_table
;
285 u16 radioa_arraylen
, radiob_arraylen
;
286 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
287 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
289 if (IS_92C_SERIAL(rtlhal
->version
)) {
290 radioa_arraylen
= RADIOA_2TARRAYLENGTH
;
291 radioa_array_table
= RTL8192CERADIOA_2TARRAY
;
292 radiob_arraylen
= RADIOB_2TARRAYLENGTH
;
293 radiob_array_table
= RTL8192CE_RADIOB_2TARRAY
;
294 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
295 ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
296 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
297 ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
299 radioa_arraylen
= RADIOA_1TARRAYLENGTH
;
300 radioa_array_table
= RTL8192CE_RADIOA_1TARRAY
;
301 radiob_arraylen
= RADIOB_1TARRAYLENGTH
;
302 radiob_array_table
= RTL8192CE_RADIOB_1TARRAY
;
303 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
304 ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
305 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
306 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
308 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, ("Radio No %x\n", rfpath
));
312 for (i
= 0; i
< radioa_arraylen
; i
= i
+ 2) {
313 if (radioa_array_table
[i
] == 0xfe)
315 else if (radioa_array_table
[i
] == 0xfd)
317 else if (radioa_array_table
[i
] == 0xfc)
319 else if (radioa_array_table
[i
] == 0xfb)
321 else if (radioa_array_table
[i
] == 0xfa)
323 else if (radioa_array_table
[i
] == 0xf9)
326 rtl_set_rfreg(hw
, rfpath
, radioa_array_table
[i
],
328 radioa_array_table
[i
+ 1]);
334 for (i
= 0; i
< radiob_arraylen
; i
= i
+ 2) {
335 if (radiob_array_table
[i
] == 0xfe) {
337 } else if (radiob_array_table
[i
] == 0xfd)
339 else if (radiob_array_table
[i
] == 0xfc)
341 else if (radiob_array_table
[i
] == 0xfb)
343 else if (radiob_array_table
[i
] == 0xfa)
345 else if (radiob_array_table
[i
] == 0xf9)
348 rtl_set_rfreg(hw
, rfpath
, radiob_array_table
[i
],
350 radiob_array_table
[i
+ 1]);
356 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
357 ("switch case not process\n"));
360 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
361 ("switch case not process\n"));
367 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw
*hw
)
369 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
370 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
371 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
372 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
376 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
,
377 ("Switch to %s bandwidth\n",
378 rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20
?
381 if (is_hal_stop(rtlhal
))
384 reg_bw_opmode
= rtl_read_byte(rtlpriv
, REG_BWOPMODE
);
385 reg_prsr_rsc
= rtl_read_byte(rtlpriv
, REG_RRSR
+ 2);
387 switch (rtlphy
->current_chan_bw
) {
388 case HT_CHANNEL_WIDTH_20
:
389 reg_bw_opmode
|= BW_OPMODE_20MHZ
;
390 rtl_write_byte(rtlpriv
, REG_BWOPMODE
, reg_bw_opmode
);
393 case HT_CHANNEL_WIDTH_20_40
:
394 reg_bw_opmode
&= ~BW_OPMODE_20MHZ
;
395 rtl_write_byte(rtlpriv
, REG_BWOPMODE
, reg_bw_opmode
);
398 (reg_prsr_rsc
& 0x90) | (mac
->cur_40_prime_sc
<< 5);
399 rtl_write_byte(rtlpriv
, REG_RRSR
+ 2, reg_prsr_rsc
);
403 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
404 ("unknown bandwidth: %#X\n", rtlphy
->current_chan_bw
));
408 switch (rtlphy
->current_chan_bw
) {
409 case HT_CHANNEL_WIDTH_20
:
410 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BRFMOD
, 0x0);
411 rtl_set_bbreg(hw
, RFPGA1_RFMOD
, BRFMOD
, 0x0);
412 rtl_set_bbreg(hw
, RFPGA0_ANALOGPARAMETER2
, BIT(10), 1);
414 case HT_CHANNEL_WIDTH_20_40
:
415 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BRFMOD
, 0x1);
416 rtl_set_bbreg(hw
, RFPGA1_RFMOD
, BRFMOD
, 0x1);
417 rtl_set_bbreg(hw
, RCCK0_SYSTEM
, BCCK_SIDEBAND
,
418 (mac
->cur_40_prime_sc
>> 1));
419 rtl_set_bbreg(hw
, ROFDM1_LSTF
, 0xC00, mac
->cur_40_prime_sc
);
420 rtl_set_bbreg(hw
, RFPGA0_ANALOGPARAMETER2
, BIT(10), 0);
421 rtl_set_bbreg(hw
, 0x818, (BIT(26) | BIT(27)),
422 (mac
->cur_40_prime_sc
==
423 HAL_PRIME_CHNL_OFFSET_LOWER
) ? 2 : 1);
426 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
427 ("unknown bandwidth: %#X\n", rtlphy
->current_chan_bw
));
430 rtl92c_phy_rf6052_set_bandwidth(hw
, rtlphy
->current_chan_bw
);
431 rtlphy
->set_bwmode_inprogress
= false;
432 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
, ("<==\n"));
435 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw
*hw
, bool is2t
)
438 u32 rf_a_mode
= 0, rf_b_mode
= 0, lc_cal
;
439 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
441 tmpreg
= rtl_read_byte(rtlpriv
, 0xd03);
443 if ((tmpreg
& 0x70) != 0)
444 rtl_write_byte(rtlpriv
, 0xd03, tmpreg
& 0x8F);
446 rtl_write_byte(rtlpriv
, REG_TXPAUSE
, 0xFF);
448 if ((tmpreg
& 0x70) != 0) {
449 rf_a_mode
= rtl_get_rfreg(hw
, RF90_PATH_A
, 0x00, MASK12BITS
);
452 rf_b_mode
= rtl_get_rfreg(hw
, RF90_PATH_B
, 0x00,
455 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x00, MASK12BITS
,
456 (rf_a_mode
& 0x8FFFF) | 0x10000);
459 rtl_set_rfreg(hw
, RF90_PATH_B
, 0x00, MASK12BITS
,
460 (rf_b_mode
& 0x8FFFF) | 0x10000);
462 lc_cal
= rtl_get_rfreg(hw
, RF90_PATH_A
, 0x18, MASK12BITS
);
464 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x18, MASK12BITS
, lc_cal
| 0x08000);
468 if ((tmpreg
& 0x70) != 0) {
469 rtl_write_byte(rtlpriv
, 0xd03, tmpreg
);
470 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x00, MASK12BITS
, rf_a_mode
);
473 rtl_set_rfreg(hw
, RF90_PATH_B
, 0x00, MASK12BITS
,
476 rtl_write_byte(rtlpriv
, REG_TXPAUSE
, 0x00);
480 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw
*hw
,
481 enum rf_pwrstate rfpwr_state
)
483 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
484 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
485 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
486 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
489 struct rtl8192_tx_ring
*ring
= NULL
;
491 ppsc
->set_rfpowerstate_inprogress
= true;
492 switch (rfpwr_state
) {
494 if ((ppsc
->rfpwr_state
== ERFOFF
) &&
495 RT_IN_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
)) {
497 u32 InitializeCount
= 0;
500 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
501 ("IPS Set eRf nic enable\n"));
502 rtstatus
= rtl_ps_enable_nic(hw
);
503 } while ((rtstatus
!= true)
504 && (InitializeCount
< 10));
505 RT_CLEAR_PS_LEVEL(ppsc
,
506 RT_RF_OFF_LEVL_HALT_NIC
);
508 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
509 ("Set ERFON sleeped:%d ms\n",
510 jiffies_to_msecs(jiffies
-
512 last_sleep_jiffies
)));
513 ppsc
->last_awake_jiffies
= jiffies
;
514 rtl92ce_phy_set_rf_on(hw
);
516 if (mac
->link_state
== MAC80211_LINKED
) {
517 rtlpriv
->cfg
->ops
->led_control(hw
,
520 rtlpriv
->cfg
->ops
->led_control(hw
,
526 for (queue_id
= 0, i
= 0;
527 queue_id
< RTL_PCI_MAX_TX_QUEUE_COUNT
;) {
528 ring
= &pcipriv
->dev
.tx_ring
[queue_id
];
529 if (skb_queue_len(&ring
->queue
) == 0 ||
530 queue_id
== BEACON_QUEUE
) {
534 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
535 ("eRf Off/Sleep: %d times "
537 "=%d before doze!\n", (i
+ 1),
539 skb_queue_len(&ring
->queue
)));
543 if (i
>= MAX_DOZE_WAITING_TIMES_9x
) {
544 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
545 ("\nERFOFF: %d times "
546 "TcbBusyQueue[%d] = %d !\n",
547 MAX_DOZE_WAITING_TIMES_9x
,
549 skb_queue_len(&ring
->queue
)));
553 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
) {
554 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
555 ("IPS Set eRf nic disable\n"));
556 rtl_ps_disable_nic(hw
);
557 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
559 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
) {
560 rtlpriv
->cfg
->ops
->led_control(hw
,
563 rtlpriv
->cfg
->ops
->led_control(hw
,
570 if (ppsc
->rfpwr_state
== ERFOFF
)
572 for (queue_id
= 0, i
= 0;
573 queue_id
< RTL_PCI_MAX_TX_QUEUE_COUNT
;) {
574 ring
= &pcipriv
->dev
.tx_ring
[queue_id
];
575 if (skb_queue_len(&ring
->queue
) == 0) {
579 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
580 ("eRf Off/Sleep: %d times "
581 "TcbBusyQueue[%d] =%d before "
582 "doze!\n", (i
+ 1), queue_id
,
583 skb_queue_len(&ring
->queue
)));
587 if (i
>= MAX_DOZE_WAITING_TIMES_9x
) {
588 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
589 ("\n ERFSLEEP: %d times "
590 "TcbBusyQueue[%d] = %d !\n",
591 MAX_DOZE_WAITING_TIMES_9x
,
593 skb_queue_len(&ring
->queue
)));
597 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
598 ("Set ERFSLEEP awaked:%d ms\n",
599 jiffies_to_msecs(jiffies
-
600 ppsc
->last_awake_jiffies
)));
601 ppsc
->last_sleep_jiffies
= jiffies
;
602 _rtl92c_phy_set_rf_sleep(hw
);
606 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
607 ("switch case not process\n"));
612 ppsc
->rfpwr_state
= rfpwr_state
;
613 ppsc
->set_rfpowerstate_inprogress
= false;
617 bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw
*hw
,
618 enum rf_pwrstate rfpwr_state
)
620 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
621 bool bresult
= false;
623 if (rfpwr_state
== ppsc
->rfpwr_state
)
625 bresult
= _rtl92ce_phy_set_rf_power_state(hw
, rfpwr_state
);