1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
37 static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw
*hw
);
39 void rtl92c_phy_rf6052_set_bandwidth(struct ieee80211_hw
*hw
, u8 bandwidth
)
41 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
42 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
45 case HT_CHANNEL_WIDTH_20
:
46 rtlphy
->rfreg_chnlval
[0] = ((rtlphy
->rfreg_chnlval
[0] &
47 0xfffff3ff) | 0x0400);
48 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_CHNLBW
, RFREG_OFFSET_MASK
,
49 rtlphy
->rfreg_chnlval
[0]);
51 case HT_CHANNEL_WIDTH_20_40
:
52 rtlphy
->rfreg_chnlval
[0] = ((rtlphy
->rfreg_chnlval
[0] &
54 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_CHNLBW
, RFREG_OFFSET_MASK
,
55 rtlphy
->rfreg_chnlval
[0]);
58 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
59 ("unknown bandwidth: %#X\n", bandwidth
));
64 void rtl92c_phy_rf6052_set_cck_txpower(struct ieee80211_hw
*hw
,
67 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
68 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
69 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
70 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
71 u32 tx_agc
[2] = {0, 0}, tmpval
;
72 bool turbo_scanoff
= false;
76 if (rtlefuse
->eeprom_regulatory
!= 0)
79 if (mac
->act_scanning
== true) {
80 tx_agc
[RF90_PATH_A
] = 0x3f3f3f3f;
81 tx_agc
[RF90_PATH_B
] = 0x3f3f3f3f;
84 for (idx1
= RF90_PATH_A
; idx1
<= RF90_PATH_B
; idx1
++) {
85 tx_agc
[idx1
] = ppowerlevel
[idx1
] |
86 (ppowerlevel
[idx1
] << 8) |
87 (ppowerlevel
[idx1
] << 16) |
88 (ppowerlevel
[idx1
] << 24);
92 for (idx1
= RF90_PATH_A
; idx1
<= RF90_PATH_B
; idx1
++) {
93 tx_agc
[idx1
] = ppowerlevel
[idx1
] |
94 (ppowerlevel
[idx1
] << 8) |
95 (ppowerlevel
[idx1
] << 16) |
96 (ppowerlevel
[idx1
] << 24);
99 if (rtlefuse
->eeprom_regulatory
== 0) {
101 (rtlphy
->mcs_txpwrlevel_origoffset
[0][6]) +
102 (rtlphy
->mcs_txpwrlevel_origoffset
[0][7] <<
104 tx_agc
[RF90_PATH_A
] += tmpval
;
106 tmpval
= (rtlphy
->mcs_txpwrlevel_origoffset
[0][14]) +
107 (rtlphy
->mcs_txpwrlevel_origoffset
[0][15] <<
109 tx_agc
[RF90_PATH_B
] += tmpval
;
113 for (idx1
= RF90_PATH_A
; idx1
<= RF90_PATH_B
; idx1
++) {
114 ptr
= (u8
*) (&(tx_agc
[idx1
]));
115 for (idx2
= 0; idx2
< 4; idx2
++) {
116 if (*ptr
> RF6052_MAX_TX_PWR
)
117 *ptr
= RF6052_MAX_TX_PWR
;
122 tmpval
= tx_agc
[RF90_PATH_A
] & 0xff;
123 rtl_set_bbreg(hw
, RTXAGC_A_CCK1_MCS32
, MASKBYTE1
, tmpval
);
125 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
126 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval
,
127 RTXAGC_A_CCK1_MCS32
));
129 tmpval
= tx_agc
[RF90_PATH_A
] >> 8;
131 if (mac
->mode
== WIRELESS_MODE_B
)
132 tmpval
= tmpval
& 0xff00ffff;
134 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_A_CCK2_11
, 0xffffff00, tmpval
);
136 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
137 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval
,
138 RTXAGC_B_CCK11_A_CCK2_11
));
140 tmpval
= tx_agc
[RF90_PATH_B
] >> 24;
141 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_A_CCK2_11
, MASKBYTE0
, tmpval
);
143 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
144 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval
,
145 RTXAGC_B_CCK11_A_CCK2_11
));
147 tmpval
= tx_agc
[RF90_PATH_B
] & 0x00ffffff;
148 rtl_set_bbreg(hw
, RTXAGC_B_CCK1_55_MCS32
, 0xffffff00, tmpval
);
150 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
151 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval
,
152 RTXAGC_B_CCK1_55_MCS32
));
155 static void rtl92c_phy_get_power_base(struct ieee80211_hw
*hw
,
156 u8
*ppowerlevel
, u8 channel
,
157 u32
*ofdmbase
, u32
*mcsbase
)
159 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
160 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
161 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
162 u32 powerBase0
, powerBase1
;
163 u8 legacy_pwrdiff
, ht20_pwrdiff
;
166 for (i
= 0; i
< 2; i
++) {
167 powerlevel
[i
] = ppowerlevel
[i
];
168 legacy_pwrdiff
= rtlefuse
->txpwr_legacyhtdiff
[i
][channel
- 1];
169 powerBase0
= powerlevel
[i
] + legacy_pwrdiff
;
171 powerBase0
= (powerBase0
<< 24) | (powerBase0
<< 16) |
172 (powerBase0
<< 8) | powerBase0
;
173 *(ofdmbase
+ i
) = powerBase0
;
174 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
175 (" [OFDM power base index rf(%c) = 0x%x]\n",
176 ((i
== 0) ? 'A' : 'B'), *(ofdmbase
+ i
)));
179 for (i
= 0; i
< 2; i
++) {
180 if (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20
) {
181 ht20_pwrdiff
= rtlefuse
->txpwr_ht20diff
[i
][channel
- 1];
182 powerlevel
[i
] += ht20_pwrdiff
;
184 powerBase1
= powerlevel
[i
];
185 powerBase1
= (powerBase1
<< 24) |
186 (powerBase1
<< 16) | (powerBase1
<< 8) | powerBase1
;
188 *(mcsbase
+ i
) = powerBase1
;
190 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
191 (" [MCS power base index rf(%c) = 0x%x]\n",
192 ((i
== 0) ? 'A' : 'B'), *(mcsbase
+ i
)));
196 static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw
*hw
,
197 u8 channel
, u8 index
,
202 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
203 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
204 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
205 u8 i
, chnlgroup
, pwr_diff_limit
[4];
206 u32 writeVal
, customer_limit
, rf
;
208 for (rf
= 0; rf
< 2; rf
++) {
209 switch (rtlefuse
->eeprom_regulatory
) {
214 rtlphy
->mcs_txpwrlevel_origoffset
[chnlgroup
][index
+
216 + ((index
< 2) ? powerBase0
[rf
] : powerBase1
[rf
]);
218 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
219 ("RTK better performance, "
220 "writeVal(%c) = 0x%x\n",
221 ((rf
== 0) ? 'A' : 'B'), writeVal
));
224 if (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20_40
) {
225 writeVal
= ((index
< 2) ? powerBase0
[rf
] :
228 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
229 ("Realtek regulatory, 40MHz, "
230 "writeVal(%c) = 0x%x\n",
231 ((rf
== 0) ? 'A' : 'B'), writeVal
));
233 if (rtlphy
->pwrgroup_cnt
== 1)
235 if (rtlphy
->pwrgroup_cnt
>= 3) {
238 else if (channel
>= 4 && channel
<= 9)
240 else if (channel
> 9)
242 if (rtlphy
->pwrgroup_cnt
== 4)
247 rtlphy
->mcs_txpwrlevel_origoffset
[chnlgroup
]
248 [index
+ (rf
? 8 : 0)] + ((index
< 2) ?
252 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
253 ("Realtek regulatory, 20MHz, "
254 "writeVal(%c) = 0x%x\n",
255 ((rf
== 0) ? 'A' : 'B'), writeVal
));
260 ((index
< 2) ? powerBase0
[rf
] : powerBase1
[rf
]);
262 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
263 ("Better regulatory, "
264 "writeVal(%c) = 0x%x\n",
265 ((rf
== 0) ? 'A' : 'B'), writeVal
));
270 if (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20_40
) {
271 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
272 ("customer's limit, 40MHz "
274 ((rf
== 0) ? 'A' : 'B'),
275 rtlefuse
->pwrgroup_ht40
[rf
][channel
-
278 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
279 ("customer's limit, 20MHz "
281 ((rf
== 0) ? 'A' : 'B'),
282 rtlefuse
->pwrgroup_ht20
[rf
][channel
-
285 for (i
= 0; i
< 4; i
++) {
287 (u8
) ((rtlphy
->mcs_txpwrlevel_origoffset
289 (rf
? 8 : 0)] & (0x7f << (i
* 8))) >>
292 if (rtlphy
->current_chan_bw
==
293 HT_CHANNEL_WIDTH_20_40
) {
294 if (pwr_diff_limit
[i
] >
296 pwrgroup_ht40
[rf
][channel
- 1])
298 rtlefuse
->pwrgroup_ht40
[rf
]
301 if (pwr_diff_limit
[i
] >
303 pwrgroup_ht20
[rf
][channel
- 1])
305 rtlefuse
->pwrgroup_ht20
[rf
]
310 customer_limit
= (pwr_diff_limit
[3] << 24) |
311 (pwr_diff_limit
[2] << 16) |
312 (pwr_diff_limit
[1] << 8) | (pwr_diff_limit
[0]);
314 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
315 ("Customer's limit rf(%c) = 0x%x\n",
316 ((rf
== 0) ? 'A' : 'B'), customer_limit
));
318 writeVal
= customer_limit
+
319 ((index
< 2) ? powerBase0
[rf
] : powerBase1
[rf
]);
321 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
322 ("Customer, writeVal rf(%c)= 0x%x\n",
323 ((rf
== 0) ? 'A' : 'B'), writeVal
));
328 rtlphy
->mcs_txpwrlevel_origoffset
[chnlgroup
]
329 [index
+ (rf
? 8 : 0)]
330 + ((index
< 2) ? powerBase0
[rf
] : powerBase1
[rf
]);
332 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
333 ("RTK better performance, writeVal "
335 ((rf
== 0) ? 'A' : 'B'), writeVal
));
339 if (rtlpriv
->dm
.dynamic_txhighpower_lvl
== TXHIGHPWRLEVEL_BT1
)
340 writeVal
= writeVal
- 0x06060606;
341 else if (rtlpriv
->dm
.dynamic_txhighpower_lvl
==
343 writeVal
= writeVal
- 0x0c0c0c0c;
344 *(p_outwriteval
+ rf
) = writeVal
;
348 static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw
*hw
,
349 u8 index
, u32
*pValue
)
351 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
352 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
354 u16 regoffset_a
[6] = {
355 RTXAGC_A_RATE18_06
, RTXAGC_A_RATE54_24
,
356 RTXAGC_A_MCS03_MCS00
, RTXAGC_A_MCS07_MCS04
,
357 RTXAGC_A_MCS11_MCS08
, RTXAGC_A_MCS15_MCS12
359 u16 regoffset_b
[6] = {
360 RTXAGC_B_RATE18_06
, RTXAGC_B_RATE54_24
,
361 RTXAGC_B_MCS03_MCS00
, RTXAGC_B_MCS07_MCS04
,
362 RTXAGC_B_MCS11_MCS08
, RTXAGC_B_MCS15_MCS12
364 u8 i
, rf
, pwr_val
[4];
368 for (rf
= 0; rf
< 2; rf
++) {
369 writeVal
= pValue
[rf
];
370 for (i
= 0; i
< 4; i
++) {
371 pwr_val
[i
] = (u8
) ((writeVal
& (0x7f <<
372 (i
* 8))) >> (i
* 8));
374 if (pwr_val
[i
] > RF6052_MAX_TX_PWR
)
375 pwr_val
[i
] = RF6052_MAX_TX_PWR
;
377 writeVal
= (pwr_val
[3] << 24) | (pwr_val
[2] << 16) |
378 (pwr_val
[1] << 8) | pwr_val
[0];
381 regoffset
= regoffset_a
[index
];
383 regoffset
= regoffset_b
[index
];
384 rtl_set_bbreg(hw
, regoffset
, MASKDWORD
, writeVal
);
386 RTPRINT(rtlpriv
, FPHY
, PHY_TXPWR
,
387 ("Set 0x%x = %08x\n", regoffset
, writeVal
));
389 if (((get_rf_type(rtlphy
) == RF_2T2R
) &&
390 (regoffset
== RTXAGC_A_MCS15_MCS12
||
391 regoffset
== RTXAGC_B_MCS15_MCS12
)) ||
392 ((get_rf_type(rtlphy
) != RF_2T2R
) &&
393 (regoffset
== RTXAGC_A_MCS07_MCS04
||
394 regoffset
== RTXAGC_B_MCS07_MCS04
))) {
396 writeVal
= pwr_val
[3];
397 if (regoffset
== RTXAGC_A_MCS15_MCS12
||
398 regoffset
== RTXAGC_A_MCS07_MCS04
)
400 if (regoffset
== RTXAGC_B_MCS15_MCS12
||
401 regoffset
== RTXAGC_B_MCS07_MCS04
)
404 for (i
= 0; i
< 3; i
++) {
405 writeVal
= (writeVal
> 6) ? (writeVal
- 6) : 0;
406 rtl_write_byte(rtlpriv
, (u32
) (regoffset
+ i
),
413 void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw
*hw
,
414 u8
*ppowerlevel
, u8 channel
)
416 u32 writeVal
[2], powerBase0
[2], powerBase1
[2];
419 rtl92c_phy_get_power_base(hw
, ppowerlevel
,
420 channel
, &powerBase0
[0], &powerBase1
[0]);
422 for (index
= 0; index
< 6; index
++) {
423 _rtl92c_get_txpower_writeval_by_regulatory(hw
,
429 _rtl92c_write_ofdm_power_reg(hw
, index
, &writeVal
[0]);
433 bool rtl92c_phy_rf6052_config(struct ieee80211_hw
*hw
)
435 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
436 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
438 if (rtlphy
->rf_type
== RF_1T1R
)
439 rtlphy
->num_total_rfpath
= 1;
441 rtlphy
->num_total_rfpath
= 2;
443 return _rtl92c_phy_rf6052_config_parafile(hw
);
446 static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw
*hw
)
448 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
449 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
453 struct bb_reg_def
*pphyreg
;
455 for (rfpath
= 0; rfpath
< rtlphy
->num_total_rfpath
; rfpath
++) {
457 pphyreg
= &rtlphy
->phyreg_def
[rfpath
];
462 u4_regvalue
= rtl_get_bbreg(hw
, pphyreg
->rfintfs
,
467 u4_regvalue
= rtl_get_bbreg(hw
, pphyreg
->rfintfs
,
472 rtl_set_bbreg(hw
, pphyreg
->rfintfe
, BRFSI_RFENV
<< 16, 0x1);
475 rtl_set_bbreg(hw
, pphyreg
->rfintfo
, BRFSI_RFENV
, 0x1);
478 rtl_set_bbreg(hw
, pphyreg
->rfhssi_para2
,
479 B3WIREADDREAALENGTH
, 0x0);
482 rtl_set_bbreg(hw
, pphyreg
->rfhssi_para2
, B3WIREDATALENGTH
, 0x0);
487 rtstatus
= rtl92c_phy_config_rf_with_headerfile(hw
,
488 (enum radio_path
) rfpath
);
491 rtstatus
= rtl92c_phy_config_rf_with_headerfile(hw
,
492 (enum radio_path
) rfpath
);
503 rtl_set_bbreg(hw
, pphyreg
->rfintfs
,
504 BRFSI_RFENV
, u4_regvalue
);
508 rtl_set_bbreg(hw
, pphyreg
->rfintfs
,
509 BRFSI_RFENV
<< 16, u4_regvalue
);
513 if (rtstatus
!= true) {
514 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
515 ("Radio[%d] Fail!!", rfpath
));
521 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, ("<---\n"));