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Merge tag 'nfc-next-3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8723be / hw.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../efuse.h"
28 #include "../base.h"
29 #include "../regd.h"
30 #include "../cam.h"
31 #include "../ps.h"
32 #include "../pci.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "dm.h"
37 #include "../rtl8723com/dm_common.h"
38 #include "fw.h"
39 #include "../rtl8723com/fw_common.h"
40 #include "led.h"
41 #include "hw.h"
42 #include "pwrseq.h"
43 #include "../btcoexist/rtl_btc.h"
44
45 #define LLT_CONFIG 5
46
47 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
48 {
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
51 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
52
53 while (skb_queue_len(&ring->queue)) {
54 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
55 struct sk_buff *skb = __skb_dequeue(&ring->queue);
56
57 pci_unmap_single(rtlpci->pdev,
58 rtlpriv->cfg->ops->get_desc(
59 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
60 skb->len, PCI_DMA_TODEVICE);
61 kfree_skb(skb);
62 ring->idx = (ring->idx + 1) % ring->entries;
63 }
64 }
65
66 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
67 u8 set_bits, u8 clear_bits)
68 {
69 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71
72 rtlpci->reg_bcn_ctrl_val |= set_bits;
73 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
74
75 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
76 }
77
78 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
79 {
80 struct rtl_priv *rtlpriv = rtl_priv(hw);
81 u8 tmp1byte;
82
83 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
84 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
85 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
86 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
87 tmp1byte &= ~(BIT(0));
88 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
89 }
90
91 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
92 {
93 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 u8 tmp1byte;
95
96 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
97 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
98 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
99 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
100 tmp1byte |= BIT(1);
101 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
102 }
103
104 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
105 {
106 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
107 }
108
109 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
110 {
111 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
112 }
113
114 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
115 bool need_turn_off_ckk)
116 {
117 struct rtl_priv *rtlpriv = rtl_priv(hw);
118 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
119 bool support_remote_wake_up;
120 u32 count = 0, isr_regaddr, content;
121 bool schedule_timer = need_turn_off_ckk;
122 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
123 (u8 *)(&support_remote_wake_up));
124
125 if (!rtlhal->fw_ready)
126 return;
127 if (!rtlpriv->psc.fw_current_inpsmode)
128 return;
129
130 while (1) {
131 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
132 if (rtlhal->fw_clk_change_in_progress) {
133 while (rtlhal->fw_clk_change_in_progress) {
134 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
135 count++;
136 udelay(100);
137 if (count > 1000)
138 return;
139 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
140 }
141 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
142 } else {
143 rtlhal->fw_clk_change_in_progress = false;
144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
145 break;
146 }
147 }
148 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
149 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
150 (u8 *)(&rpwm_val));
151 if (FW_PS_IS_ACK(rpwm_val)) {
152 isr_regaddr = REG_HISR;
153 content = rtl_read_dword(rtlpriv, isr_regaddr);
154 while (!(content & IMR_CPWM) && (count < 500)) {
155 udelay(50);
156 count++;
157 content = rtl_read_dword(rtlpriv, isr_regaddr);
158 }
159
160 if (content & IMR_CPWM) {
161 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
162 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
163 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
164 "Receive CPWM INT!!! Set "
165 "pHalData->FwPSState = %X\n",
166 rtlhal->fw_ps_state);
167 }
168 }
169 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
170 rtlhal->fw_clk_change_in_progress = false;
171 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
172 if (schedule_timer) {
173 mod_timer(&rtlpriv->works.fw_clockoff_timer,
174 jiffies + MSECS(10));
175 }
176 } else {
177 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
178 rtlhal->fw_clk_change_in_progress = false;
179 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
180 }
181 }
182
183 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
184 {
185 struct rtl_priv *rtlpriv = rtl_priv(hw);
186 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
187 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
188 struct rtl8192_tx_ring *ring;
189 enum rf_pwrstate rtstate;
190 bool schedule_timer = false;
191 u8 queue;
192
193 if (!rtlhal->fw_ready)
194 return;
195 if (!rtlpriv->psc.fw_current_inpsmode)
196 return;
197 if (!rtlhal->allow_sw_to_change_hwclc)
198 return;
199 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
200 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
201 return;
202
203 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
204 ring = &rtlpci->tx_ring[queue];
205 if (skb_queue_len(&ring->queue)) {
206 schedule_timer = true;
207 break;
208 }
209 }
210 if (schedule_timer) {
211 mod_timer(&rtlpriv->works.fw_clockoff_timer,
212 jiffies + MSECS(10));
213 return;
214 }
215 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
216 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
217 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
218 if (!rtlhal->fw_clk_change_in_progress) {
219 rtlhal->fw_clk_change_in_progress = true;
220 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
221 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
222 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
223 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
224 (u8 *)(&rpwm_val));
225 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
226 rtlhal->fw_clk_change_in_progress = false;
227 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
228 } else {
229 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
230 mod_timer(&rtlpriv->works.fw_clockoff_timer,
231 jiffies + MSECS(10));
232 }
233 }
234 }
235
236 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
237 {
238 u8 rpwm_val = 0;
239 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
240 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
241 }
242
243 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
244 {
245 struct rtl_priv *rtlpriv = rtl_priv(hw);
246 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
247 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
248 bool fw_current_inps = false;
249 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
250
251 if (ppsc->low_power_enable) {
252 rpwm_val = (FW_PS_STATE_ALL_ON_88E | FW_PS_ACK);/* RF on */
253 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
254 rtlhal->allow_sw_to_change_hwclc = false;
255 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
256 (u8 *)(&fw_pwrmode));
257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
258 (u8 *)(&fw_current_inps));
259 } else {
260 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */
261 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
262 (u8 *)(&rpwm_val));
263 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
264 (u8 *)(&fw_pwrmode));
265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
266 (u8 *)(&fw_current_inps));
267 }
268 }
269
270 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
271 {
272 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
274 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
275 bool fw_current_inps = true;
276 u8 rpwm_val;
277
278 if (ppsc->low_power_enable) {
279 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */
280 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
281 (u8 *)(&fw_current_inps));
282 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
283 (u8 *)(&ppsc->fwctrl_psmode));
284 rtlhal->allow_sw_to_change_hwclc = true;
285 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
286
287 } else {
288 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */
289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
290 (u8 *)(&fw_current_inps));
291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
292 (u8 *)(&ppsc->fwctrl_psmode));
293 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
294 (u8 *)(&rpwm_val));
295 }
296 }
297
298 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
299 {
300 struct rtl_priv *rtlpriv = rtl_priv(hw);
301 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
303
304 switch (variable) {
305 case HW_VAR_RCR:
306 *((u32 *)(val)) = rtlpci->receive_config;
307 break;
308 case HW_VAR_RF_STATE:
309 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
310 break;
311 case HW_VAR_FWLPS_RF_ON: {
312 enum rf_pwrstate rfstate;
313 u32 val_rcr;
314
315 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
316 (u8 *)(&rfstate));
317 if (rfstate == ERFOFF) {
318 *((bool *)(val)) = true;
319 } else {
320 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
321 val_rcr &= 0x00070000;
322 if (val_rcr)
323 *((bool *)(val)) = false;
324 else
325 *((bool *)(val)) = true;
326 }
327 break; }
328 case HW_VAR_FW_PSMODE_STATUS:
329 *((bool *)(val)) = ppsc->fw_current_inpsmode;
330 break;
331 case HW_VAR_CORRECT_TSF: {
332 u64 tsf;
333 u32 *ptsf_low = (u32 *)&tsf;
334 u32 *ptsf_high = ((u32 *)&tsf) + 1;
335
336 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
337 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
338
339 *((u64 *)(val)) = tsf;
340
341 break; }
342 default:
343 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
344 "switch case not process %x\n", variable);
345 break;
346 }
347 }
348
349 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
350 {
351 struct rtl_priv *rtlpriv = rtl_priv(hw);
352 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
353 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
354 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
355 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
356 u8 idx;
357
358 switch (variable) {
359 case HW_VAR_ETHER_ADDR:
360 for (idx = 0; idx < ETH_ALEN; idx++)
361 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
362 break;
363 case HW_VAR_BASIC_RATE: {
364 u16 rate_cfg = ((u16 *)val)[0];
365 u8 rate_index = 0;
366 rate_cfg = rate_cfg & 0x15f;
367 rate_cfg |= 0x01;
368 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
369 rtl_write_byte(rtlpriv, REG_RRSR + 1, (rate_cfg >> 8) & 0xff);
370 while (rate_cfg > 0x1) {
371 rate_cfg = (rate_cfg >> 1);
372 rate_index++;
373 }
374 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
375 break; }
376 case HW_VAR_BSSID:
377 for (idx = 0; idx < ETH_ALEN; idx++)
378 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
379 break;
380 case HW_VAR_SIFS:
381 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
382 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
383
384 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
385 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
386
387 if (!mac->ht_enable)
388 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
389 else
390 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
391 *((u16 *)val));
392 break;
393 case HW_VAR_SLOT_TIME: {
394 u8 e_aci;
395
396 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
397 "HW_VAR_SLOT_TIME %x\n", val[0]);
398
399 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
400
401 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
402 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
403 (u8 *)(&e_aci));
404 }
405 break; }
406 case HW_VAR_ACK_PREAMBLE: {
407 u8 reg_tmp;
408 u8 short_preamble = (bool) (*(u8 *)val);
409 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
410 if (short_preamble) {
411 reg_tmp |= 0x02;
412 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
413 } else {
414 reg_tmp &= 0xFD;
415 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
416 }
417 break; }
418 case HW_VAR_WPA_CONFIG:
419 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
420 break;
421 case HW_VAR_AMPDU_MIN_SPACE: {
422 u8 min_spacing_to_set;
423 u8 sec_min_space;
424
425 min_spacing_to_set = *((u8 *)val);
426 if (min_spacing_to_set <= 7) {
427 sec_min_space = 0;
428
429 if (min_spacing_to_set < sec_min_space)
430 min_spacing_to_set = sec_min_space;
431
432 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
433 min_spacing_to_set);
434
435 *val = min_spacing_to_set;
436
437 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
438 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
439 mac->min_space_cfg);
440
441 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
442 mac->min_space_cfg);
443 }
444 break; }
445 case HW_VAR_SHORTGI_DENSITY: {
446 u8 density_to_set;
447
448 density_to_set = *((u8 *)val);
449 mac->min_space_cfg |= (density_to_set << 3);
450
451 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
452 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
453 mac->min_space_cfg);
454
455 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
456 mac->min_space_cfg);
457 break; }
458 case HW_VAR_AMPDU_FACTOR: {
459 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
460 u8 factor_toset;
461 u8 *p_regtoset = NULL;
462 u8 index = 0;
463
464 p_regtoset = regtoset_normal;
465
466 factor_toset = *((u8 *)val);
467 if (factor_toset <= 3) {
468 factor_toset = (1 << (factor_toset + 2));
469 if (factor_toset > 0xf)
470 factor_toset = 0xf;
471
472 for (index = 0; index < 4; index++) {
473 if ((p_regtoset[index] & 0xf0) >
474 (factor_toset << 4))
475 p_regtoset[index] =
476 (p_regtoset[index] & 0x0f) |
477 (factor_toset << 4);
478
479 if ((p_regtoset[index] & 0x0f) > factor_toset)
480 p_regtoset[index] =
481 (p_regtoset[index] & 0xf0) |
482 (factor_toset);
483
484 rtl_write_byte(rtlpriv,
485 (REG_AGGLEN_LMT + index),
486 p_regtoset[index]);
487 }
488 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
489 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
490 factor_toset);
491 }
492 break; }
493 case HW_VAR_AC_PARAM: {
494 u8 e_aci = *((u8 *)val);
495 rtl8723_dm_init_edca_turbo(hw);
496
497 if (rtlpci->acm_method != EACMWAY2_SW)
498 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
499 (u8 *)(&e_aci));
500 break; }
501 case HW_VAR_ACM_CTRL: {
502 u8 e_aci = *((u8 *)val);
503 union aci_aifsn *p_aci_aifsn =
504 (union aci_aifsn *)(&(mac->ac[0].aifs));
505 u8 acm = p_aci_aifsn->f.acm;
506 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
507
508 acm_ctrl =
509 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
510
511 if (acm) {
512 switch (e_aci) {
513 case AC0_BE:
514 acm_ctrl |= ACMHW_BEQEN;
515 break;
516 case AC2_VI:
517 acm_ctrl |= ACMHW_VIQEN;
518 break;
519 case AC3_VO:
520 acm_ctrl |= ACMHW_VOQEN;
521 break;
522 default:
523 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
524 "HW_VAR_ACM_CTRL acm set "
525 "failed: eACI is %d\n", acm);
526 break;
527 }
528 } else {
529 switch (e_aci) {
530 case AC0_BE:
531 acm_ctrl &= (~ACMHW_BEQEN);
532 break;
533 case AC2_VI:
534 acm_ctrl &= (~ACMHW_VIQEN);
535 break;
536 case AC3_VO:
537 acm_ctrl &= (~ACMHW_BEQEN);
538 break;
539 default:
540 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
541 "switch case not process\n");
542 break;
543 }
544 }
545 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
546 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
547 "Write 0x%X\n", acm_ctrl);
548 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
549 break; }
550 case HW_VAR_RCR:
551 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
552 rtlpci->receive_config = ((u32 *)(val))[0];
553 break;
554 case HW_VAR_RETRY_LIMIT: {
555 u8 retry_limit = ((u8 *)(val))[0];
556
557 rtl_write_word(rtlpriv, REG_RL,
558 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
559 retry_limit << RETRY_LIMIT_LONG_SHIFT);
560 break; }
561 case HW_VAR_DUAL_TSF_RST:
562 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
563 break;
564 case HW_VAR_EFUSE_BYTES:
565 rtlefuse->efuse_usedbytes = *((u16 *)val);
566 break;
567 case HW_VAR_EFUSE_USAGE:
568 rtlefuse->efuse_usedpercentage = *((u8 *)val);
569 break;
570 case HW_VAR_IO_CMD:
571 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
572 break;
573 case HW_VAR_SET_RPWM: {
574 u8 rpwm_val;
575
576 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
577 udelay(1);
578
579 if (rpwm_val & BIT(7)) {
580 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
581 } else {
582 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
583 ((*(u8 *)val) | BIT(7)));
584 }
585 break; }
586 case HW_VAR_H2C_FW_PWRMODE:
587 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
588 break;
589 case HW_VAR_FW_PSMODE_STATUS:
590 ppsc->fw_current_inpsmode = *((bool *)val);
591 break;
592 case HW_VAR_RESUME_CLK_ON:
593 _rtl8723be_set_fw_ps_rf_on(hw);
594 break;
595 case HW_VAR_FW_LPS_ACTION: {
596 bool enter_fwlps = *((bool *)val);
597
598 if (enter_fwlps)
599 _rtl8723be_fwlps_enter(hw);
600 else
601 _rtl8723be_fwlps_leave(hw);
602
603 break; }
604 case HW_VAR_H2C_FW_JOINBSSRPT: {
605 u8 mstatus = (*(u8 *)val);
606 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
607 u8 count = 0, dlbcn_count = 0;
608 bool recover = false;
609
610 if (mstatus == RT_MEDIA_CONNECT) {
611 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
612
613 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
614 rtl_write_byte(rtlpriv, REG_CR + 1,
615 (tmp_regcr | BIT(0)));
616
617 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
618 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
619
620 tmp_reg422 = rtl_read_byte(rtlpriv,
621 REG_FWHW_TXQ_CTRL + 2);
622 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
623 tmp_reg422 & (~BIT(6)));
624 if (tmp_reg422 & BIT(6))
625 recover = true;
626
627 do {
628 bcnvalid_reg = rtl_read_byte(rtlpriv,
629 REG_TDECTRL + 2);
630 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
631 (bcnvalid_reg | BIT(0)));
632 _rtl8723be_return_beacon_queue_skb(hw);
633
634 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
635 bcnvalid_reg = rtl_read_byte(rtlpriv,
636 REG_TDECTRL + 2);
637 count = 0;
638 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
639 count++;
640 udelay(10);
641 bcnvalid_reg = rtl_read_byte(rtlpriv,
642 REG_TDECTRL + 2);
643 }
644 dlbcn_count++;
645 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
646
647 if (bcnvalid_reg & BIT(0))
648 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
649
650 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
651 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
652
653 if (recover) {
654 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
655 tmp_reg422);
656 }
657 rtl_write_byte(rtlpriv, REG_CR + 1,
658 (tmp_regcr & ~(BIT(0))));
659 }
660 rtl8723be_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
661 break; }
662 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
663 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
664 break;
665 case HW_VAR_AID: {
666 u16 u2btmp;
667 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
668 u2btmp &= 0xC000;
669 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
670 (u2btmp | mac->assoc_id));
671 break; }
672 case HW_VAR_CORRECT_TSF: {
673 u8 btype_ibss = ((u8 *)(val))[0];
674
675 if (btype_ibss)
676 _rtl8723be_stop_tx_beacon(hw);
677
678 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
679
680 rtl_write_dword(rtlpriv, REG_TSFTR,
681 (u32) (mac->tsf & 0xffffffff));
682 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
683 (u32) ((mac->tsf >> 32) & 0xffffffff));
684
685 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
686
687 if (btype_ibss)
688 _rtl8723be_resume_tx_beacon(hw);
689 break; }
690 case HW_VAR_KEEP_ALIVE: {
691 u8 array[2];
692 array[0] = 0xff;
693 array[1] = *((u8 *)val);
694 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_KEEP_ALIVE_CTRL,
695 2, array);
696 break; }
697 default:
698 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
699 "switch case not process %x\n",
700 variable);
701 break;
702 }
703 }
704
705 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
706 {
707 struct rtl_priv *rtlpriv = rtl_priv(hw);
708 bool status = true;
709 int count = 0;
710 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
711 _LLT_OP(_LLT_WRITE_ACCESS);
712
713 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
714
715 do {
716 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
717 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
718 break;
719
720 if (count > POLLING_LLT_THRESHOLD) {
721 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
722 "Failed to polling write LLT done at "
723 "address %d!\n", address);
724 status = false;
725 break;
726 }
727 } while (++count);
728
729 return status;
730 }
731
732 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
733 {
734 struct rtl_priv *rtlpriv = rtl_priv(hw);
735 unsigned short i;
736 u8 txpktbuf_bndy;
737 u8 maxpage;
738 bool status;
739
740 maxpage = 255;
741 txpktbuf_bndy = 245;
742
743 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
744 (0x27FF0000 | txpktbuf_bndy));
745 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
746
747 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
748 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
749
750 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
751 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
752 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
753
754 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
755 status = _rtl8723be_llt_write(hw, i, i + 1);
756 if (!status)
757 return status;
758 }
759 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
760
761 if (!status)
762 return status;
763
764 for (i = txpktbuf_bndy; i < maxpage; i++) {
765 status = _rtl8723be_llt_write(hw, i, (i + 1));
766 if (!status)
767 return status;
768 }
769 status = _rtl8723be_llt_write(hw, maxpage, txpktbuf_bndy);
770 if (!status)
771 return status;
772
773 rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
774 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
775
776 return true;
777 }
778
779 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
780 {
781 struct rtl_priv *rtlpriv = rtl_priv(hw);
782 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
783 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
784 struct rtl_led *pled0 = &(pcipriv->ledctl.sw_led0);
785
786 if (rtlpriv->rtlhal.up_first_time)
787 return;
788
789 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
790 rtl8723be_sw_led_on(hw, pled0);
791 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
792 rtl8723be_sw_led_on(hw, pled0);
793 else
794 rtl8723be_sw_led_off(hw, pled0);
795 }
796
797 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
798 {
799 struct rtl_priv *rtlpriv = rtl_priv(hw);
800 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
801
802 unsigned char bytetmp;
803 unsigned short wordtmp;
804 u16 retry = 0;
805 bool mac_func_enable;
806
807 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
808
809 /*Auto Power Down to CHIP-off State*/
810 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
811 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
812
813 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
814 if (bytetmp == 0xFF)
815 mac_func_enable = true;
816 else
817 mac_func_enable = false;
818
819 /* HW Power on sequence */
820 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
821 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
822 RTL8723_NIC_ENABLE_FLOW)) {
823 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
824 "init MAC Fail as power on failure\n");
825 return false;
826 }
827 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
828 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
829
830 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
831 bytetmp = 0xff;
832 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
833 mdelay(2);
834
835 bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
836 bytetmp |= 0x7f;
837 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
838 mdelay(2);
839
840 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
841 if (bytetmp & BIT(0)) {
842 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
843 bytetmp |= BIT(6);
844 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
845 }
846 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
847 bytetmp |= BIT(3);
848 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp);
849 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
850 bytetmp &= ~BIT(4);
851 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
852
853 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+3);
854 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+3, bytetmp | 0x77);
855
856 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
857
858 if (!mac_func_enable) {
859 if (!_rtl8723be_llt_table_init(hw))
860 return false;
861 }
862 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
863 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
864
865 /* Enable FW Beamformer Interrupt */
866 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
867 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
868
869 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
870 wordtmp &= 0xf;
871 wordtmp |= 0xF5B1;
872 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
873
874 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
875 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
876 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
877 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
878
879 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
880
881 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
882 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
883 DMA_BIT_MASK(32));
884 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
885 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
886 DMA_BIT_MASK(32));
887 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
888 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
889 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
890 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
891 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
892 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
893 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
894 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
895 rtl_write_dword(rtlpriv, REG_HQ_DESA,
896 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
897 DMA_BIT_MASK(32));
898 rtl_write_dword(rtlpriv, REG_RX_DESA,
899 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
900 DMA_BIT_MASK(32));
901
902 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
903 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
904
905 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
906
907 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
908 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
909
910 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
911
912 do {
913 retry++;
914 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
915 } while ((retry < 200) && (bytetmp & BIT(7)));
916
917 _rtl8723be_gen_refresh_led_state(hw);
918
919 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
920
921 bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
922 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & ~BIT(2));
923
924 return true;
925 }
926
927 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
928 {
929 struct rtl_priv *rtlpriv = rtl_priv(hw);
930 u8 reg_bw_opmode;
931 u32 reg_ratr, reg_prsr;
932
933 reg_bw_opmode = BW_OPMODE_20MHZ;
934 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
935 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
936 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
937
938 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
939 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
940 }
941
942 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
943 {
944 struct rtl_priv *rtlpriv = rtl_priv(hw);
945 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
946
947 rtl_write_byte(rtlpriv, 0x34b, 0x93);
948 rtl_write_word(rtlpriv, 0x350, 0x870c);
949 rtl_write_byte(rtlpriv, 0x352, 0x1);
950
951 if (ppsc->support_backdoor)
952 rtl_write_byte(rtlpriv, 0x349, 0x1b);
953 else
954 rtl_write_byte(rtlpriv, 0x349, 0x03);
955
956 rtl_write_word(rtlpriv, 0x350, 0x2718);
957 rtl_write_byte(rtlpriv, 0x352, 0x1);
958 }
959
960 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
961 {
962 struct rtl_priv *rtlpriv = rtl_priv(hw);
963 u8 sec_reg_value;
964
965 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
966 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
967 rtlpriv->sec.pairwise_enc_algorithm,
968 rtlpriv->sec.group_enc_algorithm);
969
970 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
971 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
972 "not open hw encryption\n");
973 return;
974 }
975 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
976
977 if (rtlpriv->sec.use_defaultkey) {
978 sec_reg_value |= SCR_TXUSEDK;
979 sec_reg_value |= SCR_RXUSEDK;
980 }
981 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
982
983 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
984
985 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "The SECR-value %x\n",
986 sec_reg_value);
987
988 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
989 }
990
991 int rtl8723be_hw_init(struct ieee80211_hw *hw)
992 {
993 struct rtl_priv *rtlpriv = rtl_priv(hw);
994 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
995 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
996 struct rtl_phy *rtlphy = &(rtlpriv->phy);
997 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
998 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
999 bool rtstatus = true;
1000 int err;
1001 u8 tmp_u1b;
1002 unsigned long flags;
1003
1004 /* reenable interrupts to not interfere with other devices */
1005 local_save_flags(flags);
1006 local_irq_enable();
1007
1008 rtlpriv->rtlhal.being_init_adapter = true;
1009 rtlpriv->intf_ops->disable_aspm(hw);
1010 rtstatus = _rtl8723be_init_mac(hw);
1011 if (!rtstatus) {
1012 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1013 err = 1;
1014 goto exit;
1015 }
1016 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1017 tmp_u1b &= 0x7F;
1018 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1019
1020 err = rtl8723_download_fw(hw, true);
1021 if (err) {
1022 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1023 "Failed to download FW. Init HW without FW now..\n");
1024 err = 1;
1025 rtlhal->fw_ready = false;
1026 goto exit;
1027 } else {
1028 rtlhal->fw_ready = true;
1029 }
1030 rtlhal->last_hmeboxnum = 0;
1031 rtl8723be_phy_mac_config(hw);
1032 /* because last function modify RCR, so we update
1033 * rcr var here, or TP will unstable for receive_config
1034 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1035 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1036 */
1037 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1038 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1039 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1040
1041 rtl8723be_phy_bb_config(hw);
1042 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1043 rtl8723be_phy_rf_config(hw);
1044
1045 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1046 RF_CHNLBW, RFREG_OFFSET_MASK);
1047 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1048 RF_CHNLBW, RFREG_OFFSET_MASK);
1049 rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1050 rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1051
1052 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1053 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1054 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1055 _rtl8723be_hw_configure(hw);
1056 rtl_cam_reset_all_entry(hw);
1057 rtl8723be_enable_hw_security_config(hw);
1058
1059 ppsc->rfpwr_state = ERFON;
1060
1061 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1062 _rtl8723be_enable_aspm_back_door(hw);
1063 rtlpriv->intf_ops->enable_aspm(hw);
1064
1065 rtl8723be_bt_hw_init(hw);
1066
1067 rtl_set_bbreg(hw, 0x64, BIT(20), 0);
1068 rtl_set_bbreg(hw, 0x64, BIT(24), 0);
1069
1070 rtl_set_bbreg(hw, 0x40, BIT(4), 0);
1071 rtl_set_bbreg(hw, 0x40, BIT(3), 1);
1072
1073 rtl_set_bbreg(hw, 0x944, BIT(0)|BIT(1), 0x3);
1074 rtl_set_bbreg(hw, 0x930, 0xff, 0x77);
1075
1076 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1);
1077
1078 rtl_set_bbreg(hw, 0xb2c, 0xffffffff, 0x80000000);
1079
1080 if (ppsc->rfpwr_state == ERFON) {
1081 rtl8723be_dm_check_txpower_tracking(hw);
1082 rtl8723be_phy_lc_calibrate(hw);
1083 }
1084 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1085 if (!(tmp_u1b & BIT(0))) {
1086 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1087 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1088 }
1089 if (!(tmp_u1b & BIT(4))) {
1090 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1091 tmp_u1b &= 0x0F;
1092 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1093 udelay(10);
1094 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1095 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1096 }
1097 rtl8723be_dm_init(hw);
1098 exit:
1099 local_irq_restore(flags);
1100 rtlpriv->rtlhal.being_init_adapter = false;
1101 return err;
1102 }
1103
1104 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1105 {
1106 struct rtl_priv *rtlpriv = rtl_priv(hw);
1107 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1108 enum version_8723e version = VERSION_UNKNOWN;
1109 u8 count = 0;
1110 u8 value8;
1111 u32 value32;
1112
1113 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0);
1114
1115 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 2);
1116 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 2, value8 | BIT(0));
1117
1118 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
1119 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, value8 | BIT(0));
1120
1121 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
1122 while (((value8 & BIT(0))) && (count++ < 100)) {
1123 udelay(10);
1124 value8 = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
1125 }
1126 count = 0;
1127 value8 = rtl_read_byte(rtlpriv, REG_ROM_VERSION);
1128 while ((value8 == 0) && (count++ < 50)) {
1129 value8 = rtl_read_byte(rtlpriv, REG_ROM_VERSION);
1130 mdelay(1);
1131 }
1132 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1133 if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1134 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unkown chip version\n");
1135 else
1136 version = (enum version_8723e) VERSION_TEST_CHIP_1T1R_8723B;
1137
1138 rtlphy->rf_type = RF_1T1R;
1139
1140 value8 = rtl_read_byte(rtlpriv, REG_ROM_VERSION);
1141 if (value8 >= 0x02)
1142 version |= BIT(3);
1143 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1144 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1145 "RF_2T2R" : "RF_1T1R");
1146
1147 return version;
1148 }
1149
1150 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1151 enum nl80211_iftype type)
1152 {
1153 struct rtl_priv *rtlpriv = rtl_priv(hw);
1154 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1155 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1156
1157 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1158 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1159 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1160
1161 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1162 type == NL80211_IFTYPE_STATION) {
1163 _rtl8723be_stop_tx_beacon(hw);
1164 _rtl8723be_enable_bcn_sub_func(hw);
1165 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1166 _rtl8723be_resume_tx_beacon(hw);
1167 _rtl8723be_disable_bcn_sub_func(hw);
1168 } else {
1169 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1170 "Set HW_VAR_MEDIA_STATUS: "
1171 "No such media status(%x).\n", type);
1172 }
1173 switch (type) {
1174 case NL80211_IFTYPE_UNSPECIFIED:
1175 bt_msr |= MSR_NOLINK;
1176 ledaction = LED_CTL_LINK;
1177 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1178 "Set Network type to NO LINK!\n");
1179 break;
1180 case NL80211_IFTYPE_ADHOC:
1181 bt_msr |= MSR_ADHOC;
1182 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1183 "Set Network type to Ad Hoc!\n");
1184 break;
1185 case NL80211_IFTYPE_STATION:
1186 bt_msr |= MSR_INFRA;
1187 ledaction = LED_CTL_LINK;
1188 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1189 "Set Network type to STA!\n");
1190 break;
1191 case NL80211_IFTYPE_AP:
1192 bt_msr |= MSR_AP;
1193 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1194 "Set Network type to AP!\n");
1195 break;
1196 default:
1197 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1198 "Network type %d not support!\n", type);
1199 return 1;
1200 }
1201 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1202 rtlpriv->cfg->ops->led_control(hw, ledaction);
1203 if ((bt_msr & 0x03) == MSR_AP)
1204 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1205 else
1206 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1207 return 0;
1208 }
1209
1210 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1211 {
1212 struct rtl_priv *rtlpriv = rtl_priv(hw);
1213 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1214 u32 reg_rcr = rtlpci->receive_config;
1215
1216 if (rtlpriv->psc.rfpwr_state != ERFON)
1217 return;
1218
1219 if (check_bssid) {
1220 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1221 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1222 (u8 *)(&reg_rcr));
1223 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1224 } else if (!check_bssid) {
1225 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1226 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1227 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1228 (u8 *)(&reg_rcr));
1229 }
1230 }
1231
1232 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1233 enum nl80211_iftype type)
1234 {
1235 struct rtl_priv *rtlpriv = rtl_priv(hw);
1236
1237 if (_rtl8723be_set_media_status(hw, type))
1238 return -EOPNOTSUPP;
1239
1240 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1241 if (type != NL80211_IFTYPE_AP)
1242 rtl8723be_set_check_bssid(hw, true);
1243 } else {
1244 rtl8723be_set_check_bssid(hw, false);
1245 }
1246 return 0;
1247 }
1248
1249 /* don't set REG_EDCA_BE_PARAM here
1250 * because mac80211 will send pkt when scan
1251 */
1252 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1253 {
1254 struct rtl_priv *rtlpriv = rtl_priv(hw);
1255 rtl8723_dm_init_edca_turbo(hw);
1256 switch (aci) {
1257 case AC1_BK:
1258 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1259 break;
1260 case AC0_BE:
1261 break;
1262 case AC2_VI:
1263 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1264 break;
1265 case AC3_VO:
1266 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1267 break;
1268 default:
1269 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1270 break;
1271 }
1272 }
1273
1274 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1275 {
1276 struct rtl_priv *rtlpriv = rtl_priv(hw);
1277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1278
1279 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1280 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1281 rtlpci->irq_enabled = true;
1282 /* there are some C2H CMDs have been sent
1283 * before system interrupt is enabled, e.g., C2H, CPWM.
1284 * So we need to clear all C2H events that FW has notified,
1285 * otherwise FW won't schedule any commands anymore.
1286 */
1287 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1288 /*enable system interrupt*/
1289 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1290 }
1291
1292 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1293 {
1294 struct rtl_priv *rtlpriv = rtl_priv(hw);
1295 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1296
1297 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1298 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1299 rtlpci->irq_enabled = false;
1300 synchronize_irq(rtlpci->pdev->irq);
1301 }
1302
1303 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1304 {
1305 struct rtl_priv *rtlpriv = rtl_priv(hw);
1306 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1307 u8 u1b_tmp;
1308
1309 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1310 /* 1. Run LPS WL RFOFF flow */
1311 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1312 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1313
1314 /* 2. 0x1F[7:0] = 0 */
1315 /* turn off RF */
1316 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1317 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1318 rtlhal->fw_ready)
1319 rtl8723be_firmware_selfreset(hw);
1320
1321 /* Reset MCU. Suggested by Filen. */
1322 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1323 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1324
1325 /* g. MCUFWDL 0x80[1:0]= 0 */
1326 /* reset MCU ready status */
1327 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1328
1329 /* HW card disable configuration. */
1330 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1331 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1332
1333 /* Reset MCU IO Wrapper */
1334 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1335 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1336 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1337 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1338
1339 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1340 /* lock ISO/CLK/Power control register */
1341 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1342 }
1343
1344 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1345 {
1346 struct rtl_priv *rtlpriv = rtl_priv(hw);
1347 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1348 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1349 enum nl80211_iftype opmode;
1350
1351 mac->link_state = MAC80211_NOLINK;
1352 opmode = NL80211_IFTYPE_UNSPECIFIED;
1353 _rtl8723be_set_media_status(hw, opmode);
1354 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1355 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1356 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1357 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1358 _rtl8723be_poweroff_adapter(hw);
1359
1360 /* after power off we should do iqk again */
1361 rtlpriv->phy.iqk_initialized = false;
1362 }
1363
1364 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1365 u32 *p_inta, u32 *p_intb)
1366 {
1367 struct rtl_priv *rtlpriv = rtl_priv(hw);
1368 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1369
1370 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1371 rtl_write_dword(rtlpriv, ISR, *p_inta);
1372
1373 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1374 rtlpci->irq_mask[1];
1375 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1376 }
1377
1378 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1379 {
1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1381 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1382 u16 bcn_interval, atim_window;
1383
1384 bcn_interval = mac->beacon_interval;
1385 atim_window = 2; /*FIX MERGE */
1386 rtl8723be_disable_interrupt(hw);
1387 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1388 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1389 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1390 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1391 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1392 rtl_write_byte(rtlpriv, 0x606, 0x30);
1393 rtl8723be_enable_interrupt(hw);
1394 }
1395
1396 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1397 {
1398 struct rtl_priv *rtlpriv = rtl_priv(hw);
1399 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1400 u16 bcn_interval = mac->beacon_interval;
1401
1402 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1403 "beacon_interval:%d\n", bcn_interval);
1404 rtl8723be_disable_interrupt(hw);
1405 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1406 rtl8723be_enable_interrupt(hw);
1407 }
1408
1409 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1410 u32 add_msr, u32 rm_msr)
1411 {
1412 struct rtl_priv *rtlpriv = rtl_priv(hw);
1413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1414
1415 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1416 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1417
1418 if (add_msr)
1419 rtlpci->irq_mask[0] |= add_msr;
1420 if (rm_msr)
1421 rtlpci->irq_mask[0] &= (~rm_msr);
1422 rtl8723be_disable_interrupt(hw);
1423 rtl8723be_enable_interrupt(hw);
1424 }
1425
1426 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1427 {
1428 u8 group;
1429
1430 if (chnl < 3)
1431 group = 0;
1432 else if (chnl < 9)
1433 group = 1;
1434 else
1435 group = 2;
1436 return group;
1437 }
1438
1439 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1440 struct txpower_info_2g *pw2g,
1441 struct txpower_info_5g *pw5g,
1442 bool autoload_fail, u8 *hwinfo)
1443 {
1444 struct rtl_priv *rtlpriv = rtl_priv(hw);
1445 u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1446
1447 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1448 "hal_ReadPowerValueFromPROM8723BE(): "
1449 "PROMContent[0x%x]= 0x%x\n",
1450 (addr + 1), hwinfo[addr + 1]);
1451 if (0xFF == hwinfo[addr + 1]) /*YJ, add, 120316*/
1452 autoload_fail = true;
1453
1454 if (autoload_fail) {
1455 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1456 "auto load fail : Use Default value!\n");
1457 for (path = 0; path < MAX_RF_PATH; path++) {
1458 /* 2.4G default value */
1459 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1460 pw2g->index_cck_base[path][group] = 0x2D;
1461 pw2g->index_bw40_base[path][group] = 0x2D;
1462 }
1463 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1464 if (cnt == 0) {
1465 pw2g->bw20_diff[path][0] = 0x02;
1466 pw2g->ofdm_diff[path][0] = 0x04;
1467 } else {
1468 pw2g->bw20_diff[path][cnt] = 0xFE;
1469 pw2g->bw40_diff[path][cnt] = 0xFE;
1470 pw2g->cck_diff[path][cnt] = 0xFE;
1471 pw2g->ofdm_diff[path][cnt] = 0xFE;
1472 }
1473 }
1474 }
1475 return;
1476 }
1477 for (path = 0; path < MAX_RF_PATH; path++) {
1478 /*2.4G default value*/
1479 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1480 pw2g->index_cck_base[path][group] = hwinfo[addr++];
1481 if (pw2g->index_cck_base[path][group] == 0xFF)
1482 pw2g->index_cck_base[path][group] = 0x2D;
1483 }
1484 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1485 pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1486 if (pw2g->index_bw40_base[path][group] == 0xFF)
1487 pw2g->index_bw40_base[path][group] = 0x2D;
1488 }
1489 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1490 if (cnt == 0) {
1491 pw2g->bw40_diff[path][cnt] = 0;
1492 if (hwinfo[addr] == 0xFF) {
1493 pw2g->bw20_diff[path][cnt] = 0x02;
1494 } else {
1495 pw2g->bw20_diff[path][cnt] =
1496 (hwinfo[addr] & 0xf0) >> 4;
1497 /*bit sign number to 8 bit sign number*/
1498 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1499 pw2g->bw20_diff[path][cnt] |= 0xF0;
1500 }
1501 if (hwinfo[addr] == 0xFF) {
1502 pw2g->ofdm_diff[path][cnt] = 0x04;
1503 } else {
1504 pw2g->ofdm_diff[path][cnt] =
1505 (hwinfo[addr] & 0x0f);
1506 /*bit sign number to 8 bit sign number*/
1507 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1508 pw2g->ofdm_diff[path][cnt] |=
1509 0xF0;
1510 }
1511 pw2g->cck_diff[path][cnt] = 0;
1512 addr++;
1513 } else {
1514 if (hwinfo[addr] == 0xFF) {
1515 pw2g->bw40_diff[path][cnt] = 0xFE;
1516 } else {
1517 pw2g->bw40_diff[path][cnt] =
1518 (hwinfo[addr] & 0xf0) >> 4;
1519 if (pw2g->bw40_diff[path][cnt] & BIT(3))
1520 pw2g->bw40_diff[path][cnt] |=
1521 0xF0;
1522 }
1523 if (hwinfo[addr] == 0xFF) {
1524 pw2g->bw20_diff[path][cnt] = 0xFE;
1525 } else {
1526 pw2g->bw20_diff[path][cnt] =
1527 (hwinfo[addr] & 0x0f);
1528 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1529 pw2g->bw20_diff[path][cnt] |=
1530 0xF0;
1531 }
1532 addr++;
1533
1534 if (hwinfo[addr] == 0xFF) {
1535 pw2g->ofdm_diff[path][cnt] = 0xFE;
1536 } else {
1537 pw2g->ofdm_diff[path][cnt] =
1538 (hwinfo[addr] & 0xf0) >> 4;
1539 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1540 pw2g->ofdm_diff[path][cnt] |=
1541 0xF0;
1542 }
1543 if (hwinfo[addr] == 0xFF) {
1544 pw2g->cck_diff[path][cnt] = 0xFE;
1545 } else {
1546 pw2g->cck_diff[path][cnt] =
1547 (hwinfo[addr] & 0x0f);
1548 if (pw2g->cck_diff[path][cnt] & BIT(3))
1549 pw2g->cck_diff[path][cnt] |=
1550 0xF0;
1551 }
1552 addr++;
1553 }
1554 }
1555 /*5G default value*/
1556 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1557 pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1558 if (pw5g->index_bw40_base[path][group] == 0xFF)
1559 pw5g->index_bw40_base[path][group] = 0xFE;
1560 }
1561 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1562 if (cnt == 0) {
1563 pw5g->bw40_diff[path][cnt] = 0;
1564
1565 if (hwinfo[addr] == 0xFF) {
1566 pw5g->bw20_diff[path][cnt] = 0;
1567 } else {
1568 pw5g->bw20_diff[path][0] =
1569 (hwinfo[addr] & 0xf0) >> 4;
1570 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1571 pw5g->bw20_diff[path][cnt] |=
1572 0xF0;
1573 }
1574 if (hwinfo[addr] == 0xFF) {
1575 pw5g->ofdm_diff[path][cnt] = 0x04;
1576 } else {
1577 pw5g->ofdm_diff[path][0] =
1578 (hwinfo[addr] & 0x0f);
1579 if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1580 pw5g->ofdm_diff[path][cnt] |=
1581 0xF0;
1582 }
1583 addr++;
1584 } else {
1585 if (hwinfo[addr] == 0xFF) {
1586 pw5g->bw40_diff[path][cnt] = 0xFE;
1587 } else {
1588 pw5g->bw40_diff[path][cnt] =
1589 (hwinfo[addr] & 0xf0) >> 4;
1590 if (pw5g->bw40_diff[path][cnt] & BIT(3))
1591 pw5g->bw40_diff[path][cnt] |= 0xF0;
1592 }
1593 if (hwinfo[addr] == 0xFF) {
1594 pw5g->bw20_diff[path][cnt] = 0xFE;
1595 } else {
1596 pw5g->bw20_diff[path][cnt] =
1597 (hwinfo[addr] & 0x0f);
1598 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1599 pw5g->bw20_diff[path][cnt] |= 0xF0;
1600 }
1601 addr++;
1602 }
1603 }
1604 if (hwinfo[addr] == 0xFF) {
1605 pw5g->ofdm_diff[path][1] = 0xFE;
1606 pw5g->ofdm_diff[path][2] = 0xFE;
1607 } else {
1608 pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1609 pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1610 }
1611 addr++;
1612
1613 if (hwinfo[addr] == 0xFF)
1614 pw5g->ofdm_diff[path][3] = 0xFE;
1615 else
1616 pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1617 addr++;
1618
1619 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1620 if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1621 pw5g->ofdm_diff[path][cnt] = 0xFE;
1622 else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1623 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1624 }
1625 }
1626 }
1627
1628 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1629 bool autoload_fail,
1630 u8 *hwinfo)
1631 {
1632 struct rtl_priv *rtlpriv = rtl_priv(hw);
1633 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1634 struct txpower_info_2g pw2g;
1635 struct txpower_info_5g pw5g;
1636 u8 rf_path, index;
1637 u8 i;
1638
1639 _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1640 hwinfo);
1641
1642 for (rf_path = 0; rf_path < 2; rf_path++) {
1643 for (i = 0; i < 14; i++) {
1644 index = _rtl8723be_get_chnl_group(i+1);
1645
1646 rtlefuse->txpwrlevel_cck[rf_path][i] =
1647 pw2g.index_cck_base[rf_path][index];
1648 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1649 pw2g.index_bw40_base[rf_path][index];
1650 }
1651 for (i = 0; i < MAX_TX_COUNT; i++) {
1652 rtlefuse->txpwr_ht20diff[rf_path][i] =
1653 pw2g.bw20_diff[rf_path][i];
1654 rtlefuse->txpwr_ht40diff[rf_path][i] =
1655 pw2g.bw40_diff[rf_path][i];
1656 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1657 pw2g.ofdm_diff[rf_path][i];
1658 }
1659 for (i = 0; i < 14; i++) {
1660 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1661 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = "
1662 "[0x%x / 0x%x ]\n", rf_path, i,
1663 rtlefuse->txpwrlevel_cck[rf_path][i],
1664 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1665 }
1666 }
1667 if (!autoload_fail)
1668 rtlefuse->eeprom_thermalmeter =
1669 hwinfo[EEPROM_THERMAL_METER_88E];
1670 else
1671 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1672
1673 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1674 rtlefuse->apk_thermalmeterignore = true;
1675 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1676 }
1677 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1678 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1679 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1680
1681 if (!autoload_fail) {
1682 rtlefuse->eeprom_regulatory =
1683 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1684 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1685 rtlefuse->eeprom_regulatory = 0;
1686 } else {
1687 rtlefuse->eeprom_regulatory = 0;
1688 }
1689 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1690 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1691 }
1692
1693 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
1694 bool pseudo_test)
1695 {
1696 struct rtl_priv *rtlpriv = rtl_priv(hw);
1697 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1698 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1699 u16 i, usvalue;
1700 u8 hwinfo[HWSET_MAX_SIZE];
1701 u16 eeprom_id;
1702 bool is_toshiba_smid1 = false;
1703 bool is_toshiba_smid2 = false;
1704 bool is_samsung_smid = false;
1705 bool is_lenovo_smid = false;
1706 u16 toshiba_smid1[] = {
1707 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
1708 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
1709 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
1710 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
1711 };
1712 u16 toshiba_smid2[] = {
1713 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
1714 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
1715 };
1716 u16 samsung_smid[] = {
1717 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
1718 0x8193, 0x9191, 0x9192, 0x9193
1719 };
1720 u16 lenovo_smid[] = {
1721 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
1722 };
1723
1724 if (pseudo_test) {
1725 /* needs to be added */
1726 return;
1727 }
1728 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1729 rtl_efuse_shadow_map_update(hw);
1730
1731 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1732 HWSET_MAX_SIZE);
1733 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1734 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1735 "RTL819X Not boot from eeprom, check it !!");
1736 }
1737 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1738 hwinfo, HWSET_MAX_SIZE);
1739
1740 eeprom_id = *((u16 *)&hwinfo[0]);
1741 if (eeprom_id != RTL8723BE_EEPROM_ID) {
1742 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1743 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1744 rtlefuse->autoload_failflag = true;
1745 } else {
1746 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1747 rtlefuse->autoload_failflag = false;
1748 }
1749 if (rtlefuse->autoload_failflag)
1750 return;
1751
1752 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1753 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1754 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1755 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1756 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1757 "EEPROMId = 0x%4x\n", eeprom_id);
1758 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1759 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1760 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1761 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1762 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1763 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1764 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1765 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1766
1767 for (i = 0; i < 6; i += 2) {
1768 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1769 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1770 }
1771 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "dev_addr: %pM\n",
1772 rtlefuse->dev_addr);
1773
1774 /*parse xtal*/
1775 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
1776 if (rtlefuse->crystalcap == 0xFF)
1777 rtlefuse->crystalcap = 0x20;
1778
1779 _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1780 hwinfo);
1781
1782 rtl8723be_read_bt_coexist_info_from_hwpg(hw,
1783 rtlefuse->autoload_failflag,
1784 hwinfo);
1785
1786 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1787 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1788 rtlefuse->txpwr_fromeprom = true;
1789 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1790
1791 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1792 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1793
1794 /* set channel plan to world wide 13 */
1795 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1796
1797 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1798 /* Does this one have a Toshiba SMID from group 1? */
1799 for (i = 0; i < sizeof(toshiba_smid1) / sizeof(u16); i++) {
1800 if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
1801 is_toshiba_smid1 = true;
1802 break;
1803 }
1804 }
1805 /* Does this one have a Toshiba SMID from group 2? */
1806 for (i = 0; i < sizeof(toshiba_smid2) / sizeof(u16); i++) {
1807 if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
1808 is_toshiba_smid2 = true;
1809 break;
1810 }
1811 }
1812 /* Does this one have a Samsung SMID? */
1813 for (i = 0; i < sizeof(samsung_smid) / sizeof(u16); i++) {
1814 if (rtlefuse->eeprom_smid == samsung_smid[i]) {
1815 is_samsung_smid = true;
1816 break;
1817 }
1818 }
1819 /* Does this one have a Lenovo SMID? */
1820 for (i = 0; i < sizeof(lenovo_smid) / sizeof(u16); i++) {
1821 if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
1822 is_lenovo_smid = true;
1823 break;
1824 }
1825 }
1826 switch (rtlefuse->eeprom_oemid) {
1827 case EEPROM_CID_DEFAULT:
1828 if (rtlefuse->eeprom_did == 0x8176) {
1829 if (rtlefuse->eeprom_svid == 0x10EC &&
1830 is_toshiba_smid1) {
1831 rtlhal->oem_id = RT_CID_TOSHIBA;
1832 } else if (rtlefuse->eeprom_svid == 0x1025) {
1833 rtlhal->oem_id = RT_CID_819X_ACER;
1834 } else if (rtlefuse->eeprom_svid == 0x10EC &&
1835 is_samsung_smid) {
1836 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
1837 } else if (rtlefuse->eeprom_svid == 0x10EC &&
1838 is_lenovo_smid) {
1839 rtlhal->oem_id = RT_CID_819X_LENOVO;
1840 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1841 rtlefuse->eeprom_smid == 0x8197) ||
1842 (rtlefuse->eeprom_svid == 0x10EC &&
1843 rtlefuse->eeprom_smid == 0x9196)) {
1844 rtlhal->oem_id = RT_CID_819X_CLEVO;
1845 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
1846 rtlefuse->eeprom_smid == 0x8194) ||
1847 (rtlefuse->eeprom_svid == 0x1028 &&
1848 rtlefuse->eeprom_smid == 0x8198) ||
1849 (rtlefuse->eeprom_svid == 0x1028 &&
1850 rtlefuse->eeprom_smid == 0x9197) ||
1851 (rtlefuse->eeprom_svid == 0x1028 &&
1852 rtlefuse->eeprom_smid == 0x9198)) {
1853 rtlhal->oem_id = RT_CID_819X_DELL;
1854 } else if ((rtlefuse->eeprom_svid == 0x103C &&
1855 rtlefuse->eeprom_smid == 0x1629)) {
1856 rtlhal->oem_id = RT_CID_819X_HP;
1857 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
1858 rtlefuse->eeprom_smid == 0x2315)) {
1859 rtlhal->oem_id = RT_CID_819X_QMI;
1860 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1861 rtlefuse->eeprom_smid == 0x8203)) {
1862 rtlhal->oem_id = RT_CID_819X_PRONETS;
1863 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
1864 rtlefuse->eeprom_smid == 0x84B5)) {
1865 rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
1866 } else {
1867 rtlhal->oem_id = RT_CID_DEFAULT;
1868 }
1869 } else if (rtlefuse->eeprom_did == 0x8178) {
1870 if (rtlefuse->eeprom_svid == 0x10EC &&
1871 is_toshiba_smid2)
1872 rtlhal->oem_id = RT_CID_TOSHIBA;
1873 else if (rtlefuse->eeprom_svid == 0x1025)
1874 rtlhal->oem_id = RT_CID_819X_ACER;
1875 else if ((rtlefuse->eeprom_svid == 0x10EC &&
1876 rtlefuse->eeprom_smid == 0x8186))
1877 rtlhal->oem_id = RT_CID_819X_PRONETS;
1878 else if ((rtlefuse->eeprom_svid == 0x1043 &&
1879 rtlefuse->eeprom_smid == 0x84B6))
1880 rtlhal->oem_id =
1881 RT_CID_819X_EDIMAX_ASUS;
1882 else
1883 rtlhal->oem_id = RT_CID_DEFAULT;
1884 } else {
1885 rtlhal->oem_id = RT_CID_DEFAULT;
1886 }
1887 break;
1888 case EEPROM_CID_TOSHIBA:
1889 rtlhal->oem_id = RT_CID_TOSHIBA;
1890 break;
1891 case EEPROM_CID_CCX:
1892 rtlhal->oem_id = RT_CID_CCX;
1893 break;
1894 case EEPROM_CID_QMI:
1895 rtlhal->oem_id = RT_CID_819X_QMI;
1896 break;
1897 case EEPROM_CID_WHQL:
1898 break;
1899 default:
1900 rtlhal->oem_id = RT_CID_DEFAULT;
1901 break;
1902 }
1903 }
1904 }
1905
1906 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
1907 {
1908 struct rtl_priv *rtlpriv = rtl_priv(hw);
1909 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1911
1912 pcipriv->ledctl.led_opendrain = true;
1913 switch (rtlhal->oem_id) {
1914 case RT_CID_819X_HP:
1915 pcipriv->ledctl.led_opendrain = true;
1916 break;
1917 case RT_CID_819X_LENOVO:
1918 case RT_CID_DEFAULT:
1919 case RT_CID_TOSHIBA:
1920 case RT_CID_CCX:
1921 case RT_CID_819X_ACER:
1922 case RT_CID_WHQL:
1923 default:
1924 break;
1925 }
1926 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1927 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1928 }
1929
1930 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
1931 {
1932 struct rtl_priv *rtlpriv = rtl_priv(hw);
1933 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1934 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1936 u8 tmp_u1b;
1937
1938 rtlhal->version = _rtl8723be_read_chip_version(hw);
1939 if (get_rf_type(rtlphy) == RF_1T1R)
1940 rtlpriv->dm.rfpath_rxenable[0] = true;
1941 else
1942 rtlpriv->dm.rfpath_rxenable[0] =
1943 rtlpriv->dm.rfpath_rxenable[1] = true;
1944 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1945 rtlhal->version);
1946 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1947 if (tmp_u1b & BIT(4)) {
1948 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1949 rtlefuse->epromtype = EEPROM_93C46;
1950 } else {
1951 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1952 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1953 }
1954 if (tmp_u1b & BIT(5)) {
1955 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1956 rtlefuse->autoload_failflag = false;
1957 _rtl8723be_read_adapter_info(hw, false);
1958 } else {
1959 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1960 }
1961 _rtl8723be_hal_customized_behavior(hw);
1962 }
1963
1964 static void rtl8723be_update_hal_rate_table(struct ieee80211_hw *hw,
1965 struct ieee80211_sta *sta)
1966 {
1967 struct rtl_priv *rtlpriv = rtl_priv(hw);
1968 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1969 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1970 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1971 u32 ratr_value;
1972 u8 ratr_index = 0;
1973 u8 nmode = mac->ht_enable;
1974 u8 mimo_ps = IEEE80211_SMPS_OFF;
1975 u16 shortgi_rate;
1976 u32 tmp_ratr_value;
1977 u8 curtxbw_40mhz = mac->bw_40;
1978 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1979 1 : 0;
1980 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1981 1 : 0;
1982 enum wireless_mode wirelessmode = mac->mode;
1983
1984 if (rtlhal->current_bandtype == BAND_ON_5G)
1985 ratr_value = sta->supp_rates[1] << 4;
1986 else
1987 ratr_value = sta->supp_rates[0];
1988 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1989 ratr_value = 0xfff;
1990 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1991 sta->ht_cap.mcs.rx_mask[0] << 12);
1992 switch (wirelessmode) {
1993 case WIRELESS_MODE_B:
1994 if (ratr_value & 0x0000000c)
1995 ratr_value &= 0x0000000d;
1996 else
1997 ratr_value &= 0x0000000f;
1998 break;
1999 case WIRELESS_MODE_G:
2000 ratr_value &= 0x00000FF5;
2001 break;
2002 case WIRELESS_MODE_N_24G:
2003 case WIRELESS_MODE_N_5G:
2004 nmode = 1;
2005 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2006 ratr_value &= 0x0007F005;
2007 } else {
2008 u32 ratr_mask;
2009
2010 if (get_rf_type(rtlphy) == RF_1T2R ||
2011 get_rf_type(rtlphy) == RF_1T1R)
2012 ratr_mask = 0x000ff005;
2013 else
2014 ratr_mask = 0x0f0ff005;
2015 ratr_value &= ratr_mask;
2016 }
2017 break;
2018 default:
2019 if (rtlphy->rf_type == RF_1T2R)
2020 ratr_value &= 0x000ff0ff;
2021 else
2022 ratr_value &= 0x0f0ff0ff;
2023 break;
2024 }
2025 if ((rtlpriv->btcoexist.bt_coexistence) &&
2026 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2027 (rtlpriv->btcoexist.bt_cur_state) &&
2028 (rtlpriv->btcoexist.bt_ant_isolation) &&
2029 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2030 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2031 ratr_value &= 0x0fffcfc0;
2032 else
2033 ratr_value &= 0x0FFFFFFF;
2034
2035 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2036 (!curtxbw_40mhz && curshortgi_20mhz))) {
2037 ratr_value |= 0x10000000;
2038 tmp_ratr_value = (ratr_value >> 12);
2039
2040 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2041 if ((1 << shortgi_rate) & tmp_ratr_value)
2042 break;
2043 }
2044 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2045 (shortgi_rate << 4) | (shortgi_rate);
2046 }
2047 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2048
2049 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2050 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2051 }
2052
2053 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2054 u8 rate_index)
2055 {
2056 u8 ret = 0;
2057
2058 switch (rate_index) {
2059 case RATR_INX_WIRELESS_NGB:
2060 ret = 1;
2061 break;
2062 case RATR_INX_WIRELESS_N:
2063 case RATR_INX_WIRELESS_NG:
2064 ret = 5;
2065 break;
2066 case RATR_INX_WIRELESS_NB:
2067 ret = 3;
2068 break;
2069 case RATR_INX_WIRELESS_GB:
2070 ret = 6;
2071 break;
2072 case RATR_INX_WIRELESS_G:
2073 ret = 7;
2074 break;
2075 case RATR_INX_WIRELESS_B:
2076 ret = 8;
2077 break;
2078 default:
2079 ret = 0;
2080 break;
2081 }
2082 return ret;
2083 }
2084
2085 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2086 struct ieee80211_sta *sta,
2087 u8 rssi_level)
2088 {
2089 struct rtl_priv *rtlpriv = rtl_priv(hw);
2090 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2091 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2092 struct rtl_sta_info *sta_entry = NULL;
2093 u32 ratr_bitmap;
2094 u8 ratr_index;
2095 u8 curtxbw_40mhz = (sta->ht_cap.cap &
2096 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2097 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2098 1 : 0;
2099 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2100 1 : 0;
2101 enum wireless_mode wirelessmode = 0;
2102 bool shortgi = false;
2103 u8 rate_mask[7];
2104 u8 macid = 0;
2105 u8 mimo_ps = IEEE80211_SMPS_OFF;
2106
2107 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2108 wirelessmode = sta_entry->wireless_mode;
2109 if (mac->opmode == NL80211_IFTYPE_STATION ||
2110 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2111 curtxbw_40mhz = mac->bw_40;
2112 else if (mac->opmode == NL80211_IFTYPE_AP ||
2113 mac->opmode == NL80211_IFTYPE_ADHOC)
2114 macid = sta->aid + 1;
2115
2116 ratr_bitmap = sta->supp_rates[0];
2117
2118 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2119 ratr_bitmap = 0xfff;
2120
2121 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2122 sta->ht_cap.mcs.rx_mask[0] << 12);
2123 switch (wirelessmode) {
2124 case WIRELESS_MODE_B:
2125 ratr_index = RATR_INX_WIRELESS_B;
2126 if (ratr_bitmap & 0x0000000c)
2127 ratr_bitmap &= 0x0000000d;
2128 else
2129 ratr_bitmap &= 0x0000000f;
2130 break;
2131 case WIRELESS_MODE_G:
2132 ratr_index = RATR_INX_WIRELESS_GB;
2133
2134 if (rssi_level == 1)
2135 ratr_bitmap &= 0x00000f00;
2136 else if (rssi_level == 2)
2137 ratr_bitmap &= 0x00000ff0;
2138 else
2139 ratr_bitmap &= 0x00000ff5;
2140 break;
2141 case WIRELESS_MODE_A:
2142 ratr_index = RATR_INX_WIRELESS_A;
2143 ratr_bitmap &= 0x00000ff0;
2144 break;
2145 case WIRELESS_MODE_N_24G:
2146 case WIRELESS_MODE_N_5G:
2147 ratr_index = RATR_INX_WIRELESS_NGB;
2148
2149 if (mimo_ps == IEEE80211_SMPS_STATIC ||
2150 mimo_ps == IEEE80211_SMPS_DYNAMIC) {
2151 if (rssi_level == 1)
2152 ratr_bitmap &= 0x00070000;
2153 else if (rssi_level == 2)
2154 ratr_bitmap &= 0x0007f000;
2155 else
2156 ratr_bitmap &= 0x0007f005;
2157 } else {
2158 if (rtlphy->rf_type == RF_1T1R) {
2159 if (curtxbw_40mhz) {
2160 if (rssi_level == 1)
2161 ratr_bitmap &= 0x000f0000;
2162 else if (rssi_level == 2)
2163 ratr_bitmap &= 0x000ff000;
2164 else
2165 ratr_bitmap &= 0x000ff015;
2166 } else {
2167 if (rssi_level == 1)
2168 ratr_bitmap &= 0x000f0000;
2169 else if (rssi_level == 2)
2170 ratr_bitmap &= 0x000ff000;
2171 else
2172 ratr_bitmap &= 0x000ff005;
2173 }
2174 } else {
2175 if (curtxbw_40mhz) {
2176 if (rssi_level == 1)
2177 ratr_bitmap &= 0x0f8f0000;
2178 else if (rssi_level == 2)
2179 ratr_bitmap &= 0x0f8ff000;
2180 else
2181 ratr_bitmap &= 0x0f8ff015;
2182 } else {
2183 if (rssi_level == 1)
2184 ratr_bitmap &= 0x0f8f0000;
2185 else if (rssi_level == 2)
2186 ratr_bitmap &= 0x0f8ff000;
2187 else
2188 ratr_bitmap &= 0x0f8ff005;
2189 }
2190 }
2191 }
2192 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2193 (!curtxbw_40mhz && curshortgi_20mhz)) {
2194 if (macid == 0)
2195 shortgi = true;
2196 else if (macid == 1)
2197 shortgi = false;
2198 }
2199 break;
2200 default:
2201 ratr_index = RATR_INX_WIRELESS_NGB;
2202
2203 if (rtlphy->rf_type == RF_1T2R)
2204 ratr_bitmap &= 0x000ff0ff;
2205 else
2206 ratr_bitmap &= 0x0f0ff0ff;
2207 break;
2208 }
2209 sta_entry->ratr_index = ratr_index;
2210
2211 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2212 "ratr_bitmap :%x\n", ratr_bitmap);
2213 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2214 rate_mask[0] = macid;
2215 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2216 (shortgi ? 0x80 : 0x00);
2217 rate_mask[2] = curtxbw_40mhz;
2218 /* if (prox_priv->proxim_modeinfo->power_output > 0)
2219 * rate_mask[2] |= BIT(6);
2220 */
2221
2222 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2223 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2224 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2225 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2226
2227 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2228 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2229 ratr_index, ratr_bitmap,
2230 rate_mask[0], rate_mask[1],
2231 rate_mask[2], rate_mask[3],
2232 rate_mask[4], rate_mask[5],
2233 rate_mask[6]);
2234 rtl8723be_fill_h2c_cmd(hw, H2C_8723BE_RA_MASK, 7, rate_mask);
2235 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2236 }
2237
2238 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2239 struct ieee80211_sta *sta,
2240 u8 rssi_level)
2241 {
2242 struct rtl_priv *rtlpriv = rtl_priv(hw);
2243 if (rtlpriv->dm.useramask)
2244 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level);
2245 else
2246 rtl8723be_update_hal_rate_table(hw, sta);
2247 }
2248
2249 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2250 {
2251 struct rtl_priv *rtlpriv = rtl_priv(hw);
2252 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2253 u16 sifs_timer;
2254
2255 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2256 (u8 *)&mac->slot_time);
2257 if (!mac->ht_enable)
2258 sifs_timer = 0x0a0a;
2259 else
2260 sifs_timer = 0x0e0e;
2261 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2262 }
2263
2264 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2265 {
2266 struct rtl_priv *rtlpriv = rtl_priv(hw);
2267 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2268 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2269 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2270 u8 u1tmp;
2271 bool actuallyset = false;
2272
2273 if (rtlpriv->rtlhal.being_init_adapter)
2274 return false;
2275
2276 if (ppsc->swrf_processing)
2277 return false;
2278
2279 spin_lock(&rtlpriv->locks.rf_ps_lock);
2280 if (ppsc->rfchange_inprogress) {
2281 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2282 return false;
2283 } else {
2284 ppsc->rfchange_inprogress = true;
2285 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2286 }
2287 cur_rfstate = ppsc->rfpwr_state;
2288
2289 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2290 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2291
2292 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2293
2294 if (rtlphy->polarity_ctl)
2295 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2296 else
2297 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2298
2299 if (ppsc->hwradiooff &&
2300 (e_rfpowerstate_toset == ERFON)) {
2301 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2302 "GPIOChangeRF - HW Radio ON, RF ON\n");
2303
2304 e_rfpowerstate_toset = ERFON;
2305 ppsc->hwradiooff = false;
2306 actuallyset = true;
2307 } else if (!ppsc->hwradiooff &&
2308 (e_rfpowerstate_toset == ERFOFF)) {
2309 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2310 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2311
2312 e_rfpowerstate_toset = ERFOFF;
2313 ppsc->hwradiooff = true;
2314 actuallyset = true;
2315 }
2316 if (actuallyset) {
2317 spin_lock(&rtlpriv->locks.rf_ps_lock);
2318 ppsc->rfchange_inprogress = false;
2319 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2320 } else {
2321 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2322 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2323
2324 spin_lock(&rtlpriv->locks.rf_ps_lock);
2325 ppsc->rfchange_inprogress = false;
2326 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2327 }
2328 *valid = 1;
2329 return !ppsc->hwradiooff;
2330 }
2331
2332 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2333 u8 *p_macaddr, bool is_group, u8 enc_algo,
2334 bool is_wepkey, bool clear_all)
2335 {
2336 struct rtl_priv *rtlpriv = rtl_priv(hw);
2337 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2338 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2339 u8 *macaddr = p_macaddr;
2340 u32 entry_id = 0;
2341 bool is_pairwise = false;
2342
2343 static u8 cam_const_addr[4][6] = {
2344 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2345 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2346 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2347 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2348 };
2349 static u8 cam_const_broad[] = {
2350 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2351 };
2352
2353 if (clear_all) {
2354 u8 idx = 0;
2355 u8 cam_offset = 0;
2356 u8 clear_number = 5;
2357
2358 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2359
2360 for (idx = 0; idx < clear_number; idx++) {
2361 rtl_cam_mark_invalid(hw, cam_offset + idx);
2362 rtl_cam_empty_entry(hw, cam_offset + idx);
2363
2364 if (idx < 5) {
2365 memset(rtlpriv->sec.key_buf[idx], 0,
2366 MAX_KEY_LEN);
2367 rtlpriv->sec.key_len[idx] = 0;
2368 }
2369 }
2370 } else {
2371 switch (enc_algo) {
2372 case WEP40_ENCRYPTION:
2373 enc_algo = CAM_WEP40;
2374 break;
2375 case WEP104_ENCRYPTION:
2376 enc_algo = CAM_WEP104;
2377 break;
2378 case TKIP_ENCRYPTION:
2379 enc_algo = CAM_TKIP;
2380 break;
2381 case AESCCMP_ENCRYPTION:
2382 enc_algo = CAM_AES;
2383 break;
2384 default:
2385 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2386 "switch case not process\n");
2387 enc_algo = CAM_TKIP;
2388 break;
2389 }
2390
2391 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2392 macaddr = cam_const_addr[key_index];
2393 entry_id = key_index;
2394 } else {
2395 if (is_group) {
2396 macaddr = cam_const_broad;
2397 entry_id = key_index;
2398 } else {
2399 if (mac->opmode == NL80211_IFTYPE_AP) {
2400 entry_id = rtl_cam_get_free_entry(hw,
2401 p_macaddr);
2402 if (entry_id >= TOTAL_CAM_ENTRY) {
2403 RT_TRACE(rtlpriv, COMP_SEC,
2404 DBG_EMERG,
2405 "Can not find free"
2406 " hw security cam "
2407 "entry\n");
2408 return;
2409 }
2410 } else {
2411 entry_id = CAM_PAIRWISE_KEY_POSITION;
2412 }
2413 key_index = PAIRWISE_KEYIDX;
2414 is_pairwise = true;
2415 }
2416 }
2417 if (rtlpriv->sec.key_len[key_index] == 0) {
2418 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2419 "delete one entry, entry_id is %d\n",
2420 entry_id);
2421 if (mac->opmode == NL80211_IFTYPE_AP)
2422 rtl_cam_del_entry(hw, p_macaddr);
2423 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2424 } else {
2425 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2426 "add one entry\n");
2427 if (is_pairwise) {
2428 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2429 "set Pairwise key\n");
2430
2431 rtl_cam_add_one_entry(hw, macaddr, key_index,
2432 entry_id, enc_algo,
2433 CAM_CONFIG_NO_USEDK,
2434 rtlpriv->sec.key_buf[key_index]);
2435 } else {
2436 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2437 "set group key\n");
2438
2439 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2440 rtl_cam_add_one_entry(hw,
2441 rtlefuse->dev_addr,
2442 PAIRWISE_KEYIDX,
2443 CAM_PAIRWISE_KEY_POSITION,
2444 enc_algo,
2445 CAM_CONFIG_NO_USEDK,
2446 rtlpriv->sec.key_buf
2447 [entry_id]);
2448 }
2449 rtl_cam_add_one_entry(hw, macaddr, key_index,
2450 entry_id, enc_algo,
2451 CAM_CONFIG_NO_USEDK,
2452 rtlpriv->sec.key_buf[entry_id]);
2453 }
2454 }
2455 }
2456 }
2457
2458 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2459 bool auto_load_fail, u8 *hwinfo)
2460 {
2461 struct rtl_priv *rtlpriv = rtl_priv(hw);
2462 u8 value;
2463 u32 tmpu_32;
2464
2465 if (!auto_load_fail) {
2466 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2467 if (tmpu_32 & BIT(18))
2468 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2469 else
2470 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2471 value = hwinfo[RF_OPTION4];
2472 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2473 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2474 } else {
2475 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2476 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2477 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2478 }
2479 }
2480
2481 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2482 {
2483 struct rtl_priv *rtlpriv = rtl_priv(hw);
2484
2485 /* 0:Low, 1:High, 2:From Efuse. */
2486 rtlpriv->btcoexist.reg_bt_iso = 2;
2487 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2488 rtlpriv->btcoexist.reg_bt_sco = 3;
2489 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2490 rtlpriv->btcoexist.reg_bt_sco = 0;
2491 }
2492
2493 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2494 {
2495 struct rtl_priv *rtlpriv = rtl_priv(hw);
2496
2497 if (rtlpriv->cfg->ops->get_btc_status())
2498 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2499 }
2500
2501 void rtl8723be_suspend(struct ieee80211_hw *hw)
2502 {
2503 }
2504
2505 void rtl8723be_resume(struct ieee80211_hw *hw)
2506 {
2507 }
2508
2509 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2510 void rtl8723be_allow_all_destaddr(struct ieee80211_hw *hw, bool allow_all_da,
2511 bool write_into_reg)
2512 {
2513 struct rtl_priv *rtlpriv = rtl_priv(hw);
2514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2515
2516 if (allow_all_da) /* Set BIT0 */
2517 rtlpci->receive_config |= RCR_AAP;
2518 else /* Clear BIT0 */
2519 rtlpci->receive_config &= ~RCR_AAP;
2520
2521 if (write_into_reg)
2522 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2523
2524 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2525 "receive_config = 0x%08X, write_into_reg =%d\n",
2526 rtlpci->receive_config, write_into_reg);
2527 }
Linux kernel - Deliverables
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