drivers/net/wireless/rtlwifi/wifi.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_WIFI_H__
  31 #define __RTL_WIFI_H__
  32
  33 #include <linux/sched.h>
  34 #include <linux/firmware.h>
  35 #include <linux/version.h>
  36 #include <linux/etherdevice.h>
  37 #include <net/mac80211.h>
  38 #include "debug.h"
  39
  40 #define RF_CHANGE_BY_INIT                       0
  41 #define RF_CHANGE_BY_IPS                        BIT(28)
  42 #define RF_CHANGE_BY_PS                         BIT(29)
  43 #define RF_CHANGE_BY_HW                         BIT(30)
  44 #define RF_CHANGE_BY_SW                         BIT(31)
  45
  46 #define IQK_ADDA_REG_NUM                        16
  47 #define IQK_MAC_REG_NUM                         4
  48
  49 #define MAX_KEY_LEN                             61
  50 #define KEY_BUF_SIZE                            5
  51
  52 /* QoS related. */
  53 /*aci: 0x00     Best Effort*/
  54 /*aci: 0x01     Background*/
  55 /*aci: 0x10     Video*/
  56 /*aci: 0x11     Voice*/
  57 /*Max: define total number.*/
  58 #define AC0_BE                                  0
  59 #define AC1_BK                                  1
  60 #define AC2_VI                                  2
  61 #define AC3_VO                                  3
  62 #define AC_MAX                                  4
  63 #define QOS_QUEUE_NUM                           4
  64 #define RTL_MAC80211_NUM_QUEUE                  5
  65
  66 #define QBSS_LOAD_SIZE                          5
  67 #define MAX_WMMELE_LENGTH                       64
  68
  69 /*slot time for 11g. */
  70 #define RTL_SLOT_TIME_9                         9
  71 #define RTL_SLOT_TIME_20                        20
  72
  73 /*related with tcp/ip. */
  74 /*if_ehther.h*/
  75 #define ETH_P_PAE               0x888E  /*Port Access Entity (IEEE 802.1X) */
  76 #define ETH_P_IP                0x0800  /*Internet Protocol packet */
  77 #define ETH_P_ARP               0x0806  /*Address Resolution packet */
  78 #define SNAP_SIZE               6
  79 #define PROTOC_TYPE_SIZE        2
  80
  81 /*related with 802.11 frame*/
  82 #define MAC80211_3ADDR_LEN                      24
  83 #define MAC80211_4ADDR_LEN                      30
  84
  85 enum intf_type {
  86         INTF_PCI = 0,
  87         INTF_USB = 1,
  88 };
  89
  90 enum radio_path {
  91         RF90_PATH_A = 0,
  92         RF90_PATH_B = 1,
  93         RF90_PATH_C = 2,
  94         RF90_PATH_D = 3,
  95 };
  96
  97 enum rt_eeprom_type {
  98         EEPROM_93C46,
  99         EEPROM_93C56,
 100         EEPROM_BOOT_EFUSE,
 101 };
 102
 103 enum rtl_status {
 104         RTL_STATUS_INTERFACE_START = 0,
 105 };
 106
 107 enum hardware_type {
 108         HARDWARE_TYPE_RTL8192E,
 109         HARDWARE_TYPE_RTL8192U,
 110         HARDWARE_TYPE_RTL8192SE,
 111         HARDWARE_TYPE_RTL8192SU,
 112         HARDWARE_TYPE_RTL8192CE,
 113         HARDWARE_TYPE_RTL8192CU,
 114         HARDWARE_TYPE_RTL8192DE,
 115         HARDWARE_TYPE_RTL8192DU,
 116
 117         /*keep it last*/
 118         HARDWARE_TYPE_NUM
 119 };
 120
 121 enum scan_operation_backup_opt {
 122         SCAN_OPT_BACKUP = 0,
 123         SCAN_OPT_RESTORE,
 124         SCAN_OPT_MAX
 125 };
 126
 127 /*RF state.*/
 128 enum rf_pwrstate {
 129         ERFON,
 130         ERFSLEEP,
 131         ERFOFF
 132 };
 133
 134 struct bb_reg_def {
 135         u32 rfintfs;
 136         u32 rfintfi;
 137         u32 rfintfo;
 138         u32 rfintfe;
 139         u32 rf3wire_offset;
 140         u32 rflssi_select;
 141         u32 rftxgain_stage;
 142         u32 rfhssi_para1;
 143         u32 rfhssi_para2;
 144         u32 rfswitch_control;
 145         u32 rfagc_control1;
 146         u32 rfagc_control2;
 147         u32 rfrxiq_imbalance;
 148         u32 rfrx_afe;
 149         u32 rftxiq_imbalance;
 150         u32 rftx_afe;
 151         u32 rflssi_readback;
 152         u32 rflssi_readbackpi;
 153 };
 154
 155 enum io_type {
 156         IO_CMD_PAUSE_DM_BY_SCAN = 0,
 157         IO_CMD_RESUME_DM_BY_SCAN = 1,
 158 };
 159
 160 enum hw_variables {
 161         HW_VAR_ETHER_ADDR,
 162         HW_VAR_MULTICAST_REG,
 163         HW_VAR_BASIC_RATE,
 164         HW_VAR_BSSID,
 165         HW_VAR_MEDIA_STATUS,
 166         HW_VAR_SECURITY_CONF,
 167         HW_VAR_BEACON_INTERVAL,
 168         HW_VAR_ATIM_WINDOW,
 169         HW_VAR_LISTEN_INTERVAL,
 170         HW_VAR_CS_COUNTER,
 171         HW_VAR_DEFAULTKEY0,
 172         HW_VAR_DEFAULTKEY1,
 173         HW_VAR_DEFAULTKEY2,
 174         HW_VAR_DEFAULTKEY3,
 175         HW_VAR_SIFS,
 176         HW_VAR_DIFS,
 177         HW_VAR_EIFS,
 178         HW_VAR_SLOT_TIME,
 179         HW_VAR_ACK_PREAMBLE,
 180         HW_VAR_CW_CONFIG,
 181         HW_VAR_CW_VALUES,
 182         HW_VAR_RATE_FALLBACK_CONTROL,
 183         HW_VAR_CONTENTION_WINDOW,
 184         HW_VAR_RETRY_COUNT,
 185         HW_VAR_TR_SWITCH,
 186         HW_VAR_COMMAND,
 187         HW_VAR_WPA_CONFIG,
 188         HW_VAR_AMPDU_MIN_SPACE,
 189         HW_VAR_SHORTGI_DENSITY,
 190         HW_VAR_AMPDU_FACTOR,
 191         HW_VAR_MCS_RATE_AVAILABLE,
 192         HW_VAR_AC_PARAM,
 193         HW_VAR_ACM_CTRL,
 194         HW_VAR_DIS_Req_Qsize,
 195         HW_VAR_CCX_CHNL_LOAD,
 196         HW_VAR_CCX_NOISE_HISTOGRAM,
 197         HW_VAR_CCX_CLM_NHM,
 198         HW_VAR_TxOPLimit,
 199         HW_VAR_TURBO_MODE,
 200         HW_VAR_RF_STATE,
 201         HW_VAR_RF_OFF_BY_HW,
 202         HW_VAR_BUS_SPEED,
 203         HW_VAR_SET_DEV_POWER,
 204
 205         HW_VAR_RCR,
 206         HW_VAR_RATR_0,
 207         HW_VAR_RRSR,
 208         HW_VAR_CPU_RST,
 209         HW_VAR_CECHK_BSSID,
 210         HW_VAR_LBK_MODE,
 211         HW_VAR_AES_11N_FIX,
 212         HW_VAR_USB_RX_AGGR,
 213         HW_VAR_USER_CONTROL_TURBO_MODE,
 214         HW_VAR_RETRY_LIMIT,
 215         HW_VAR_INIT_TX_RATE,
 216         HW_VAR_TX_RATE_REG,
 217         HW_VAR_EFUSE_USAGE,
 218         HW_VAR_EFUSE_BYTES,
 219         HW_VAR_AUTOLOAD_STATUS,
 220         HW_VAR_RF_2R_DISABLE,
 221         HW_VAR_SET_RPWM,
 222         HW_VAR_H2C_FW_PWRMODE,
 223         HW_VAR_H2C_FW_JOINBSSRPT,
 224         HW_VAR_FW_PSMODE_STATUS,
 225         HW_VAR_1X1_RECV_COMBINE,
 226         HW_VAR_STOP_SEND_BEACON,
 227         HW_VAR_TSF_TIMER,
 228         HW_VAR_IO_CMD,
 229
 230         HW_VAR_RF_RECOVERY,
 231         HW_VAR_H2C_FW_UPDATE_GTK,
 232         HW_VAR_WF_MASK,
 233         HW_VAR_WF_CRC,
 234         HW_VAR_WF_IS_MAC_ADDR,
 235         HW_VAR_H2C_FW_OFFLOAD,
 236         HW_VAR_RESET_WFCRC,
 237
 238         HW_VAR_HANDLE_FW_C2H,
 239         HW_VAR_DL_FW_RSVD_PAGE,
 240         HW_VAR_AID,
 241         HW_VAR_HW_SEQ_ENABLE,
 242         HW_VAR_CORRECT_TSF,
 243         HW_VAR_BCN_VALID,
 244         HW_VAR_FWLPS_RF_ON,
 245         HW_VAR_DUAL_TSF_RST,
 246         HW_VAR_SWITCH_EPHY_WoWLAN,
 247         HW_VAR_INT_MIGRATION,
 248         HW_VAR_INT_AC,
 249         HW_VAR_RF_TIMING,
 250
 251         HW_VAR_MRC,
 252
 253         HW_VAR_MGT_FILTER,
 254         HW_VAR_CTRL_FILTER,
 255         HW_VAR_DATA_FILTER,
 256 };
 257
 258 enum _RT_MEDIA_STATUS {
 259         RT_MEDIA_DISCONNECT = 0,
 260         RT_MEDIA_CONNECT = 1
 261 };
 262
 263 enum rt_oem_id {
 264         RT_CID_DEFAULT = 0,
 265         RT_CID_8187_ALPHA0 = 1,
 266         RT_CID_8187_SERCOMM_PS = 2,
 267         RT_CID_8187_HW_LED = 3,
 268         RT_CID_8187_NETGEAR = 4,
 269         RT_CID_WHQL = 5,
 270         RT_CID_819x_CAMEO = 6,
 271         RT_CID_819x_RUNTOP = 7,
 272         RT_CID_819x_Senao = 8,
 273         RT_CID_TOSHIBA = 9,
 274         RT_CID_819x_Netcore = 10,
 275         RT_CID_Nettronix = 11,
 276         RT_CID_DLINK = 12,
 277         RT_CID_PRONET = 13,
 278         RT_CID_COREGA = 14,
 279         RT_CID_819x_ALPHA = 15,
 280         RT_CID_819x_Sitecom = 16,
 281         RT_CID_CCX = 17,
 282         RT_CID_819x_Lenovo = 18,
 283         RT_CID_819x_QMI = 19,
 284         RT_CID_819x_Edimax_Belkin = 20,
 285         RT_CID_819x_Sercomm_Belkin = 21,
 286         RT_CID_819x_CAMEO1 = 22,
 287         RT_CID_819x_MSI = 23,
 288         RT_CID_819x_Acer = 24,
 289         RT_CID_819x_HP = 27,
 290         RT_CID_819x_CLEVO = 28,
 291         RT_CID_819x_Arcadyan_Belkin = 29,
 292         RT_CID_819x_SAMSUNG = 30,
 293         RT_CID_819x_WNC_COREGA = 31,
 294         RT_CID_819x_Foxcoon = 32,
 295         RT_CID_819x_DELL = 33,
 296 };
 297
 298 enum hw_descs {
 299         HW_DESC_OWN,
 300         HW_DESC_RXOWN,
 301         HW_DESC_TX_NEXTDESC_ADDR,
 302         HW_DESC_TXBUFF_ADDR,
 303         HW_DESC_RXBUFF_ADDR,
 304         HW_DESC_RXPKT_LEN,
 305         HW_DESC_RXERO,
 306 };
 307
 308 enum prime_sc {
 309         PRIME_CHNL_OFFSET_DONT_CARE = 0,
 310         PRIME_CHNL_OFFSET_LOWER = 1,
 311         PRIME_CHNL_OFFSET_UPPER = 2,
 312 };
 313
 314 enum rf_type {
 315         RF_1T1R = 0,
 316         RF_1T2R = 1,
 317         RF_2T2R = 2,
 318 };
 319
 320 enum ht_channel_width {
 321         HT_CHANNEL_WIDTH_20 = 0,
 322         HT_CHANNEL_WIDTH_20_40 = 1,
 323 };
 324
 325 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
 326 Cipher Suites Encryption Algorithms */
 327 enum rt_enc_alg {
 328         NO_ENCRYPTION = 0,
 329         WEP40_ENCRYPTION = 1,
 330         TKIP_ENCRYPTION = 2,
 331         RSERVED_ENCRYPTION = 3,
 332         AESCCMP_ENCRYPTION = 4,
 333         WEP104_ENCRYPTION = 5,
 334 };
 335
 336 enum rtl_hal_state {
 337         _HAL_STATE_STOP = 0,
 338         _HAL_STATE_START = 1,
 339 };
 340
 341 enum rtl_var_map {
 342         /*reg map */
 343         SYS_ISO_CTRL = 0,
 344         SYS_FUNC_EN,
 345         SYS_CLK,
 346         MAC_RCR_AM,
 347         MAC_RCR_AB,
 348         MAC_RCR_ACRC32,
 349         MAC_RCR_ACF,
 350         MAC_RCR_AAP,
 351
 352         /*efuse map */
 353         EFUSE_TEST,
 354         EFUSE_CTRL,
 355         EFUSE_CLK,
 356         EFUSE_CLK_CTRL,
 357         EFUSE_PWC_EV12V,
 358         EFUSE_FEN_ELDR,
 359         EFUSE_LOADER_CLK_EN,
 360         EFUSE_ANA8M,
 361         EFUSE_HWSET_MAX_SIZE,
 362
 363         /*CAM map */
 364         RWCAM,
 365         WCAMI,
 366         RCAMO,
 367         CAMDBG,
 368         SECR,
 369         SEC_CAM_NONE,
 370         SEC_CAM_WEP40,
 371         SEC_CAM_TKIP,
 372         SEC_CAM_AES,
 373         SEC_CAM_WEP104,
 374
 375         /*IMR map */
 376         RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
 377         RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
 378         RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
 379         RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
 380         RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
 381         RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
 382         RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrup 8 */
 383         RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrup 7 */
 384         RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrup 6 */
 385         RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrup 5 */
 386         RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrup 4 */
 387         RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrup 3 */
 388         RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrup 2 */
 389         RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrup 1 */
 390         RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
 391         RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
 392         RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
 393         RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
 394         RTL_IMR_BcnInt,         /*Beacon DMA Interrupt 0 */
 395         RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
 396         RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
 397         RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
 398         RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrup */
 399         RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
 400         RTL_IMR_TBDOK,          /*Transmit Beacon OK interrup */
 401         RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
 402         RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
 403         RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
 404         RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
 405         RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
 406         RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
 407         RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
 408         RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BcnInt|RTL_IMR_TBDOK|RTL_IMR_TBDER)*/
 409
 410         /*CCK Rates, TxHT = 0 */
 411         RTL_RC_CCK_RATE1M,
 412         RTL_RC_CCK_RATE2M,
 413         RTL_RC_CCK_RATE5_5M,
 414         RTL_RC_CCK_RATE11M,
 415
 416         /*OFDM Rates, TxHT = 0 */
 417         RTL_RC_OFDM_RATE6M,
 418         RTL_RC_OFDM_RATE9M,
 419         RTL_RC_OFDM_RATE12M,
 420         RTL_RC_OFDM_RATE18M,
 421         RTL_RC_OFDM_RATE24M,
 422         RTL_RC_OFDM_RATE36M,
 423         RTL_RC_OFDM_RATE48M,
 424         RTL_RC_OFDM_RATE54M,
 425
 426         RTL_RC_HT_RATEMCS7,
 427         RTL_RC_HT_RATEMCS15,
 428
 429         /*keep it last */
 430         RTL_VAR_MAP_MAX,
 431 };
 432
 433 /*Firmware PS mode for control LPS.*/
 434 enum _fw_ps_mode {
 435         FW_PS_ACTIVE_MODE = 0,
 436         FW_PS_MIN_MODE = 1,
 437         FW_PS_MAX_MODE = 2,
 438         FW_PS_DTIM_MODE = 3,
 439         FW_PS_VOIP_MODE = 4,
 440         FW_PS_UAPSD_WMM_MODE = 5,
 441         FW_PS_UAPSD_MODE = 6,
 442         FW_PS_IBSS_MODE = 7,
 443         FW_PS_WWLAN_MODE = 8,
 444         FW_PS_PM_Radio_Off = 9,
 445         FW_PS_PM_Card_Disable = 10,
 446 };
 447
 448 enum rt_psmode {
 449         EACTIVE,                /*Active/Continuous access. */
 450         EMAXPS,                 /*Max power save mode. */
 451         EFASTPS,                /*Fast power save mode. */
 452         EAUTOPS,                /*Auto power save mode. */
 453 };
 454
 455 /*LED related.*/
 456 enum led_ctl_mode {
 457         LED_CTL_POWER_ON = 1,
 458         LED_CTL_LINK = 2,
 459         LED_CTL_NO_LINK = 3,
 460         LED_CTL_TX = 4,
 461         LED_CTL_RX = 5,
 462         LED_CTL_SITE_SURVEY = 6,
 463         LED_CTL_POWER_OFF = 7,
 464         LED_CTL_START_TO_LINK = 8,
 465         LED_CTL_START_WPS = 9,
 466         LED_CTL_STOP_WPS = 10,
 467 };
 468
 469 enum rtl_led_pin {
 470         LED_PIN_GPIO0,
 471         LED_PIN_LED0,
 472         LED_PIN_LED1,
 473         LED_PIN_LED2
 474 };
 475
 476 /*QoS related.*/
 477 /*acm implementation method.*/
 478 enum acm_method {
 479         eAcmWay0_SwAndHw = 0,
 480         eAcmWay1_HW = 1,
 481         eAcmWay2_SW = 2,
 482 };
 483
 484 /*aci/aifsn Field.
 485 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
 486 union aci_aifsn {
 487         u8 char_data;
 488
 489         struct {
 490                 u8 aifsn:4;
 491                 u8 acm:1;
 492                 u8 aci:2;
 493                 u8 reserved:1;
 494         } f;                    /* Field */
 495 };
 496
 497 /*mlme related.*/
 498 enum wireless_mode {
 499         WIRELESS_MODE_UNKNOWN = 0x00,
 500         WIRELESS_MODE_A = 0x01,
 501         WIRELESS_MODE_B = 0x02,
 502         WIRELESS_MODE_G = 0x04,
 503         WIRELESS_MODE_AUTO = 0x08,
 504         WIRELESS_MODE_N_24G = 0x10,
 505         WIRELESS_MODE_N_5G = 0x20
 506 };
 507
 508 enum ratr_table_mode {
 509         RATR_INX_WIRELESS_NGB = 0,
 510         RATR_INX_WIRELESS_NG = 1,
 511         RATR_INX_WIRELESS_NB = 2,
 512         RATR_INX_WIRELESS_N = 3,
 513         RATR_INX_WIRELESS_GB = 4,
 514         RATR_INX_WIRELESS_G = 5,
 515         RATR_INX_WIRELESS_B = 6,
 516         RATR_INX_WIRELESS_MC = 7,
 517         RATR_INX_WIRELESS_A = 8,
 518 };
 519
 520 enum rtl_link_state {
 521         MAC80211_NOLINK = 0,
 522         MAC80211_LINKING = 1,
 523         MAC80211_LINKED = 2,
 524         MAC80211_LINKED_SCANNING = 3,
 525 };
 526
 527 enum act_category {
 528         ACT_CAT_QOS = 1,
 529         ACT_CAT_DLS = 2,
 530         ACT_CAT_BA = 3,
 531         ACT_CAT_HT = 7,
 532         ACT_CAT_WMM = 17,
 533 };
 534
 535 enum ba_action {
 536         ACT_ADDBAREQ = 0,
 537         ACT_ADDBARSP = 1,
 538         ACT_DELBA = 2,
 539 };
 540
 541 struct octet_string {
 542         u8 *octet;
 543         u16 length;
 544 };
 545
 546 struct rtl_hdr_3addr {
 547         __le16 frame_ctl;
 548         __le16 duration_id;
 549         u8 addr1[ETH_ALEN];
 550         u8 addr2[ETH_ALEN];
 551         u8 addr3[ETH_ALEN];
 552         __le16 seq_ctl;
 553         u8 payload[0];
 554 } __packed;
 555
 556 struct rtl_info_element {
 557         u8 id;
 558         u8 len;
 559         u8 data[0];
 560 } __packed;
 561
 562 struct rtl_probe_rsp {
 563         struct rtl_hdr_3addr header;
 564         u32 time_stamp[2];
 565         __le16 beacon_interval;
 566         __le16 capability;
 567         /*SSID, supported rates, FH params, DS params,
 568            CF params, IBSS params, TIM (if beacon), RSN */
 569         struct rtl_info_element info_element[0];
 570 } __packed;
 571
 572 /*LED related.*/
 573 /*ledpin Identify how to implement this SW led.*/
 574 struct rtl_led {
 575         void *hw;
 576         enum rtl_led_pin ledpin;
 577         bool b_ledon;
 578 };
 579
 580 struct rtl_led_ctl {
 581         bool bled_opendrain;
 582         struct rtl_led sw_led0;
 583         struct rtl_led sw_led1;
 584 };
 585
 586 struct rtl_qos_parameters {
 587         __le16 cw_min;
 588         __le16 cw_max;
 589         u8 aifs;
 590         u8 flag;
 591         __le16 tx_op;
 592 } __packed;
 593
 594 struct rt_smooth_data {
 595         u32 elements[100];      /*array to store values */
 596         u32 index;              /*index to current array to store */
 597         u32 total_num;          /*num of valid elements */
 598         u32 total_val;          /*sum of valid elements */
 599 };
 600
 601 struct false_alarm_statistics {
 602         u32 cnt_parity_fail;
 603         u32 cnt_rate_illegal;
 604         u32 cnt_crc8_fail;
 605         u32 cnt_mcs_fail;
 606         u32 cnt_ofdm_fail;
 607         u32 cnt_cck_fail;
 608         u32 cnt_all;
 609 };
 610
 611 struct init_gain {
 612         u8 xaagccore1;
 613         u8 xbagccore1;
 614         u8 xcagccore1;
 615         u8 xdagccore1;
 616         u8 cca;
 617
 618 };
 619
 620 struct wireless_stats {
 621         unsigned long txbytesunicast;
 622         unsigned long txbytesmulticast;
 623         unsigned long txbytesbroadcast;
 624         unsigned long rxbytesunicast;
 625
 626         long rx_snr_db[4];
 627         /*Correct smoothed ss in Dbm, only used
 628            in driver to report real power now. */
 629         long recv_signal_power;
 630         long signal_quality;
 631         long last_sigstrength_inpercent;
 632
 633         u32 rssi_calculate_cnt;
 634
 635         /*Transformed, in dbm. Beautified signal
 636            strength for UI, not correct. */
 637         long signal_strength;
 638
 639         u8 rx_rssi_percentage[4];
 640         u8 rx_evm_percentage[2];
 641
 642         struct rt_smooth_data ui_rssi;
 643         struct rt_smooth_data ui_link_quality;
 644 };
 645
 646 struct rate_adaptive {
 647         u8 rate_adaptive_disabled;
 648         u8 ratr_state;
 649         u16 reserve;
 650
 651         u32 high_rssi_thresh_for_ra;
 652         u32 high2low_rssi_thresh_for_ra;
 653         u8 low2high_rssi_thresh_for_ra40m;
 654         u32 low_rssi_thresh_for_ra40M;
 655         u8 low2high_rssi_thresh_for_ra20m;
 656         u32 low_rssi_thresh_for_ra20M;
 657         u32 upper_rssi_threshold_ratr;
 658         u32 middleupper_rssi_threshold_ratr;
 659         u32 middle_rssi_threshold_ratr;
 660         u32 middlelow_rssi_threshold_ratr;
 661         u32 low_rssi_threshold_ratr;
 662         u32 ultralow_rssi_threshold_ratr;
 663         u32 low_rssi_threshold_ratr_40m;
 664         u32 low_rssi_threshold_ratr_20m;
 665         u8 ping_rssi_enable;
 666         u32 ping_rssi_ratr;
 667         u32 ping_rssi_thresh_for_ra;
 668         u32 last_ratr;
 669         u8 pre_ratr_state;
 670 };
 671
 672 struct regd_pair_mapping {
 673         u16 reg_dmnenum;
 674         u16 reg_5ghz_ctl;
 675         u16 reg_2ghz_ctl;
 676 };
 677
 678 struct rtl_regulatory {
 679         char alpha2[2];
 680         u16 country_code;
 681         u16 max_power_level;
 682         u32 tp_scale;
 683         u16 current_rd;
 684         u16 current_rd_ext;
 685         int16_t power_limit;
 686         struct regd_pair_mapping *regpair;
 687 };
 688
 689 struct rtl_rfkill {
 690         bool rfkill_state;      /*0 is off, 1 is on */
 691 };
 692
 693 struct rtl_phy {
 694         struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
 695         struct init_gain initgain_backup;
 696         enum io_type current_io_type;
 697
 698         u8 rf_mode;
 699         u8 rf_type;
 700         u8 current_chan_bw;
 701         u8 set_bwmode_inprogress;
 702         u8 sw_chnl_inprogress;
 703         u8 sw_chnl_stage;
 704         u8 sw_chnl_step;
 705         u8 current_channel;
 706         u8 h2c_box_num;
 707         u8 set_io_inprogress;
 708
 709         /*record for power tracking*/
 710         s32 reg_e94;
 711         s32 reg_e9c;
 712         s32 reg_ea4;
 713         s32 reg_eac;
 714         s32 reg_eb4;
 715         s32 reg_ebc;
 716         s32 reg_ec4;
 717         s32 reg_ecc;
 718         u8 rfpienable;
 719         u8 reserve_0;
 720         u16 reserve_1;
 721         u32 reg_c04, reg_c08, reg_874;
 722         u32 adda_backup[16];
 723         u32 iqk_mac_backup[IQK_MAC_REG_NUM];
 724         u32 iqk_bb_backup[10];
 725
 726         bool b_rfpi_enable;
 727
 728         u8 pwrgroup_cnt;
 729         u8 bcck_high_power;
 730         /* 3 groups of pwr diff by rates*/
 731         u32 mcs_txpwrlevel_origoffset[4][16];
 732         u8 default_initialgain[4];
 733
 734         /*the current Tx power level*/
 735         u8 cur_cck_txpwridx;
 736         u8 cur_ofdm24g_txpwridx;
 737
 738         u32 rfreg_chnlval[2];
 739         bool b_apk_done;
 740
 741         /*fsync*/
 742         u8 framesync;
 743         u32 framesync_c34;
 744
 745         u8 num_total_rfpath;
 746 };
 747
 748 #define MAX_TID_COUNT                           9
 749 #define RTL_AGG_OFF                             0
 750 #define RTL_AGG_ON                              1
 751 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
 752 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
 753
 754 struct rtl_ht_agg {
 755         u16 txq_id;
 756         u16 wait_for_ba;
 757         u16 start_idx;
 758         u64 bitmap;
 759         u32 rate_n_flags;
 760         u8 agg_state;
 761 };
 762
 763 struct rtl_tid_data {
 764         u16 seq_number;
 765         struct rtl_ht_agg agg;
 766 };
 767
 768 struct rtl_priv;
 769 struct rtl_io {
 770         struct device *dev;
 771
 772         /*PCI MEM map */
 773         unsigned long pci_mem_end;      /*shared mem end        */
 774         unsigned long pci_mem_start;    /*shared mem start */
 775
 776         /*PCI IO map */
 777         unsigned long pci_base_addr;    /*device I/O address */
 778
 779         void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
 780         void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
 781         void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
 782
 783          u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
 784          u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
 785          u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
 786
 787 };
 788
 789 struct rtl_mac {
 790         u8 mac_addr[ETH_ALEN];
 791         u8 mac80211_registered;
 792         u8 beacon_enabled;
 793
 794         u32 tx_ss_num;
 795         u32 rx_ss_num;
 796
 797         struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
 798         struct ieee80211_hw *hw;
 799         struct ieee80211_vif *vif;
 800         enum nl80211_iftype opmode;
 801
 802         /*Probe Beacon management */
 803         struct rtl_tid_data tids[MAX_TID_COUNT];
 804         enum rtl_link_state link_state;
 805
 806         int n_channels;
 807         int n_bitrates;
 808
 809         /*filters */
 810         u32 rx_conf;
 811         u16 rx_mgt_filter;
 812         u16 rx_ctrl_filter;
 813         u16 rx_data_filter;
 814
 815         bool act_scanning;
 816         u8 cnt_after_linked;
 817
 818          /*RDG*/ bool rdg_en;
 819
 820          /*AP*/ u8 bssid[6];
 821         u8 mcs[16];     /*16 bytes mcs for HT rates.*/
 822         u32 basic_rates; /*b/g rates*/
 823         u8 ht_enable;
 824         u8 sgi_40;
 825         u8 sgi_20;
 826         u8 bw_40;
 827         u8 mode;                /*wireless mode*/
 828         u8 slot_time;
 829         u8 short_preamble;
 830         u8 use_cts_protect;
 831         u8 cur_40_prime_sc;
 832         u8 cur_40_prime_sc_bk;
 833         u64 tsf;
 834         u8 retry_short;
 835         u8 retry_long;
 836         u16 assoc_id;
 837
 838          /*IBSS*/ int beacon_interval;
 839
 840          /*AMPDU*/ u8 min_space_cfg;    /*For Min spacing configurations */
 841         u8 max_mss_density;
 842         u8 current_ampdu_factor;
 843         u8 current_ampdu_density;
 844
 845         /*QOS & EDCA */
 846         struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
 847         struct rtl_qos_parameters ac[AC_MAX];
 848 };
 849
 850 struct rtl_hal {
 851         struct ieee80211_hw *hw;
 852
 853         enum intf_type interface;
 854         u16 hw_type;            /*92c or 92d or 92s and so on */
 855         u8 oem_id;
 856         u8 version;             /*version of chip */
 857         u8 state;               /*stop 0, start 1 */
 858
 859         /*firmware */
 860         u8 *pfirmware;
 861         bool b_h2c_setinprogress;
 862         u8 last_hmeboxnum;
 863         bool bfw_ready;
 864         /*Reserve page start offset except beacon in TxQ. */
 865         u8 fw_rsvdpage_startoffset;
 866 };
 867
 868 struct rtl_security {
 869         /*default 0 */
 870         bool use_sw_sec;
 871
 872         bool being_setkey;
 873         bool use_defaultkey;
 874         /*Encryption Algorithm for Unicast Packet */
 875         enum rt_enc_alg pairwise_enc_algorithm;
 876         /*Encryption Algorithm for Brocast/Multicast */
 877         enum rt_enc_alg group_enc_algorithm;
 878
 879         /*local Key buffer, indx 0 is for
 880            pairwise key 1-4 is for agoup key. */
 881         u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
 882         u8 key_len[KEY_BUF_SIZE];
 883
 884         /*The pointer of Pairwise Key,
 885            it always points to KeyBuf[4] */
 886         u8 *pairwise_key;
 887 };
 888
 889 struct rtl_dm {
 890         /*PHY status for DM */
 891         long entry_min_undecoratedsmoothed_pwdb;
 892         long undecorated_smoothed_pwdb; /*out dm */
 893         long entry_max_undecoratedsmoothed_pwdb;
 894         bool b_dm_initialgain_enable;
 895         bool bdynamic_txpower_enable;
 896         bool bcurrent_turbo_edca;
 897         bool bis_any_nonbepkts; /*out dm */
 898         bool bis_cur_rdlstate;
 899         bool btxpower_trackingInit;
 900         bool b_disable_framebursting;
 901         bool b_cck_inch14;
 902         bool btxpower_tracking;
 903         bool b_useramask;
 904         bool brfpath_rxenable[4];
 905
 906         u8 thermalvalue_iqk;
 907         u8 thermalvalue_lck;
 908         u8 thermalvalue;
 909         u8 last_dtp_lvl;
 910         u8 dynamic_txhighpower_lvl;     /*Tx high power level */
 911         u8 dm_flag;     /*Indicate if each dynamic mechanism's status. */
 912         u8 dm_type;
 913         u8 txpower_track_control;
 914
 915         char ofdm_index[2];
 916         char cck_index;
 917 };
 918
 919 #define EFUSE_MAX_LOGICAL_SIZE                   128
 920
 921 struct rtl_efuse {
 922         bool bautoLoad_ok;
 923         bool bootfromefuse;
 924         u16 max_physical_size;
 925         u8 contents[EFUSE_MAX_LOGICAL_SIZE];
 926
 927         u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
 928         u16 efuse_usedbytes;
 929         u8 efuse_usedpercentage;
 930
 931         u8 autoload_failflag;
 932
 933         short epromtype;
 934         u16 eeprom_vid;
 935         u16 eeprom_did;
 936         u16 eeprom_svid;
 937         u16 eeprom_smid;
 938         u8 eeprom_oemid;
 939         u16 eeprom_channelplan;
 940         u8 eeprom_version;
 941
 942         u8 dev_addr[6];
 943
 944         bool b_txpwr_fromeprom;
 945         u8 eeprom_tssi[2];
 946         u8 eeprom_pwrlimit_ht20[3];
 947         u8 eeprom_pwrlimit_ht40[3];
 948         u8 eeprom_chnlarea_txpwr_cck[2][3];
 949         u8 eeprom_chnlarea_txpwr_ht40_1s[2][3];
 950         u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3];
 951         u8 txpwrlevel_cck[2][14];
 952         u8 txpwrlevel_ht40_1s[2][14];   /*For HT 40MHZ pwr */
 953         u8 txpwrlevel_ht40_2s[2][14];   /*For HT 40MHZ pwr */
 954
 955         /*For power group */
 956         u8 pwrgroup_ht20[2][14];
 957         u8 pwrgroup_ht40[2][14];
 958
 959         char txpwr_ht20diff[2][14];     /*HT 20<->40 Pwr diff */
 960         u8 txpwr_legacyhtdiff[2][14];   /*For HT<->legacy pwr diff */
 961
 962         u8 eeprom_regulatory;
 963         u8 eeprom_thermalmeter;
 964         /*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
 965         u8 thermalmeter[2];
 966
 967         u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
 968         bool b_apk_thermalmeterignore;
 969 };
 970
 971 struct rtl_ps_ctl {
 972         bool set_rfpowerstate_inprogress;
 973         bool b_in_powersavemode;
 974         bool rfchange_inprogress;
 975         bool b_swrf_processing;
 976         bool b_hwradiooff;
 977
 978         u32 last_sleep_jiffies;
 979         u32 last_awake_jiffies;
 980         u32 last_delaylps_stamp_jiffies;
 981
 982         /*
 983          * just for PCIE ASPM
 984          * If it supports ASPM, Offset[560h] = 0x40,
 985          * otherwise Offset[560h] = 0x00.
 986          * */
 987         bool b_support_aspm;
 988         bool b_support_backdoor;
 989
 990         /*for LPS */
 991         enum rt_psmode dot11_psmode;    /*Power save mode configured. */
 992         bool b_leisure_ps;
 993         bool b_fwctrl_lps;
 994         u8 fwctrl_psmode;
 995         /*For Fw control LPS mode */
 996         u8 b_reg_fwctrl_lps;
 997         /*Record Fw PS mode status. */
 998         bool b_fw_current_inpsmode;
 999         u8 reg_max_lps_awakeintvl;
1000         bool report_linked;
1001
1002         /*for IPS */
1003         bool b_inactiveps;
1004
1005         u32 rfoff_reason;
1006
1007         /*RF OFF Level */
1008         u32 cur_ps_level;
1009         u32 reg_rfps_level;
1010
1011         /*just for PCIE ASPM */
1012         u8 const_amdpci_aspm;
1013
1014         enum rf_pwrstate inactive_pwrstate;
1015         enum rf_pwrstate rfpwr_state;   /*cur power state */
1016 };
1017
1018 struct rtl_stats {
1019         u32 mac_time[2];
1020         s8 rssi;
1021         u8 signal;
1022         u8 noise;
1023         u16 rate;               /*in 100 kbps */
1024         u8 received_channel;
1025         u8 control;
1026         u8 mask;
1027         u8 freq;
1028         u16 len;
1029         u64 tsf;
1030         u32 beacon_time;
1031         u8 nic_type;
1032         u16 length;
1033         u8 signalquality;       /*in 0-100 index. */
1034         /*
1035          * Real power in dBm for this packet,
1036          * no beautification and aggregation.
1037          * */
1038         s32 recvsignalpower;
1039         s8 rxpower;             /*in dBm Translate from PWdB */
1040         u8 signalstrength;      /*in 0-100 index. */
1041         u16 b_hwerror:1;
1042         u16 b_crc:1;
1043         u16 b_icv:1;
1044         u16 b_shortpreamble:1;
1045         u16 antenna:1;
1046         u16 decrypted:1;
1047         u16 wakeup:1;
1048         u32 timestamp_low;
1049         u32 timestamp_high;
1050
1051         u8 rx_drvinfo_size;
1052         u8 rx_bufshift;
1053         bool b_isampdu;
1054         bool rx_is40Mhzpacket;
1055         u32 rx_pwdb_all;
1056         u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
1057         s8 rx_mimo_signalquality[2];
1058         bool b_packet_matchbssid;
1059         bool b_is_cck;
1060         bool b_packet_toself;
1061         bool b_packet_beacon;   /*for rssi */
1062         char cck_adc_pwdb[4];   /*for rx path selection */
1063 };
1064
1065 struct rt_link_detect {
1066         u32 num_tx_in4period[4];
1067         u32 num_rx_in4period[4];
1068
1069         u32 num_tx_inperiod;
1070         u32 num_rx_inperiod;
1071
1072         bool b_busytraffic;
1073         bool b_higher_busytraffic;
1074         bool b_higher_busyrxtraffic;
1075 };
1076
1077 struct rtl_tcb_desc {
1078         u8 b_packet_bw:1;
1079         u8 b_multicast:1;
1080         u8 b_broadcast:1;
1081
1082         u8 b_rts_stbc:1;
1083         u8 b_rts_enable:1;
1084         u8 b_cts_enable:1;
1085         u8 b_rts_use_shortpreamble:1;
1086         u8 b_rts_use_shortgi:1;
1087         u8 rts_sc:1;
1088         u8 b_rts_bw:1;
1089         u8 rts_rate;
1090
1091         u8 use_shortgi:1;
1092         u8 use_shortpreamble:1;
1093         u8 use_driver_rate:1;
1094         u8 disable_ratefallback:1;
1095
1096         u8 ratr_index;
1097         u8 mac_id;
1098         u8 hw_rate;
1099 };
1100
1101 struct rtl_hal_ops {
1102         int (*init_sw_vars) (struct ieee80211_hw *hw);
1103         void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1104         void (*read_eeprom_info) (struct ieee80211_hw *hw);
1105         void (*interrupt_recognized) (struct ieee80211_hw *hw,
1106                                       u32 *p_inta, u32 *p_intb);
1107         int (*hw_init) (struct ieee80211_hw *hw);
1108         void (*hw_disable) (struct ieee80211_hw *hw);
1109         void (*enable_interrupt) (struct ieee80211_hw *hw);
1110         void (*disable_interrupt) (struct ieee80211_hw *hw);
1111         int (*set_network_type) (struct ieee80211_hw *hw,
1112                                  enum nl80211_iftype type);
1113         void (*set_bw_mode) (struct ieee80211_hw *hw,
1114                              enum nl80211_channel_type ch_type);
1115          u8(*switch_channel) (struct ieee80211_hw *hw);
1116         void (*set_qos) (struct ieee80211_hw *hw, int aci);
1117         void (*set_bcn_reg) (struct ieee80211_hw *hw);
1118         void (*set_bcn_intv) (struct ieee80211_hw *hw);
1119         void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1120                                        u32 add_msr, u32 rm_msr);
1121         void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1122         void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1123         void (*update_rate_table) (struct ieee80211_hw *hw);
1124         void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1125         void (*fill_tx_desc) (struct ieee80211_hw *hw,
1126                               struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1127                               struct ieee80211_tx_info *info,
1128                               struct sk_buff *skb, unsigned int queue_index);
1129         void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1130                                  bool b_firstseg, bool b_lastseg,
1131                                  struct sk_buff *skb);
1132          bool(*query_rx_desc) (struct ieee80211_hw *hw,
1133                                struct rtl_stats *stats,
1134                                struct ieee80211_rx_status *rx_status,
1135                                u8 *pdesc, struct sk_buff *skb);
1136         void (*set_channel_access) (struct ieee80211_hw *hw);
1137          bool(*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1138         void (*dm_watchdog) (struct ieee80211_hw *hw);
1139         void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1140          bool(*set_rf_power_state) (struct ieee80211_hw *hw,
1141                                     enum rf_pwrstate rfpwr_state);
1142         void (*led_control) (struct ieee80211_hw *hw,
1143                              enum led_ctl_mode ledaction);
1144         void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1145          u32(*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1146         void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
1147         void (*enable_hw_sec) (struct ieee80211_hw *hw);
1148         void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1149                          u8 *p_macaddr, bool is_group, u8 enc_algo,
1150                          bool is_wepkey, bool clear_all);
1151         void (*init_sw_leds) (struct ieee80211_hw *hw);
1152         void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1153          u32(*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1154         void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1155                            u32 data);
1156          u32(*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1157                           u32 regaddr, u32 bitmask);
1158         void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1159                            u32 regaddr, u32 bitmask, u32 data);
1160 };
1161
1162 struct rtl_intf_ops {
1163         /*com */
1164         int (*adapter_start) (struct ieee80211_hw *hw);
1165         void (*adapter_stop) (struct ieee80211_hw *hw);
1166
1167         int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
1168         int (*reset_trx_ring) (struct ieee80211_hw *hw);
1169
1170         /*pci */
1171         void (*disable_aspm) (struct ieee80211_hw *hw);
1172         void (*enable_aspm) (struct ieee80211_hw *hw);
1173
1174         /*usb */
1175 };
1176
1177 struct rtl_mod_params {
1178         /* default: 0 = using hardware encryption */
1179         int sw_crypto;
1180 };
1181
1182 struct rtl_hal_cfg {
1183         char *name;
1184         char *fw_name;
1185         struct rtl_hal_ops *ops;
1186         struct rtl_mod_params *mod_params;
1187
1188         /*this map used for some registers or vars
1189            defined int HAL but used in MAIN */
1190         u32 maps[RTL_VAR_MAP_MAX];
1191
1192 };
1193
1194 struct rtl_locks {
1195         /* mutex */
1196         struct mutex conf_mutex;
1197
1198         /*spin lock */
1199         spinlock_t ips_lock;
1200         spinlock_t irq_th_lock;
1201         spinlock_t h2c_lock;
1202         spinlock_t rf_ps_lock;
1203         spinlock_t rf_lock;
1204         spinlock_t lps_lock;
1205 };
1206
1207 struct rtl_works {
1208         struct ieee80211_hw *hw;
1209
1210         /*timer */
1211         struct timer_list watchdog_timer;
1212
1213         /*task */
1214         struct tasklet_struct irq_tasklet;
1215         struct tasklet_struct irq_prepare_bcn_tasklet;
1216
1217         /*work queue */
1218         struct workqueue_struct *rtl_wq;
1219         struct delayed_work watchdog_wq;
1220         struct delayed_work ips_nic_off_wq;
1221 };
1222
1223 struct rtl_debug {
1224         u32 dbgp_type[DBGP_TYPE_MAX];
1225         u32 global_debuglevel;
1226         u64 global_debugcomponents;
1227 };
1228
1229 struct rtl_priv {
1230         struct rtl_locks locks;
1231         struct rtl_works works;
1232         struct rtl_mac mac80211;
1233         struct rtl_hal rtlhal;
1234         struct rtl_regulatory regd;
1235         struct rtl_rfkill rfkill;
1236         struct rtl_io io;
1237         struct rtl_phy phy;
1238         struct rtl_dm dm;
1239         struct rtl_security sec;
1240         struct rtl_efuse efuse;
1241
1242         struct rtl_ps_ctl psc;
1243         struct rate_adaptive ra;
1244         struct wireless_stats stats;
1245         struct rt_link_detect link_info;
1246         struct false_alarm_statistics falsealm_cnt;
1247
1248         struct rtl_rate_priv *rate_priv;
1249
1250         struct rtl_debug dbg;
1251
1252         /*
1253          *hal_cfg : for diff cards
1254          *intf_ops : for diff interrface usb/pcie
1255          */
1256         struct rtl_hal_cfg *cfg;
1257         struct rtl_intf_ops *intf_ops;
1258
1259         /*this var will be set by set_bit,
1260            and was used to indicate status of
1261            interface or hardware */
1262         unsigned long status;
1263
1264         /*This must be the last item so
1265            that it points to the data allocated
1266            beyond  this structure like:
1267            rtl_pci_priv or rtl_usb_priv */
1268         u8 priv[0];
1269 };
1270
1271 #define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
1272 #define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
1273 #define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
1274 #define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
1275 #define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
1276
1277 /****************************************
1278         mem access macro define start
1279         Call endian free function when
1280         1. Read/write packet content.
1281         2. Before write integer to IO.
1282         3. After read integer from IO.
1283 ****************************************/
1284 /* Convert little data endian to host */
1285 #define EF1BYTE(_val)           \
1286         ((u8)(_val))
1287 #define EF2BYTE(_val)           \
1288         (le16_to_cpu(_val))
1289 #define EF4BYTE(_val)           \
1290         (le32_to_cpu(_val))
1291
1292 /* Read data from memory */
1293 #define READEF1BYTE(_ptr)       \
1294         EF1BYTE(*((u8 *)(_ptr)))
1295 #define READEF2BYTE(_ptr)       \
1296         EF2BYTE(*((u16 *)(_ptr)))
1297 #define READEF4BYTE(_ptr)       \
1298         EF4BYTE(*((u32 *)(_ptr)))
1299
1300 /* Write data to memory */
1301 #define WRITEEF1BYTE(_ptr, _val)        \
1302         (*((u8 *)(_ptr))) = EF1BYTE(_val)
1303 #define WRITEEF2BYTE(_ptr, _val)        \
1304         (*((u16 *)(_ptr))) = EF2BYTE(_val)
1305 #define WRITEEF4BYTE(_ptr, _val)        \
1306         (*((u32 *)(_ptr))) = EF4BYTE(_val)
1307
1308 /*Example:
1309 BIT_LEN_MASK_32(0) => 0x00000000
1310 BIT_LEN_MASK_32(1) => 0x00000001
1311 BIT_LEN_MASK_32(2) => 0x00000003
1312 BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
1313 #define BIT_LEN_MASK_32(__bitlen)        \
1314         (0xFFFFFFFF >> (32 - (__bitlen)))
1315 #define BIT_LEN_MASK_16(__bitlen)        \
1316         (0xFFFF >> (16 - (__bitlen)))
1317 #define BIT_LEN_MASK_8(__bitlen) \
1318         (0xFF >> (8 - (__bitlen)))
1319
1320 /*Example:
1321 BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1322 BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
1323 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1324         (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1325 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1326         (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1327 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1328         (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1329
1330 /*Description:
1331 Return 4-byte value in host byte ordering from
1332 4-byte pointer in little-endian system.*/
1333 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1334         (EF4BYTE(*((u32 *)(__pstart))))
1335 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1336         (EF2BYTE(*((u16 *)(__pstart))))
1337 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1338         (EF1BYTE(*((u8 *)(__pstart))))
1339
1340 /*Description:
1341 Translate subfield (continuous bits in little-endian) of 4-byte
1342 value to host byte ordering.*/
1343 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1344         ( \
1345                 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
1346                 BIT_LEN_MASK_32(__bitlen) \
1347         )
1348 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1349         ( \
1350                 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1351                 BIT_LEN_MASK_16(__bitlen) \
1352         )
1353 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1354         ( \
1355                 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1356                 BIT_LEN_MASK_8(__bitlen) \
1357         )
1358
1359 /*Description:
1360 Mask subfield (continuous bits in little-endian) of 4-byte value
1361 and return the result in 4-byte value in host byte ordering.*/
1362 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1363         ( \
1364                 LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
1365                 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1366         )
1367 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1368         ( \
1369                 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1370                 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1371         )
1372 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1373         ( \
1374                 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1375                 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1376         )
1377
1378 /*Description:
1379 Set subfield of little-endian 4-byte value to specified value.  */
1380 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1381         *((u32 *)(__pstart)) = EF4BYTE \
1382         ( \
1383                 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1384                 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1385         );
1386 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1387         *((u16 *)(__pstart)) = EF2BYTE \
1388         ( \
1389                 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1390                 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1391         );
1392 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1393         *((u8 *)(__pstart)) = EF1BYTE \
1394         ( \
1395                 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1396                 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1397         );
1398
1399 /****************************************
1400         mem access macro define end
1401 ****************************************/
1402
1403 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1404 #define RTL_WATCH_DOG_TIME      2000
1405 #define MSECS(t)                msecs_to_jiffies(t)
1406 #define WLAN_FC_GET_VERS(fc)    ((fc) & IEEE80211_FCTL_VERS)
1407 #define WLAN_FC_GET_TYPE(fc)    ((fc) & IEEE80211_FCTL_FTYPE)
1408 #define WLAN_FC_GET_STYPE(fc)   ((fc) & IEEE80211_FCTL_STYPE)
1409 #define WLAN_FC_MORE_DATA(fc)   ((fc) & IEEE80211_FCTL_MOREDATA)
1410 #define SEQ_TO_SN(seq)          (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1411 #define SN_TO_SEQ(ssn)          (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1412 #define MAX_SN                  ((IEEE80211_SCTL_SEQ) >> 4)
1413
1414 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
1415 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
1416 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
1417 /*NIC halt, re-initialize hw parameters*/
1418 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
1419 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
1420 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
1421 /*Always enable ASPM and Clock Req in initialization.*/
1422 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
1423 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1424 #define RT_RF_LPS_DISALBE_2R            BIT(30)
1425 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
1426 #define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
1427         ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1428 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
1429         (ppsc->cur_ps_level &= (~(_ps_flg)))
1430 #define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
1431         (ppsc->cur_ps_level |= _ps_flg)
1432
1433 #define container_of_dwork_rtl(x, y, z) \
1434         container_of(container_of(x, struct delayed_work, work), y, z)
1435
1436 #define FILL_OCTET_STRING(_os, _octet, _len)    \
1437                 (_os).octet = (u8 *)(_octet);           \
1438                 (_os).length = (_len);
1439
1440 #define CP_MACADDR(des, src)    \
1441         ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1442         (des)[2] = (src)[2], (des)[3] = (src)[3],\
1443         (des)[4] = (src)[4], (des)[5] = (src)[5])
1444
1445 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1446 {
1447         return rtlpriv->io.read8_sync(rtlpriv, addr);
1448 }
1449
1450 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1451 {
1452         return rtlpriv->io.read16_sync(rtlpriv, addr);
1453 }
1454
1455 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1456 {
1457         return rtlpriv->io.read32_sync(rtlpriv, addr);
1458 }
1459
1460 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1461 {
1462         rtlpriv->io.write8_async(rtlpriv, addr, val8);
1463 }
1464
1465 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1466 {
1467         rtlpriv->io.write16_async(rtlpriv, addr, val16);
1468 }
1469
1470 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1471                                    u32 addr, u32 val32)
1472 {
1473         rtlpriv->io.write32_async(rtlpriv, addr, val32);
1474 }
1475
1476 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1477                                 u32 regaddr, u32 bitmask)
1478 {
1479         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1480                                                                     regaddr,
1481                                                                     bitmask);
1482 }
1483
1484 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1485                                  u32 bitmask, u32 data)
1486 {
1487         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1488                                                              regaddr, bitmask,
1489                                                              data);
1490
1491 }
1492
1493 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1494                                 enum radio_path rfpath, u32 regaddr,
1495                                 u32 bitmask)
1496 {
1497         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1498                                                                     rfpath,
1499                                                                     regaddr,
1500                                                                     bitmask);
1501 }
1502
1503 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1504                                  enum radio_path rfpath, u32 regaddr,
1505                                  u32 bitmask, u32 data)
1506 {
1507         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1508                                                              rfpath, regaddr,
1509                                                              bitmask, data);
1510 }
1511
1512 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1513 {
1514         return (_HAL_STATE_STOP == rtlhal->state);
1515 }
1516
1517 static inline void set_hal_start(struct rtl_hal *rtlhal)
1518 {
1519         rtlhal->state = _HAL_STATE_START;
1520 }
1521
1522 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1523 {
1524         rtlhal->state = _HAL_STATE_STOP;
1525 }
1526
1527 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1528 {
1529         return rtlphy->rf_type;
1530 }
1531
1532 #endif