2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/msi.h>
18 #include <linux/of_address.h>
19 #include <linux/of_pci.h>
20 #include <linux/pci.h>
21 #include <linux/pci_regs.h>
22 #include <linux/platform_device.h>
23 #include <linux/types.h>
24 #include <linux/delay.h>
26 #include "pcie-designware.h"
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34 #define PORT_LINK_MODE_8_LANES (0xf << 16)
36 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
37 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
38 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
39 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
41 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
42 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
44 #define PCIE_MSI_ADDR_LO 0x820
45 #define PCIE_MSI_ADDR_HI 0x824
46 #define PCIE_MSI_INTR0_ENABLE 0x828
47 #define PCIE_MSI_INTR0_MASK 0x82C
48 #define PCIE_MSI_INTR0_STATUS 0x830
50 #define PCIE_ATU_VIEWPORT 0x900
51 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
52 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
53 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
54 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
55 #define PCIE_ATU_CR1 0x904
56 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
57 #define PCIE_ATU_TYPE_IO (0x2 << 0)
58 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
59 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
60 #define PCIE_ATU_CR2 0x908
61 #define PCIE_ATU_ENABLE (0x1 << 31)
62 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
63 #define PCIE_ATU_LOWER_BASE 0x90C
64 #define PCIE_ATU_UPPER_BASE 0x910
65 #define PCIE_ATU_LIMIT 0x914
66 #define PCIE_ATU_LOWER_TARGET 0x918
67 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
68 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
69 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
70 #define PCIE_ATU_UPPER_TARGET 0x91C
72 /* PCIe Port Logic registers */
73 #define PLR_OFFSET 0x700
74 #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
75 #define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
77 static struct pci_ops dw_pcie_ops
;
79 int dw_pcie_cfg_read(void __iomem
*addr
, int size
, u32
*val
)
81 if ((uintptr_t)addr
& (size
- 1)) {
83 return PCIBIOS_BAD_REGISTER_NUMBER
;
94 return PCIBIOS_BAD_REGISTER_NUMBER
;
97 return PCIBIOS_SUCCESSFUL
;
100 int dw_pcie_cfg_write(void __iomem
*addr
, int size
, u32 val
)
102 if ((uintptr_t)addr
& (size
- 1))
103 return PCIBIOS_BAD_REGISTER_NUMBER
;
112 return PCIBIOS_BAD_REGISTER_NUMBER
;
114 return PCIBIOS_SUCCESSFUL
;
117 static inline void dw_pcie_readl_rc(struct pcie_port
*pp
, u32 reg
, u32
*val
)
119 if (pp
->ops
->readl_rc
)
120 pp
->ops
->readl_rc(pp
, pp
->dbi_base
+ reg
, val
);
122 *val
= readl(pp
->dbi_base
+ reg
);
125 static inline void dw_pcie_writel_rc(struct pcie_port
*pp
, u32 val
, u32 reg
)
127 if (pp
->ops
->writel_rc
)
128 pp
->ops
->writel_rc(pp
, val
, pp
->dbi_base
+ reg
);
130 writel(val
, pp
->dbi_base
+ reg
);
133 static int dw_pcie_rd_own_conf(struct pcie_port
*pp
, int where
, int size
,
136 if (pp
->ops
->rd_own_conf
)
137 return pp
->ops
->rd_own_conf(pp
, where
, size
, val
);
139 return dw_pcie_cfg_read(pp
->dbi_base
+ where
, size
, val
);
142 static int dw_pcie_wr_own_conf(struct pcie_port
*pp
, int where
, int size
,
145 if (pp
->ops
->wr_own_conf
)
146 return pp
->ops
->wr_own_conf(pp
, where
, size
, val
);
148 return dw_pcie_cfg_write(pp
->dbi_base
+ where
, size
, val
);
151 static void dw_pcie_prog_outbound_atu(struct pcie_port
*pp
, int index
,
152 int type
, u64 cpu_addr
, u64 pci_addr
, u32 size
)
156 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| index
,
158 dw_pcie_writel_rc(pp
, lower_32_bits(cpu_addr
), PCIE_ATU_LOWER_BASE
);
159 dw_pcie_writel_rc(pp
, upper_32_bits(cpu_addr
), PCIE_ATU_UPPER_BASE
);
160 dw_pcie_writel_rc(pp
, lower_32_bits(cpu_addr
+ size
- 1),
162 dw_pcie_writel_rc(pp
, lower_32_bits(pci_addr
), PCIE_ATU_LOWER_TARGET
);
163 dw_pcie_writel_rc(pp
, upper_32_bits(pci_addr
), PCIE_ATU_UPPER_TARGET
);
164 dw_pcie_writel_rc(pp
, type
, PCIE_ATU_CR1
);
165 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
168 * Make sure ATU enable takes effect before any subsequent config
171 dw_pcie_readl_rc(pp
, PCIE_ATU_CR2
, &val
);
174 static struct irq_chip dw_msi_irq_chip
= {
176 .irq_enable
= pci_msi_unmask_irq
,
177 .irq_disable
= pci_msi_mask_irq
,
178 .irq_mask
= pci_msi_mask_irq
,
179 .irq_unmask
= pci_msi_unmask_irq
,
182 /* MSI int handler */
183 irqreturn_t
dw_handle_msi_irq(struct pcie_port
*pp
)
187 irqreturn_t ret
= IRQ_NONE
;
189 for (i
= 0; i
< MAX_MSI_CTRLS
; i
++) {
190 dw_pcie_rd_own_conf(pp
, PCIE_MSI_INTR0_STATUS
+ i
* 12, 4,
195 while ((pos
= find_next_bit(&val
, 32, pos
)) != 32) {
196 irq
= irq_find_mapping(pp
->irq_domain
,
198 dw_pcie_wr_own_conf(pp
,
199 PCIE_MSI_INTR0_STATUS
+ i
* 12,
201 generic_handle_irq(irq
);
210 void dw_pcie_msi_init(struct pcie_port
*pp
)
214 pp
->msi_data
= __get_free_pages(GFP_KERNEL
, 0);
215 msi_target
= virt_to_phys((void *)pp
->msi_data
);
217 /* program the msi_data */
218 dw_pcie_wr_own_conf(pp
, PCIE_MSI_ADDR_LO
, 4,
219 (u32
)(msi_target
& 0xffffffff));
220 dw_pcie_wr_own_conf(pp
, PCIE_MSI_ADDR_HI
, 4,
221 (u32
)(msi_target
>> 32 & 0xffffffff));
224 static void dw_pcie_msi_clear_irq(struct pcie_port
*pp
, int irq
)
226 unsigned int res
, bit
, val
;
228 res
= (irq
/ 32) * 12;
230 dw_pcie_rd_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, &val
);
232 dw_pcie_wr_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, val
);
235 static void clear_irq_range(struct pcie_port
*pp
, unsigned int irq_base
,
236 unsigned int nvec
, unsigned int pos
)
240 for (i
= 0; i
< nvec
; i
++) {
241 irq_set_msi_desc_off(irq_base
, i
, NULL
);
242 /* Disable corresponding interrupt on MSI controller */
243 if (pp
->ops
->msi_clear_irq
)
244 pp
->ops
->msi_clear_irq(pp
, pos
+ i
);
246 dw_pcie_msi_clear_irq(pp
, pos
+ i
);
249 bitmap_release_region(pp
->msi_irq_in_use
, pos
, order_base_2(nvec
));
252 static void dw_pcie_msi_set_irq(struct pcie_port
*pp
, int irq
)
254 unsigned int res
, bit
, val
;
256 res
= (irq
/ 32) * 12;
258 dw_pcie_rd_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, &val
);
260 dw_pcie_wr_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, val
);
263 static int assign_irq(int no_irqs
, struct msi_desc
*desc
, int *pos
)
266 struct pcie_port
*pp
= (struct pcie_port
*) msi_desc_to_pci_sysdata(desc
);
268 pos0
= bitmap_find_free_region(pp
->msi_irq_in_use
, MAX_MSI_IRQS
,
269 order_base_2(no_irqs
));
273 irq
= irq_find_mapping(pp
->irq_domain
, pos0
);
278 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
279 * descs so there is no need to allocate descs here. We can therefore
280 * assume that if irq_find_mapping above returns non-zero, then the
281 * descs are also successfully allocated.
284 for (i
= 0; i
< no_irqs
; i
++) {
285 if (irq_set_msi_desc_off(irq
, i
, desc
) != 0) {
286 clear_irq_range(pp
, irq
, i
, pos0
);
289 /*Enable corresponding interrupt in MSI interrupt controller */
290 if (pp
->ops
->msi_set_irq
)
291 pp
->ops
->msi_set_irq(pp
, pos0
+ i
);
293 dw_pcie_msi_set_irq(pp
, pos0
+ i
);
297 desc
->nvec_used
= no_irqs
;
298 desc
->msi_attrib
.multiple
= order_base_2(no_irqs
);
307 static void dw_msi_setup_msg(struct pcie_port
*pp
, unsigned int irq
, u32 pos
)
312 if (pp
->ops
->get_msi_addr
)
313 msi_target
= pp
->ops
->get_msi_addr(pp
);
315 msi_target
= virt_to_phys((void *)pp
->msi_data
);
317 msg
.address_lo
= (u32
)(msi_target
& 0xffffffff);
318 msg
.address_hi
= (u32
)(msi_target
>> 32 & 0xffffffff);
320 if (pp
->ops
->get_msi_data
)
321 msg
.data
= pp
->ops
->get_msi_data(pp
, pos
);
325 pci_write_msi_msg(irq
, &msg
);
328 static int dw_msi_setup_irq(struct msi_controller
*chip
, struct pci_dev
*pdev
,
329 struct msi_desc
*desc
)
332 struct pcie_port
*pp
= pdev
->bus
->sysdata
;
334 if (desc
->msi_attrib
.is_msix
)
337 irq
= assign_irq(1, desc
, &pos
);
341 dw_msi_setup_msg(pp
, irq
, pos
);
346 static int dw_msi_setup_irqs(struct msi_controller
*chip
, struct pci_dev
*pdev
,
349 #ifdef CONFIG_PCI_MSI
351 struct msi_desc
*desc
;
352 struct pcie_port
*pp
= pdev
->bus
->sysdata
;
354 /* MSI-X interrupts are not supported */
355 if (type
== PCI_CAP_ID_MSIX
)
358 WARN_ON(!list_is_singular(&pdev
->dev
.msi_list
));
359 desc
= list_entry(pdev
->dev
.msi_list
.next
, struct msi_desc
, list
);
361 irq
= assign_irq(nvec
, desc
, &pos
);
365 dw_msi_setup_msg(pp
, irq
, pos
);
373 static void dw_msi_teardown_irq(struct msi_controller
*chip
, unsigned int irq
)
375 struct irq_data
*data
= irq_get_irq_data(irq
);
376 struct msi_desc
*msi
= irq_data_get_msi_desc(data
);
377 struct pcie_port
*pp
= (struct pcie_port
*) msi_desc_to_pci_sysdata(msi
);
379 clear_irq_range(pp
, irq
, 1, data
->hwirq
);
382 static struct msi_controller dw_pcie_msi_chip
= {
383 .setup_irq
= dw_msi_setup_irq
,
384 .setup_irqs
= dw_msi_setup_irqs
,
385 .teardown_irq
= dw_msi_teardown_irq
,
388 int dw_pcie_wait_for_link(struct pcie_port
*pp
)
392 /* check if the link is up or not */
393 for (retries
= 0; retries
< LINK_WAIT_MAX_RETRIES
; retries
++) {
394 if (dw_pcie_link_up(pp
)) {
395 dev_info(pp
->dev
, "link up\n");
398 usleep_range(LINK_WAIT_USLEEP_MIN
, LINK_WAIT_USLEEP_MAX
);
401 dev_err(pp
->dev
, "phy link never came up\n");
406 int dw_pcie_link_up(struct pcie_port
*pp
)
410 if (pp
->ops
->link_up
)
411 return pp
->ops
->link_up(pp
);
413 val
= readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R1
);
414 return val
& PCIE_PHY_DEBUG_R1_LINK_UP
;
417 static int dw_pcie_msi_map(struct irq_domain
*domain
, unsigned int irq
,
418 irq_hw_number_t hwirq
)
420 irq_set_chip_and_handler(irq
, &dw_msi_irq_chip
, handle_simple_irq
);
421 irq_set_chip_data(irq
, domain
->host_data
);
426 static const struct irq_domain_ops msi_domain_ops
= {
427 .map
= dw_pcie_msi_map
,
430 int dw_pcie_host_init(struct pcie_port
*pp
)
432 struct device_node
*np
= pp
->dev
->of_node
;
433 struct platform_device
*pdev
= to_platform_device(pp
->dev
);
434 struct pci_bus
*bus
, *child
;
435 struct resource
*cfg_res
;
438 struct resource_entry
*win
;
440 cfg_res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "config");
442 pp
->cfg0_size
= resource_size(cfg_res
)/2;
443 pp
->cfg1_size
= resource_size(cfg_res
)/2;
444 pp
->cfg0_base
= cfg_res
->start
;
445 pp
->cfg1_base
= cfg_res
->start
+ pp
->cfg0_size
;
446 } else if (!pp
->va_cfg0_base
) {
447 dev_err(pp
->dev
, "missing *config* reg space\n");
450 ret
= of_pci_get_host_bridge_resources(np
, 0, 0xff, &res
, &pp
->io_base
);
454 ret
= devm_request_pci_bus_resources(&pdev
->dev
, &res
);
458 /* Get the I/O and memory ranges from DT */
459 resource_list_for_each_entry(win
, &res
) {
460 switch (resource_type(win
->res
)) {
463 pp
->io
->name
= "I/O";
464 pp
->io_size
= resource_size(pp
->io
);
465 pp
->io_bus_addr
= pp
->io
->start
- win
->offset
;
466 ret
= pci_remap_iospace(pp
->io
, pp
->io_base
);
468 dev_warn(pp
->dev
, "error %d: failed to map resource %pR\n",
473 pp
->mem
->name
= "MEM";
474 pp
->mem_size
= resource_size(pp
->mem
);
475 pp
->mem_bus_addr
= pp
->mem
->start
- win
->offset
;
479 pp
->cfg0_size
= resource_size(pp
->cfg
)/2;
480 pp
->cfg1_size
= resource_size(pp
->cfg
)/2;
481 pp
->cfg0_base
= pp
->cfg
->start
;
482 pp
->cfg1_base
= pp
->cfg
->start
+ pp
->cfg0_size
;
491 pp
->dbi_base
= devm_ioremap(pp
->dev
, pp
->cfg
->start
,
492 resource_size(pp
->cfg
));
494 dev_err(pp
->dev
, "error with ioremap\n");
500 pp
->mem_base
= pp
->mem
->start
;
502 if (!pp
->va_cfg0_base
) {
503 pp
->va_cfg0_base
= devm_ioremap(pp
->dev
, pp
->cfg0_base
,
505 if (!pp
->va_cfg0_base
) {
506 dev_err(pp
->dev
, "error with ioremap in function\n");
512 if (!pp
->va_cfg1_base
) {
513 pp
->va_cfg1_base
= devm_ioremap(pp
->dev
, pp
->cfg1_base
,
515 if (!pp
->va_cfg1_base
) {
516 dev_err(pp
->dev
, "error with ioremap\n");
522 ret
= of_property_read_u32(np
, "num-lanes", &pp
->lanes
);
526 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
527 if (!pp
->ops
->msi_host_init
) {
528 pp
->irq_domain
= irq_domain_add_linear(pp
->dev
->of_node
,
529 MAX_MSI_IRQS
, &msi_domain_ops
,
531 if (!pp
->irq_domain
) {
532 dev_err(pp
->dev
, "irq domain init failed\n");
537 for (i
= 0; i
< MAX_MSI_IRQS
; i
++)
538 irq_create_mapping(pp
->irq_domain
, i
);
540 ret
= pp
->ops
->msi_host_init(pp
, &dw_pcie_msi_chip
);
546 if (pp
->ops
->host_init
)
547 pp
->ops
->host_init(pp
);
549 pp
->root_bus_nr
= pp
->busn
->start
;
550 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
551 bus
= pci_scan_root_bus_msi(pp
->dev
, pp
->root_bus_nr
,
552 &dw_pcie_ops
, pp
, &res
,
554 dw_pcie_msi_chip
.dev
= pp
->dev
;
556 bus
= pci_scan_root_bus(pp
->dev
, pp
->root_bus_nr
, &dw_pcie_ops
,
563 if (pp
->ops
->scan_bus
)
564 pp
->ops
->scan_bus(pp
);
567 /* support old dtbs that incorrectly describe IRQs */
568 pci_fixup_irqs(pci_common_swizzle
, of_irq_parse_and_map_pci
);
571 pci_bus_size_bridges(bus
);
572 pci_bus_assign_resources(bus
);
574 list_for_each_entry(child
, &bus
->children
, node
)
575 pcie_bus_configure_settings(child
);
577 pci_bus_add_devices(bus
);
581 pci_free_resource_list(&res
);
585 static int dw_pcie_rd_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
586 u32 devfn
, int where
, int size
, u32
*val
)
589 u32 busdev
, cfg_size
;
591 void __iomem
*va_cfg_base
;
593 if (pp
->ops
->rd_other_conf
)
594 return pp
->ops
->rd_other_conf(pp
, bus
, devfn
, where
, size
, val
);
596 busdev
= PCIE_ATU_BUS(bus
->number
) | PCIE_ATU_DEV(PCI_SLOT(devfn
)) |
597 PCIE_ATU_FUNC(PCI_FUNC(devfn
));
599 if (bus
->parent
->number
== pp
->root_bus_nr
) {
600 type
= PCIE_ATU_TYPE_CFG0
;
601 cpu_addr
= pp
->cfg0_base
;
602 cfg_size
= pp
->cfg0_size
;
603 va_cfg_base
= pp
->va_cfg0_base
;
605 type
= PCIE_ATU_TYPE_CFG1
;
606 cpu_addr
= pp
->cfg1_base
;
607 cfg_size
= pp
->cfg1_size
;
608 va_cfg_base
= pp
->va_cfg1_base
;
611 dw_pcie_prog_outbound_atu(pp
, PCIE_ATU_REGION_INDEX0
,
614 ret
= dw_pcie_cfg_read(va_cfg_base
+ where
, size
, val
);
615 dw_pcie_prog_outbound_atu(pp
, PCIE_ATU_REGION_INDEX0
,
616 PCIE_ATU_TYPE_IO
, pp
->io_base
,
617 pp
->io_bus_addr
, pp
->io_size
);
622 static int dw_pcie_wr_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
623 u32 devfn
, int where
, int size
, u32 val
)
626 u32 busdev
, cfg_size
;
628 void __iomem
*va_cfg_base
;
630 if (pp
->ops
->wr_other_conf
)
631 return pp
->ops
->wr_other_conf(pp
, bus
, devfn
, where
, size
, val
);
633 busdev
= PCIE_ATU_BUS(bus
->number
) | PCIE_ATU_DEV(PCI_SLOT(devfn
)) |
634 PCIE_ATU_FUNC(PCI_FUNC(devfn
));
636 if (bus
->parent
->number
== pp
->root_bus_nr
) {
637 type
= PCIE_ATU_TYPE_CFG0
;
638 cpu_addr
= pp
->cfg0_base
;
639 cfg_size
= pp
->cfg0_size
;
640 va_cfg_base
= pp
->va_cfg0_base
;
642 type
= PCIE_ATU_TYPE_CFG1
;
643 cpu_addr
= pp
->cfg1_base
;
644 cfg_size
= pp
->cfg1_size
;
645 va_cfg_base
= pp
->va_cfg1_base
;
648 dw_pcie_prog_outbound_atu(pp
, PCIE_ATU_REGION_INDEX0
,
651 ret
= dw_pcie_cfg_write(va_cfg_base
+ where
, size
, val
);
652 dw_pcie_prog_outbound_atu(pp
, PCIE_ATU_REGION_INDEX0
,
653 PCIE_ATU_TYPE_IO
, pp
->io_base
,
654 pp
->io_bus_addr
, pp
->io_size
);
659 static int dw_pcie_valid_config(struct pcie_port
*pp
,
660 struct pci_bus
*bus
, int dev
)
662 /* If there is no link, then there is no device */
663 if (bus
->number
!= pp
->root_bus_nr
) {
664 if (!dw_pcie_link_up(pp
))
668 /* access only one slot on each root port */
669 if (bus
->number
== pp
->root_bus_nr
&& dev
> 0)
673 * do not read more than one device on the bus directly attached
674 * to RC's (Virtual Bridge's) DS side.
676 if (bus
->primary
== pp
->root_bus_nr
&& dev
> 0)
682 static int dw_pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
685 struct pcie_port
*pp
= bus
->sysdata
;
687 if (dw_pcie_valid_config(pp
, bus
, PCI_SLOT(devfn
)) == 0) {
689 return PCIBIOS_DEVICE_NOT_FOUND
;
692 if (bus
->number
== pp
->root_bus_nr
)
693 return dw_pcie_rd_own_conf(pp
, where
, size
, val
);
695 return dw_pcie_rd_other_conf(pp
, bus
, devfn
, where
, size
, val
);
698 static int dw_pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
699 int where
, int size
, u32 val
)
701 struct pcie_port
*pp
= bus
->sysdata
;
703 if (dw_pcie_valid_config(pp
, bus
, PCI_SLOT(devfn
)) == 0)
704 return PCIBIOS_DEVICE_NOT_FOUND
;
706 if (bus
->number
== pp
->root_bus_nr
)
707 return dw_pcie_wr_own_conf(pp
, where
, size
, val
);
709 return dw_pcie_wr_other_conf(pp
, bus
, devfn
, where
, size
, val
);
712 static struct pci_ops dw_pcie_ops
= {
713 .read
= dw_pcie_rd_conf
,
714 .write
= dw_pcie_wr_conf
,
717 void dw_pcie_setup_rc(struct pcie_port
*pp
)
721 /* set the number of lanes */
722 dw_pcie_readl_rc(pp
, PCIE_PORT_LINK_CONTROL
, &val
);
723 val
&= ~PORT_LINK_MODE_MASK
;
726 val
|= PORT_LINK_MODE_1_LANES
;
729 val
|= PORT_LINK_MODE_2_LANES
;
732 val
|= PORT_LINK_MODE_4_LANES
;
735 val
|= PORT_LINK_MODE_8_LANES
;
738 dev_err(pp
->dev
, "num-lanes %u: invalid value\n", pp
->lanes
);
741 dw_pcie_writel_rc(pp
, val
, PCIE_PORT_LINK_CONTROL
);
743 /* set link width speed control register */
744 dw_pcie_readl_rc(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, &val
);
745 val
&= ~PORT_LOGIC_LINK_WIDTH_MASK
;
748 val
|= PORT_LOGIC_LINK_WIDTH_1_LANES
;
751 val
|= PORT_LOGIC_LINK_WIDTH_2_LANES
;
754 val
|= PORT_LOGIC_LINK_WIDTH_4_LANES
;
757 val
|= PORT_LOGIC_LINK_WIDTH_8_LANES
;
760 dw_pcie_writel_rc(pp
, val
, PCIE_LINK_WIDTH_SPEED_CONTROL
);
763 dw_pcie_writel_rc(pp
, 0x00000004, PCI_BASE_ADDRESS_0
);
764 dw_pcie_writel_rc(pp
, 0x00000000, PCI_BASE_ADDRESS_1
);
766 /* setup interrupt pins */
767 dw_pcie_readl_rc(pp
, PCI_INTERRUPT_LINE
, &val
);
770 dw_pcie_writel_rc(pp
, val
, PCI_INTERRUPT_LINE
);
772 /* setup bus numbers */
773 dw_pcie_readl_rc(pp
, PCI_PRIMARY_BUS
, &val
);
776 dw_pcie_writel_rc(pp
, val
, PCI_PRIMARY_BUS
);
778 /* setup command register */
779 dw_pcie_readl_rc(pp
, PCI_COMMAND
, &val
);
781 val
|= PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
782 PCI_COMMAND_MASTER
| PCI_COMMAND_SERR
;
783 dw_pcie_writel_rc(pp
, val
, PCI_COMMAND
);
786 * If the platform provides ->rd_other_conf, it means the platform
787 * uses its own address translation component rather than ATU, so
788 * we should not program the ATU here.
790 if (!pp
->ops
->rd_other_conf
)
791 dw_pcie_prog_outbound_atu(pp
, PCIE_ATU_REGION_INDEX1
,
792 PCIE_ATU_TYPE_MEM
, pp
->mem_base
,
793 pp
->mem_bus_addr
, pp
->mem_size
);
795 dw_pcie_wr_own_conf(pp
, PCI_BASE_ADDRESS_0
, 4, 0);
797 /* program correct class for RC */
798 dw_pcie_wr_own_conf(pp
, PCI_CLASS_DEVICE
, 2, PCI_CLASS_BRIDGE_PCI
);
800 dw_pcie_rd_own_conf(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, 4, &val
);
801 val
|= PORT_LOGIC_SPEED_CHANGE
;
802 dw_pcie_wr_own_conf(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, 4, val
);