drivers/pci/host/pcie-designware.h

   1 /*
   2  * Synopsys Designware PCIe host controller driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Author: Jingoo Han <jg1.han@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef _PCIE_DESIGNWARE_H
  15 #define _PCIE_DESIGNWARE_H
  16
  17 /*
  18  * Maximum number of MSI IRQs can be 256 per controller. But keep
  19  * it 32 as of now. Probably we will never need more than 32. If needed,
  20  * then increment it in multiple of 32.
  21  */
  22 #define MAX_MSI_IRQS                    32
  23 #define MAX_MSI_CTRLS                   (MAX_MSI_IRQS / 32)
  24
  25 struct pcie_port {
  26         struct device           *dev;
  27         u8                      root_bus_nr;
  28         void __iomem            *dbi_base;
  29         u64                     cfg0_base;
  30         u64                     cfg0_mod_base;
  31         void __iomem            *va_cfg0_base;
  32         u32                     cfg0_size;
  33         u64                     cfg1_base;
  34         u64                     cfg1_mod_base;
  35         void __iomem            *va_cfg1_base;
  36         u32                     cfg1_size;
  37         u64                     io_base;
  38         u64                     io_mod_base;
  39         phys_addr_t             io_bus_addr;
  40         u32                     io_size;
  41         u64                     mem_base;
  42         u64                     mem_mod_base;
  43         phys_addr_t             mem_bus_addr;
  44         u32                     mem_size;
  45         struct resource         cfg;
  46         struct resource         io;
  47         struct resource         mem;
  48         struct resource         busn;
  49         int                     irq;
  50         u32                     lanes;
  51         struct pcie_host_ops    *ops;
  52         int                     msi_irq;
  53         struct irq_domain       *irq_domain;
  54         unsigned long           msi_data;
  55         DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
  56 };
  57
  58 struct pcie_host_ops {
  59         void (*readl_rc)(struct pcie_port *pp,
  60                         void __iomem *dbi_base, u32 *val);
  61         void (*writel_rc)(struct pcie_port *pp,
  62                         u32 val, void __iomem *dbi_base);
  63         int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
  64         int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
  65         int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
  66                         unsigned int devfn, int where, int size, u32 *val);
  67         int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
  68                         unsigned int devfn, int where, int size, u32 val);
  69         int (*link_up)(struct pcie_port *pp);
  70         void (*host_init)(struct pcie_port *pp);
  71         void (*msi_set_irq)(struct pcie_port *pp, int irq);
  72         void (*msi_clear_irq)(struct pcie_port *pp, int irq);
  73         u32 (*get_msi_addr)(struct pcie_port *pp);
  74         u32 (*get_msi_data)(struct pcie_port *pp, int pos);
  75         void (*scan_bus)(struct pcie_port *pp);
  76         int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
  77 };
  78
  79 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
  80 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
  81 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
  82 void dw_pcie_msi_init(struct pcie_port *pp);
  83 int dw_pcie_link_up(struct pcie_port *pp);
  84 void dw_pcie_setup_rc(struct pcie_port *pp);
  85 int dw_pcie_host_init(struct pcie_port *pp);
  86
  87 #endif /* _PCIE_DESIGNWARE_H */