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PCI: pciehp: ignore undefined bit in link status register
[deliverable/linux.git] / drivers / pci / hotplug / pciehp_hpc.c
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
45 struct ctrl_reg {
46 u8 cap_id;
47 u8 nxt_ptr;
48 u16 cap_reg;
49 u32 dev_cap;
50 u16 dev_ctrl;
51 u16 dev_status;
52 u32 lnk_cap;
53 u16 lnk_ctrl;
54 u16 lnk_status;
55 u32 slot_cap;
56 u16 slot_ctrl;
57 u16 slot_status;
58 u16 root_ctrl;
59 u16 rsvp;
60 u32 root_status;
61 } __attribute__ ((packed));
62
63 /* offsets to the controller registers based on the above structure layout */
64 enum ctrl_offsets {
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
79 };
80
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
82 {
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
85 }
86
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
88 {
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
91 }
92
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
94 {
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
97 }
98
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
100 {
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
103 }
104
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
110
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
119
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
124
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
128 #define LINK_ACTIVE_REPORTING 0x00100000
129
130 /* Link Width Encoding */
131 #define LNK_X1 0x01
132 #define LNK_X2 0x02
133 #define LNK_X4 0x04
134 #define LNK_X8 0x08
135 #define LNK_X12 0x0C
136 #define LNK_X16 0x10
137 #define LNK_X32 0x20
138
139 /*Field definitions of Link Status Register */
140 #define LNK_SPEED 0x000F
141 #define NEG_LINK_WD 0x03F0
142 #define LNK_TRN_ERR 0x0400
143 #define LNK_TRN 0x0800
144 #define SLOT_CLK_CONF 0x1000
145 #define LINK_ACTIVE 0x2000
146
147 /* Field definitions in Slot Capabilities Register */
148 #define ATTN_BUTTN_PRSN 0x00000001
149 #define PWR_CTRL_PRSN 0x00000002
150 #define MRL_SENS_PRSN 0x00000004
151 #define ATTN_LED_PRSN 0x00000008
152 #define PWR_LED_PRSN 0x00000010
153 #define HP_SUPR_RM_SUP 0x00000020
154 #define HP_CAP 0x00000040
155 #define SLOT_PWR_VALUE 0x000003F8
156 #define SLOT_PWR_LIMIT 0x00000C00
157 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
158
159 /* Field definitions in Slot Control Register */
160 #define ATTN_BUTTN_ENABLE 0x0001
161 #define PWR_FAULT_DETECT_ENABLE 0x0002
162 #define MRL_DETECT_ENABLE 0x0004
163 #define PRSN_DETECT_ENABLE 0x0008
164 #define CMD_CMPL_INTR_ENABLE 0x0010
165 #define HP_INTR_ENABLE 0x0020
166 #define ATTN_LED_CTRL 0x00C0
167 #define PWR_LED_CTRL 0x0300
168 #define PWR_CTRL 0x0400
169 #define EMI_CTRL 0x0800
170
171 /* Attention indicator and Power indicator states */
172 #define LED_ON 0x01
173 #define LED_BLINK 0x10
174 #define LED_OFF 0x11
175
176 /* Power Control Command */
177 #define POWER_ON 0
178 #define POWER_OFF 0x0400
179
180 /* EMI Status defines */
181 #define EMI_DISENGAGED 0
182 #define EMI_ENGAGED 1
183
184 /* Field definitions in Slot Status Register */
185 #define ATTN_BUTTN_PRESSED 0x0001
186 #define PWR_FAULT_DETECTED 0x0002
187 #define MRL_SENS_CHANGED 0x0004
188 #define PRSN_DETECT_CHANGED 0x0008
189 #define CMD_COMPLETED 0x0010
190 #define MRL_STATE 0x0020
191 #define PRSN_STATE 0x0040
192 #define EMI_STATE 0x0080
193 #define EMI_STATUS_BIT 7
194
195 static irqreturn_t pcie_isr(int irq, void *dev_id);
196 static void start_int_poll_timer(struct controller *ctrl, int sec);
197
198 /* This is the interrupt polling timeout function. */
199 static void int_poll_timeout(unsigned long data)
200 {
201 struct controller *ctrl = (struct controller *)data;
202
203 /* Poll for interrupt events. regs == NULL => polling */
204 pcie_isr(0, ctrl);
205
206 init_timer(&ctrl->poll_timer);
207 if (!pciehp_poll_time)
208 pciehp_poll_time = 2; /* default polling interval is 2 sec */
209
210 start_int_poll_timer(ctrl, pciehp_poll_time);
211 }
212
213 /* This function starts the interrupt polling timer. */
214 static void start_int_poll_timer(struct controller *ctrl, int sec)
215 {
216 /* Clamp to sane value */
217 if ((sec <= 0) || (sec > 60))
218 sec = 2;
219
220 ctrl->poll_timer.function = &int_poll_timeout;
221 ctrl->poll_timer.data = (unsigned long)ctrl;
222 ctrl->poll_timer.expires = jiffies + sec * HZ;
223 add_timer(&ctrl->poll_timer);
224 }
225
226 static inline int pciehp_request_irq(struct controller *ctrl)
227 {
228 int retval, irq = ctrl->pcie->irq;
229
230 /* Install interrupt polling timer. Start with 10 sec delay */
231 if (pciehp_poll_mode) {
232 init_timer(&ctrl->poll_timer);
233 start_int_poll_timer(ctrl, 10);
234 return 0;
235 }
236
237 /* Installs the interrupt handler */
238 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
239 if (retval)
240 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
241 irq);
242 return retval;
243 }
244
245 static inline void pciehp_free_irq(struct controller *ctrl)
246 {
247 if (pciehp_poll_mode)
248 del_timer_sync(&ctrl->poll_timer);
249 else
250 free_irq(ctrl->pcie->irq, ctrl);
251 }
252
253 static int pcie_poll_cmd(struct controller *ctrl)
254 {
255 u16 slot_status;
256 int timeout = 1000;
257
258 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
259 if (slot_status & CMD_COMPLETED) {
260 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
261 return 1;
262 }
263 }
264 while (timeout > 0) {
265 msleep(10);
266 timeout -= 10;
267 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
268 if (slot_status & CMD_COMPLETED) {
269 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
270 return 1;
271 }
272 }
273 }
274 return 0; /* timeout */
275 }
276
277 static void pcie_wait_cmd(struct controller *ctrl, int poll)
278 {
279 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
280 unsigned long timeout = msecs_to_jiffies(msecs);
281 int rc;
282
283 if (poll)
284 rc = pcie_poll_cmd(ctrl);
285 else
286 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
287 if (!rc)
288 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
289 }
290
291 /**
292 * pcie_write_cmd - Issue controller command
293 * @ctrl: controller to which the command is issued
294 * @cmd: command value written to slot control register
295 * @mask: bitmask of slot control register to be modified
296 */
297 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
298 {
299 int retval = 0;
300 u16 slot_status;
301 u16 slot_ctrl;
302
303 mutex_lock(&ctrl->ctrl_lock);
304
305 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
306 if (retval) {
307 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
308 __func__);
309 goto out;
310 }
311
312 if (slot_status & CMD_COMPLETED) {
313 if (!ctrl->no_cmd_complete) {
314 /*
315 * After 1 sec and CMD_COMPLETED still not set, just
316 * proceed forward to issue the next command according
317 * to spec. Just print out the error message.
318 */
319 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
320 } else if (!NO_CMD_CMPL(ctrl)) {
321 /*
322 * This controller semms to notify of command completed
323 * event even though it supports none of power
324 * controller, attention led, power led and EMI.
325 */
326 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
327 "wait for command completed event.\n");
328 ctrl->no_cmd_complete = 0;
329 } else {
330 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
331 "the controller is broken.\n");
332 }
333 }
334
335 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
336 if (retval) {
337 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
338 goto out;
339 }
340
341 slot_ctrl &= ~mask;
342 slot_ctrl |= (cmd & mask);
343 ctrl->cmd_busy = 1;
344 smp_mb();
345 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
346 if (retval)
347 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
348
349 /*
350 * Wait for command completion.
351 */
352 if (!retval && !ctrl->no_cmd_complete) {
353 int poll = 0;
354 /*
355 * if hotplug interrupt is not enabled or command
356 * completed interrupt is not enabled, we need to poll
357 * command completed event.
358 */
359 if (!(slot_ctrl & HP_INTR_ENABLE) ||
360 !(slot_ctrl & CMD_CMPL_INTR_ENABLE))
361 poll = 1;
362 pcie_wait_cmd(ctrl, poll);
363 }
364 out:
365 mutex_unlock(&ctrl->ctrl_lock);
366 return retval;
367 }
368
369 static inline int check_link_active(struct controller *ctrl)
370 {
371 u16 link_status;
372
373 if (pciehp_readw(ctrl, LNKSTATUS, &link_status))
374 return 0;
375 return !!(link_status & LINK_ACTIVE);
376 }
377
378 static void pcie_wait_link_active(struct controller *ctrl)
379 {
380 int timeout = 1000;
381
382 if (check_link_active(ctrl))
383 return;
384 while (timeout > 0) {
385 msleep(10);
386 timeout -= 10;
387 if (check_link_active(ctrl))
388 return;
389 }
390 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
391 }
392
393 static int hpc_check_lnk_status(struct controller *ctrl)
394 {
395 u16 lnk_status;
396 int retval = 0;
397
398 /*
399 * Data Link Layer Link Active Reporting must be capable for
400 * hot-plug capable downstream port. But old controller might
401 * not implement it. In this case, we wait for 1000 ms.
402 */
403 if (ctrl->link_active_reporting){
404 /* Wait for Data Link Layer Link Active bit to be set */
405 pcie_wait_link_active(ctrl);
406 /*
407 * We must wait for 100 ms after the Data Link Layer
408 * Link Active bit reads 1b before initiating a
409 * configuration access to the hot added device.
410 */
411 msleep(100);
412 } else
413 msleep(1000);
414
415 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
416 if (retval) {
417 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
418 return retval;
419 }
420
421 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
422 if ((lnk_status & LNK_TRN) || !(lnk_status & NEG_LINK_WD)) {
423 ctrl_err(ctrl, "Link Training Error occurs \n");
424 retval = -1;
425 return retval;
426 }
427
428 return retval;
429 }
430
431 static int hpc_get_attention_status(struct slot *slot, u8 *status)
432 {
433 struct controller *ctrl = slot->ctrl;
434 u16 slot_ctrl;
435 u8 atten_led_state;
436 int retval = 0;
437
438 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
439 if (retval) {
440 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
441 return retval;
442 }
443
444 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
445 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
446
447 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
448
449 switch (atten_led_state) {
450 case 0:
451 *status = 0xFF; /* Reserved */
452 break;
453 case 1:
454 *status = 1; /* On */
455 break;
456 case 2:
457 *status = 2; /* Blink */
458 break;
459 case 3:
460 *status = 0; /* Off */
461 break;
462 default:
463 *status = 0xFF;
464 break;
465 }
466
467 return 0;
468 }
469
470 static int hpc_get_power_status(struct slot *slot, u8 *status)
471 {
472 struct controller *ctrl = slot->ctrl;
473 u16 slot_ctrl;
474 u8 pwr_state;
475 int retval = 0;
476
477 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
478 if (retval) {
479 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
480 return retval;
481 }
482 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
483 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
484
485 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
486
487 switch (pwr_state) {
488 case 0:
489 *status = 1;
490 break;
491 case 1:
492 *status = 0;
493 break;
494 default:
495 *status = 0xFF;
496 break;
497 }
498
499 return retval;
500 }
501
502 static int hpc_get_latch_status(struct slot *slot, u8 *status)
503 {
504 struct controller *ctrl = slot->ctrl;
505 u16 slot_status;
506 int retval = 0;
507
508 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
509 if (retval) {
510 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
511 __func__);
512 return retval;
513 }
514
515 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
516
517 return 0;
518 }
519
520 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
521 {
522 struct controller *ctrl = slot->ctrl;
523 u16 slot_status;
524 u8 card_state;
525 int retval = 0;
526
527 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
528 if (retval) {
529 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
530 __func__);
531 return retval;
532 }
533 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
534 *status = (card_state == 1) ? 1 : 0;
535
536 return 0;
537 }
538
539 static int hpc_query_power_fault(struct slot *slot)
540 {
541 struct controller *ctrl = slot->ctrl;
542 u16 slot_status;
543 u8 pwr_fault;
544 int retval = 0;
545
546 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
547 if (retval) {
548 ctrl_err(ctrl, "Cannot check for power fault\n");
549 return retval;
550 }
551 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
552
553 return pwr_fault;
554 }
555
556 static int hpc_get_emi_status(struct slot *slot, u8 *status)
557 {
558 struct controller *ctrl = slot->ctrl;
559 u16 slot_status;
560 int retval = 0;
561
562 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
563 if (retval) {
564 ctrl_err(ctrl, "Cannot check EMI status\n");
565 return retval;
566 }
567 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
568
569 return retval;
570 }
571
572 static int hpc_toggle_emi(struct slot *slot)
573 {
574 u16 slot_cmd;
575 u16 cmd_mask;
576 int rc;
577
578 slot_cmd = EMI_CTRL;
579 cmd_mask = EMI_CTRL;
580 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
581 slot->last_emi_toggle = get_seconds();
582
583 return rc;
584 }
585
586 static int hpc_set_attention_status(struct slot *slot, u8 value)
587 {
588 struct controller *ctrl = slot->ctrl;
589 u16 slot_cmd;
590 u16 cmd_mask;
591 int rc;
592
593 cmd_mask = ATTN_LED_CTRL;
594 switch (value) {
595 case 0 : /* turn off */
596 slot_cmd = 0x00C0;
597 break;
598 case 1: /* turn on */
599 slot_cmd = 0x0040;
600 break;
601 case 2: /* turn blink */
602 slot_cmd = 0x0080;
603 break;
604 default:
605 return -1;
606 }
607 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
608 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
609 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
610
611 return rc;
612 }
613
614 static void hpc_set_green_led_on(struct slot *slot)
615 {
616 struct controller *ctrl = slot->ctrl;
617 u16 slot_cmd;
618 u16 cmd_mask;
619
620 slot_cmd = 0x0100;
621 cmd_mask = PWR_LED_CTRL;
622 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
623 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
624 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
625 }
626
627 static void hpc_set_green_led_off(struct slot *slot)
628 {
629 struct controller *ctrl = slot->ctrl;
630 u16 slot_cmd;
631 u16 cmd_mask;
632
633 slot_cmd = 0x0300;
634 cmd_mask = PWR_LED_CTRL;
635 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
636 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
637 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
638 }
639
640 static void hpc_set_green_led_blink(struct slot *slot)
641 {
642 struct controller *ctrl = slot->ctrl;
643 u16 slot_cmd;
644 u16 cmd_mask;
645
646 slot_cmd = 0x0200;
647 cmd_mask = PWR_LED_CTRL;
648 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
649 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
650 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
651 }
652
653 static int hpc_power_on_slot(struct slot * slot)
654 {
655 struct controller *ctrl = slot->ctrl;
656 u16 slot_cmd;
657 u16 cmd_mask;
658 u16 slot_status;
659 int retval = 0;
660
661 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
662
663 /* Clear sticky power-fault bit from previous power failures */
664 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
665 if (retval) {
666 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
667 __func__);
668 return retval;
669 }
670 slot_status &= PWR_FAULT_DETECTED;
671 if (slot_status) {
672 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
673 if (retval) {
674 ctrl_err(ctrl,
675 "%s: Cannot write to SLOTSTATUS register\n",
676 __func__);
677 return retval;
678 }
679 }
680
681 slot_cmd = POWER_ON;
682 cmd_mask = PWR_CTRL;
683 /* Enable detection that we turned off at slot power-off time */
684 if (!pciehp_poll_mode) {
685 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
686 PRSN_DETECT_ENABLE);
687 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
688 PRSN_DETECT_ENABLE);
689 }
690
691 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
692
693 if (retval) {
694 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
695 return -1;
696 }
697 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
698 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
699
700 return retval;
701 }
702
703 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
704 {
705 struct pci_dev *dev = ctrl->pci_dev;
706 int pos;
707 u32 reg;
708
709 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
710 if (!pos)
711 return 0;
712 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
713 if (reg & PCI_ERR_COR_BAD_DLLP)
714 return 0;
715 reg |= PCI_ERR_COR_BAD_DLLP;
716 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
717 return 1;
718 }
719
720 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
721 {
722 struct pci_dev *dev = ctrl->pci_dev;
723 u32 reg;
724 int pos;
725
726 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
727 if (!pos)
728 return;
729 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
730 if (!(reg & PCI_ERR_COR_BAD_DLLP))
731 return;
732 reg &= ~PCI_ERR_COR_BAD_DLLP;
733 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
734 }
735
736 static int hpc_power_off_slot(struct slot * slot)
737 {
738 struct controller *ctrl = slot->ctrl;
739 u16 slot_cmd;
740 u16 cmd_mask;
741 int retval = 0;
742 int changed;
743
744 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
745
746 /*
747 * Set Bad DLLP Mask bit in Correctable Error Mask
748 * Register. This is the workaround against Bad DLLP error
749 * that sometimes happens during turning power off the slot
750 * which conforms to PCI Express 1.0a spec.
751 */
752 changed = pcie_mask_bad_dllp(ctrl);
753
754 slot_cmd = POWER_OFF;
755 cmd_mask = PWR_CTRL;
756 /*
757 * If we get MRL or presence detect interrupts now, the isr
758 * will notice the sticky power-fault bit too and issue power
759 * indicator change commands. This will lead to an endless loop
760 * of command completions, since the power-fault bit remains on
761 * till the slot is powered on again.
762 */
763 if (!pciehp_poll_mode) {
764 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
765 PRSN_DETECT_ENABLE);
766 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
767 PRSN_DETECT_ENABLE);
768 }
769
770 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
771 if (retval) {
772 ctrl_err(ctrl, "Write command failed!\n");
773 retval = -1;
774 goto out;
775 }
776 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
777 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
778 out:
779 if (changed)
780 pcie_unmask_bad_dllp(ctrl);
781
782 return retval;
783 }
784
785 static irqreturn_t pcie_isr(int irq, void *dev_id)
786 {
787 struct controller *ctrl = (struct controller *)dev_id;
788 u16 detected, intr_loc;
789 struct slot *p_slot;
790
791 /*
792 * In order to guarantee that all interrupt events are
793 * serviced, we need to re-inspect Slot Status register after
794 * clearing what is presumed to be the last pending interrupt.
795 */
796 intr_loc = 0;
797 do {
798 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
799 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
800 __func__);
801 return IRQ_NONE;
802 }
803
804 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
805 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
806 CMD_COMPLETED);
807 intr_loc |= detected;
808 if (!intr_loc)
809 return IRQ_NONE;
810 if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) {
811 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
812 __func__);
813 return IRQ_NONE;
814 }
815 } while (detected);
816
817 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
818
819 /* Check Command Complete Interrupt Pending */
820 if (intr_loc & CMD_COMPLETED) {
821 ctrl->cmd_busy = 0;
822 smp_mb();
823 wake_up(&ctrl->queue);
824 }
825
826 if (!(intr_loc & ~CMD_COMPLETED))
827 return IRQ_HANDLED;
828
829 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
830
831 /* Check MRL Sensor Changed */
832 if (intr_loc & MRL_SENS_CHANGED)
833 pciehp_handle_switch_change(p_slot);
834
835 /* Check Attention Button Pressed */
836 if (intr_loc & ATTN_BUTTN_PRESSED)
837 pciehp_handle_attention_button(p_slot);
838
839 /* Check Presence Detect Changed */
840 if (intr_loc & PRSN_DETECT_CHANGED)
841 pciehp_handle_presence_change(p_slot);
842
843 /* Check Power Fault Detected */
844 if (intr_loc & PWR_FAULT_DETECTED)
845 pciehp_handle_power_fault(p_slot);
846
847 return IRQ_HANDLED;
848 }
849
850 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
851 {
852 struct controller *ctrl = slot->ctrl;
853 enum pcie_link_speed lnk_speed;
854 u32 lnk_cap;
855 int retval = 0;
856
857 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
858 if (retval) {
859 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
860 return retval;
861 }
862
863 switch (lnk_cap & 0x000F) {
864 case 1:
865 lnk_speed = PCIE_2PT5GB;
866 break;
867 default:
868 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
869 break;
870 }
871
872 *value = lnk_speed;
873 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
874
875 return retval;
876 }
877
878 static int hpc_get_max_lnk_width(struct slot *slot,
879 enum pcie_link_width *value)
880 {
881 struct controller *ctrl = slot->ctrl;
882 enum pcie_link_width lnk_wdth;
883 u32 lnk_cap;
884 int retval = 0;
885
886 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
887 if (retval) {
888 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
889 return retval;
890 }
891
892 switch ((lnk_cap & 0x03F0) >> 4){
893 case 0:
894 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
895 break;
896 case 1:
897 lnk_wdth = PCIE_LNK_X1;
898 break;
899 case 2:
900 lnk_wdth = PCIE_LNK_X2;
901 break;
902 case 4:
903 lnk_wdth = PCIE_LNK_X4;
904 break;
905 case 8:
906 lnk_wdth = PCIE_LNK_X8;
907 break;
908 case 12:
909 lnk_wdth = PCIE_LNK_X12;
910 break;
911 case 16:
912 lnk_wdth = PCIE_LNK_X16;
913 break;
914 case 32:
915 lnk_wdth = PCIE_LNK_X32;
916 break;
917 default:
918 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
919 break;
920 }
921
922 *value = lnk_wdth;
923 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
924
925 return retval;
926 }
927
928 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
929 {
930 struct controller *ctrl = slot->ctrl;
931 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
932 int retval = 0;
933 u16 lnk_status;
934
935 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
936 if (retval) {
937 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
938 __func__);
939 return retval;
940 }
941
942 switch (lnk_status & 0x0F) {
943 case 1:
944 lnk_speed = PCIE_2PT5GB;
945 break;
946 default:
947 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
948 break;
949 }
950
951 *value = lnk_speed;
952 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
953
954 return retval;
955 }
956
957 static int hpc_get_cur_lnk_width(struct slot *slot,
958 enum pcie_link_width *value)
959 {
960 struct controller *ctrl = slot->ctrl;
961 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
962 int retval = 0;
963 u16 lnk_status;
964
965 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
966 if (retval) {
967 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
968 __func__);
969 return retval;
970 }
971
972 switch ((lnk_status & 0x03F0) >> 4){
973 case 0:
974 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
975 break;
976 case 1:
977 lnk_wdth = PCIE_LNK_X1;
978 break;
979 case 2:
980 lnk_wdth = PCIE_LNK_X2;
981 break;
982 case 4:
983 lnk_wdth = PCIE_LNK_X4;
984 break;
985 case 8:
986 lnk_wdth = PCIE_LNK_X8;
987 break;
988 case 12:
989 lnk_wdth = PCIE_LNK_X12;
990 break;
991 case 16:
992 lnk_wdth = PCIE_LNK_X16;
993 break;
994 case 32:
995 lnk_wdth = PCIE_LNK_X32;
996 break;
997 default:
998 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
999 break;
1000 }
1001
1002 *value = lnk_wdth;
1003 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
1004
1005 return retval;
1006 }
1007
1008 static void pcie_release_ctrl(struct controller *ctrl);
1009 static struct hpc_ops pciehp_hpc_ops = {
1010 .power_on_slot = hpc_power_on_slot,
1011 .power_off_slot = hpc_power_off_slot,
1012 .set_attention_status = hpc_set_attention_status,
1013 .get_power_status = hpc_get_power_status,
1014 .get_attention_status = hpc_get_attention_status,
1015 .get_latch_status = hpc_get_latch_status,
1016 .get_adapter_status = hpc_get_adapter_status,
1017 .get_emi_status = hpc_get_emi_status,
1018 .toggle_emi = hpc_toggle_emi,
1019
1020 .get_max_bus_speed = hpc_get_max_lnk_speed,
1021 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1022 .get_max_lnk_width = hpc_get_max_lnk_width,
1023 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1024
1025 .query_power_fault = hpc_query_power_fault,
1026 .green_led_on = hpc_set_green_led_on,
1027 .green_led_off = hpc_set_green_led_off,
1028 .green_led_blink = hpc_set_green_led_blink,
1029
1030 .release_ctlr = pcie_release_ctrl,
1031 .check_lnk_status = hpc_check_lnk_status,
1032 };
1033
1034 int pcie_enable_notification(struct controller *ctrl)
1035 {
1036 u16 cmd, mask;
1037
1038 cmd = PRSN_DETECT_ENABLE;
1039 if (ATTN_BUTTN(ctrl))
1040 cmd |= ATTN_BUTTN_ENABLE;
1041 if (POWER_CTRL(ctrl))
1042 cmd |= PWR_FAULT_DETECT_ENABLE;
1043 if (MRL_SENS(ctrl))
1044 cmd |= MRL_DETECT_ENABLE;
1045 if (!pciehp_poll_mode)
1046 cmd |= HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
1047
1048 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
1049 PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
1050
1051 if (pcie_write_cmd(ctrl, cmd, mask)) {
1052 ctrl_err(ctrl, "Cannot enable software notification\n");
1053 return -1;
1054 }
1055 return 0;
1056 }
1057
1058 static void pcie_disable_notification(struct controller *ctrl)
1059 {
1060 u16 mask;
1061 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
1062 PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
1063 if (pcie_write_cmd(ctrl, 0, mask))
1064 ctrl_warn(ctrl, "Cannot disable software notification\n");
1065 }
1066
1067 static int pcie_init_notification(struct controller *ctrl)
1068 {
1069 if (pciehp_request_irq(ctrl))
1070 return -1;
1071 if (pcie_enable_notification(ctrl)) {
1072 pciehp_free_irq(ctrl);
1073 return -1;
1074 }
1075 return 0;
1076 }
1077
1078 static void pcie_shutdown_notification(struct controller *ctrl)
1079 {
1080 pcie_disable_notification(ctrl);
1081 pciehp_free_irq(ctrl);
1082 }
1083
1084 static int pcie_init_slot(struct controller *ctrl)
1085 {
1086 struct slot *slot;
1087
1088 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
1089 if (!slot)
1090 return -ENOMEM;
1091
1092 slot->hp_slot = 0;
1093 slot->ctrl = ctrl;
1094 slot->bus = ctrl->pci_dev->subordinate->number;
1095 slot->device = ctrl->slot_device_offset + slot->hp_slot;
1096 slot->hpc_ops = ctrl->hpc_ops;
1097 slot->number = ctrl->first_slot;
1098 mutex_init(&slot->lock);
1099 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
1100 list_add(&slot->slot_list, &ctrl->slot_list);
1101 return 0;
1102 }
1103
1104 static void pcie_cleanup_slot(struct controller *ctrl)
1105 {
1106 struct slot *slot;
1107 slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
1108 list_del(&slot->slot_list);
1109 cancel_delayed_work(&slot->work);
1110 flush_scheduled_work();
1111 flush_workqueue(pciehp_wq);
1112 kfree(slot);
1113 }
1114
1115 static inline void dbg_ctrl(struct controller *ctrl)
1116 {
1117 int i;
1118 u16 reg16;
1119 struct pci_dev *pdev = ctrl->pci_dev;
1120
1121 if (!pciehp_debug)
1122 return;
1123
1124 ctrl_info(ctrl, "Hotplug Controller:\n");
1125 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
1126 pci_name(pdev), pdev->irq);
1127 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
1128 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
1129 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
1130 pdev->subsystem_device);
1131 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
1132 pdev->subsystem_vendor);
1133 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
1134 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1135 if (!pci_resource_len(pdev, i))
1136 continue;
1137 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
1138 i, (unsigned long long)pci_resource_len(pdev, i),
1139 (unsigned long long)pci_resource_start(pdev, i));
1140 }
1141 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1142 ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot);
1143 ctrl_info(ctrl, " Attention Button : %3s\n",
1144 ATTN_BUTTN(ctrl) ? "yes" : "no");
1145 ctrl_info(ctrl, " Power Controller : %3s\n",
1146 POWER_CTRL(ctrl) ? "yes" : "no");
1147 ctrl_info(ctrl, " MRL Sensor : %3s\n",
1148 MRL_SENS(ctrl) ? "yes" : "no");
1149 ctrl_info(ctrl, " Attention Indicator : %3s\n",
1150 ATTN_LED(ctrl) ? "yes" : "no");
1151 ctrl_info(ctrl, " Power Indicator : %3s\n",
1152 PWR_LED(ctrl) ? "yes" : "no");
1153 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
1154 HP_SUPR_RM(ctrl) ? "yes" : "no");
1155 ctrl_info(ctrl, " EMI Present : %3s\n",
1156 EMI(ctrl) ? "yes" : "no");
1157 ctrl_info(ctrl, " Command Completed : %3s\n",
1158 NO_CMD_CMPL(ctrl) ? "no" : "yes");
1159 pciehp_readw(ctrl, SLOTSTATUS, &reg16);
1160 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
1161 pciehp_readw(ctrl, SLOTCTRL, &reg16);
1162 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
1163 }
1164
1165 struct controller *pcie_init(struct pcie_device *dev)
1166 {
1167 struct controller *ctrl;
1168 u32 slot_cap, link_cap;
1169 struct pci_dev *pdev = dev->port;
1170
1171 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1172 if (!ctrl) {
1173 dev_err(&dev->device, "%s: Out of memory\n", __func__);
1174 goto abort;
1175 }
1176 INIT_LIST_HEAD(&ctrl->slot_list);
1177
1178 ctrl->pcie = dev;
1179 ctrl->pci_dev = pdev;
1180 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1181 if (!ctrl->cap_base) {
1182 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
1183 goto abort_ctrl;
1184 }
1185 if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1186 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
1187 goto abort_ctrl;
1188 }
1189
1190 ctrl->slot_cap = slot_cap;
1191 ctrl->first_slot = slot_cap >> 19;
1192 ctrl->slot_device_offset = 0;
1193 ctrl->num_slots = 1;
1194 ctrl->hpc_ops = &pciehp_hpc_ops;
1195 mutex_init(&ctrl->crit_sect);
1196 mutex_init(&ctrl->ctrl_lock);
1197 init_waitqueue_head(&ctrl->queue);
1198 dbg_ctrl(ctrl);
1199 /*
1200 * Controller doesn't notify of command completion if the "No
1201 * Command Completed Support" bit is set in Slot Capability
1202 * register or the controller supports none of power
1203 * controller, attention led, power led and EMI.
1204 */
1205 if (NO_CMD_CMPL(ctrl) ||
1206 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1207 ctrl->no_cmd_complete = 1;
1208
1209 /* Check if Data Link Layer Link Active Reporting is implemented */
1210 if (pciehp_readl(ctrl, LNKCAP, &link_cap)) {
1211 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1212 goto abort_ctrl;
1213 }
1214 if (link_cap & LINK_ACTIVE_REPORTING) {
1215 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1216 ctrl->link_active_reporting = 1;
1217 }
1218
1219 /* Clear all remaining event bits in Slot Status register */
1220 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f))
1221 goto abort_ctrl;
1222
1223 /* Disable sotfware notification */
1224 pcie_disable_notification(ctrl);
1225
1226 /*
1227 * If this is the first controller to be initialized,
1228 * initialize the pciehp work queue
1229 */
1230 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1231 pciehp_wq = create_singlethread_workqueue("pciehpd");
1232 if (!pciehp_wq)
1233 goto abort_ctrl;
1234 }
1235
1236 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1237 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1238 pdev->subsystem_device);
1239
1240 if (pcie_init_slot(ctrl))
1241 goto abort_ctrl;
1242
1243 if (pcie_init_notification(ctrl))
1244 goto abort_slot;
1245
1246 return ctrl;
1247
1248 abort_slot:
1249 pcie_cleanup_slot(ctrl);
1250 abort_ctrl:
1251 kfree(ctrl);
1252 abort:
1253 return NULL;
1254 }
1255
1256 void pcie_release_ctrl(struct controller *ctrl)
1257 {
1258 pcie_shutdown_notification(ctrl);
1259 pcie_cleanup_slot(ctrl);
1260 /*
1261 * If this is the last controller to be released, destroy the
1262 * pciehp work queue
1263 */
1264 if (atomic_dec_and_test(&pciehp_num_controllers))
1265 destroy_workqueue(pciehp_wq);
1266 kfree(ctrl);
1267 }
Linux kernel - Deliverables
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