drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39 #include <linux/slab.h>
  40
  41 #include "../pci.h"
  42 #include "pciehp.h"
  43
  44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  45 {
  46         struct pci_dev *dev = ctrl->pcie->port;
  47         return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
  48 }
  49
  50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  51 {
  52         struct pci_dev *dev = ctrl->pcie->port;
  53         return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  54 }
  55
  56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  57 {
  58         struct pci_dev *dev = ctrl->pcie->port;
  59         return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
  60 }
  61
  62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
  63 {
  64         struct pci_dev *dev = ctrl->pcie->port;
  65         return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  66 }
  67
  68 /* Power Control Command */
  69 #define POWER_ON        0
  70 #define POWER_OFF       PCI_EXP_SLTCTL_PCC
  71
  72 static irqreturn_t pcie_isr(int irq, void *dev_id);
  73 static void start_int_poll_timer(struct controller *ctrl, int sec);
  74
  75 /* This is the interrupt polling timeout function. */
  76 static void int_poll_timeout(unsigned long data)
  77 {
  78         struct controller *ctrl = (struct controller *)data;
  79
  80         /* Poll for interrupt events.  regs == NULL => polling */
  81         pcie_isr(0, ctrl);
  82
  83         init_timer(&ctrl->poll_timer);
  84         if (!pciehp_poll_time)
  85                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  86
  87         start_int_poll_timer(ctrl, pciehp_poll_time);
  88 }
  89
  90 /* This function starts the interrupt polling timer. */
  91 static void start_int_poll_timer(struct controller *ctrl, int sec)
  92 {
  93         /* Clamp to sane value */
  94         if ((sec <= 0) || (sec > 60))
  95                 sec = 2;
  96
  97         ctrl->poll_timer.function = &int_poll_timeout;
  98         ctrl->poll_timer.data = (unsigned long)ctrl;
  99         ctrl->poll_timer.expires = jiffies + sec * HZ;
 100         add_timer(&ctrl->poll_timer);
 101 }
 102
 103 static inline int pciehp_request_irq(struct controller *ctrl)
 104 {
 105         int retval, irq = ctrl->pcie->irq;
 106
 107         /* Install interrupt polling timer. Start with 10 sec delay */
 108         if (pciehp_poll_mode) {
 109                 init_timer(&ctrl->poll_timer);
 110                 start_int_poll_timer(ctrl, 10);
 111                 return 0;
 112         }
 113
 114         /* Installs the interrupt handler */
 115         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
 116         if (retval)
 117                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
 118                          irq);
 119         return retval;
 120 }
 121
 122 static inline void pciehp_free_irq(struct controller *ctrl)
 123 {
 124         if (pciehp_poll_mode)
 125                 del_timer_sync(&ctrl->poll_timer);
 126         else
 127                 free_irq(ctrl->pcie->irq, ctrl);
 128 }
 129
 130 static int pcie_poll_cmd(struct controller *ctrl)
 131 {
 132         u16 slot_status;
 133         int err, timeout = 1000;
 134
 135         err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 136         if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 137                 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 138                 return 1;
 139         }
 140         while (timeout > 0) {
 141                 msleep(10);
 142                 timeout -= 10;
 143                 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 144                 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 145                         pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 146                         return 1;
 147                 }
 148         }
 149         return 0;       /* timeout */
 150 }
 151
 152 static void pcie_wait_cmd(struct controller *ctrl, int poll)
 153 {
 154         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 155         unsigned long timeout = msecs_to_jiffies(msecs);
 156         int rc;
 157
 158         if (poll)
 159                 rc = pcie_poll_cmd(ctrl);
 160         else
 161                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 162         if (!rc)
 163                 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
 164 }
 165
 166 /**
 167  * pcie_write_cmd - Issue controller command
 168  * @ctrl: controller to which the command is issued
 169  * @cmd:  command value written to slot control register
 170  * @mask: bitmask of slot control register to be modified
 171  */
 172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 173 {
 174         int retval = 0;
 175         u16 slot_status;
 176         u16 slot_ctrl;
 177
 178         mutex_lock(&ctrl->ctrl_lock);
 179
 180         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 181         if (retval) {
 182                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 183                          __func__);
 184                 goto out;
 185         }
 186
 187         if (slot_status & PCI_EXP_SLTSTA_CC) {
 188                 if (!ctrl->no_cmd_complete) {
 189                         /*
 190                          * After 1 sec and CMD_COMPLETED still not set, just
 191                          * proceed forward to issue the next command according
 192                          * to spec. Just print out the error message.
 193                          */
 194                         ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
 195                 } else if (!NO_CMD_CMPL(ctrl)) {
 196                         /*
 197                          * This controller semms to notify of command completed
 198                          * event even though it supports none of power
 199                          * controller, attention led, power led and EMI.
 200                          */
 201                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
 202                                  "wait for command completed event.\n");
 203                         ctrl->no_cmd_complete = 0;
 204                 } else {
 205                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
 206                                  "the controller is broken.\n");
 207                 }
 208         }
 209
 210         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 211         if (retval) {
 212                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 213                 goto out;
 214         }
 215
 216         slot_ctrl &= ~mask;
 217         slot_ctrl |= (cmd & mask);
 218         ctrl->cmd_busy = 1;
 219         smp_mb();
 220         retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
 221         if (retval)
 222                 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
 223
 224         /*
 225          * Wait for command completion.
 226          */
 227         if (!retval && !ctrl->no_cmd_complete) {
 228                 int poll = 0;
 229                 /*
 230                  * if hotplug interrupt is not enabled or command
 231                  * completed interrupt is not enabled, we need to poll
 232                  * command completed event.
 233                  */
 234                 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
 235                     !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
 236                         poll = 1;
 237                 pcie_wait_cmd(ctrl, poll);
 238         }
 239  out:
 240         mutex_unlock(&ctrl->ctrl_lock);
 241         return retval;
 242 }
 243
 244 static inline int check_link_active(struct controller *ctrl)
 245 {
 246         u16 link_status;
 247
 248         if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
 249                 return 0;
 250         return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
 251 }
 252
 253 static void pcie_wait_link_active(struct controller *ctrl)
 254 {
 255         int timeout = 1000;
 256
 257         if (check_link_active(ctrl))
 258                 return;
 259         while (timeout > 0) {
 260                 msleep(10);
 261                 timeout -= 10;
 262                 if (check_link_active(ctrl))
 263                         return;
 264         }
 265         ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
 266 }
 267
 268 int pciehp_check_link_status(struct controller *ctrl)
 269 {
 270         u16 lnk_status;
 271         int retval = 0;
 272
 273         /*
 274          * Data Link Layer Link Active Reporting must be capable for
 275          * hot-plug capable downstream port. But old controller might
 276          * not implement it. In this case, we wait for 1000 ms.
 277          */
 278         if (ctrl->link_active_reporting){
 279                 /* Wait for Data Link Layer Link Active bit to be set */
 280                 pcie_wait_link_active(ctrl);
 281                 /*
 282                  * We must wait for 100 ms after the Data Link Layer
 283                  * Link Active bit reads 1b before initiating a
 284                  * configuration access to the hot added device.
 285                  */
 286                 msleep(100);
 287         } else
 288                 msleep(1000);
 289
 290         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 291         if (retval) {
 292                 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
 293                 return retval;
 294         }
 295
 296         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 297         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 298             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 299                 ctrl_err(ctrl, "Link Training Error occurs \n");
 300                 retval = -1;
 301                 return retval;
 302         }
 303
 304         return retval;
 305 }
 306
 307 int pciehp_get_attention_status(struct slot *slot, u8 *status)
 308 {
 309         struct controller *ctrl = slot->ctrl;
 310         u16 slot_ctrl;
 311         u8 atten_led_state;
 312         int retval = 0;
 313
 314         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 315         if (retval) {
 316                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 317                 return retval;
 318         }
 319
 320         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 321                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 322
 323         atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
 324
 325         switch (atten_led_state) {
 326         case 0:
 327                 *status = 0xFF; /* Reserved */
 328                 break;
 329         case 1:
 330                 *status = 1;    /* On */
 331                 break;
 332         case 2:
 333                 *status = 2;    /* Blink */
 334                 break;
 335         case 3:
 336                 *status = 0;    /* Off */
 337                 break;
 338         default:
 339                 *status = 0xFF;
 340                 break;
 341         }
 342
 343         return 0;
 344 }
 345
 346 int pciehp_get_power_status(struct slot *slot, u8 *status)
 347 {
 348         struct controller *ctrl = slot->ctrl;
 349         u16 slot_ctrl;
 350         u8 pwr_state;
 351         int     retval = 0;
 352
 353         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 354         if (retval) {
 355                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 356                 return retval;
 357         }
 358         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 359                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 360
 361         pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
 362
 363         switch (pwr_state) {
 364         case 0:
 365                 *status = 1;
 366                 break;
 367         case 1:
 368                 *status = 0;
 369                 break;
 370         default:
 371                 *status = 0xFF;
 372                 break;
 373         }
 374
 375         return retval;
 376 }
 377
 378 int pciehp_get_latch_status(struct slot *slot, u8 *status)
 379 {
 380         struct controller *ctrl = slot->ctrl;
 381         u16 slot_status;
 382         int retval;
 383
 384         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 385         if (retval) {
 386                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 387                          __func__);
 388                 return retval;
 389         }
 390         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 391         return 0;
 392 }
 393
 394 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
 395 {
 396         struct controller *ctrl = slot->ctrl;
 397         u16 slot_status;
 398         int retval;
 399
 400         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 401         if (retval) {
 402                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 403                          __func__);
 404                 return retval;
 405         }
 406         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 407         return 0;
 408 }
 409
 410 int pciehp_query_power_fault(struct slot *slot)
 411 {
 412         struct controller *ctrl = slot->ctrl;
 413         u16 slot_status;
 414         int retval;
 415
 416         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 417         if (retval) {
 418                 ctrl_err(ctrl, "Cannot check for power fault\n");
 419                 return retval;
 420         }
 421         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 422 }
 423
 424 int pciehp_set_attention_status(struct slot *slot, u8 value)
 425 {
 426         struct controller *ctrl = slot->ctrl;
 427         u16 slot_cmd;
 428         u16 cmd_mask;
 429
 430         cmd_mask = PCI_EXP_SLTCTL_AIC;
 431         switch (value) {
 432         case 0 :        /* turn off */
 433                 slot_cmd = 0x00C0;
 434                 break;
 435         case 1:         /* turn on */
 436                 slot_cmd = 0x0040;
 437                 break;
 438         case 2:         /* turn blink */
 439                 slot_cmd = 0x0080;
 440                 break;
 441         default:
 442                 return -EINVAL;
 443         }
 444         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 445                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 446         return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 447 }
 448
 449 void pciehp_green_led_on(struct slot *slot)
 450 {
 451         struct controller *ctrl = slot->ctrl;
 452         u16 slot_cmd;
 453         u16 cmd_mask;
 454
 455         slot_cmd = 0x0100;
 456         cmd_mask = PCI_EXP_SLTCTL_PIC;
 457         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 458         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 459                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 460 }
 461
 462 void pciehp_green_led_off(struct slot *slot)
 463 {
 464         struct controller *ctrl = slot->ctrl;
 465         u16 slot_cmd;
 466         u16 cmd_mask;
 467
 468         slot_cmd = 0x0300;
 469         cmd_mask = PCI_EXP_SLTCTL_PIC;
 470         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 471         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 472                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 473 }
 474
 475 void pciehp_green_led_blink(struct slot *slot)
 476 {
 477         struct controller *ctrl = slot->ctrl;
 478         u16 slot_cmd;
 479         u16 cmd_mask;
 480
 481         slot_cmd = 0x0200;
 482         cmd_mask = PCI_EXP_SLTCTL_PIC;
 483         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 484         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 485                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 486 }
 487
 488 int pciehp_power_on_slot(struct slot * slot)
 489 {
 490         struct controller *ctrl = slot->ctrl;
 491         u16 slot_cmd;
 492         u16 cmd_mask;
 493         u16 slot_status;
 494         u16 lnk_status;
 495         int retval = 0;
 496
 497         /* Clear sticky power-fault bit from previous power failures */
 498         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 499         if (retval) {
 500                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 501                          __func__);
 502                 return retval;
 503         }
 504         slot_status &= PCI_EXP_SLTSTA_PFD;
 505         if (slot_status) {
 506                 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
 507                 if (retval) {
 508                         ctrl_err(ctrl,
 509                                  "%s: Cannot write to SLOTSTATUS register\n",
 510                                  __func__);
 511                         return retval;
 512                 }
 513         }
 514         ctrl->power_fault_detected = 0;
 515
 516         slot_cmd = POWER_ON;
 517         cmd_mask = PCI_EXP_SLTCTL_PCC;
 518         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 519         if (retval) {
 520                 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
 521                 return retval;
 522         }
 523         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 524                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 525
 526         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 527         if (retval) {
 528                 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
 529                                 __func__);
 530                 return retval;
 531         }
 532         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 533
 534         return retval;
 535 }
 536
 537 int pciehp_power_off_slot(struct slot * slot)
 538 {
 539         struct controller *ctrl = slot->ctrl;
 540         u16 slot_cmd;
 541         u16 cmd_mask;
 542         int retval;
 543
 544         slot_cmd = POWER_OFF;
 545         cmd_mask = PCI_EXP_SLTCTL_PCC;
 546         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 547         if (retval) {
 548                 ctrl_err(ctrl, "Write command failed!\n");
 549                 return retval;
 550         }
 551         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 552                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 553         return 0;
 554 }
 555
 556 static irqreturn_t pcie_isr(int irq, void *dev_id)
 557 {
 558         struct controller *ctrl = (struct controller *)dev_id;
 559         struct slot *slot = ctrl->slot;
 560         u16 detected, intr_loc;
 561
 562         /*
 563          * In order to guarantee that all interrupt events are
 564          * serviced, we need to re-inspect Slot Status register after
 565          * clearing what is presumed to be the last pending interrupt.
 566          */
 567         intr_loc = 0;
 568         do {
 569                 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
 570                         ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
 571                                  __func__);
 572                         return IRQ_NONE;
 573                 }
 574
 575                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 576                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 577                              PCI_EXP_SLTSTA_CC);
 578                 detected &= ~intr_loc;
 579                 intr_loc |= detected;
 580                 if (!intr_loc)
 581                         return IRQ_NONE;
 582                 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
 583                         ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
 584                                  __func__);
 585                         return IRQ_NONE;
 586                 }
 587         } while (detected);
 588
 589         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 590
 591         /* Check Command Complete Interrupt Pending */
 592         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 593                 ctrl->cmd_busy = 0;
 594                 smp_mb();
 595                 wake_up(&ctrl->queue);
 596         }
 597
 598         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 599                 return IRQ_HANDLED;
 600
 601         /* Check MRL Sensor Changed */
 602         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 603                 pciehp_handle_switch_change(slot);
 604
 605         /* Check Attention Button Pressed */
 606         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 607                 pciehp_handle_attention_button(slot);
 608
 609         /* Check Presence Detect Changed */
 610         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 611                 pciehp_handle_presence_change(slot);
 612
 613         /* Check Power Fault Detected */
 614         if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 615                 ctrl->power_fault_detected = 1;
 616                 pciehp_handle_power_fault(slot);
 617         }
 618         return IRQ_HANDLED;
 619 }
 620
 621 int pciehp_get_max_lnk_width(struct slot *slot,
 622                                  enum pcie_link_width *value)
 623 {
 624         struct controller *ctrl = slot->ctrl;
 625         enum pcie_link_width lnk_wdth;
 626         u32     lnk_cap;
 627         int retval = 0;
 628
 629         retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
 630         if (retval) {
 631                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 632                 return retval;
 633         }
 634
 635         switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
 636         case 0:
 637                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 638                 break;
 639         case 1:
 640                 lnk_wdth = PCIE_LNK_X1;
 641                 break;
 642         case 2:
 643                 lnk_wdth = PCIE_LNK_X2;
 644                 break;
 645         case 4:
 646                 lnk_wdth = PCIE_LNK_X4;
 647                 break;
 648         case 8:
 649                 lnk_wdth = PCIE_LNK_X8;
 650                 break;
 651         case 12:
 652                 lnk_wdth = PCIE_LNK_X12;
 653                 break;
 654         case 16:
 655                 lnk_wdth = PCIE_LNK_X16;
 656                 break;
 657         case 32:
 658                 lnk_wdth = PCIE_LNK_X32;
 659                 break;
 660         default:
 661                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 662                 break;
 663         }
 664
 665         *value = lnk_wdth;
 666         ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
 667
 668         return retval;
 669 }
 670
 671 int pciehp_get_cur_lnk_width(struct slot *slot,
 672                                  enum pcie_link_width *value)
 673 {
 674         struct controller *ctrl = slot->ctrl;
 675         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 676         int retval = 0;
 677         u16 lnk_status;
 678
 679         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 680         if (retval) {
 681                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 682                          __func__);
 683                 return retval;
 684         }
 685
 686         switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
 687         case 0:
 688                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 689                 break;
 690         case 1:
 691                 lnk_wdth = PCIE_LNK_X1;
 692                 break;
 693         case 2:
 694                 lnk_wdth = PCIE_LNK_X2;
 695                 break;
 696         case 4:
 697                 lnk_wdth = PCIE_LNK_X4;
 698                 break;
 699         case 8:
 700                 lnk_wdth = PCIE_LNK_X8;
 701                 break;
 702         case 12:
 703                 lnk_wdth = PCIE_LNK_X12;
 704                 break;
 705         case 16:
 706                 lnk_wdth = PCIE_LNK_X16;
 707                 break;
 708         case 32:
 709                 lnk_wdth = PCIE_LNK_X32;
 710                 break;
 711         default:
 712                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 713                 break;
 714         }
 715
 716         *value = lnk_wdth;
 717         ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
 718
 719         return retval;
 720 }
 721
 722 int pcie_enable_notification(struct controller *ctrl)
 723 {
 724         u16 cmd, mask;
 725
 726         /*
 727          * TBD: Power fault detected software notification support.
 728          *
 729          * Power fault detected software notification is not enabled
 730          * now, because it caused power fault detected interrupt storm
 731          * on some machines. On those machines, power fault detected
 732          * bit in the slot status register was set again immediately
 733          * when it is cleared in the interrupt service routine, and
 734          * next power fault detected interrupt was notified again.
 735          */
 736         cmd = PCI_EXP_SLTCTL_PDCE;
 737         if (ATTN_BUTTN(ctrl))
 738                 cmd |= PCI_EXP_SLTCTL_ABPE;
 739         if (MRL_SENS(ctrl))
 740                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 741         if (!pciehp_poll_mode)
 742                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 743
 744         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 745                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 746                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
 747
 748         if (pcie_write_cmd(ctrl, cmd, mask)) {
 749                 ctrl_err(ctrl, "Cannot enable software notification\n");
 750                 return -1;
 751         }
 752         return 0;
 753 }
 754
 755 static void pcie_disable_notification(struct controller *ctrl)
 756 {
 757         u16 mask;
 758         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 759                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 760                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 761                 PCI_EXP_SLTCTL_DLLSCE);
 762         if (pcie_write_cmd(ctrl, 0, mask))
 763                 ctrl_warn(ctrl, "Cannot disable software notification\n");
 764 }
 765
 766 int pcie_init_notification(struct controller *ctrl)
 767 {
 768         if (pciehp_request_irq(ctrl))
 769                 return -1;
 770         if (pcie_enable_notification(ctrl)) {
 771                 pciehp_free_irq(ctrl);
 772                 return -1;
 773         }
 774         ctrl->notification_enabled = 1;
 775         return 0;
 776 }
 777
 778 static void pcie_shutdown_notification(struct controller *ctrl)
 779 {
 780         if (ctrl->notification_enabled) {
 781                 pcie_disable_notification(ctrl);
 782                 pciehp_free_irq(ctrl);
 783                 ctrl->notification_enabled = 0;
 784         }
 785 }
 786
 787 static int pcie_init_slot(struct controller *ctrl)
 788 {
 789         struct slot *slot;
 790
 791         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 792         if (!slot)
 793                 return -ENOMEM;
 794
 795         slot->ctrl = ctrl;
 796         mutex_init(&slot->lock);
 797         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 798         ctrl->slot = slot;
 799         return 0;
 800 }
 801
 802 static void pcie_cleanup_slot(struct controller *ctrl)
 803 {
 804         struct slot *slot = ctrl->slot;
 805         cancel_delayed_work(&slot->work);
 806         flush_workqueue(pciehp_wq);
 807         flush_workqueue(pciehp_ordered_wq);
 808         kfree(slot);
 809 }
 810
 811 static inline void dbg_ctrl(struct controller *ctrl)
 812 {
 813         int i;
 814         u16 reg16;
 815         struct pci_dev *pdev = ctrl->pcie->port;
 816
 817         if (!pciehp_debug)
 818                 return;
 819
 820         ctrl_info(ctrl, "Hotplug Controller:\n");
 821         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
 822                   pci_name(pdev), pdev->irq);
 823         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
 824         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
 825         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
 826                   pdev->subsystem_device);
 827         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
 828                   pdev->subsystem_vendor);
 829         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n",
 830                   pci_pcie_cap(pdev));
 831         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 832                 if (!pci_resource_len(pdev, i))
 833                         continue;
 834                 ctrl_info(ctrl, "  PCI resource [%d]     : %pR\n",
 835                           i, &pdev->resource[i]);
 836         }
 837         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 838         ctrl_info(ctrl, "  Physical Slot Number : %d\n", PSN(ctrl));
 839         ctrl_info(ctrl, "  Attention Button     : %3s\n",
 840                   ATTN_BUTTN(ctrl) ? "yes" : "no");
 841         ctrl_info(ctrl, "  Power Controller     : %3s\n",
 842                   POWER_CTRL(ctrl) ? "yes" : "no");
 843         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
 844                   MRL_SENS(ctrl)   ? "yes" : "no");
 845         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
 846                   ATTN_LED(ctrl)   ? "yes" : "no");
 847         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
 848                   PWR_LED(ctrl)    ? "yes" : "no");
 849         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
 850                   HP_SUPR_RM(ctrl) ? "yes" : "no");
 851         ctrl_info(ctrl, "  EMI Present          : %3s\n",
 852                   EMI(ctrl)        ? "yes" : "no");
 853         ctrl_info(ctrl, "  Command Completed    : %3s\n",
 854                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
 855         pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
 856         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 857         pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
 858         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 859 }
 860
 861 struct controller *pcie_init(struct pcie_device *dev)
 862 {
 863         struct controller *ctrl;
 864         u32 slot_cap, link_cap;
 865         struct pci_dev *pdev = dev->port;
 866
 867         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 868         if (!ctrl) {
 869                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 870                 goto abort;
 871         }
 872         ctrl->pcie = dev;
 873         if (!pci_pcie_cap(pdev)) {
 874                 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
 875                 goto abort_ctrl;
 876         }
 877         if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
 878                 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
 879                 goto abort_ctrl;
 880         }
 881
 882         ctrl->slot_cap = slot_cap;
 883         mutex_init(&ctrl->ctrl_lock);
 884         init_waitqueue_head(&ctrl->queue);
 885         dbg_ctrl(ctrl);
 886         /*
 887          * Controller doesn't notify of command completion if the "No
 888          * Command Completed Support" bit is set in Slot Capability
 889          * register or the controller supports none of power
 890          * controller, attention led, power led and EMI.
 891          */
 892         if (NO_CMD_CMPL(ctrl) ||
 893             !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
 894             ctrl->no_cmd_complete = 1;
 895
 896         /* Check if Data Link Layer Link Active Reporting is implemented */
 897         if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
 898                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 899                 goto abort_ctrl;
 900         }
 901         if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
 902                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
 903                 ctrl->link_active_reporting = 1;
 904         }
 905
 906         /* Clear all remaining event bits in Slot Status register */
 907         if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
 908                 goto abort_ctrl;
 909
 910         /* Disable sotfware notification */
 911         pcie_disable_notification(ctrl);
 912
 913         ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
 914                   pdev->vendor, pdev->device, pdev->subsystem_vendor,
 915                   pdev->subsystem_device);
 916
 917         if (pcie_init_slot(ctrl))
 918                 goto abort_ctrl;
 919
 920         return ctrl;
 921
 922 abort_ctrl:
 923         kfree(ctrl);
 924 abort:
 925         return NULL;
 926 }
 927
 928 void pciehp_release_ctrl(struct controller *ctrl)
 929 {
 930         pcie_shutdown_notification(ctrl);
 931         pcie_cleanup_slot(ctrl);
 932         kfree(ctrl);
 933 }