2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers
= ATOMIC_INIT(0);
61 } __attribute__ ((packed
));
63 /* offsets to the controller registers based on the above structure layout */
65 PCIECAPID
= offsetof(struct ctrl_reg
, cap_id
),
66 NXTCAPPTR
= offsetof(struct ctrl_reg
, nxt_ptr
),
67 CAPREG
= offsetof(struct ctrl_reg
, cap_reg
),
68 DEVCAP
= offsetof(struct ctrl_reg
, dev_cap
),
69 DEVCTRL
= offsetof(struct ctrl_reg
, dev_ctrl
),
70 DEVSTATUS
= offsetof(struct ctrl_reg
, dev_status
),
71 LNKCAP
= offsetof(struct ctrl_reg
, lnk_cap
),
72 LNKCTRL
= offsetof(struct ctrl_reg
, lnk_ctrl
),
73 LNKSTATUS
= offsetof(struct ctrl_reg
, lnk_status
),
74 SLOTCAP
= offsetof(struct ctrl_reg
, slot_cap
),
75 SLOTCTRL
= offsetof(struct ctrl_reg
, slot_ctrl
),
76 SLOTSTATUS
= offsetof(struct ctrl_reg
, slot_status
),
77 ROOTCTRL
= offsetof(struct ctrl_reg
, root_ctrl
),
78 ROOTSTATUS
= offsetof(struct ctrl_reg
, root_status
),
81 static inline int pciehp_readw(struct controller
*ctrl
, int reg
, u16
*value
)
83 struct pci_dev
*dev
= ctrl
->pci_dev
;
84 return pci_read_config_word(dev
, ctrl
->cap_base
+ reg
, value
);
87 static inline int pciehp_readl(struct controller
*ctrl
, int reg
, u32
*value
)
89 struct pci_dev
*dev
= ctrl
->pci_dev
;
90 return pci_read_config_dword(dev
, ctrl
->cap_base
+ reg
, value
);
93 static inline int pciehp_writew(struct controller
*ctrl
, int reg
, u16 value
)
95 struct pci_dev
*dev
= ctrl
->pci_dev
;
96 return pci_write_config_word(dev
, ctrl
->cap_base
+ reg
, value
);
99 static inline int pciehp_writel(struct controller
*ctrl
, int reg
, u32 value
)
101 struct pci_dev
*dev
= ctrl
->pci_dev
;
102 return pci_write_config_dword(dev
, ctrl
->cap_base
+ reg
, value
);
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
128 #define LINK_ACTIVE_REPORTING 0x00100000
130 /* Link Width Encoding */
139 /*Field definitions of Link Status Register */
140 #define LNK_SPEED 0x000F
141 #define NEG_LINK_WD 0x03F0
142 #define LNK_TRN_ERR 0x0400
143 #define LNK_TRN 0x0800
144 #define SLOT_CLK_CONF 0x1000
145 #define LINK_ACTIVE 0x2000
147 /* Field definitions in Slot Capabilities Register */
148 #define ATTN_BUTTN_PRSN 0x00000001
149 #define PWR_CTRL_PRSN 0x00000002
150 #define MRL_SENS_PRSN 0x00000004
151 #define ATTN_LED_PRSN 0x00000008
152 #define PWR_LED_PRSN 0x00000010
153 #define HP_SUPR_RM_SUP 0x00000020
154 #define HP_CAP 0x00000040
155 #define SLOT_PWR_VALUE 0x000003F8
156 #define SLOT_PWR_LIMIT 0x00000C00
157 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
159 /* Field definitions in Slot Control Register */
160 #define ATTN_BUTTN_ENABLE 0x0001
161 #define PWR_FAULT_DETECT_ENABLE 0x0002
162 #define MRL_DETECT_ENABLE 0x0004
163 #define PRSN_DETECT_ENABLE 0x0008
164 #define CMD_CMPL_INTR_ENABLE 0x0010
165 #define HP_INTR_ENABLE 0x0020
166 #define ATTN_LED_CTRL 0x00C0
167 #define PWR_LED_CTRL 0x0300
168 #define PWR_CTRL 0x0400
169 #define EMI_CTRL 0x0800
171 /* Attention indicator and Power indicator states */
173 #define LED_BLINK 0x10
176 /* Power Control Command */
178 #define POWER_OFF 0x0400
180 /* EMI Status defines */
181 #define EMI_DISENGAGED 0
182 #define EMI_ENGAGED 1
184 /* Field definitions in Slot Status Register */
185 #define ATTN_BUTTN_PRESSED 0x0001
186 #define PWR_FAULT_DETECTED 0x0002
187 #define MRL_SENS_CHANGED 0x0004
188 #define PRSN_DETECT_CHANGED 0x0008
189 #define CMD_COMPLETED 0x0010
190 #define MRL_STATE 0x0020
191 #define PRSN_STATE 0x0040
192 #define EMI_STATE 0x0080
193 #define EMI_STATUS_BIT 7
195 static irqreturn_t
pcie_isr(int irq
, void *dev_id
);
196 static void start_int_poll_timer(struct controller
*ctrl
, int sec
);
198 /* This is the interrupt polling timeout function. */
199 static void int_poll_timeout(unsigned long data
)
201 struct controller
*ctrl
= (struct controller
*)data
;
203 /* Poll for interrupt events. regs == NULL => polling */
206 init_timer(&ctrl
->poll_timer
);
207 if (!pciehp_poll_time
)
208 pciehp_poll_time
= 2; /* default polling interval is 2 sec */
210 start_int_poll_timer(ctrl
, pciehp_poll_time
);
213 /* This function starts the interrupt polling timer. */
214 static void start_int_poll_timer(struct controller
*ctrl
, int sec
)
216 /* Clamp to sane value */
217 if ((sec
<= 0) || (sec
> 60))
220 ctrl
->poll_timer
.function
= &int_poll_timeout
;
221 ctrl
->poll_timer
.data
= (unsigned long)ctrl
;
222 ctrl
->poll_timer
.expires
= jiffies
+ sec
* HZ
;
223 add_timer(&ctrl
->poll_timer
);
226 static inline int pciehp_request_irq(struct controller
*ctrl
)
228 int retval
, irq
= ctrl
->pcie
->irq
;
230 /* Install interrupt polling timer. Start with 10 sec delay */
231 if (pciehp_poll_mode
) {
232 init_timer(&ctrl
->poll_timer
);
233 start_int_poll_timer(ctrl
, 10);
237 /* Installs the interrupt handler */
238 retval
= request_irq(irq
, pcie_isr
, IRQF_SHARED
, MY_NAME
, ctrl
);
240 ctrl_err(ctrl
, "Cannot get irq %d for the hotplug controller\n",
245 static inline void pciehp_free_irq(struct controller
*ctrl
)
247 if (pciehp_poll_mode
)
248 del_timer_sync(&ctrl
->poll_timer
);
250 free_irq(ctrl
->pcie
->irq
, ctrl
);
253 static int pcie_poll_cmd(struct controller
*ctrl
)
258 if (!pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
)) {
259 if (slot_status
& CMD_COMPLETED
) {
260 pciehp_writew(ctrl
, SLOTSTATUS
, CMD_COMPLETED
);
264 while (timeout
> 0) {
267 if (!pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
)) {
268 if (slot_status
& CMD_COMPLETED
) {
269 pciehp_writew(ctrl
, SLOTSTATUS
, CMD_COMPLETED
);
274 return 0; /* timeout */
277 static void pcie_wait_cmd(struct controller
*ctrl
, int poll
)
279 unsigned int msecs
= pciehp_poll_mode
? 2500 : 1000;
280 unsigned long timeout
= msecs_to_jiffies(msecs
);
284 rc
= pcie_poll_cmd(ctrl
);
286 rc
= wait_event_timeout(ctrl
->queue
, !ctrl
->cmd_busy
, timeout
);
288 ctrl_dbg(ctrl
, "Command not completed in 1000 msec\n");
292 * pcie_write_cmd - Issue controller command
293 * @ctrl: controller to which the command is issued
294 * @cmd: command value written to slot control register
295 * @mask: bitmask of slot control register to be modified
297 static int pcie_write_cmd(struct controller
*ctrl
, u16 cmd
, u16 mask
)
303 mutex_lock(&ctrl
->ctrl_lock
);
305 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
307 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
312 if (slot_status
& CMD_COMPLETED
) {
313 if (!ctrl
->no_cmd_complete
) {
315 * After 1 sec and CMD_COMPLETED still not set, just
316 * proceed forward to issue the next command according
317 * to spec. Just print out the error message.
320 "%s: CMD_COMPLETED not clear after 1 sec.\n",
322 } else if (!NO_CMD_CMPL(ctrl
)) {
324 * This controller semms to notify of command completed
325 * event even though it supports none of power
326 * controller, attention led, power led and EMI.
328 ctrl_dbg(ctrl
, "%s: Unexpected CMD_COMPLETED. Need to "
329 "wait for command completed event.\n",
331 ctrl
->no_cmd_complete
= 0;
333 ctrl_dbg(ctrl
, "%s: Unexpected CMD_COMPLETED. Maybe "
334 "the controller is broken.\n", __func__
);
338 retval
= pciehp_readw(ctrl
, SLOTCTRL
, &slot_ctrl
);
340 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
345 slot_ctrl
|= (cmd
& mask
);
348 retval
= pciehp_writew(ctrl
, SLOTCTRL
, slot_ctrl
);
350 ctrl_err(ctrl
, "%s: Cannot write to SLOTCTRL register\n",
354 * Wait for command completion.
356 if (!retval
&& !ctrl
->no_cmd_complete
) {
359 * if hotplug interrupt is not enabled or command
360 * completed interrupt is not enabled, we need to poll
361 * command completed event.
363 if (!(slot_ctrl
& HP_INTR_ENABLE
) ||
364 !(slot_ctrl
& CMD_CMPL_INTR_ENABLE
))
366 pcie_wait_cmd(ctrl
, poll
);
369 mutex_unlock(&ctrl
->ctrl_lock
);
373 static inline int check_link_active(struct controller
*ctrl
)
377 if (pciehp_readw(ctrl
, LNKSTATUS
, &link_status
))
379 return !!(link_status
& LINK_ACTIVE
);
382 static void pcie_wait_link_active(struct controller
*ctrl
)
386 if (check_link_active(ctrl
))
388 while (timeout
> 0) {
391 if (check_link_active(ctrl
))
394 ctrl_dbg(ctrl
, "Data Link Layer Link Active not set in 1000 msec\n");
397 static int hpc_check_lnk_status(struct controller
*ctrl
)
403 * Data Link Layer Link Active Reporting must be capable for
404 * hot-plug capable downstream port. But old controller might
405 * not implement it. In this case, we wait for 1000 ms.
407 if (ctrl
->link_active_reporting
){
408 /* Wait for Data Link Layer Link Active bit to be set */
409 pcie_wait_link_active(ctrl
);
411 * We must wait for 100 ms after the Data Link Layer
412 * Link Active bit reads 1b before initiating a
413 * configuration access to the hot added device.
419 retval
= pciehp_readw(ctrl
, LNKSTATUS
, &lnk_status
);
421 ctrl_err(ctrl
, "%s: Cannot read LNKSTATUS register\n",
426 ctrl_dbg(ctrl
, "%s: lnk_status = %x\n", __func__
, lnk_status
);
427 if ( (lnk_status
& LNK_TRN
) || (lnk_status
& LNK_TRN_ERR
) ||
428 !(lnk_status
& NEG_LINK_WD
)) {
429 ctrl_err(ctrl
, "%s : Link Training Error occurs \n", __func__
);
437 static int hpc_get_attention_status(struct slot
*slot
, u8
*status
)
439 struct controller
*ctrl
= slot
->ctrl
;
444 retval
= pciehp_readw(ctrl
, SLOTCTRL
, &slot_ctrl
);
446 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
450 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x, value read %x\n",
451 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_ctrl
);
453 atten_led_state
= (slot_ctrl
& ATTN_LED_CTRL
) >> 6;
455 switch (atten_led_state
) {
457 *status
= 0xFF; /* Reserved */
460 *status
= 1; /* On */
463 *status
= 2; /* Blink */
466 *status
= 0; /* Off */
476 static int hpc_get_power_status(struct slot
*slot
, u8
*status
)
478 struct controller
*ctrl
= slot
->ctrl
;
483 retval
= pciehp_readw(ctrl
, SLOTCTRL
, &slot_ctrl
);
485 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
488 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x value read %x\n",
489 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_ctrl
);
491 pwr_state
= (slot_ctrl
& PWR_CTRL
) >> 10;
508 static int hpc_get_latch_status(struct slot
*slot
, u8
*status
)
510 struct controller
*ctrl
= slot
->ctrl
;
514 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
516 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
521 *status
= (((slot_status
& MRL_STATE
) >> 5) == 0) ? 0 : 1;
526 static int hpc_get_adapter_status(struct slot
*slot
, u8
*status
)
528 struct controller
*ctrl
= slot
->ctrl
;
533 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
535 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
539 card_state
= (u8
)((slot_status
& PRSN_STATE
) >> 6);
540 *status
= (card_state
== 1) ? 1 : 0;
545 static int hpc_query_power_fault(struct slot
*slot
)
547 struct controller
*ctrl
= slot
->ctrl
;
552 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
554 ctrl_err(ctrl
, "%s: Cannot check for power fault\n", __func__
);
557 pwr_fault
= (u8
)((slot_status
& PWR_FAULT_DETECTED
) >> 1);
562 static int hpc_get_emi_status(struct slot
*slot
, u8
*status
)
564 struct controller
*ctrl
= slot
->ctrl
;
568 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
570 ctrl_err(ctrl
, "%s : Cannot check EMI status\n", __func__
);
573 *status
= (slot_status
& EMI_STATE
) >> EMI_STATUS_BIT
;
578 static int hpc_toggle_emi(struct slot
*slot
)
586 rc
= pcie_write_cmd(slot
->ctrl
, slot_cmd
, cmd_mask
);
587 slot
->last_emi_toggle
= get_seconds();
592 static int hpc_set_attention_status(struct slot
*slot
, u8 value
)
594 struct controller
*ctrl
= slot
->ctrl
;
599 cmd_mask
= ATTN_LED_CTRL
;
601 case 0 : /* turn off */
604 case 1: /* turn on */
607 case 2: /* turn blink */
613 rc
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
614 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
615 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
620 static void hpc_set_green_led_on(struct slot
*slot
)
622 struct controller
*ctrl
= slot
->ctrl
;
627 cmd_mask
= PWR_LED_CTRL
;
628 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
629 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
630 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
633 static void hpc_set_green_led_off(struct slot
*slot
)
635 struct controller
*ctrl
= slot
->ctrl
;
640 cmd_mask
= PWR_LED_CTRL
;
641 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
642 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
643 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
646 static void hpc_set_green_led_blink(struct slot
*slot
)
648 struct controller
*ctrl
= slot
->ctrl
;
653 cmd_mask
= PWR_LED_CTRL
;
654 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
655 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
656 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
659 static int hpc_power_on_slot(struct slot
* slot
)
661 struct controller
*ctrl
= slot
->ctrl
;
667 ctrl_dbg(ctrl
, "%s: slot->hp_slot %x\n", __func__
, slot
->hp_slot
);
669 /* Clear sticky power-fault bit from previous power failures */
670 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
672 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
676 slot_status
&= PWR_FAULT_DETECTED
;
678 retval
= pciehp_writew(ctrl
, SLOTSTATUS
, slot_status
);
681 "%s: Cannot write to SLOTSTATUS register\n",
689 /* Enable detection that we turned off at slot power-off time */
690 if (!pciehp_poll_mode
) {
691 slot_cmd
|= (PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
693 cmd_mask
|= (PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
697 retval
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
700 ctrl_err(ctrl
, "%s: Write %x command failed!\n",
704 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
705 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
710 static inline int pcie_mask_bad_dllp(struct controller
*ctrl
)
712 struct pci_dev
*dev
= ctrl
->pci_dev
;
716 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
719 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®
);
720 if (reg
& PCI_ERR_COR_BAD_DLLP
)
722 reg
|= PCI_ERR_COR_BAD_DLLP
;
723 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg
);
727 static inline void pcie_unmask_bad_dllp(struct controller
*ctrl
)
729 struct pci_dev
*dev
= ctrl
->pci_dev
;
733 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
736 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®
);
737 if (!(reg
& PCI_ERR_COR_BAD_DLLP
))
739 reg
&= ~PCI_ERR_COR_BAD_DLLP
;
740 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg
);
743 static int hpc_power_off_slot(struct slot
* slot
)
745 struct controller
*ctrl
= slot
->ctrl
;
751 ctrl_dbg(ctrl
, "%s: slot->hp_slot %x\n", __func__
, slot
->hp_slot
);
754 * Set Bad DLLP Mask bit in Correctable Error Mask
755 * Register. This is the workaround against Bad DLLP error
756 * that sometimes happens during turning power off the slot
757 * which conforms to PCI Express 1.0a spec.
759 changed
= pcie_mask_bad_dllp(ctrl
);
761 slot_cmd
= POWER_OFF
;
764 * If we get MRL or presence detect interrupts now, the isr
765 * will notice the sticky power-fault bit too and issue power
766 * indicator change commands. This will lead to an endless loop
767 * of command completions, since the power-fault bit remains on
768 * till the slot is powered on again.
770 if (!pciehp_poll_mode
) {
771 slot_cmd
&= ~(PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
773 cmd_mask
|= (PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
777 retval
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
779 ctrl_err(ctrl
, "%s: Write command failed!\n", __func__
);
783 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
784 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
787 pcie_unmask_bad_dllp(ctrl
);
792 static irqreturn_t
pcie_isr(int irq
, void *dev_id
)
794 struct controller
*ctrl
= (struct controller
*)dev_id
;
795 u16 detected
, intr_loc
;
799 * In order to guarantee that all interrupt events are
800 * serviced, we need to re-inspect Slot Status register after
801 * clearing what is presumed to be the last pending interrupt.
805 if (pciehp_readw(ctrl
, SLOTSTATUS
, &detected
)) {
806 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS\n",
811 detected
&= (ATTN_BUTTN_PRESSED
| PWR_FAULT_DETECTED
|
812 MRL_SENS_CHANGED
| PRSN_DETECT_CHANGED
|
814 intr_loc
|= detected
;
817 if (detected
&& pciehp_writew(ctrl
, SLOTSTATUS
, detected
)) {
818 ctrl_err(ctrl
, "%s: Cannot write to SLOTSTATUS\n",
824 ctrl_dbg(ctrl
, "%s: intr_loc %x\n", __func__
, intr_loc
);
826 /* Check Command Complete Interrupt Pending */
827 if (intr_loc
& CMD_COMPLETED
) {
830 wake_up(&ctrl
->queue
);
833 if (!(intr_loc
& ~CMD_COMPLETED
))
836 p_slot
= pciehp_find_slot(ctrl
, ctrl
->slot_device_offset
);
838 /* Check MRL Sensor Changed */
839 if (intr_loc
& MRL_SENS_CHANGED
)
840 pciehp_handle_switch_change(p_slot
);
842 /* Check Attention Button Pressed */
843 if (intr_loc
& ATTN_BUTTN_PRESSED
)
844 pciehp_handle_attention_button(p_slot
);
846 /* Check Presence Detect Changed */
847 if (intr_loc
& PRSN_DETECT_CHANGED
)
848 pciehp_handle_presence_change(p_slot
);
850 /* Check Power Fault Detected */
851 if (intr_loc
& PWR_FAULT_DETECTED
)
852 pciehp_handle_power_fault(p_slot
);
857 static int hpc_get_max_lnk_speed(struct slot
*slot
, enum pci_bus_speed
*value
)
859 struct controller
*ctrl
= slot
->ctrl
;
860 enum pcie_link_speed lnk_speed
;
864 retval
= pciehp_readl(ctrl
, LNKCAP
, &lnk_cap
);
866 ctrl_err(ctrl
, "%s: Cannot read LNKCAP register\n", __func__
);
870 switch (lnk_cap
& 0x000F) {
872 lnk_speed
= PCIE_2PT5GB
;
875 lnk_speed
= PCIE_LNK_SPEED_UNKNOWN
;
880 ctrl_dbg(ctrl
, "Max link speed = %d\n", lnk_speed
);
885 static int hpc_get_max_lnk_width(struct slot
*slot
,
886 enum pcie_link_width
*value
)
888 struct controller
*ctrl
= slot
->ctrl
;
889 enum pcie_link_width lnk_wdth
;
893 retval
= pciehp_readl(ctrl
, LNKCAP
, &lnk_cap
);
895 ctrl_err(ctrl
, "%s: Cannot read LNKCAP register\n", __func__
);
899 switch ((lnk_cap
& 0x03F0) >> 4){
901 lnk_wdth
= PCIE_LNK_WIDTH_RESRV
;
904 lnk_wdth
= PCIE_LNK_X1
;
907 lnk_wdth
= PCIE_LNK_X2
;
910 lnk_wdth
= PCIE_LNK_X4
;
913 lnk_wdth
= PCIE_LNK_X8
;
916 lnk_wdth
= PCIE_LNK_X12
;
919 lnk_wdth
= PCIE_LNK_X16
;
922 lnk_wdth
= PCIE_LNK_X32
;
925 lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
930 ctrl_dbg(ctrl
, "Max link width = %d\n", lnk_wdth
);
935 static int hpc_get_cur_lnk_speed(struct slot
*slot
, enum pci_bus_speed
*value
)
937 struct controller
*ctrl
= slot
->ctrl
;
938 enum pcie_link_speed lnk_speed
= PCI_SPEED_UNKNOWN
;
942 retval
= pciehp_readw(ctrl
, LNKSTATUS
, &lnk_status
);
944 ctrl_err(ctrl
, "%s: Cannot read LNKSTATUS register\n",
949 switch (lnk_status
& 0x0F) {
951 lnk_speed
= PCIE_2PT5GB
;
954 lnk_speed
= PCIE_LNK_SPEED_UNKNOWN
;
959 ctrl_dbg(ctrl
, "Current link speed = %d\n", lnk_speed
);
964 static int hpc_get_cur_lnk_width(struct slot
*slot
,
965 enum pcie_link_width
*value
)
967 struct controller
*ctrl
= slot
->ctrl
;
968 enum pcie_link_width lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
972 retval
= pciehp_readw(ctrl
, LNKSTATUS
, &lnk_status
);
974 ctrl_err(ctrl
, "%s: Cannot read LNKSTATUS register\n",
979 switch ((lnk_status
& 0x03F0) >> 4){
981 lnk_wdth
= PCIE_LNK_WIDTH_RESRV
;
984 lnk_wdth
= PCIE_LNK_X1
;
987 lnk_wdth
= PCIE_LNK_X2
;
990 lnk_wdth
= PCIE_LNK_X4
;
993 lnk_wdth
= PCIE_LNK_X8
;
996 lnk_wdth
= PCIE_LNK_X12
;
999 lnk_wdth
= PCIE_LNK_X16
;
1002 lnk_wdth
= PCIE_LNK_X32
;
1005 lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
1010 ctrl_dbg(ctrl
, "Current link width = %d\n", lnk_wdth
);
1015 static void pcie_release_ctrl(struct controller
*ctrl
);
1016 static struct hpc_ops pciehp_hpc_ops
= {
1017 .power_on_slot
= hpc_power_on_slot
,
1018 .power_off_slot
= hpc_power_off_slot
,
1019 .set_attention_status
= hpc_set_attention_status
,
1020 .get_power_status
= hpc_get_power_status
,
1021 .get_attention_status
= hpc_get_attention_status
,
1022 .get_latch_status
= hpc_get_latch_status
,
1023 .get_adapter_status
= hpc_get_adapter_status
,
1024 .get_emi_status
= hpc_get_emi_status
,
1025 .toggle_emi
= hpc_toggle_emi
,
1027 .get_max_bus_speed
= hpc_get_max_lnk_speed
,
1028 .get_cur_bus_speed
= hpc_get_cur_lnk_speed
,
1029 .get_max_lnk_width
= hpc_get_max_lnk_width
,
1030 .get_cur_lnk_width
= hpc_get_cur_lnk_width
,
1032 .query_power_fault
= hpc_query_power_fault
,
1033 .green_led_on
= hpc_set_green_led_on
,
1034 .green_led_off
= hpc_set_green_led_off
,
1035 .green_led_blink
= hpc_set_green_led_blink
,
1037 .release_ctlr
= pcie_release_ctrl
,
1038 .check_lnk_status
= hpc_check_lnk_status
,
1041 int pcie_enable_notification(struct controller
*ctrl
)
1045 cmd
= PRSN_DETECT_ENABLE
;
1046 if (ATTN_BUTTN(ctrl
))
1047 cmd
|= ATTN_BUTTN_ENABLE
;
1048 if (POWER_CTRL(ctrl
))
1049 cmd
|= PWR_FAULT_DETECT_ENABLE
;
1051 cmd
|= MRL_DETECT_ENABLE
;
1052 if (!pciehp_poll_mode
)
1053 cmd
|= HP_INTR_ENABLE
| CMD_CMPL_INTR_ENABLE
;
1055 mask
= PRSN_DETECT_ENABLE
| ATTN_BUTTN_ENABLE
| MRL_DETECT_ENABLE
|
1056 PWR_FAULT_DETECT_ENABLE
| HP_INTR_ENABLE
| CMD_CMPL_INTR_ENABLE
;
1058 if (pcie_write_cmd(ctrl
, cmd
, mask
)) {
1059 ctrl_err(ctrl
, "%s: Cannot enable software notification\n",
1066 static void pcie_disable_notification(struct controller
*ctrl
)
1069 mask
= PRSN_DETECT_ENABLE
| ATTN_BUTTN_ENABLE
| MRL_DETECT_ENABLE
|
1070 PWR_FAULT_DETECT_ENABLE
| HP_INTR_ENABLE
| CMD_CMPL_INTR_ENABLE
;
1071 if (pcie_write_cmd(ctrl
, 0, mask
))
1072 ctrl_warn(ctrl
, "%s: Cannot disable software notification\n",
1076 static int pcie_init_notification(struct controller
*ctrl
)
1078 if (pciehp_request_irq(ctrl
))
1080 if (pcie_enable_notification(ctrl
)) {
1081 pciehp_free_irq(ctrl
);
1087 static void pcie_shutdown_notification(struct controller
*ctrl
)
1089 pcie_disable_notification(ctrl
);
1090 pciehp_free_irq(ctrl
);
1093 static int pcie_init_slot(struct controller
*ctrl
)
1097 slot
= kzalloc(sizeof(*slot
), GFP_KERNEL
);
1103 slot
->bus
= ctrl
->pci_dev
->subordinate
->number
;
1104 slot
->device
= ctrl
->slot_device_offset
+ slot
->hp_slot
;
1105 slot
->hpc_ops
= ctrl
->hpc_ops
;
1106 slot
->number
= ctrl
->first_slot
;
1107 mutex_init(&slot
->lock
);
1108 INIT_DELAYED_WORK(&slot
->work
, pciehp_queue_pushbutton_work
);
1109 list_add(&slot
->slot_list
, &ctrl
->slot_list
);
1113 static void pcie_cleanup_slot(struct controller
*ctrl
)
1116 slot
= list_first_entry(&ctrl
->slot_list
, struct slot
, slot_list
);
1117 list_del(&slot
->slot_list
);
1118 cancel_delayed_work(&slot
->work
);
1119 flush_scheduled_work();
1120 flush_workqueue(pciehp_wq
);
1124 static inline void dbg_ctrl(struct controller
*ctrl
)
1128 struct pci_dev
*pdev
= ctrl
->pci_dev
;
1133 ctrl_info(ctrl
, "Hotplug Controller:\n");
1134 ctrl_info(ctrl
, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
1135 pci_name(pdev
), pdev
->irq
);
1136 ctrl_info(ctrl
, " Vendor ID : 0x%04x\n", pdev
->vendor
);
1137 ctrl_info(ctrl
, " Device ID : 0x%04x\n", pdev
->device
);
1138 ctrl_info(ctrl
, " Subsystem ID : 0x%04x\n",
1139 pdev
->subsystem_device
);
1140 ctrl_info(ctrl
, " Subsystem Vendor ID : 0x%04x\n",
1141 pdev
->subsystem_vendor
);
1142 ctrl_info(ctrl
, " PCIe Cap offset : 0x%02x\n", ctrl
->cap_base
);
1143 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1144 if (!pci_resource_len(pdev
, i
))
1146 ctrl_info(ctrl
, " PCI resource [%d] : 0x%llx@0x%llx\n",
1147 i
, (unsigned long long)pci_resource_len(pdev
, i
),
1148 (unsigned long long)pci_resource_start(pdev
, i
));
1150 ctrl_info(ctrl
, "Slot Capabilities : 0x%08x\n", ctrl
->slot_cap
);
1151 ctrl_info(ctrl
, " Physical Slot Number : %d\n", ctrl
->first_slot
);
1152 ctrl_info(ctrl
, " Attention Button : %3s\n",
1153 ATTN_BUTTN(ctrl
) ? "yes" : "no");
1154 ctrl_info(ctrl
, " Power Controller : %3s\n",
1155 POWER_CTRL(ctrl
) ? "yes" : "no");
1156 ctrl_info(ctrl
, " MRL Sensor : %3s\n",
1157 MRL_SENS(ctrl
) ? "yes" : "no");
1158 ctrl_info(ctrl
, " Attention Indicator : %3s\n",
1159 ATTN_LED(ctrl
) ? "yes" : "no");
1160 ctrl_info(ctrl
, " Power Indicator : %3s\n",
1161 PWR_LED(ctrl
) ? "yes" : "no");
1162 ctrl_info(ctrl
, " Hot-Plug Surprise : %3s\n",
1163 HP_SUPR_RM(ctrl
) ? "yes" : "no");
1164 ctrl_info(ctrl
, " EMI Present : %3s\n",
1165 EMI(ctrl
) ? "yes" : "no");
1166 ctrl_info(ctrl
, " Command Completed : %3s\n",
1167 NO_CMD_CMPL(ctrl
) ? "no" : "yes");
1168 pciehp_readw(ctrl
, SLOTSTATUS
, ®16
);
1169 ctrl_info(ctrl
, "Slot Status : 0x%04x\n", reg16
);
1170 pciehp_readw(ctrl
, SLOTCTRL
, ®16
);
1171 ctrl_info(ctrl
, "Slot Control : 0x%04x\n", reg16
);
1174 struct controller
*pcie_init(struct pcie_device
*dev
)
1176 struct controller
*ctrl
;
1177 u32 slot_cap
, link_cap
;
1178 struct pci_dev
*pdev
= dev
->port
;
1180 ctrl
= kzalloc(sizeof(*ctrl
), GFP_KERNEL
);
1182 dev_err(&dev
->device
, "%s : out of memory\n", __func__
);
1185 INIT_LIST_HEAD(&ctrl
->slot_list
);
1188 ctrl
->pci_dev
= pdev
;
1189 ctrl
->cap_base
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1190 if (!ctrl
->cap_base
) {
1191 ctrl_err(ctrl
, "%s: Cannot find PCI Express capability\n",
1195 if (pciehp_readl(ctrl
, SLOTCAP
, &slot_cap
)) {
1196 ctrl_err(ctrl
, "%s: Cannot read SLOTCAP register\n", __func__
);
1200 ctrl
->slot_cap
= slot_cap
;
1201 ctrl
->first_slot
= slot_cap
>> 19;
1202 ctrl
->slot_device_offset
= 0;
1203 ctrl
->num_slots
= 1;
1204 ctrl
->hpc_ops
= &pciehp_hpc_ops
;
1205 mutex_init(&ctrl
->crit_sect
);
1206 mutex_init(&ctrl
->ctrl_lock
);
1207 init_waitqueue_head(&ctrl
->queue
);
1210 * Controller doesn't notify of command completion if the "No
1211 * Command Completed Support" bit is set in Slot Capability
1212 * register or the controller supports none of power
1213 * controller, attention led, power led and EMI.
1215 if (NO_CMD_CMPL(ctrl
) ||
1216 !(POWER_CTRL(ctrl
) | ATTN_LED(ctrl
) | PWR_LED(ctrl
) | EMI(ctrl
)))
1217 ctrl
->no_cmd_complete
= 1;
1219 /* Check if Data Link Layer Link Active Reporting is implemented */
1220 if (pciehp_readl(ctrl
, LNKCAP
, &link_cap
)) {
1221 ctrl_err(ctrl
, "%s: Cannot read LNKCAP register\n", __func__
);
1224 if (link_cap
& LINK_ACTIVE_REPORTING
) {
1225 ctrl_dbg(ctrl
, "Link Active Reporting supported\n");
1226 ctrl
->link_active_reporting
= 1;
1229 /* Clear all remaining event bits in Slot Status register */
1230 if (pciehp_writew(ctrl
, SLOTSTATUS
, 0x1f))
1233 /* Disable sotfware notification */
1234 pcie_disable_notification(ctrl
);
1237 * If this is the first controller to be initialized,
1238 * initialize the pciehp work queue
1240 if (atomic_add_return(1, &pciehp_num_controllers
) == 1) {
1241 pciehp_wq
= create_singlethread_workqueue("pciehpd");
1246 ctrl_info(ctrl
, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1247 pdev
->vendor
, pdev
->device
, pdev
->subsystem_vendor
,
1248 pdev
->subsystem_device
);
1250 if (pcie_init_slot(ctrl
))
1253 if (pcie_init_notification(ctrl
))
1259 pcie_cleanup_slot(ctrl
);
1266 void pcie_release_ctrl(struct controller
*ctrl
)
1268 pcie_shutdown_notification(ctrl
);
1269 pcie_cleanup_slot(ctrl
);
1271 * If this is the last controller to be released, destroy the
1274 if (atomic_dec_and_test(&pciehp_num_controllers
))
1275 destroy_workqueue(pciehp_wq
);