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[PATCH] shpchp: Remove unnecessary hpc_ctlr_handle check
[deliverable/linux.git] / drivers / pci / hotplug / shpchp_hpc.c
1 /*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 #include "shpchp.h"
37
38 #ifdef DEBUG
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
47
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49
50 #define DBG_PRINT( dbg_flags, args... ) \
51 do { \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
53 { \
54 int len; \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
59 } \
60 } while (0)
61
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64 #else
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
68 #endif /* DEBUG */
69
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
75
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
84
85 /* Slot Configuration */
86 #define SLOT_NUM 0x0000001F
87 #define FIRST_DEV_NUM 0x00001F00
88 #define PSN 0x07FF0000
89 #define UPDOWN 0x20000000
90 #define MRLSENSOR 0x40000000
91 #define ATTN_BUTTON 0x80000000
92
93 /*
94 * Controller SERR-INT Register
95 */
96 #define GLOBAL_INTR_MASK (1 << 0)
97 #define GLOBAL_SERR_MASK (1 << 1)
98 #define COMMAND_INTR_MASK (1 << 2)
99 #define ARBITER_SERR_MASK (1 << 3)
100 #define COMMAND_DETECTED (1 << 16)
101 #define ARBITER_DETECTED (1 << 17)
102 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
103
104 /*
105 * Logical Slot Register definitions
106 */
107 #define SLOT_REG(i) (SLOT1 + (4 * i))
108
109 #define SLOT_STATE_SHIFT (0)
110 #define SLOT_STATE_MASK (3 << 0)
111 #define SLOT_STATE_PWRONLY (1)
112 #define SLOT_STATE_ENABLED (2)
113 #define SLOT_STATE_DISABLED (3)
114 #define PWR_LED_STATE_SHIFT (2)
115 #define PWR_LED_STATE_MASK (3 << 2)
116 #define ATN_LED_STATE_SHIFT (4)
117 #define ATN_LED_STATE_MASK (3 << 4)
118 #define ATN_LED_STATE_ON (1)
119 #define ATN_LED_STATE_BLINK (2)
120 #define ATN_LED_STATE_OFF (3)
121 #define POWER_FAULT (1 << 6)
122 #define ATN_BUTTON (1 << 7)
123 #define MRL_SENSOR (1 << 8)
124 #define MHZ66_CAP (1 << 9)
125 #define PRSNT_SHIFT (10)
126 #define PRSNT_MASK (3 << 10)
127 #define PCIX_CAP_SHIFT (12)
128 #define PCIX_CAP_MASK_PI1 (3 << 12)
129 #define PCIX_CAP_MASK_PI2 (7 << 12)
130 #define PRSNT_CHANGE_DETECTED (1 << 16)
131 #define ISO_PFAULT_DETECTED (1 << 17)
132 #define BUTTON_PRESS_DETECTED (1 << 18)
133 #define MRL_CHANGE_DETECTED (1 << 19)
134 #define CON_PFAULT_DETECTED (1 << 20)
135 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
136 #define ISO_PFAULT_INTR_MASK (1 << 25)
137 #define BUTTON_PRESS_INTR_MASK (1 << 26)
138 #define MRL_CHANGE_INTR_MASK (1 << 27)
139 #define CON_PFAULT_INTR_MASK (1 << 28)
140 #define MRL_CHANGE_SERR_MASK (1 << 29)
141 #define CON_PFAULT_SERR_MASK (1 << 30)
142 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
143
144 /* SHPC 'write' operations/commands */
145
146 /* Slot operation - 0x00h to 0x3Fh */
147
148 #define NO_CHANGE 0x00
149
150 /* Slot state - Bits 0 & 1 of controller command register */
151 #define SET_SLOT_PWR 0x01
152 #define SET_SLOT_ENABLE 0x02
153 #define SET_SLOT_DISABLE 0x03
154
155 /* Power indicator state - Bits 2 & 3 of controller command register*/
156 #define SET_PWR_ON 0x04
157 #define SET_PWR_BLINK 0x08
158 #define SET_PWR_OFF 0x0C
159
160 /* Attention indicator state - Bits 4 & 5 of controller command register*/
161 #define SET_ATTN_ON 0x010
162 #define SET_ATTN_BLINK 0x020
163 #define SET_ATTN_OFF 0x030
164
165 /* Set bus speed/mode A - 0x40h to 0x47h */
166 #define SETA_PCI_33MHZ 0x40
167 #define SETA_PCI_66MHZ 0x41
168 #define SETA_PCIX_66MHZ 0x42
169 #define SETA_PCIX_100MHZ 0x43
170 #define SETA_PCIX_133MHZ 0x44
171 #define RESERV_1 0x45
172 #define RESERV_2 0x46
173 #define RESERV_3 0x47
174
175 /* Set bus speed/mode B - 0x50h to 0x5fh */
176 #define SETB_PCI_33MHZ 0x50
177 #define SETB_PCI_66MHZ 0x51
178 #define SETB_PCIX_66MHZ_PM 0x52
179 #define SETB_PCIX_100MHZ_PM 0x53
180 #define SETB_PCIX_133MHZ_PM 0x54
181 #define SETB_PCIX_66MHZ_EM 0x55
182 #define SETB_PCIX_100MHZ_EM 0x56
183 #define SETB_PCIX_133MHZ_EM 0x57
184 #define SETB_PCIX_66MHZ_266 0x58
185 #define SETB_PCIX_100MHZ_266 0x59
186 #define SETB_PCIX_133MHZ_266 0x5a
187 #define SETB_PCIX_66MHZ_533 0x5b
188 #define SETB_PCIX_100MHZ_533 0x5c
189 #define SETB_PCIX_133MHZ_533 0x5d
190
191
192 /* Power-on all slots - 0x48h */
193 #define SET_PWR_ON_ALL 0x48
194
195 /* Enable all slots - 0x49h */
196 #define SET_ENABLE_ALL 0x49
197
198 /* SHPC controller command error code */
199 #define SWITCH_OPEN 0x1
200 #define INVALID_CMD 0x2
201 #define INVALID_SPEED_MODE 0x4
202
203 /* For accessing SHPC Working Register Set */
204 #define DWORD_SELECT 0x2
205 #define DWORD_DATA 0x4
206 #define BASE_OFFSET 0x0
207
208 /* Field Offset in Logical Slot Register - byte boundary */
209 #define SLOT_EVENT_LATCH 0x2
210 #define SLOT_SERR_INT_MASK 0x3
211
212 static spinlock_t hpc_event_lock;
213
214 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
215 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
216 static int ctlr_seq_num = 0; /* Controller sequenc # */
217 static spinlock_t list_lock;
218
219 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
220
221 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
222
223 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
224 static int hpc_check_cmd_status(struct controller *ctrl);
225
226 static inline u8 shpc_readb(struct controller *ctrl, int reg)
227 {
228 return readb(ctrl->hpc_ctlr_handle->creg + reg);
229 }
230
231 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
232 {
233 writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
234 }
235
236 static inline u16 shpc_readw(struct controller *ctrl, int reg)
237 {
238 return readw(ctrl->hpc_ctlr_handle->creg + reg);
239 }
240
241 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
242 {
243 writew(val, ctrl->hpc_ctlr_handle->creg + reg);
244 }
245
246 static inline u32 shpc_readl(struct controller *ctrl, int reg)
247 {
248 return readl(ctrl->hpc_ctlr_handle->creg + reg);
249 }
250
251 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
252 {
253 writel(val, ctrl->hpc_ctlr_handle->creg + reg);
254 }
255
256 static inline int shpc_indirect_read(struct controller *ctrl, int index,
257 u32 *value)
258 {
259 int rc;
260 u32 cap_offset = ctrl->cap_offset;
261 struct pci_dev *pdev = ctrl->pci_dev;
262
263 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
264 if (rc)
265 return rc;
266 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
267 }
268
269 /* This is the interrupt polling timeout function. */
270 static void int_poll_timeout(unsigned long lphp_ctlr)
271 {
272 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
273
274 DBG_ENTER_ROUTINE
275
276 if ( !php_ctlr ) {
277 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
278 return;
279 }
280
281 /* Poll for interrupt events. regs == NULL => polling */
282 shpc_isr( 0, (void *)php_ctlr, NULL );
283
284 init_timer(&php_ctlr->int_poll_timer);
285 if (!shpchp_poll_time)
286 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
287
288 start_int_poll_timer(php_ctlr, shpchp_poll_time);
289
290 return;
291 }
292
293 /* This function starts the interrupt polling timer. */
294 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
295 {
296 if (!php_ctlr) {
297 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
298 return;
299 }
300
301 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
302 seconds = 2; /* Clamp to sane value */
303
304 php_ctlr->int_poll_timer.function = &int_poll_timeout;
305 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
306 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
307 add_timer(&php_ctlr->int_poll_timer);
308
309 return;
310 }
311
312 static inline int shpc_wait_cmd(struct controller *ctrl)
313 {
314 int retval = 0;
315 unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000;
316 unsigned long timeout = msecs_to_jiffies(timeout_msec);
317 int rc = wait_event_interruptible_timeout(ctrl->queue,
318 !ctrl->cmd_busy, timeout);
319 if (!rc) {
320 retval = -EIO;
321 err("Command not completed in %d msec\n", timeout_msec);
322 } else if (rc < 0) {
323 retval = -EINTR;
324 info("Command was interrupted by a signal\n");
325 }
326 ctrl->cmd_busy = 0;
327
328 return retval;
329 }
330
331 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
332 {
333 struct controller *ctrl = slot->ctrl;
334 u16 cmd_status;
335 int retval = 0;
336 u16 temp_word;
337 int i;
338
339 DBG_ENTER_ROUTINE
340
341 mutex_lock(&slot->ctrl->cmd_lock);
342
343 for (i = 0; i < 10; i++) {
344 cmd_status = shpc_readw(ctrl, CMD_STATUS);
345
346 if (!(cmd_status & 0x1))
347 break;
348 /* Check every 0.1 sec for a total of 1 sec*/
349 msleep(100);
350 }
351
352 cmd_status = shpc_readw(ctrl, CMD_STATUS);
353
354 if (cmd_status & 0x1) {
355 /* After 1 sec and and the controller is still busy */
356 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
357 retval = -EBUSY;
358 goto out;
359 }
360
361 ++t_slot;
362 temp_word = (t_slot << 8) | (cmd & 0xFF);
363 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
364
365 /* To make sure the Controller Busy bit is 0 before we send out the
366 * command.
367 */
368 slot->ctrl->cmd_busy = 1;
369 shpc_writew(ctrl, CMD, temp_word);
370
371 /*
372 * Wait for command completion.
373 */
374 retval = shpc_wait_cmd(slot->ctrl);
375 if (retval)
376 goto out;
377
378 cmd_status = hpc_check_cmd_status(slot->ctrl);
379 if (cmd_status) {
380 err("%s: Failed to issued command 0x%x (error code = %d)\n",
381 __FUNCTION__, cmd, cmd_status);
382 retval = -EIO;
383 }
384 out:
385 mutex_unlock(&slot->ctrl->cmd_lock);
386
387 DBG_LEAVE_ROUTINE
388 return retval;
389 }
390
391 static int hpc_check_cmd_status(struct controller *ctrl)
392 {
393 u16 cmd_status;
394 int retval = 0;
395
396 DBG_ENTER_ROUTINE
397
398 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
399
400 switch (cmd_status >> 1) {
401 case 0:
402 retval = 0;
403 break;
404 case 1:
405 retval = SWITCH_OPEN;
406 err("%s: Switch opened!\n", __FUNCTION__);
407 break;
408 case 2:
409 retval = INVALID_CMD;
410 err("%s: Invalid HPC command!\n", __FUNCTION__);
411 break;
412 case 4:
413 retval = INVALID_SPEED_MODE;
414 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
415 break;
416 default:
417 retval = cmd_status;
418 }
419
420 DBG_LEAVE_ROUTINE
421 return retval;
422 }
423
424
425 static int hpc_get_attention_status(struct slot *slot, u8 *status)
426 {
427 struct controller *ctrl = slot->ctrl;
428 u32 slot_reg;
429 u8 state;
430
431 DBG_ENTER_ROUTINE
432
433 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
434 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
435
436 switch (state) {
437 case ATN_LED_STATE_ON:
438 *status = 1; /* On */
439 break;
440 case ATN_LED_STATE_BLINK:
441 *status = 2; /* Blink */
442 break;
443 case ATN_LED_STATE_OFF:
444 *status = 0; /* Off */
445 break;
446 default:
447 *status = 0xFF; /* Reserved */
448 break;
449 }
450
451 DBG_LEAVE_ROUTINE
452 return 0;
453 }
454
455 static int hpc_get_power_status(struct slot * slot, u8 *status)
456 {
457 struct controller *ctrl = slot->ctrl;
458 u32 slot_reg;
459 u8 state;
460
461 DBG_ENTER_ROUTINE
462
463 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
464 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
465
466 switch (state) {
467 case SLOT_STATE_PWRONLY:
468 *status = 2; /* Powered only */
469 break;
470 case SLOT_STATE_ENABLED:
471 *status = 1; /* Enabled */
472 break;
473 case SLOT_STATE_DISABLED:
474 *status = 0; /* Disabled */
475 break;
476 default:
477 *status = 0xFF; /* Reserved */
478 break;
479 }
480
481 DBG_LEAVE_ROUTINE
482 return 0;
483 }
484
485
486 static int hpc_get_latch_status(struct slot *slot, u8 *status)
487 {
488 struct controller *ctrl = slot->ctrl;
489 u32 slot_reg;
490
491 DBG_ENTER_ROUTINE
492
493 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
494 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
495
496 DBG_LEAVE_ROUTINE
497 return 0;
498 }
499
500 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
501 {
502 struct controller *ctrl = slot->ctrl;
503 u32 slot_reg;
504 u8 state;
505
506 DBG_ENTER_ROUTINE
507
508 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
509 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
510 *status = (state != 0x3) ? 1 : 0;
511
512 DBG_LEAVE_ROUTINE
513 return 0;
514 }
515
516 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
517 {
518 struct controller *ctrl = slot->ctrl;
519
520 DBG_ENTER_ROUTINE
521
522 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
523
524 DBG_LEAVE_ROUTINE
525 return 0;
526 }
527
528 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
529 {
530 int retval = 0;
531 struct controller *ctrl = slot->ctrl;
532 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
533 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
534 u8 pi, pcix_cap;
535
536 DBG_ENTER_ROUTINE
537
538 if ((retval = hpc_get_prog_int(slot, &pi)))
539 return retval;
540
541 switch (pi) {
542 case 1:
543 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
544 break;
545 case 2:
546 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
547 break;
548 default:
549 return -ENODEV;
550 }
551
552 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
553 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
554
555 switch (pcix_cap) {
556 case 0x0:
557 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
558 break;
559 case 0x1:
560 *value = PCI_SPEED_66MHz_PCIX;
561 break;
562 case 0x3:
563 *value = PCI_SPEED_133MHz_PCIX;
564 break;
565 case 0x4:
566 *value = PCI_SPEED_133MHz_PCIX_266;
567 break;
568 case 0x5:
569 *value = PCI_SPEED_133MHz_PCIX_533;
570 break;
571 case 0x2:
572 default:
573 *value = PCI_SPEED_UNKNOWN;
574 retval = -ENODEV;
575 break;
576 }
577
578 dbg("Adapter speed = %d\n", *value);
579 DBG_LEAVE_ROUTINE
580 return retval;
581 }
582
583 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
584 {
585 struct controller *ctrl = slot->ctrl;
586 u16 sec_bus_status;
587 u8 pi;
588 int retval = 0;
589
590 DBG_ENTER_ROUTINE
591
592 pi = shpc_readb(ctrl, PROG_INTERFACE);
593 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
594
595 if (pi == 2) {
596 *mode = (sec_bus_status & 0x0100) >> 8;
597 } else {
598 retval = -1;
599 }
600
601 dbg("Mode 1 ECC cap = %d\n", *mode);
602
603 DBG_LEAVE_ROUTINE
604 return retval;
605 }
606
607 static int hpc_query_power_fault(struct slot * slot)
608 {
609 struct controller *ctrl = slot->ctrl;
610 u32 slot_reg;
611
612 DBG_ENTER_ROUTINE
613
614 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
615
616 DBG_LEAVE_ROUTINE
617 /* Note: Logic 0 => fault */
618 return !(slot_reg & POWER_FAULT);
619 }
620
621 static int hpc_set_attention_status(struct slot *slot, u8 value)
622 {
623 u8 slot_cmd = 0;
624
625 switch (value) {
626 case 0 :
627 slot_cmd = 0x30; /* OFF */
628 break;
629 case 1:
630 slot_cmd = 0x10; /* ON */
631 break;
632 case 2:
633 slot_cmd = 0x20; /* BLINK */
634 break;
635 default:
636 return -1;
637 }
638
639 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
640 }
641
642
643 static void hpc_set_green_led_on(struct slot *slot)
644 {
645 shpc_write_cmd(slot, slot->hp_slot, 0x04);
646 }
647
648 static void hpc_set_green_led_off(struct slot *slot)
649 {
650 shpc_write_cmd(slot, slot->hp_slot, 0x0c);
651 }
652
653 static void hpc_set_green_led_blink(struct slot *slot)
654 {
655 shpc_write_cmd(slot, slot->hp_slot, 0x08);
656 }
657
658 int shpc_get_ctlr_slot_config(struct controller *ctrl,
659 int *num_ctlr_slots, /* number of slots in this HPC */
660 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
661 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
662 int *updown, /* physical_slot_num increament: 1 or -1 */
663 int *flags)
664 {
665 u32 slot_config;
666
667 DBG_ENTER_ROUTINE
668
669 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
670 *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
671 *num_ctlr_slots = slot_config & SLOT_NUM;
672 *physical_slot_num = (slot_config & PSN) >> 16;
673 *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
674
675 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
676
677 DBG_LEAVE_ROUTINE
678 return 0;
679 }
680
681 static void hpc_release_ctlr(struct controller *ctrl)
682 {
683 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
684 struct php_ctlr_state_s *p, *p_prev;
685 int i;
686 u32 slot_reg, serr_int;
687
688 DBG_ENTER_ROUTINE
689
690 /*
691 * Mask event interrupts and SERRs of all slots
692 */
693 for (i = 0; i < ctrl->num_slots; i++) {
694 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
695 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
696 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
697 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
698 CON_PFAULT_SERR_MASK);
699 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
700 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
701 }
702
703 cleanup_slots(ctrl);
704
705 /*
706 * Mask SERR and System Interrut generation
707 */
708 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
709 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
710 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
711 serr_int &= ~SERR_INTR_RSVDZ_MASK;
712 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
713
714 if (shpchp_poll_mode) {
715 del_timer(&php_ctlr->int_poll_timer);
716 } else {
717 if (php_ctlr->irq) {
718 free_irq(php_ctlr->irq, ctrl);
719 php_ctlr->irq = 0;
720 pci_disable_msi(php_ctlr->pci_dev);
721 }
722 }
723
724 if (php_ctlr->pci_dev) {
725 iounmap(php_ctlr->creg);
726 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
727 php_ctlr->pci_dev = NULL;
728 }
729
730 spin_lock(&list_lock);
731 p = php_ctlr_list_head;
732 p_prev = NULL;
733 while (p) {
734 if (p == php_ctlr) {
735 if (p_prev)
736 p_prev->pnext = p->pnext;
737 else
738 php_ctlr_list_head = p->pnext;
739 break;
740 } else {
741 p_prev = p;
742 p = p->pnext;
743 }
744 }
745 spin_unlock(&list_lock);
746
747 kfree(php_ctlr);
748
749 /*
750 * If this is the last controller to be released, destroy the
751 * shpchpd work queue
752 */
753 if (atomic_dec_and_test(&shpchp_num_controllers))
754 destroy_workqueue(shpchp_wq);
755
756 DBG_LEAVE_ROUTINE
757
758 }
759
760 static int hpc_power_on_slot(struct slot * slot)
761 {
762 int retval;
763
764 DBG_ENTER_ROUTINE
765
766 retval = shpc_write_cmd(slot, slot->hp_slot, 0x01);
767 if (retval) {
768 err("%s: Write command failed!\n", __FUNCTION__);
769 return retval;
770 }
771
772 DBG_LEAVE_ROUTINE
773
774 return 0;
775 }
776
777 static int hpc_slot_enable(struct slot * slot)
778 {
779 int retval;
780
781 DBG_ENTER_ROUTINE
782
783 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
784 retval = shpc_write_cmd(slot, slot->hp_slot, 0x3a);
785 if (retval) {
786 err("%s: Write command failed!\n", __FUNCTION__);
787 return retval;
788 }
789
790 DBG_LEAVE_ROUTINE
791 return 0;
792 }
793
794 static int hpc_slot_disable(struct slot * slot)
795 {
796 int retval;
797
798 DBG_ENTER_ROUTINE
799
800 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
801 retval = shpc_write_cmd(slot, slot->hp_slot, 0x1f);
802 if (retval) {
803 err("%s: Write command failed!\n", __FUNCTION__);
804 return retval;
805 }
806
807 DBG_LEAVE_ROUTINE
808 return 0;
809 }
810
811 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
812 {
813 int retval;
814 struct controller *ctrl = slot->ctrl;
815 u8 pi, cmd;
816
817 DBG_ENTER_ROUTINE
818
819 pi = shpc_readb(ctrl, PROG_INTERFACE);
820 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
821 return -EINVAL;
822
823 switch (value) {
824 case PCI_SPEED_33MHz:
825 cmd = SETA_PCI_33MHZ;
826 break;
827 case PCI_SPEED_66MHz:
828 cmd = SETA_PCI_66MHZ;
829 break;
830 case PCI_SPEED_66MHz_PCIX:
831 cmd = SETA_PCIX_66MHZ;
832 break;
833 case PCI_SPEED_100MHz_PCIX:
834 cmd = SETA_PCIX_100MHZ;
835 break;
836 case PCI_SPEED_133MHz_PCIX:
837 cmd = SETA_PCIX_133MHZ;
838 break;
839 case PCI_SPEED_66MHz_PCIX_ECC:
840 cmd = SETB_PCIX_66MHZ_EM;
841 break;
842 case PCI_SPEED_100MHz_PCIX_ECC:
843 cmd = SETB_PCIX_100MHZ_EM;
844 break;
845 case PCI_SPEED_133MHz_PCIX_ECC:
846 cmd = SETB_PCIX_133MHZ_EM;
847 break;
848 case PCI_SPEED_66MHz_PCIX_266:
849 cmd = SETB_PCIX_66MHZ_266;
850 break;
851 case PCI_SPEED_100MHz_PCIX_266:
852 cmd = SETB_PCIX_100MHZ_266;
853 break;
854 case PCI_SPEED_133MHz_PCIX_266:
855 cmd = SETB_PCIX_133MHZ_266;
856 break;
857 case PCI_SPEED_66MHz_PCIX_533:
858 cmd = SETB_PCIX_66MHZ_533;
859 break;
860 case PCI_SPEED_100MHz_PCIX_533:
861 cmd = SETB_PCIX_100MHZ_533;
862 break;
863 case PCI_SPEED_133MHz_PCIX_533:
864 cmd = SETB_PCIX_133MHZ_533;
865 break;
866 default:
867 return -EINVAL;
868 }
869
870 retval = shpc_write_cmd(slot, 0, cmd);
871 if (retval)
872 err("%s: Write command failed!\n", __FUNCTION__);
873
874 DBG_LEAVE_ROUTINE
875 return retval;
876 }
877
878 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
879 {
880 struct controller *ctrl = NULL;
881 struct php_ctlr_state_s *php_ctlr;
882 u8 schedule_flag = 0;
883 u32 temp_dword, intr_loc, intr_loc2;
884 int hp_slot;
885
886 if (!dev_id)
887 return IRQ_NONE;
888
889 if (!shpchp_poll_mode) {
890 ctrl = (struct controller *)dev_id;
891 php_ctlr = ctrl->hpc_ctlr_handle;
892 } else {
893 php_ctlr = (struct php_ctlr_state_s *) dev_id;
894 ctrl = (struct controller *)php_ctlr->callback_instance_id;
895 }
896
897 if (!ctrl)
898 return IRQ_NONE;
899
900 if (!php_ctlr || !php_ctlr->creg)
901 return IRQ_NONE;
902
903 /* Check to see if it was our interrupt */
904 intr_loc = shpc_readl(ctrl, INTR_LOC);
905
906 if (!intr_loc)
907 return IRQ_NONE;
908 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
909
910 if(!shpchp_poll_mode) {
911 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
912 /* of SHPC spec rev 1.0*/
913 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
914 temp_dword |= GLOBAL_INTR_MASK;
915 temp_dword &= ~SERR_INTR_RSVDZ_MASK;
916 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
917
918 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
919 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
920 }
921
922 if (intr_loc & 0x0001) {
923 /*
924 * Command Complete Interrupt Pending
925 * RO only - clear by writing 1 to the Command Completion
926 * Detect bit in Controller SERR-INT register
927 */
928 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
929 temp_dword &= ~SERR_INTR_RSVDZ_MASK;
930 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
931 ctrl->cmd_busy = 0;
932 wake_up_interruptible(&ctrl->queue);
933 }
934
935 if ((intr_loc = (intr_loc >> 1)) == 0)
936 goto out;
937
938 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
939 /* To find out which slot has interrupt pending */
940 if ((intr_loc >> hp_slot) & 0x01) {
941 temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot));
942 dbg("%s: Slot %x with intr, slot register = %x\n",
943 __FUNCTION__, hp_slot, temp_dword);
944 if ((php_ctlr->switch_change_callback) &&
945 (temp_dword & MRL_CHANGE_DETECTED))
946 schedule_flag += php_ctlr->switch_change_callback(
947 hp_slot, php_ctlr->callback_instance_id);
948 if ((php_ctlr->attention_button_callback) &&
949 (temp_dword & BUTTON_PRESS_DETECTED))
950 schedule_flag += php_ctlr->attention_button_callback(
951 hp_slot, php_ctlr->callback_instance_id);
952 if ((php_ctlr->presence_change_callback) &&
953 (temp_dword & PRSNT_CHANGE_DETECTED))
954 schedule_flag += php_ctlr->presence_change_callback(
955 hp_slot , php_ctlr->callback_instance_id);
956 if ((php_ctlr->power_fault_callback) &&
957 (temp_dword & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)))
958 schedule_flag += php_ctlr->power_fault_callback(
959 hp_slot, php_ctlr->callback_instance_id);
960
961 /* Clear all slot events */
962 temp_dword &= ~SLOT_REG_RSVDZ_MASK;
963 shpc_writel(ctrl, SLOT_REG(hp_slot), temp_dword);
964
965 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
966 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
967 }
968 }
969 out:
970 if (!shpchp_poll_mode) {
971 /* Unmask Global Interrupt Mask */
972 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
973 temp_dword &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
974 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
975 }
976
977 return IRQ_HANDLED;
978 }
979
980 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
981 {
982 int retval = 0;
983 struct controller *ctrl = slot->ctrl;
984 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
985 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
986 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
987 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
988
989 DBG_ENTER_ROUTINE
990
991 if (pi == 2) {
992 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
993 bus_speed = PCI_SPEED_133MHz_PCIX_533;
994 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
995 bus_speed = PCI_SPEED_100MHz_PCIX_533;
996 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
997 bus_speed = PCI_SPEED_66MHz_PCIX_533;
998 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
999 bus_speed = PCI_SPEED_133MHz_PCIX_266;
1000 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
1001 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1002 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1003 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1004 }
1005
1006 if (bus_speed == PCI_SPEED_UNKNOWN) {
1007 if (slot_avail1 & SLOT_133MHZ_PCIX)
1008 bus_speed = PCI_SPEED_133MHz_PCIX;
1009 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1010 bus_speed = PCI_SPEED_100MHz_PCIX;
1011 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1012 bus_speed = PCI_SPEED_66MHz_PCIX;
1013 else if (slot_avail2 & SLOT_66MHZ)
1014 bus_speed = PCI_SPEED_66MHz;
1015 else if (slot_avail1 & SLOT_33MHZ)
1016 bus_speed = PCI_SPEED_33MHz;
1017 else
1018 retval = -ENODEV;
1019 }
1020
1021 *value = bus_speed;
1022 dbg("Max bus speed = %d\n", bus_speed);
1023 DBG_LEAVE_ROUTINE
1024 return retval;
1025 }
1026
1027 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1028 {
1029 int retval = 0;
1030 struct controller *ctrl = slot->ctrl;
1031 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1032 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
1033 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1034 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
1035
1036 DBG_ENTER_ROUTINE
1037
1038 if ((pi == 1) && (speed_mode > 4)) {
1039 *value = PCI_SPEED_UNKNOWN;
1040 return -ENODEV;
1041 }
1042
1043 switch (speed_mode) {
1044 case 0x0:
1045 *value = PCI_SPEED_33MHz;
1046 break;
1047 case 0x1:
1048 *value = PCI_SPEED_66MHz;
1049 break;
1050 case 0x2:
1051 *value = PCI_SPEED_66MHz_PCIX;
1052 break;
1053 case 0x3:
1054 *value = PCI_SPEED_100MHz_PCIX;
1055 break;
1056 case 0x4:
1057 *value = PCI_SPEED_133MHz_PCIX;
1058 break;
1059 case 0x5:
1060 *value = PCI_SPEED_66MHz_PCIX_ECC;
1061 break;
1062 case 0x6:
1063 *value = PCI_SPEED_100MHz_PCIX_ECC;
1064 break;
1065 case 0x7:
1066 *value = PCI_SPEED_133MHz_PCIX_ECC;
1067 break;
1068 case 0x8:
1069 *value = PCI_SPEED_66MHz_PCIX_266;
1070 break;
1071 case 0x9:
1072 *value = PCI_SPEED_100MHz_PCIX_266;
1073 break;
1074 case 0xa:
1075 *value = PCI_SPEED_133MHz_PCIX_266;
1076 break;
1077 case 0xb:
1078 *value = PCI_SPEED_66MHz_PCIX_533;
1079 break;
1080 case 0xc:
1081 *value = PCI_SPEED_100MHz_PCIX_533;
1082 break;
1083 case 0xd:
1084 *value = PCI_SPEED_133MHz_PCIX_533;
1085 break;
1086 default:
1087 *value = PCI_SPEED_UNKNOWN;
1088 retval = -ENODEV;
1089 break;
1090 }
1091
1092 dbg("Current bus speed = %d\n", bus_speed);
1093 DBG_LEAVE_ROUTINE
1094 return retval;
1095 }
1096
1097 static struct hpc_ops shpchp_hpc_ops = {
1098 .power_on_slot = hpc_power_on_slot,
1099 .slot_enable = hpc_slot_enable,
1100 .slot_disable = hpc_slot_disable,
1101 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1102 .set_attention_status = hpc_set_attention_status,
1103 .get_power_status = hpc_get_power_status,
1104 .get_attention_status = hpc_get_attention_status,
1105 .get_latch_status = hpc_get_latch_status,
1106 .get_adapter_status = hpc_get_adapter_status,
1107
1108 .get_max_bus_speed = hpc_get_max_bus_speed,
1109 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1110 .get_adapter_speed = hpc_get_adapter_speed,
1111 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1112 .get_prog_int = hpc_get_prog_int,
1113
1114 .query_power_fault = hpc_query_power_fault,
1115 .green_led_on = hpc_set_green_led_on,
1116 .green_led_off = hpc_set_green_led_off,
1117 .green_led_blink = hpc_set_green_led_blink,
1118
1119 .release_ctlr = hpc_release_ctlr,
1120 };
1121
1122 int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1123 {
1124 struct php_ctlr_state_s *php_ctlr, *p;
1125 void *instance_id = ctrl;
1126 int rc, num_slots = 0;
1127 u8 hp_slot;
1128 static int first = 1;
1129 u32 shpc_base_offset;
1130 u32 tempdword, slot_reg, slot_config;
1131 u8 i;
1132
1133 DBG_ENTER_ROUTINE
1134
1135 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1136
1137 spin_lock_init(&list_lock);
1138 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);
1139
1140 if (!php_ctlr) { /* allocate controller state data */
1141 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1142 goto abort;
1143 }
1144
1145 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1146
1147 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1148 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1149 /* amd shpc driver doesn't use Base Offset; assume 0 */
1150 ctrl->mmio_base = pci_resource_start(pdev, 0);
1151 ctrl->mmio_size = pci_resource_len(pdev, 0);
1152 } else {
1153 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1154 if (!ctrl->cap_offset) {
1155 err("%s : cap_offset == 0\n", __FUNCTION__);
1156 goto abort_free_ctlr;
1157 }
1158 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1159
1160 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
1161 if (rc) {
1162 err("%s: cannot read base_offset\n", __FUNCTION__);
1163 goto abort_free_ctlr;
1164 }
1165
1166 rc = shpc_indirect_read(ctrl, 3, &tempdword);
1167 if (rc) {
1168 err("%s: cannot read slot config\n", __FUNCTION__);
1169 goto abort_free_ctlr;
1170 }
1171 num_slots = tempdword & SLOT_NUM;
1172 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1173
1174 for (i = 0; i < 9 + num_slots; i++) {
1175 rc = shpc_indirect_read(ctrl, i, &tempdword);
1176 if (rc) {
1177 err("%s: cannot read creg (index = %d)\n",
1178 __FUNCTION__, i);
1179 goto abort_free_ctlr;
1180 }
1181 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1182 tempdword);
1183 }
1184
1185 ctrl->mmio_base =
1186 pci_resource_start(pdev, 0) + shpc_base_offset;
1187 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1188 }
1189
1190 if (first) {
1191 spin_lock_init(&hpc_event_lock);
1192 first = 0;
1193 }
1194
1195 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1196 pdev->subsystem_device);
1197
1198 if (pci_enable_device(pdev))
1199 goto abort_free_ctlr;
1200
1201 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1202 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1203 goto abort_free_ctlr;
1204 }
1205
1206 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1207 if (!php_ctlr->creg) {
1208 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1209 ctrl->mmio_size, ctrl->mmio_base);
1210 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1211 goto abort_free_ctlr;
1212 }
1213 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1214
1215 mutex_init(&ctrl->crit_sect);
1216 mutex_init(&ctrl->cmd_lock);
1217
1218 /* Setup wait queue */
1219 init_waitqueue_head(&ctrl->queue);
1220
1221 /* Find the IRQ */
1222 php_ctlr->irq = pdev->irq;
1223 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1224 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1225 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1226 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1227 php_ctlr->callback_instance_id = instance_id;
1228
1229 ctrl->hpc_ctlr_handle = php_ctlr;
1230 ctrl->hpc_ops = &shpchp_hpc_ops;
1231
1232 /* Return PCI Controller Info */
1233 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1234 php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1235 php_ctlr->num_slots = slot_config & SLOT_NUM;
1236 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1237 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1238
1239 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1240 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1241 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1242 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1243 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1244 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1245 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1246 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1247 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1248
1249 /* Mask the MRL sensor SERR Mask of individual slot in
1250 * Slot SERR-INT Mask & clear all the existing event if any
1251 */
1252 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1253 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1254 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1255 hp_slot, slot_reg);
1256 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1257 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1258 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1259 CON_PFAULT_SERR_MASK);
1260 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1261 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1262 }
1263
1264 if (shpchp_poll_mode) {/* Install interrupt polling code */
1265 /* Install and start the interrupt polling timer */
1266 init_timer(&php_ctlr->int_poll_timer);
1267 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1268 } else {
1269 /* Installs the interrupt handler */
1270 rc = pci_enable_msi(pdev);
1271 if (rc) {
1272 info("Can't get msi for the hotplug controller\n");
1273 info("Use INTx for the hotplug controller\n");
1274 } else
1275 php_ctlr->irq = pdev->irq;
1276
1277 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1278 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1279 if (rc) {
1280 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1281 goto abort_free_ctlr;
1282 }
1283 }
1284 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1285 pdev->bus->number, PCI_SLOT(pdev->devfn),
1286 PCI_FUNC(pdev->devfn), pdev->irq);
1287 get_hp_hw_control_from_firmware(pdev);
1288
1289 /* Add this HPC instance into the HPC list */
1290 spin_lock(&list_lock);
1291 if (php_ctlr_list_head == 0) {
1292 php_ctlr_list_head = php_ctlr;
1293 p = php_ctlr_list_head;
1294 p->pnext = NULL;
1295 } else {
1296 p = php_ctlr_list_head;
1297
1298 while (p->pnext)
1299 p = p->pnext;
1300
1301 p->pnext = php_ctlr;
1302 }
1303 spin_unlock(&list_lock);
1304
1305 ctlr_seq_num++;
1306
1307 /*
1308 * If this is the first controller to be initialized,
1309 * initialize the shpchpd work queue
1310 */
1311 if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
1312 shpchp_wq = create_singlethread_workqueue("shpchpd");
1313 if (!shpchp_wq)
1314 return -ENOMEM;
1315 }
1316
1317 /*
1318 * Unmask all event interrupts of all slots
1319 */
1320 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1321 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1322 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1323 hp_slot, slot_reg);
1324 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1325 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1326 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1327 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1328 }
1329 if (!shpchp_poll_mode) {
1330 /* Unmask all general input interrupts and SERR */
1331 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1332 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1333 SERR_INTR_RSVDZ_MASK);
1334 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1335 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1336 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1337 }
1338
1339 DBG_LEAVE_ROUTINE
1340 return 0;
1341
1342 /* We end up here for the many possible ways to fail this API. */
1343 abort_free_ctlr:
1344 kfree(php_ctlr);
1345 abort:
1346 DBG_LEAVE_ROUTINE
1347 return -1;
1348 }
Linux kernel - Deliverables
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