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Merge branch 'parisc' from /home/kyle/repos/parisc-2.6.git
[deliverable/linux.git] / drivers / pci / hotplug / shpchp_hpc.c
1 /*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 #include "shpchp.h"
37
38 #ifdef DEBUG
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
47
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49
50 #define DBG_PRINT( dbg_flags, args... ) \
51 do { \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
53 { \
54 int len; \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
59 } \
60 } while (0)
61
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64 #else
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
68 #endif /* DEBUG */
69
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
75
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
84
85 /* Slot Configuration */
86 #define SLOT_NUM 0x0000001F
87 #define FIRST_DEV_NUM 0x00001F00
88 #define PSN 0x07FF0000
89 #define UPDOWN 0x20000000
90 #define MRLSENSOR 0x40000000
91 #define ATTN_BUTTON 0x80000000
92
93 /*
94 * Interrupt Locator Register definitions
95 */
96 #define CMD_INTR_PENDING (1 << 0)
97 #define SLOT_INTR_PENDING(i) (1 << (i + 1))
98
99 /*
100 * Controller SERR-INT Register
101 */
102 #define GLOBAL_INTR_MASK (1 << 0)
103 #define GLOBAL_SERR_MASK (1 << 1)
104 #define COMMAND_INTR_MASK (1 << 2)
105 #define ARBITER_SERR_MASK (1 << 3)
106 #define COMMAND_DETECTED (1 << 16)
107 #define ARBITER_DETECTED (1 << 17)
108 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
109
110 /*
111 * Logical Slot Register definitions
112 */
113 #define SLOT_REG(i) (SLOT1 + (4 * i))
114
115 #define SLOT_STATE_SHIFT (0)
116 #define SLOT_STATE_MASK (3 << 0)
117 #define SLOT_STATE_PWRONLY (1)
118 #define SLOT_STATE_ENABLED (2)
119 #define SLOT_STATE_DISABLED (3)
120 #define PWR_LED_STATE_SHIFT (2)
121 #define PWR_LED_STATE_MASK (3 << 2)
122 #define ATN_LED_STATE_SHIFT (4)
123 #define ATN_LED_STATE_MASK (3 << 4)
124 #define ATN_LED_STATE_ON (1)
125 #define ATN_LED_STATE_BLINK (2)
126 #define ATN_LED_STATE_OFF (3)
127 #define POWER_FAULT (1 << 6)
128 #define ATN_BUTTON (1 << 7)
129 #define MRL_SENSOR (1 << 8)
130 #define MHZ66_CAP (1 << 9)
131 #define PRSNT_SHIFT (10)
132 #define PRSNT_MASK (3 << 10)
133 #define PCIX_CAP_SHIFT (12)
134 #define PCIX_CAP_MASK_PI1 (3 << 12)
135 #define PCIX_CAP_MASK_PI2 (7 << 12)
136 #define PRSNT_CHANGE_DETECTED (1 << 16)
137 #define ISO_PFAULT_DETECTED (1 << 17)
138 #define BUTTON_PRESS_DETECTED (1 << 18)
139 #define MRL_CHANGE_DETECTED (1 << 19)
140 #define CON_PFAULT_DETECTED (1 << 20)
141 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
142 #define ISO_PFAULT_INTR_MASK (1 << 25)
143 #define BUTTON_PRESS_INTR_MASK (1 << 26)
144 #define MRL_CHANGE_INTR_MASK (1 << 27)
145 #define CON_PFAULT_INTR_MASK (1 << 28)
146 #define MRL_CHANGE_SERR_MASK (1 << 29)
147 #define CON_PFAULT_SERR_MASK (1 << 30)
148 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
149
150 /*
151 * SHPC Command Code definitnions
152 *
153 * Slot Operation 00h - 3Fh
154 * Set Bus Segment Speed/Mode A 40h - 47h
155 * Power-Only All Slots 48h
156 * Enable All Slots 49h
157 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
158 * Reserved Command Codes 60h - BFh
159 * Vendor Specific Commands C0h - FFh
160 */
161 #define SET_SLOT_PWR 0x01 /* Slot Operation */
162 #define SET_SLOT_ENABLE 0x02
163 #define SET_SLOT_DISABLE 0x03
164 #define SET_PWR_ON 0x04
165 #define SET_PWR_BLINK 0x08
166 #define SET_PWR_OFF 0x0c
167 #define SET_ATTN_ON 0x10
168 #define SET_ATTN_BLINK 0x20
169 #define SET_ATTN_OFF 0x30
170 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
171 #define SETA_PCI_66MHZ 0x41
172 #define SETA_PCIX_66MHZ 0x42
173 #define SETA_PCIX_100MHZ 0x43
174 #define SETA_PCIX_133MHZ 0x44
175 #define SETA_RESERVED1 0x45
176 #define SETA_RESERVED2 0x46
177 #define SETA_RESERVED3 0x47
178 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
179 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */
180 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
181 #define SETB_PCI_66MHZ 0x51
182 #define SETB_PCIX_66MHZ_PM 0x52
183 #define SETB_PCIX_100MHZ_PM 0x53
184 #define SETB_PCIX_133MHZ_PM 0x54
185 #define SETB_PCIX_66MHZ_EM 0x55
186 #define SETB_PCIX_100MHZ_EM 0x56
187 #define SETB_PCIX_133MHZ_EM 0x57
188 #define SETB_PCIX_66MHZ_266 0x58
189 #define SETB_PCIX_100MHZ_266 0x59
190 #define SETB_PCIX_133MHZ_266 0x5a
191 #define SETB_PCIX_66MHZ_533 0x5b
192 #define SETB_PCIX_100MHZ_533 0x5c
193 #define SETB_PCIX_133MHZ_533 0x5d
194 #define SETB_RESERVED1 0x5e
195 #define SETB_RESERVED2 0x5f
196
197 /*
198 * SHPC controller command error code
199 */
200 #define SWITCH_OPEN 0x1
201 #define INVALID_CMD 0x2
202 #define INVALID_SPEED_MODE 0x4
203
204 /*
205 * For accessing SHPC Working Register Set via PCI Configuration Space
206 */
207 #define DWORD_SELECT 0x2
208 #define DWORD_DATA 0x4
209
210 /* Field Offset in Logical Slot Register - byte boundary */
211 #define SLOT_EVENT_LATCH 0x2
212 #define SLOT_SERR_INT_MASK 0x3
213
214 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
215 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
216
217 static irqreturn_t shpc_isr(int irq, void *dev_id);
218 static void start_int_poll_timer(struct controller *ctrl, int sec);
219 static int hpc_check_cmd_status(struct controller *ctrl);
220
221 static inline u8 shpc_readb(struct controller *ctrl, int reg)
222 {
223 return readb(ctrl->creg + reg);
224 }
225
226 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
227 {
228 writeb(val, ctrl->creg + reg);
229 }
230
231 static inline u16 shpc_readw(struct controller *ctrl, int reg)
232 {
233 return readw(ctrl->creg + reg);
234 }
235
236 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
237 {
238 writew(val, ctrl->creg + reg);
239 }
240
241 static inline u32 shpc_readl(struct controller *ctrl, int reg)
242 {
243 return readl(ctrl->creg + reg);
244 }
245
246 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
247 {
248 writel(val, ctrl->creg + reg);
249 }
250
251 static inline int shpc_indirect_read(struct controller *ctrl, int index,
252 u32 *value)
253 {
254 int rc;
255 u32 cap_offset = ctrl->cap_offset;
256 struct pci_dev *pdev = ctrl->pci_dev;
257
258 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
259 if (rc)
260 return rc;
261 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
262 }
263
264 /*
265 * This is the interrupt polling timeout function.
266 */
267 static void int_poll_timeout(unsigned long data)
268 {
269 struct controller *ctrl = (struct controller *)data;
270
271 DBG_ENTER_ROUTINE
272
273 /* Poll for interrupt events. regs == NULL => polling */
274 shpc_isr(0, ctrl);
275
276 init_timer(&ctrl->poll_timer);
277 if (!shpchp_poll_time)
278 shpchp_poll_time = 2; /* default polling interval is 2 sec */
279
280 start_int_poll_timer(ctrl, shpchp_poll_time);
281
282 DBG_LEAVE_ROUTINE
283 }
284
285 /*
286 * This function starts the interrupt polling timer.
287 */
288 static void start_int_poll_timer(struct controller *ctrl, int sec)
289 {
290 /* Clamp to sane value */
291 if ((sec <= 0) || (sec > 60))
292 sec = 2;
293
294 ctrl->poll_timer.function = &int_poll_timeout;
295 ctrl->poll_timer.data = (unsigned long)ctrl;
296 ctrl->poll_timer.expires = jiffies + sec * HZ;
297 add_timer(&ctrl->poll_timer);
298 }
299
300 static inline int is_ctrl_busy(struct controller *ctrl)
301 {
302 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
303 return cmd_status & 0x1;
304 }
305
306 /*
307 * Returns 1 if SHPC finishes executing a command within 1 sec,
308 * otherwise returns 0.
309 */
310 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
311 {
312 int i;
313
314 if (!is_ctrl_busy(ctrl))
315 return 1;
316
317 /* Check every 0.1 sec for a total of 1 sec */
318 for (i = 0; i < 10; i++) {
319 msleep(100);
320 if (!is_ctrl_busy(ctrl))
321 return 1;
322 }
323
324 return 0;
325 }
326
327 static inline int shpc_wait_cmd(struct controller *ctrl)
328 {
329 int retval = 0;
330 unsigned long timeout = msecs_to_jiffies(1000);
331 int rc;
332
333 if (shpchp_poll_mode)
334 rc = shpc_poll_ctrl_busy(ctrl);
335 else
336 rc = wait_event_interruptible_timeout(ctrl->queue,
337 !is_ctrl_busy(ctrl), timeout);
338 if (!rc && is_ctrl_busy(ctrl)) {
339 retval = -EIO;
340 err("Command not completed in 1000 msec\n");
341 } else if (rc < 0) {
342 retval = -EINTR;
343 info("Command was interrupted by a signal\n");
344 }
345
346 return retval;
347 }
348
349 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
350 {
351 struct controller *ctrl = slot->ctrl;
352 u16 cmd_status;
353 int retval = 0;
354 u16 temp_word;
355
356 DBG_ENTER_ROUTINE
357
358 mutex_lock(&slot->ctrl->cmd_lock);
359
360 if (!shpc_poll_ctrl_busy(ctrl)) {
361 /* After 1 sec and and the controller is still busy */
362 err("%s : Controller is still busy after 1 sec.\n",
363 __FUNCTION__);
364 retval = -EBUSY;
365 goto out;
366 }
367
368 ++t_slot;
369 temp_word = (t_slot << 8) | (cmd & 0xFF);
370 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
371
372 /* To make sure the Controller Busy bit is 0 before we send out the
373 * command.
374 */
375 shpc_writew(ctrl, CMD, temp_word);
376
377 /*
378 * Wait for command completion.
379 */
380 retval = shpc_wait_cmd(slot->ctrl);
381 if (retval)
382 goto out;
383
384 cmd_status = hpc_check_cmd_status(slot->ctrl);
385 if (cmd_status) {
386 err("%s: Failed to issued command 0x%x (error code = %d)\n",
387 __FUNCTION__, cmd, cmd_status);
388 retval = -EIO;
389 }
390 out:
391 mutex_unlock(&slot->ctrl->cmd_lock);
392
393 DBG_LEAVE_ROUTINE
394 return retval;
395 }
396
397 static int hpc_check_cmd_status(struct controller *ctrl)
398 {
399 u16 cmd_status;
400 int retval = 0;
401
402 DBG_ENTER_ROUTINE
403
404 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
405
406 switch (cmd_status >> 1) {
407 case 0:
408 retval = 0;
409 break;
410 case 1:
411 retval = SWITCH_OPEN;
412 err("%s: Switch opened!\n", __FUNCTION__);
413 break;
414 case 2:
415 retval = INVALID_CMD;
416 err("%s: Invalid HPC command!\n", __FUNCTION__);
417 break;
418 case 4:
419 retval = INVALID_SPEED_MODE;
420 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
421 break;
422 default:
423 retval = cmd_status;
424 }
425
426 DBG_LEAVE_ROUTINE
427 return retval;
428 }
429
430
431 static int hpc_get_attention_status(struct slot *slot, u8 *status)
432 {
433 struct controller *ctrl = slot->ctrl;
434 u32 slot_reg;
435 u8 state;
436
437 DBG_ENTER_ROUTINE
438
439 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
440 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
441
442 switch (state) {
443 case ATN_LED_STATE_ON:
444 *status = 1; /* On */
445 break;
446 case ATN_LED_STATE_BLINK:
447 *status = 2; /* Blink */
448 break;
449 case ATN_LED_STATE_OFF:
450 *status = 0; /* Off */
451 break;
452 default:
453 *status = 0xFF; /* Reserved */
454 break;
455 }
456
457 DBG_LEAVE_ROUTINE
458 return 0;
459 }
460
461 static int hpc_get_power_status(struct slot * slot, u8 *status)
462 {
463 struct controller *ctrl = slot->ctrl;
464 u32 slot_reg;
465 u8 state;
466
467 DBG_ENTER_ROUTINE
468
469 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
470 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
471
472 switch (state) {
473 case SLOT_STATE_PWRONLY:
474 *status = 2; /* Powered only */
475 break;
476 case SLOT_STATE_ENABLED:
477 *status = 1; /* Enabled */
478 break;
479 case SLOT_STATE_DISABLED:
480 *status = 0; /* Disabled */
481 break;
482 default:
483 *status = 0xFF; /* Reserved */
484 break;
485 }
486
487 DBG_LEAVE_ROUTINE
488 return 0;
489 }
490
491
492 static int hpc_get_latch_status(struct slot *slot, u8 *status)
493 {
494 struct controller *ctrl = slot->ctrl;
495 u32 slot_reg;
496
497 DBG_ENTER_ROUTINE
498
499 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
500 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
501
502 DBG_LEAVE_ROUTINE
503 return 0;
504 }
505
506 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
507 {
508 struct controller *ctrl = slot->ctrl;
509 u32 slot_reg;
510 u8 state;
511
512 DBG_ENTER_ROUTINE
513
514 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
515 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
516 *status = (state != 0x3) ? 1 : 0;
517
518 DBG_LEAVE_ROUTINE
519 return 0;
520 }
521
522 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
523 {
524 struct controller *ctrl = slot->ctrl;
525
526 DBG_ENTER_ROUTINE
527
528 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
529
530 DBG_LEAVE_ROUTINE
531 return 0;
532 }
533
534 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
535 {
536 int retval = 0;
537 struct controller *ctrl = slot->ctrl;
538 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
539 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
540 u8 pi, pcix_cap;
541
542 DBG_ENTER_ROUTINE
543
544 if ((retval = hpc_get_prog_int(slot, &pi)))
545 return retval;
546
547 switch (pi) {
548 case 1:
549 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
550 break;
551 case 2:
552 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
553 break;
554 default:
555 return -ENODEV;
556 }
557
558 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
559 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
560
561 switch (pcix_cap) {
562 case 0x0:
563 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
564 break;
565 case 0x1:
566 *value = PCI_SPEED_66MHz_PCIX;
567 break;
568 case 0x3:
569 *value = PCI_SPEED_133MHz_PCIX;
570 break;
571 case 0x4:
572 *value = PCI_SPEED_133MHz_PCIX_266;
573 break;
574 case 0x5:
575 *value = PCI_SPEED_133MHz_PCIX_533;
576 break;
577 case 0x2:
578 default:
579 *value = PCI_SPEED_UNKNOWN;
580 retval = -ENODEV;
581 break;
582 }
583
584 dbg("Adapter speed = %d\n", *value);
585 DBG_LEAVE_ROUTINE
586 return retval;
587 }
588
589 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
590 {
591 struct controller *ctrl = slot->ctrl;
592 u16 sec_bus_status;
593 u8 pi;
594 int retval = 0;
595
596 DBG_ENTER_ROUTINE
597
598 pi = shpc_readb(ctrl, PROG_INTERFACE);
599 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
600
601 if (pi == 2) {
602 *mode = (sec_bus_status & 0x0100) >> 8;
603 } else {
604 retval = -1;
605 }
606
607 dbg("Mode 1 ECC cap = %d\n", *mode);
608
609 DBG_LEAVE_ROUTINE
610 return retval;
611 }
612
613 static int hpc_query_power_fault(struct slot * slot)
614 {
615 struct controller *ctrl = slot->ctrl;
616 u32 slot_reg;
617
618 DBG_ENTER_ROUTINE
619
620 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
621
622 DBG_LEAVE_ROUTINE
623 /* Note: Logic 0 => fault */
624 return !(slot_reg & POWER_FAULT);
625 }
626
627 static int hpc_set_attention_status(struct slot *slot, u8 value)
628 {
629 u8 slot_cmd = 0;
630
631 switch (value) {
632 case 0 :
633 slot_cmd = SET_ATTN_OFF; /* OFF */
634 break;
635 case 1:
636 slot_cmd = SET_ATTN_ON; /* ON */
637 break;
638 case 2:
639 slot_cmd = SET_ATTN_BLINK; /* BLINK */
640 break;
641 default:
642 return -1;
643 }
644
645 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
646 }
647
648
649 static void hpc_set_green_led_on(struct slot *slot)
650 {
651 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
652 }
653
654 static void hpc_set_green_led_off(struct slot *slot)
655 {
656 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
657 }
658
659 static void hpc_set_green_led_blink(struct slot *slot)
660 {
661 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
662 }
663
664 static void hpc_release_ctlr(struct controller *ctrl)
665 {
666 int i;
667 u32 slot_reg, serr_int;
668
669 DBG_ENTER_ROUTINE
670
671 /*
672 * Mask event interrupts and SERRs of all slots
673 */
674 for (i = 0; i < ctrl->num_slots; i++) {
675 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
676 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
677 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
678 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
679 CON_PFAULT_SERR_MASK);
680 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
681 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
682 }
683
684 cleanup_slots(ctrl);
685
686 /*
687 * Mask SERR and System Interrut generation
688 */
689 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
690 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
691 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
692 serr_int &= ~SERR_INTR_RSVDZ_MASK;
693 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
694
695 if (shpchp_poll_mode)
696 del_timer(&ctrl->poll_timer);
697 else {
698 free_irq(ctrl->pci_dev->irq, ctrl);
699 pci_disable_msi(ctrl->pci_dev);
700 }
701
702 iounmap(ctrl->creg);
703 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
704
705 /*
706 * If this is the last controller to be released, destroy the
707 * shpchpd work queue
708 */
709 if (atomic_dec_and_test(&shpchp_num_controllers))
710 destroy_workqueue(shpchp_wq);
711
712 DBG_LEAVE_ROUTINE
713 }
714
715 static int hpc_power_on_slot(struct slot * slot)
716 {
717 int retval;
718
719 DBG_ENTER_ROUTINE
720
721 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
722 if (retval) {
723 err("%s: Write command failed!\n", __FUNCTION__);
724 return retval;
725 }
726
727 DBG_LEAVE_ROUTINE
728
729 return 0;
730 }
731
732 static int hpc_slot_enable(struct slot * slot)
733 {
734 int retval;
735
736 DBG_ENTER_ROUTINE
737
738 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
739 retval = shpc_write_cmd(slot, slot->hp_slot,
740 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
741 if (retval) {
742 err("%s: Write command failed!\n", __FUNCTION__);
743 return retval;
744 }
745
746 DBG_LEAVE_ROUTINE
747 return 0;
748 }
749
750 static int hpc_slot_disable(struct slot * slot)
751 {
752 int retval;
753
754 DBG_ENTER_ROUTINE
755
756 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
757 retval = shpc_write_cmd(slot, slot->hp_slot,
758 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
759 if (retval) {
760 err("%s: Write command failed!\n", __FUNCTION__);
761 return retval;
762 }
763
764 DBG_LEAVE_ROUTINE
765 return 0;
766 }
767
768 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
769 {
770 int retval;
771 struct controller *ctrl = slot->ctrl;
772 u8 pi, cmd;
773
774 DBG_ENTER_ROUTINE
775
776 pi = shpc_readb(ctrl, PROG_INTERFACE);
777 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
778 return -EINVAL;
779
780 switch (value) {
781 case PCI_SPEED_33MHz:
782 cmd = SETA_PCI_33MHZ;
783 break;
784 case PCI_SPEED_66MHz:
785 cmd = SETA_PCI_66MHZ;
786 break;
787 case PCI_SPEED_66MHz_PCIX:
788 cmd = SETA_PCIX_66MHZ;
789 break;
790 case PCI_SPEED_100MHz_PCIX:
791 cmd = SETA_PCIX_100MHZ;
792 break;
793 case PCI_SPEED_133MHz_PCIX:
794 cmd = SETA_PCIX_133MHZ;
795 break;
796 case PCI_SPEED_66MHz_PCIX_ECC:
797 cmd = SETB_PCIX_66MHZ_EM;
798 break;
799 case PCI_SPEED_100MHz_PCIX_ECC:
800 cmd = SETB_PCIX_100MHZ_EM;
801 break;
802 case PCI_SPEED_133MHz_PCIX_ECC:
803 cmd = SETB_PCIX_133MHZ_EM;
804 break;
805 case PCI_SPEED_66MHz_PCIX_266:
806 cmd = SETB_PCIX_66MHZ_266;
807 break;
808 case PCI_SPEED_100MHz_PCIX_266:
809 cmd = SETB_PCIX_100MHZ_266;
810 break;
811 case PCI_SPEED_133MHz_PCIX_266:
812 cmd = SETB_PCIX_133MHZ_266;
813 break;
814 case PCI_SPEED_66MHz_PCIX_533:
815 cmd = SETB_PCIX_66MHZ_533;
816 break;
817 case PCI_SPEED_100MHz_PCIX_533:
818 cmd = SETB_PCIX_100MHZ_533;
819 break;
820 case PCI_SPEED_133MHz_PCIX_533:
821 cmd = SETB_PCIX_133MHZ_533;
822 break;
823 default:
824 return -EINVAL;
825 }
826
827 retval = shpc_write_cmd(slot, 0, cmd);
828 if (retval)
829 err("%s: Write command failed!\n", __FUNCTION__);
830
831 DBG_LEAVE_ROUTINE
832 return retval;
833 }
834
835 static irqreturn_t shpc_isr(int irq, void *dev_id)
836 {
837 struct controller *ctrl = (struct controller *)dev_id;
838 u32 serr_int, slot_reg, intr_loc, intr_loc2;
839 int hp_slot;
840
841 /* Check to see if it was our interrupt */
842 intr_loc = shpc_readl(ctrl, INTR_LOC);
843 if (!intr_loc)
844 return IRQ_NONE;
845
846 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
847
848 if(!shpchp_poll_mode) {
849 /*
850 * Mask Global Interrupt Mask - see implementation
851 * note on p. 139 of SHPC spec rev 1.0
852 */
853 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
854 serr_int |= GLOBAL_INTR_MASK;
855 serr_int &= ~SERR_INTR_RSVDZ_MASK;
856 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
857
858 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
859 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
860 }
861
862 if (intr_loc & CMD_INTR_PENDING) {
863 /*
864 * Command Complete Interrupt Pending
865 * RO only - clear by writing 1 to the Command Completion
866 * Detect bit in Controller SERR-INT register
867 */
868 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
869 serr_int &= ~SERR_INTR_RSVDZ_MASK;
870 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
871
872 wake_up_interruptible(&ctrl->queue);
873 }
874
875 if (!(intr_loc & ~CMD_INTR_PENDING))
876 goto out;
877
878 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
879 /* To find out which slot has interrupt pending */
880 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
881 continue;
882
883 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
884 dbg("%s: Slot %x with intr, slot register = %x\n",
885 __FUNCTION__, hp_slot, slot_reg);
886
887 if (slot_reg & MRL_CHANGE_DETECTED)
888 shpchp_handle_switch_change(hp_slot, ctrl);
889
890 if (slot_reg & BUTTON_PRESS_DETECTED)
891 shpchp_handle_attention_button(hp_slot, ctrl);
892
893 if (slot_reg & PRSNT_CHANGE_DETECTED)
894 shpchp_handle_presence_change(hp_slot, ctrl);
895
896 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
897 shpchp_handle_power_fault(hp_slot, ctrl);
898
899 /* Clear all slot events */
900 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
901 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
902 }
903 out:
904 if (!shpchp_poll_mode) {
905 /* Unmask Global Interrupt Mask */
906 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
907 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
908 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
909 }
910
911 return IRQ_HANDLED;
912 }
913
914 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
915 {
916 int retval = 0;
917 struct controller *ctrl = slot->ctrl;
918 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
919 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
920 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
921 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
922
923 DBG_ENTER_ROUTINE
924
925 if (pi == 2) {
926 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
927 bus_speed = PCI_SPEED_133MHz_PCIX_533;
928 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
929 bus_speed = PCI_SPEED_100MHz_PCIX_533;
930 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
931 bus_speed = PCI_SPEED_66MHz_PCIX_533;
932 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
933 bus_speed = PCI_SPEED_133MHz_PCIX_266;
934 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
935 bus_speed = PCI_SPEED_100MHz_PCIX_266;
936 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
937 bus_speed = PCI_SPEED_66MHz_PCIX_266;
938 }
939
940 if (bus_speed == PCI_SPEED_UNKNOWN) {
941 if (slot_avail1 & SLOT_133MHZ_PCIX)
942 bus_speed = PCI_SPEED_133MHz_PCIX;
943 else if (slot_avail1 & SLOT_100MHZ_PCIX)
944 bus_speed = PCI_SPEED_100MHz_PCIX;
945 else if (slot_avail1 & SLOT_66MHZ_PCIX)
946 bus_speed = PCI_SPEED_66MHz_PCIX;
947 else if (slot_avail2 & SLOT_66MHZ)
948 bus_speed = PCI_SPEED_66MHz;
949 else if (slot_avail1 & SLOT_33MHZ)
950 bus_speed = PCI_SPEED_33MHz;
951 else
952 retval = -ENODEV;
953 }
954
955 *value = bus_speed;
956 dbg("Max bus speed = %d\n", bus_speed);
957 DBG_LEAVE_ROUTINE
958 return retval;
959 }
960
961 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
962 {
963 int retval = 0;
964 struct controller *ctrl = slot->ctrl;
965 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
966 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
967 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
968 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
969
970 DBG_ENTER_ROUTINE
971
972 if ((pi == 1) && (speed_mode > 4)) {
973 *value = PCI_SPEED_UNKNOWN;
974 return -ENODEV;
975 }
976
977 switch (speed_mode) {
978 case 0x0:
979 *value = PCI_SPEED_33MHz;
980 break;
981 case 0x1:
982 *value = PCI_SPEED_66MHz;
983 break;
984 case 0x2:
985 *value = PCI_SPEED_66MHz_PCIX;
986 break;
987 case 0x3:
988 *value = PCI_SPEED_100MHz_PCIX;
989 break;
990 case 0x4:
991 *value = PCI_SPEED_133MHz_PCIX;
992 break;
993 case 0x5:
994 *value = PCI_SPEED_66MHz_PCIX_ECC;
995 break;
996 case 0x6:
997 *value = PCI_SPEED_100MHz_PCIX_ECC;
998 break;
999 case 0x7:
1000 *value = PCI_SPEED_133MHz_PCIX_ECC;
1001 break;
1002 case 0x8:
1003 *value = PCI_SPEED_66MHz_PCIX_266;
1004 break;
1005 case 0x9:
1006 *value = PCI_SPEED_100MHz_PCIX_266;
1007 break;
1008 case 0xa:
1009 *value = PCI_SPEED_133MHz_PCIX_266;
1010 break;
1011 case 0xb:
1012 *value = PCI_SPEED_66MHz_PCIX_533;
1013 break;
1014 case 0xc:
1015 *value = PCI_SPEED_100MHz_PCIX_533;
1016 break;
1017 case 0xd:
1018 *value = PCI_SPEED_133MHz_PCIX_533;
1019 break;
1020 default:
1021 *value = PCI_SPEED_UNKNOWN;
1022 retval = -ENODEV;
1023 break;
1024 }
1025
1026 dbg("Current bus speed = %d\n", bus_speed);
1027 DBG_LEAVE_ROUTINE
1028 return retval;
1029 }
1030
1031 static struct hpc_ops shpchp_hpc_ops = {
1032 .power_on_slot = hpc_power_on_slot,
1033 .slot_enable = hpc_slot_enable,
1034 .slot_disable = hpc_slot_disable,
1035 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1036 .set_attention_status = hpc_set_attention_status,
1037 .get_power_status = hpc_get_power_status,
1038 .get_attention_status = hpc_get_attention_status,
1039 .get_latch_status = hpc_get_latch_status,
1040 .get_adapter_status = hpc_get_adapter_status,
1041
1042 .get_max_bus_speed = hpc_get_max_bus_speed,
1043 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1044 .get_adapter_speed = hpc_get_adapter_speed,
1045 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1046 .get_prog_int = hpc_get_prog_int,
1047
1048 .query_power_fault = hpc_query_power_fault,
1049 .green_led_on = hpc_set_green_led_on,
1050 .green_led_off = hpc_set_green_led_off,
1051 .green_led_blink = hpc_set_green_led_blink,
1052
1053 .release_ctlr = hpc_release_ctlr,
1054 };
1055
1056 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1057 {
1058 int rc = -1, num_slots = 0;
1059 u8 hp_slot;
1060 u32 shpc_base_offset;
1061 u32 tempdword, slot_reg, slot_config;
1062 u8 i;
1063
1064 DBG_ENTER_ROUTINE
1065
1066 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1067
1068 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1069 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1070 /* amd shpc driver doesn't use Base Offset; assume 0 */
1071 ctrl->mmio_base = pci_resource_start(pdev, 0);
1072 ctrl->mmio_size = pci_resource_len(pdev, 0);
1073 } else {
1074 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1075 if (!ctrl->cap_offset) {
1076 err("%s : cap_offset == 0\n", __FUNCTION__);
1077 goto abort;
1078 }
1079 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1080
1081 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
1082 if (rc) {
1083 err("%s: cannot read base_offset\n", __FUNCTION__);
1084 goto abort;
1085 }
1086
1087 rc = shpc_indirect_read(ctrl, 3, &tempdword);
1088 if (rc) {
1089 err("%s: cannot read slot config\n", __FUNCTION__);
1090 goto abort;
1091 }
1092 num_slots = tempdword & SLOT_NUM;
1093 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1094
1095 for (i = 0; i < 9 + num_slots; i++) {
1096 rc = shpc_indirect_read(ctrl, i, &tempdword);
1097 if (rc) {
1098 err("%s: cannot read creg (index = %d)\n",
1099 __FUNCTION__, i);
1100 goto abort;
1101 }
1102 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1103 tempdword);
1104 }
1105
1106 ctrl->mmio_base =
1107 pci_resource_start(pdev, 0) + shpc_base_offset;
1108 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1109 }
1110
1111 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1112 pdev->subsystem_device);
1113
1114 rc = pci_enable_device(pdev);
1115 if (rc) {
1116 err("%s: pci_enable_device failed\n", __FUNCTION__);
1117 goto abort;
1118 }
1119
1120 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1121 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1122 rc = -1;
1123 goto abort;
1124 }
1125
1126 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1127 if (!ctrl->creg) {
1128 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1129 ctrl->mmio_size, ctrl->mmio_base);
1130 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1131 rc = -1;
1132 goto abort;
1133 }
1134 dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg);
1135
1136 mutex_init(&ctrl->crit_sect);
1137 mutex_init(&ctrl->cmd_lock);
1138
1139 /* Setup wait queue */
1140 init_waitqueue_head(&ctrl->queue);
1141
1142 ctrl->hpc_ops = &shpchp_hpc_ops;
1143
1144 /* Return PCI Controller Info */
1145 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1146 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1147 ctrl->num_slots = slot_config & SLOT_NUM;
1148 ctrl->first_slot = (slot_config & PSN) >> 16;
1149 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1150
1151 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1152 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1153 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1154 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1155 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1156 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1157 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1158 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1159 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1160
1161 /* Mask the MRL sensor SERR Mask of individual slot in
1162 * Slot SERR-INT Mask & clear all the existing event if any
1163 */
1164 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1165 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1166 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1167 hp_slot, slot_reg);
1168 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1169 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1170 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1171 CON_PFAULT_SERR_MASK);
1172 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1173 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1174 }
1175
1176 if (shpchp_poll_mode) {
1177 /* Install interrupt polling timer. Start with 10 sec delay */
1178 init_timer(&ctrl->poll_timer);
1179 start_int_poll_timer(ctrl, 10);
1180 } else {
1181 /* Installs the interrupt handler */
1182 rc = pci_enable_msi(pdev);
1183 if (rc) {
1184 info("Can't get msi for the hotplug controller\n");
1185 info("Use INTx for the hotplug controller\n");
1186 }
1187
1188 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1189 MY_NAME, (void *)ctrl);
1190 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1191 __FUNCTION__, ctrl->pci_dev->irq,
1192 atomic_read(&shpchp_num_controllers), rc);
1193 if (rc) {
1194 err("Can't get irq %d for the hotplug controller\n",
1195 ctrl->pci_dev->irq);
1196 goto abort_iounmap;
1197 }
1198 }
1199 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1200 pdev->bus->number, PCI_SLOT(pdev->devfn),
1201 PCI_FUNC(pdev->devfn), pdev->irq);
1202 get_hp_hw_control_from_firmware(pdev);
1203
1204 /*
1205 * If this is the first controller to be initialized,
1206 * initialize the shpchpd work queue
1207 */
1208 if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
1209 shpchp_wq = create_singlethread_workqueue("shpchpd");
1210 if (!shpchp_wq) {
1211 rc = -ENOMEM;
1212 goto abort_iounmap;
1213 }
1214 }
1215
1216 /*
1217 * Unmask all event interrupts of all slots
1218 */
1219 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1220 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1221 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1222 hp_slot, slot_reg);
1223 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1224 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1225 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1226 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1227 }
1228 if (!shpchp_poll_mode) {
1229 /* Unmask all general input interrupts and SERR */
1230 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1231 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1232 SERR_INTR_RSVDZ_MASK);
1233 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1234 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1235 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1236 }
1237
1238 DBG_LEAVE_ROUTINE
1239 return 0;
1240
1241 /* We end up here for the many possible ways to fail this API. */
1242 abort_iounmap:
1243 iounmap(ctrl->creg);
1244 abort:
1245 DBG_LEAVE_ROUTINE
1246 return rc;
1247 }
Linux kernel - Deliverables
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