3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
26 static int pci_msi_enable
= 1;
30 #ifndef arch_msi_check_device
31 int arch_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
37 #ifndef arch_setup_msi_irqs
38 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
40 struct msi_desc
*entry
;
44 * If an architecture wants to support multiple MSI, it needs to
45 * override arch_setup_msi_irqs()
47 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
50 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
51 ret
= arch_setup_msi_irq(dev
, entry
);
62 #ifndef arch_teardown_msi_irqs
63 void arch_teardown_msi_irqs(struct pci_dev
*dev
)
65 struct msi_desc
*entry
;
67 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
71 nvec
= 1 << entry
->msi_attrib
.multiple
;
72 for (i
= 0; i
< nvec
; i
++)
73 arch_teardown_msi_irq(entry
->irq
+ i
);
78 static void msi_set_enable(struct pci_dev
*dev
, int pos
, int enable
)
84 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
85 control
&= ~PCI_MSI_FLAGS_ENABLE
;
87 control
|= PCI_MSI_FLAGS_ENABLE
;
88 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
91 static void msix_set_enable(struct pci_dev
*dev
, int enable
)
96 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
98 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
99 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
101 control
|= PCI_MSIX_FLAGS_ENABLE
;
102 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
106 static inline __attribute_const__ u32
msi_mask(unsigned x
)
108 /* Don't shift by >= width of type */
111 return (1 << (1 << x
)) - 1;
114 static inline __attribute_const__ u32
msi_capable_mask(u16 control
)
116 return msi_mask((control
>> 1) & 7);
119 static inline __attribute_const__ u32
msi_enabled_mask(u16 control
)
121 return msi_mask((control
>> 4) & 7);
125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
126 * mask all MSI interrupts by clearing the MSI enable bit does not work
127 * reliably as devices without an INTx disable bit will then generate a
128 * level IRQ which will never be cleared.
130 static u32
__msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
132 u32 mask_bits
= desc
->masked
;
134 if (!desc
->msi_attrib
.maskbit
)
139 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
144 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
146 desc
->masked
= __msi_mask_irq(desc
, mask
, flag
);
150 * This internal function does not flush PCI writes to the device.
151 * All users must ensure that they read from the device before either
152 * assuming that the device state is up to date, or returning out of this
153 * file. This saves a few milliseconds when initialising devices with lots
154 * of MSI-X interrupts.
156 static u32
__msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
158 u32 mask_bits
= desc
->masked
;
159 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
160 PCI_MSIX_ENTRY_VECTOR_CTRL
;
163 writel(mask_bits
, desc
->mask_base
+ offset
);
168 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
170 desc
->masked
= __msix_mask_irq(desc
, flag
);
173 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
175 struct msi_desc
*desc
= irq_data_get_msi(data
);
177 if (desc
->msi_attrib
.is_msix
) {
178 msix_mask_irq(desc
, flag
);
179 readl(desc
->mask_base
); /* Flush write to device */
181 unsigned offset
= data
->irq
- desc
->dev
->irq
;
182 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
186 void mask_msi_irq(struct irq_data
*data
)
188 msi_set_mask_bit(data
, 1);
191 void unmask_msi_irq(struct irq_data
*data
)
193 msi_set_mask_bit(data
, 0);
196 void __read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
198 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
200 if (entry
->msi_attrib
.is_msix
) {
201 void __iomem
*base
= entry
->mask_base
+
202 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
204 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
205 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
206 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
208 struct pci_dev
*dev
= entry
->dev
;
209 int pos
= entry
->msi_attrib
.pos
;
212 pci_read_config_dword(dev
, msi_lower_address_reg(pos
),
214 if (entry
->msi_attrib
.is_64
) {
215 pci_read_config_dword(dev
, msi_upper_address_reg(pos
),
217 pci_read_config_word(dev
, msi_data_reg(pos
, 1), &data
);
220 pci_read_config_word(dev
, msi_data_reg(pos
, 0), &data
);
226 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
228 struct msi_desc
*entry
= get_irq_msi(irq
);
230 __read_msi_msg(entry
, msg
);
233 void __get_cached_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
235 /* Assert that the cache is valid, assuming that
236 * valid messages are not all-zeroes. */
237 BUG_ON(!(entry
->msg
.address_hi
| entry
->msg
.address_lo
|
243 void get_cached_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
245 struct msi_desc
*entry
= get_irq_msi(irq
);
247 __get_cached_msi_msg(entry
, msg
);
250 void __write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
252 if (entry
->dev
->current_state
!= PCI_D0
) {
253 /* Don't touch the hardware now */
254 } else if (entry
->msi_attrib
.is_msix
) {
256 base
= entry
->mask_base
+
257 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
259 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
260 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
261 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
263 struct pci_dev
*dev
= entry
->dev
;
264 int pos
= entry
->msi_attrib
.pos
;
267 pci_read_config_word(dev
, msi_control_reg(pos
), &msgctl
);
268 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
269 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
270 pci_write_config_word(dev
, msi_control_reg(pos
), msgctl
);
272 pci_write_config_dword(dev
, msi_lower_address_reg(pos
),
274 if (entry
->msi_attrib
.is_64
) {
275 pci_write_config_dword(dev
, msi_upper_address_reg(pos
),
277 pci_write_config_word(dev
, msi_data_reg(pos
, 1),
280 pci_write_config_word(dev
, msi_data_reg(pos
, 0),
287 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
289 struct msi_desc
*entry
= get_irq_msi(irq
);
291 __write_msi_msg(entry
, msg
);
294 static void free_msi_irqs(struct pci_dev
*dev
)
296 struct msi_desc
*entry
, *tmp
;
298 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
302 nvec
= 1 << entry
->msi_attrib
.multiple
;
303 for (i
= 0; i
< nvec
; i
++)
304 BUG_ON(irq_has_action(entry
->irq
+ i
));
307 arch_teardown_msi_irqs(dev
);
309 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
310 if (entry
->msi_attrib
.is_msix
) {
311 if (list_is_last(&entry
->list
, &dev
->msi_list
))
312 iounmap(entry
->mask_base
);
314 list_del(&entry
->list
);
319 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
321 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
325 INIT_LIST_HEAD(&desc
->list
);
331 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
333 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
334 pci_intx(dev
, enable
);
337 static void __pci_restore_msi_state(struct pci_dev
*dev
)
341 struct msi_desc
*entry
;
343 if (!dev
->msi_enabled
)
346 entry
= get_irq_msi(dev
->irq
);
347 pos
= entry
->msi_attrib
.pos
;
349 pci_intx_for_msi(dev
, 0);
350 msi_set_enable(dev
, pos
, 0);
351 write_msi_msg(dev
->irq
, &entry
->msg
);
353 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
354 msi_mask_irq(entry
, msi_capable_mask(control
), entry
->masked
);
355 control
&= ~PCI_MSI_FLAGS_QSIZE
;
356 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
357 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
360 static void __pci_restore_msix_state(struct pci_dev
*dev
)
363 struct msi_desc
*entry
;
366 if (!dev
->msix_enabled
)
368 BUG_ON(list_empty(&dev
->msi_list
));
369 entry
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
370 pos
= entry
->msi_attrib
.pos
;
371 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
373 /* route the table */
374 pci_intx_for_msi(dev
, 0);
375 control
|= PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
;
376 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
378 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
379 write_msi_msg(entry
->irq
, &entry
->msg
);
380 msix_mask_irq(entry
, entry
->masked
);
383 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
384 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
387 void pci_restore_msi_state(struct pci_dev
*dev
)
389 __pci_restore_msi_state(dev
);
390 __pci_restore_msix_state(dev
);
392 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
395 * msi_capability_init - configure device's MSI capability structure
396 * @dev: pointer to the pci_dev data structure of MSI device function
397 * @nvec: number of interrupts to allocate
399 * Setup the MSI capability structure of the device with the requested
400 * number of interrupts. A return value of zero indicates the successful
401 * setup of an entry with the new MSI irq. A negative return value indicates
402 * an error, and a positive return value indicates the number of interrupts
403 * which could have been allocated.
405 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
407 struct msi_desc
*entry
;
412 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
413 msi_set_enable(dev
, pos
, 0); /* Disable MSI during set up */
415 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
416 /* MSI Entry Initialization */
417 entry
= alloc_msi_entry(dev
);
421 entry
->msi_attrib
.is_msix
= 0;
422 entry
->msi_attrib
.is_64
= is_64bit_address(control
);
423 entry
->msi_attrib
.entry_nr
= 0;
424 entry
->msi_attrib
.maskbit
= is_mask_bit_support(control
);
425 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
426 entry
->msi_attrib
.pos
= pos
;
428 entry
->mask_pos
= msi_mask_reg(pos
, entry
->msi_attrib
.is_64
);
429 /* All MSIs are unmasked by default, Mask them all */
430 if (entry
->msi_attrib
.maskbit
)
431 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
432 mask
= msi_capable_mask(control
);
433 msi_mask_irq(entry
, mask
, mask
);
435 list_add_tail(&entry
->list
, &dev
->msi_list
);
437 /* Configure MSI capability structure */
438 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
440 msi_mask_irq(entry
, mask
, ~mask
);
445 /* Set MSI enabled bits */
446 pci_intx_for_msi(dev
, 0);
447 msi_set_enable(dev
, pos
, 1);
448 dev
->msi_enabled
= 1;
450 dev
->irq
= entry
->irq
;
454 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned pos
,
457 resource_size_t phys_addr
;
461 pci_read_config_dword(dev
, msix_table_offset_reg(pos
), &table_offset
);
462 bir
= (u8
)(table_offset
& PCI_MSIX_FLAGS_BIRMASK
);
463 table_offset
&= ~PCI_MSIX_FLAGS_BIRMASK
;
464 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
466 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
469 static int msix_setup_entries(struct pci_dev
*dev
, unsigned pos
,
470 void __iomem
*base
, struct msix_entry
*entries
,
473 struct msi_desc
*entry
;
476 for (i
= 0; i
< nvec
; i
++) {
477 entry
= alloc_msi_entry(dev
);
483 /* No enough memory. Don't try again */
487 entry
->msi_attrib
.is_msix
= 1;
488 entry
->msi_attrib
.is_64
= 1;
489 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
490 entry
->msi_attrib
.default_irq
= dev
->irq
;
491 entry
->msi_attrib
.pos
= pos
;
492 entry
->mask_base
= base
;
494 list_add_tail(&entry
->list
, &dev
->msi_list
);
500 static void msix_program_entries(struct pci_dev
*dev
,
501 struct msix_entry
*entries
)
503 struct msi_desc
*entry
;
506 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
507 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
508 PCI_MSIX_ENTRY_VECTOR_CTRL
;
510 entries
[i
].vector
= entry
->irq
;
511 set_irq_msi(entry
->irq
, entry
);
512 entry
->masked
= readl(entry
->mask_base
+ offset
);
513 msix_mask_irq(entry
, 1);
519 * msix_capability_init - configure device's MSI-X capability
520 * @dev: pointer to the pci_dev data structure of MSI-X device function
521 * @entries: pointer to an array of struct msix_entry entries
522 * @nvec: number of @entries
524 * Setup the MSI-X capability structure of device function with a
525 * single MSI-X irq. A return of zero indicates the successful setup of
526 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
528 static int msix_capability_init(struct pci_dev
*dev
,
529 struct msix_entry
*entries
, int nvec
)
535 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
536 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
538 /* Ensure MSI-X is disabled while it is set up */
539 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
540 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
542 /* Request & Map MSI-X table region */
543 base
= msix_map_region(dev
, pos
, multi_msix_capable(control
));
547 ret
= msix_setup_entries(dev
, pos
, base
, entries
, nvec
);
551 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
556 * Some devices require MSI-X to be enabled before we can touch the
557 * MSI-X registers. We need to mask all the vectors to prevent
558 * interrupts coming in before they're fully set up.
560 control
|= PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
;
561 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
563 msix_program_entries(dev
, entries
);
565 /* Set MSI-X enabled bits and unmask the function */
566 pci_intx_for_msi(dev
, 0);
567 dev
->msix_enabled
= 1;
569 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
570 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
577 * If we had some success, report the number of irqs
578 * we succeeded in setting up.
580 struct msi_desc
*entry
;
583 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
597 * pci_msi_check_device - check whether MSI may be enabled on a device
598 * @dev: pointer to the pci_dev data structure of MSI device function
599 * @nvec: how many MSIs have been requested ?
600 * @type: are we checking for MSI or MSI-X ?
602 * Look at global flags, the device itself, and its parent busses
603 * to determine if MSI/-X are supported for the device. If MSI/-X is
604 * supported return 0, else return an error code.
606 static int pci_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
611 /* MSI must be globally enabled and supported by the device */
612 if (!pci_msi_enable
|| !dev
|| dev
->no_msi
)
616 * You can't ask to have 0 or less MSIs configured.
618 * b) the list manipulation code assumes nvec >= 1.
624 * Any bridge which does NOT route MSI transactions from its
625 * secondary bus to its primary bus must set NO_MSI flag on
626 * the secondary pci_bus.
627 * We expect only arch-specific PCI host bus controller driver
628 * or quirks for specific PCI bridges to be setting NO_MSI.
630 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
631 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
634 ret
= arch_msi_check_device(dev
, nvec
, type
);
638 if (!pci_find_capability(dev
, type
))
645 * pci_enable_msi_block - configure device's MSI capability structure
646 * @dev: device to configure
647 * @nvec: number of interrupts to configure
649 * Allocate IRQs for a device with the MSI capability.
650 * This function returns a negative errno if an error occurs. If it
651 * is unable to allocate the number of interrupts requested, it returns
652 * the number of interrupts it might be able to allocate. If it successfully
653 * allocates at least the number of interrupts requested, it returns 0 and
654 * updates the @dev's irq member to the lowest new interrupt number; the
655 * other interrupt numbers allocated to this device are consecutive.
657 int pci_enable_msi_block(struct pci_dev
*dev
, unsigned int nvec
)
659 int status
, pos
, maxvec
;
662 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
665 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
666 maxvec
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
670 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSI
);
674 WARN_ON(!!dev
->msi_enabled
);
676 /* Check whether driver already requested MSI-X irqs */
677 if (dev
->msix_enabled
) {
678 dev_info(&dev
->dev
, "can't enable MSI "
679 "(MSI-X already enabled)\n");
683 status
= msi_capability_init(dev
, nvec
);
686 EXPORT_SYMBOL(pci_enable_msi_block
);
688 void pci_msi_shutdown(struct pci_dev
*dev
)
690 struct msi_desc
*desc
;
695 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
698 BUG_ON(list_empty(&dev
->msi_list
));
699 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
700 pos
= desc
->msi_attrib
.pos
;
702 msi_set_enable(dev
, pos
, 0);
703 pci_intx_for_msi(dev
, 1);
704 dev
->msi_enabled
= 0;
706 /* Return the device with MSI unmasked as initial states */
707 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &ctrl
);
708 mask
= msi_capable_mask(ctrl
);
709 /* Keep cached state to be restored */
710 __msi_mask_irq(desc
, mask
, ~mask
);
712 /* Restore dev->irq to its default pin-assertion irq */
713 dev
->irq
= desc
->msi_attrib
.default_irq
;
716 void pci_disable_msi(struct pci_dev
*dev
)
718 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
721 pci_msi_shutdown(dev
);
724 EXPORT_SYMBOL(pci_disable_msi
);
727 * pci_msix_table_size - return the number of device's MSI-X table entries
728 * @dev: pointer to the pci_dev data structure of MSI-X device function
730 int pci_msix_table_size(struct pci_dev
*dev
)
735 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
739 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
740 return multi_msix_capable(control
);
744 * pci_enable_msix - configure device's MSI-X capability structure
745 * @dev: pointer to the pci_dev data structure of MSI-X device function
746 * @entries: pointer to an array of MSI-X entries
747 * @nvec: number of MSI-X irqs requested for allocation by device driver
749 * Setup the MSI-X capability structure of device function with the number
750 * of requested irqs upon its software driver call to request for
751 * MSI-X mode enabled on its hardware device function. A return of zero
752 * indicates the successful configuration of MSI-X capability structure
753 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
754 * Or a return of > 0 indicates that driver request is exceeding the number
755 * of irqs or MSI-X vectors available. Driver should use the returned value to
756 * re-send its request.
758 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
760 int status
, nr_entries
;
766 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSIX
);
770 nr_entries
= pci_msix_table_size(dev
);
771 if (nvec
> nr_entries
)
774 /* Check for any invalid entries */
775 for (i
= 0; i
< nvec
; i
++) {
776 if (entries
[i
].entry
>= nr_entries
)
777 return -EINVAL
; /* invalid entry */
778 for (j
= i
+ 1; j
< nvec
; j
++) {
779 if (entries
[i
].entry
== entries
[j
].entry
)
780 return -EINVAL
; /* duplicate entry */
783 WARN_ON(!!dev
->msix_enabled
);
785 /* Check whether driver already requested for MSI irq */
786 if (dev
->msi_enabled
) {
787 dev_info(&dev
->dev
, "can't enable MSI-X "
788 "(MSI IRQ already assigned)\n");
791 status
= msix_capability_init(dev
, entries
, nvec
);
794 EXPORT_SYMBOL(pci_enable_msix
);
796 void pci_msix_shutdown(struct pci_dev
*dev
)
798 struct msi_desc
*entry
;
800 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
803 /* Return the device with MSI-X masked as initial states */
804 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
805 /* Keep cached states to be restored */
806 __msix_mask_irq(entry
, 1);
809 msix_set_enable(dev
, 0);
810 pci_intx_for_msi(dev
, 1);
811 dev
->msix_enabled
= 0;
814 void pci_disable_msix(struct pci_dev
*dev
)
816 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
819 pci_msix_shutdown(dev
);
822 EXPORT_SYMBOL(pci_disable_msix
);
825 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
826 * @dev: pointer to the pci_dev data structure of MSI(X) device function
828 * Being called during hotplug remove, from which the device function
829 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
830 * allocated for this device function, are reclaimed to unused state,
831 * which may be used later on.
833 void msi_remove_pci_irq_vectors(struct pci_dev
*dev
)
835 if (!pci_msi_enable
|| !dev
)
838 if (dev
->msi_enabled
|| dev
->msix_enabled
)
842 void pci_no_msi(void)
848 * pci_msi_enabled - is MSI enabled?
850 * Returns true if MSI has not been disabled by the command-line option
853 int pci_msi_enabled(void)
855 return pci_msi_enable
;
857 EXPORT_SYMBOL(pci_msi_enabled
);
859 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
861 INIT_LIST_HEAD(&dev
->msi_list
);