drivers/pci/msi.c

   1 /*
   2  * File:        msi.c
   3  * Purpose:     PCI Message Signaled Interrupt (MSI)
   4  *
   5  * Copyright (C) 2003-2004 Intel
   6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mm.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/pci.h>
  16 #include <linux/proc_fs.h>
  17 #include <linux/msi.h>
  18 #include <linux/smp.h>
  19
  20 #include <asm/errno.h>
  21 #include <asm/io.h>
  22
  23 #include "pci.h"
  24 #include "msi.h"
  25
  26 static int pci_msi_enable = 1;
  27
  28 /* Arch hooks */
  29
  30 #ifndef arch_msi_check_device
  31 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
  32 {
  33         return 0;
  34 }
  35 #endif
  36
  37 #ifndef arch_setup_msi_irqs
  38 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  39 {
  40         struct msi_desc *entry;
  41         int ret;
  42
  43         /*
  44          * If an architecture wants to support multiple MSI, it needs to
  45          * override arch_setup_msi_irqs()
  46          */
  47         if (type == PCI_CAP_ID_MSI && nvec > 1)
  48                 return 1;
  49
  50         list_for_each_entry(entry, &dev->msi_list, list) {
  51                 ret = arch_setup_msi_irq(dev, entry);
  52                 if (ret < 0)
  53                         return ret;
  54                 if (ret > 0)
  55                         return -ENOSPC;
  56         }
  57
  58         return 0;
  59 }
  60 #endif
  61
  62 #ifndef arch_teardown_msi_irqs
  63 void arch_teardown_msi_irqs(struct pci_dev *dev)
  64 {
  65         struct msi_desc *entry;
  66
  67         list_for_each_entry(entry, &dev->msi_list, list) {
  68                 int i, nvec;
  69                 if (entry->irq == 0)
  70                         continue;
  71                 nvec = 1 << entry->msi_attrib.multiple;
  72                 for (i = 0; i < nvec; i++)
  73                         arch_teardown_msi_irq(entry->irq + i);
  74         }
  75 }
  76 #endif
  77
  78 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
  79 {
  80         u16 control;
  81
  82         BUG_ON(!pos);
  83
  84         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
  85         control &= ~PCI_MSI_FLAGS_ENABLE;
  86         if (enable)
  87                 control |= PCI_MSI_FLAGS_ENABLE;
  88         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
  89 }
  90
  91 static void msix_set_enable(struct pci_dev *dev, int enable)
  92 {
  93         int pos;
  94         u16 control;
  95
  96         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  97         if (pos) {
  98                 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
  99                 control &= ~PCI_MSIX_FLAGS_ENABLE;
 100                 if (enable)
 101                         control |= PCI_MSIX_FLAGS_ENABLE;
 102                 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 103         }
 104 }
 105
 106 static inline __attribute_const__ u32 msi_mask(unsigned x)
 107 {
 108         /* Don't shift by >= width of type */
 109         if (x >= 5)
 110                 return 0xffffffff;
 111         return (1 << (1 << x)) - 1;
 112 }
 113
 114 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
 115 {
 116         return msi_mask((control >> 1) & 7);
 117 }
 118
 119 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
 120 {
 121         return msi_mask((control >> 4) & 7);
 122 }
 123
 124 /*
 125  * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
 126  * mask all MSI interrupts by clearing the MSI enable bit does not work
 127  * reliably as devices without an INTx disable bit will then generate a
 128  * level IRQ which will never be cleared.
 129  */
 130 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 131 {
 132         u32 mask_bits = desc->masked;
 133
 134         if (!desc->msi_attrib.maskbit)
 135                 return 0;
 136
 137         mask_bits &= ~mask;
 138         mask_bits |= flag;
 139         pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
 140
 141         return mask_bits;
 142 }
 143
 144 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 145 {
 146         desc->masked = __msi_mask_irq(desc, mask, flag);
 147 }
 148
 149 /*
 150  * This internal function does not flush PCI writes to the device.
 151  * All users must ensure that they read from the device before either
 152  * assuming that the device state is up to date, or returning out of this
 153  * file.  This saves a few milliseconds when initialising devices with lots
 154  * of MSI-X interrupts.
 155  */
 156 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
 157 {
 158         u32 mask_bits = desc->masked;
 159         unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
 160                                                 PCI_MSIX_ENTRY_VECTOR_CTRL;
 161         mask_bits &= ~1;
 162         mask_bits |= flag;
 163         writel(mask_bits, desc->mask_base + offset);
 164
 165         return mask_bits;
 166 }
 167
 168 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
 169 {
 170         desc->masked = __msix_mask_irq(desc, flag);
 171 }
 172
 173 static void msi_set_mask_bit(unsigned irq, u32 flag)
 174 {
 175         struct msi_desc *desc = get_irq_msi(irq);
 176
 177         if (desc->msi_attrib.is_msix) {
 178                 msix_mask_irq(desc, flag);
 179                 readl(desc->mask_base);         /* Flush write to device */
 180         } else {
 181                 unsigned offset = irq - desc->dev->irq;
 182                 msi_mask_irq(desc, 1 << offset, flag << offset);
 183         }
 184 }
 185
 186 void mask_msi_irq(unsigned int irq)
 187 {
 188         msi_set_mask_bit(irq, 1);
 189 }
 190
 191 void unmask_msi_irq(unsigned int irq)
 192 {
 193         msi_set_mask_bit(irq, 0);
 194 }
 195
 196 void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
 197 {
 198         struct msi_desc *entry = get_irq_desc_msi(desc);
 199         if (entry->msi_attrib.is_msix) {
 200                 void __iomem *base = entry->mask_base +
 201                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 202
 203                 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
 204                 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
 205                 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
 206         } else {
 207                 struct pci_dev *dev = entry->dev;
 208                 int pos = entry->msi_attrib.pos;
 209                 u16 data;
 210
 211                 pci_read_config_dword(dev, msi_lower_address_reg(pos),
 212                                         &msg->address_lo);
 213                 if (entry->msi_attrib.is_64) {
 214                         pci_read_config_dword(dev, msi_upper_address_reg(pos),
 215                                                 &msg->address_hi);
 216                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
 217                 } else {
 218                         msg->address_hi = 0;
 219                         pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
 220                 }
 221                 msg->data = data;
 222         }
 223 }
 224
 225 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
 226 {
 227         struct irq_desc *desc = irq_to_desc(irq);
 228
 229         read_msi_msg_desc(desc, msg);
 230 }
 231
 232 void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
 233 {
 234         struct msi_desc *entry = get_irq_desc_msi(desc);
 235         if (entry->msi_attrib.is_msix) {
 236                 void __iomem *base;
 237                 base = entry->mask_base +
 238                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 239
 240                 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
 241                 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
 242                 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
 243         } else {
 244                 struct pci_dev *dev = entry->dev;
 245                 int pos = entry->msi_attrib.pos;
 246                 u16 msgctl;
 247
 248                 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
 249                 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
 250                 msgctl |= entry->msi_attrib.multiple << 4;
 251                 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
 252
 253                 pci_write_config_dword(dev, msi_lower_address_reg(pos),
 254                                         msg->address_lo);
 255                 if (entry->msi_attrib.is_64) {
 256                         pci_write_config_dword(dev, msi_upper_address_reg(pos),
 257                                                 msg->address_hi);
 258                         pci_write_config_word(dev, msi_data_reg(pos, 1),
 259                                                 msg->data);
 260                 } else {
 261                         pci_write_config_word(dev, msi_data_reg(pos, 0),
 262                                                 msg->data);
 263                 }
 264         }
 265         entry->msg = *msg;
 266 }
 267
 268 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 269 {
 270         struct irq_desc *desc = irq_to_desc(irq);
 271
 272         write_msi_msg_desc(desc, msg);
 273 }
 274
 275 static void free_msi_irqs(struct pci_dev *dev)
 276 {
 277         struct msi_desc *entry, *tmp;
 278
 279         list_for_each_entry(entry, &dev->msi_list, list) {
 280                 int i, nvec;
 281                 if (!entry->irq)
 282                         continue;
 283                 nvec = 1 << entry->msi_attrib.multiple;
 284                 for (i = 0; i < nvec; i++)
 285                         BUG_ON(irq_has_action(entry->irq + i));
 286         }
 287
 288         arch_teardown_msi_irqs(dev);
 289
 290         list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
 291                 if (entry->msi_attrib.is_msix) {
 292                         if (list_is_last(&entry->list, &dev->msi_list))
 293                                 iounmap(entry->mask_base);
 294                 }
 295                 list_del(&entry->list);
 296                 kfree(entry);
 297         }
 298 }
 299
 300 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
 301 {
 302         struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 303         if (!desc)
 304                 return NULL;
 305
 306         INIT_LIST_HEAD(&desc->list);
 307         desc->dev = dev;
 308
 309         return desc;
 310 }
 311
 312 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
 313 {
 314         if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
 315                 pci_intx(dev, enable);
 316 }
 317
 318 static void __pci_restore_msi_state(struct pci_dev *dev)
 319 {
 320         int pos;
 321         u16 control;
 322         struct msi_desc *entry;
 323
 324         if (!dev->msi_enabled)
 325                 return;
 326
 327         entry = get_irq_msi(dev->irq);
 328         pos = entry->msi_attrib.pos;
 329
 330         pci_intx_for_msi(dev, 0);
 331         msi_set_enable(dev, pos, 0);
 332         write_msi_msg(dev->irq, &entry->msg);
 333
 334         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
 335         msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
 336         control &= ~PCI_MSI_FLAGS_QSIZE;
 337         control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
 338         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 339 }
 340
 341 static void __pci_restore_msix_state(struct pci_dev *dev)
 342 {
 343         int pos;
 344         struct msi_desc *entry;
 345         u16 control;
 346
 347         if (!dev->msix_enabled)
 348                 return;
 349         BUG_ON(list_empty(&dev->msi_list));
 350         entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
 351         pos = entry->msi_attrib.pos;
 352         pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 353
 354         /* route the table */
 355         pci_intx_for_msi(dev, 0);
 356         control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
 357         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 358
 359         list_for_each_entry(entry, &dev->msi_list, list) {
 360                 write_msi_msg(entry->irq, &entry->msg);
 361                 msix_mask_irq(entry, entry->masked);
 362         }
 363
 364         control &= ~PCI_MSIX_FLAGS_MASKALL;
 365         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 366 }
 367
 368 void pci_restore_msi_state(struct pci_dev *dev)
 369 {
 370         __pci_restore_msi_state(dev);
 371         __pci_restore_msix_state(dev);
 372 }
 373 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
 374
 375 /**
 376  * msi_capability_init - configure device's MSI capability structure
 377  * @dev: pointer to the pci_dev data structure of MSI device function
 378  * @nvec: number of interrupts to allocate
 379  *
 380  * Setup the MSI capability structure of the device with the requested
 381  * number of interrupts.  A return value of zero indicates the successful
 382  * setup of an entry with the new MSI irq.  A negative return value indicates
 383  * an error, and a positive return value indicates the number of interrupts
 384  * which could have been allocated.
 385  */
 386 static int msi_capability_init(struct pci_dev *dev, int nvec)
 387 {
 388         struct msi_desc *entry;
 389         int pos, ret;
 390         u16 control;
 391         unsigned mask;
 392
 393         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 394         msi_set_enable(dev, pos, 0);    /* Disable MSI during set up */
 395
 396         pci_read_config_word(dev, msi_control_reg(pos), &control);
 397         /* MSI Entry Initialization */
 398         entry = alloc_msi_entry(dev);
 399         if (!entry)
 400                 return -ENOMEM;
 401
 402         entry->msi_attrib.is_msix = 0;
 403         entry->msi_attrib.is_64 = is_64bit_address(control);
 404         entry->msi_attrib.entry_nr = 0;
 405         entry->msi_attrib.maskbit = is_mask_bit_support(control);
 406         entry->msi_attrib.default_irq = dev->irq;       /* Save IOAPIC IRQ */
 407         entry->msi_attrib.pos = pos;
 408
 409         entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
 410         /* All MSIs are unmasked by default, Mask them all */
 411         if (entry->msi_attrib.maskbit)
 412                 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
 413         mask = msi_capable_mask(control);
 414         msi_mask_irq(entry, mask, mask);
 415
 416         list_add_tail(&entry->list, &dev->msi_list);
 417
 418         /* Configure MSI capability structure */
 419         ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
 420         if (ret) {
 421                 msi_mask_irq(entry, mask, ~mask);
 422                 free_msi_irqs(dev);
 423                 return ret;
 424         }
 425
 426         /* Set MSI enabled bits  */
 427         pci_intx_for_msi(dev, 0);
 428         msi_set_enable(dev, pos, 1);
 429         dev->msi_enabled = 1;
 430
 431         dev->irq = entry->irq;
 432         return 0;
 433 }
 434
 435 /**
 436  * msix_capability_init - configure device's MSI-X capability
 437  * @dev: pointer to the pci_dev data structure of MSI-X device function
 438  * @entries: pointer to an array of struct msix_entry entries
 439  * @nvec: number of @entries
 440  *
 441  * Setup the MSI-X capability structure of device function with a
 442  * single MSI-X irq. A return of zero indicates the successful setup of
 443  * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 444  **/
 445 static int msix_capability_init(struct pci_dev *dev,
 446                                 struct msix_entry *entries, int nvec)
 447 {
 448         struct msi_desc *entry;
 449         int pos, i, j, nr_entries, ret;
 450         unsigned long phys_addr;
 451         u32 table_offset;
 452         u16 control;
 453         u8 bir;
 454         void __iomem *base;
 455
 456         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 457         pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 458
 459         /* Ensure MSI-X is disabled while it is set up */
 460         control &= ~PCI_MSIX_FLAGS_ENABLE;
 461         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 462
 463         /* Request & Map MSI-X table region */
 464         nr_entries = multi_msix_capable(control);
 465
 466         pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 467         bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 468         table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 469         phys_addr = pci_resource_start (dev, bir) + table_offset;
 470         base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 471         if (base == NULL)
 472                 return -ENOMEM;
 473
 474         for (i = 0; i < nvec; i++) {
 475                 entry = alloc_msi_entry(dev);
 476                 if (!entry) {
 477                         if (!i)
 478                                 iounmap(base);
 479                         else
 480                                 free_msi_irqs(dev);
 481                         /* No enough memory. Don't try again */
 482                         return -ENOMEM;
 483                 }
 484
 485                 j = entries[i].entry;
 486                 entry->msi_attrib.is_msix = 1;
 487                 entry->msi_attrib.is_64 = 1;
 488                 entry->msi_attrib.entry_nr = j;
 489                 entry->msi_attrib.default_irq = dev->irq;
 490                 entry->msi_attrib.pos = pos;
 491                 entry->mask_base = base;
 492
 493                 list_add_tail(&entry->list, &dev->msi_list);
 494         }
 495
 496         ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
 497         if (ret)
 498                 goto error;
 499
 500         /*
 501          * Some devices require MSI-X to be enabled before we can touch the
 502          * MSI-X registers.  We need to mask all the vectors to prevent
 503          * interrupts coming in before they're fully set up.
 504          */
 505         control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
 506         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 507
 508         i = 0;
 509         list_for_each_entry(entry, &dev->msi_list, list) {
 510                 entries[i].vector = entry->irq;
 511                 set_irq_msi(entry->irq, entry);
 512                 j = entries[i].entry;
 513                 entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
 514                                                 PCI_MSIX_ENTRY_VECTOR_CTRL);
 515                 msix_mask_irq(entry, 1);
 516                 i++;
 517         }
 518
 519         /* Set MSI-X enabled bits and unmask the function */
 520         pci_intx_for_msi(dev, 0);
 521         dev->msix_enabled = 1;
 522
 523         control &= ~PCI_MSIX_FLAGS_MASKALL;
 524         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 525
 526         return 0;
 527
 528 error:
 529         if (ret < 0) {
 530                 /*
 531                  * If we had some success, report the number of irqs
 532                  * we succeeded in setting up.
 533                  */
 534                 int avail = 0;
 535
 536                 list_for_each_entry(entry, &dev->msi_list, list) {
 537                         if (entry->irq != 0)
 538                                 avail++;
 539                 }
 540                 if (avail != 0)
 541                         ret = avail;
 542         }
 543
 544         free_msi_irqs(dev);
 545
 546         return ret;
 547 }
 548
 549 /**
 550  * pci_msi_check_device - check whether MSI may be enabled on a device
 551  * @dev: pointer to the pci_dev data structure of MSI device function
 552  * @nvec: how many MSIs have been requested ?
 553  * @type: are we checking for MSI or MSI-X ?
 554  *
 555  * Look at global flags, the device itself, and its parent busses
 556  * to determine if MSI/-X are supported for the device. If MSI/-X is
 557  * supported return 0, else return an error code.
 558  **/
 559 static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type)
 560 {
 561         struct pci_bus *bus;
 562         int ret;
 563
 564         /* MSI must be globally enabled and supported by the device */
 565         if (!pci_msi_enable || !dev || dev->no_msi)
 566                 return -EINVAL;
 567
 568         /*
 569          * You can't ask to have 0 or less MSIs configured.
 570          *  a) it's stupid ..
 571          *  b) the list manipulation code assumes nvec >= 1.
 572          */
 573         if (nvec < 1)
 574                 return -ERANGE;
 575
 576         /* Any bridge which does NOT route MSI transactions from it's
 577          * secondary bus to it's primary bus must set NO_MSI flag on
 578          * the secondary pci_bus.
 579          * We expect only arch-specific PCI host bus controller driver
 580          * or quirks for specific PCI bridges to be setting NO_MSI.
 581          */
 582         for (bus = dev->bus; bus; bus = bus->parent)
 583                 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 584                         return -EINVAL;
 585
 586         ret = arch_msi_check_device(dev, nvec, type);
 587         if (ret)
 588                 return ret;
 589
 590         if (!pci_find_capability(dev, type))
 591                 return -EINVAL;
 592
 593         return 0;
 594 }
 595
 596 /**
 597  * pci_enable_msi_block - configure device's MSI capability structure
 598  * @dev: device to configure
 599  * @nvec: number of interrupts to configure
 600  *
 601  * Allocate IRQs for a device with the MSI capability.
 602  * This function returns a negative errno if an error occurs.  If it
 603  * is unable to allocate the number of interrupts requested, it returns
 604  * the number of interrupts it might be able to allocate.  If it successfully
 605  * allocates at least the number of interrupts requested, it returns 0 and
 606  * updates the @dev's irq member to the lowest new interrupt number; the
 607  * other interrupt numbers allocated to this device are consecutive.
 608  */
 609 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
 610 {
 611         int status, pos, maxvec;
 612         u16 msgctl;
 613
 614         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 615         if (!pos)
 616                 return -EINVAL;
 617         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
 618         maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
 619         if (nvec > maxvec)
 620                 return maxvec;
 621
 622         status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
 623         if (status)
 624                 return status;
 625
 626         WARN_ON(!!dev->msi_enabled);
 627
 628         /* Check whether driver already requested MSI-X irqs */
 629         if (dev->msix_enabled) {
 630                 dev_info(&dev->dev, "can't enable MSI "
 631                          "(MSI-X already enabled)\n");
 632                 return -EINVAL;
 633         }
 634
 635         status = msi_capability_init(dev, nvec);
 636         return status;
 637 }
 638 EXPORT_SYMBOL(pci_enable_msi_block);
 639
 640 void pci_msi_shutdown(struct pci_dev *dev)
 641 {
 642         struct msi_desc *desc;
 643         u32 mask;
 644         u16 ctrl;
 645         unsigned pos;
 646
 647         if (!pci_msi_enable || !dev || !dev->msi_enabled)
 648                 return;
 649
 650         BUG_ON(list_empty(&dev->msi_list));
 651         desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
 652         pos = desc->msi_attrib.pos;
 653
 654         msi_set_enable(dev, pos, 0);
 655         pci_intx_for_msi(dev, 1);
 656         dev->msi_enabled = 0;
 657
 658         /* Return the device with MSI unmasked as initial states */
 659         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
 660         mask = msi_capable_mask(ctrl);
 661         /* Keep cached state to be restored */
 662         __msi_mask_irq(desc, mask, ~mask);
 663
 664         /* Restore dev->irq to its default pin-assertion irq */
 665         dev->irq = desc->msi_attrib.default_irq;
 666 }
 667
 668 void pci_disable_msi(struct pci_dev* dev)
 669 {
 670         if (!pci_msi_enable || !dev || !dev->msi_enabled)
 671                 return;
 672
 673         pci_msi_shutdown(dev);
 674         free_msi_irqs(dev);
 675 }
 676 EXPORT_SYMBOL(pci_disable_msi);
 677
 678 /**
 679  * pci_msix_table_size - return the number of device's MSI-X table entries
 680  * @dev: pointer to the pci_dev data structure of MSI-X device function
 681  */
 682 int pci_msix_table_size(struct pci_dev *dev)
 683 {
 684         int pos;
 685         u16 control;
 686
 687         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 688         if (!pos)
 689                 return 0;
 690
 691         pci_read_config_word(dev, msi_control_reg(pos), &control);
 692         return multi_msix_capable(control);
 693 }
 694
 695 /**
 696  * pci_enable_msix - configure device's MSI-X capability structure
 697  * @dev: pointer to the pci_dev data structure of MSI-X device function
 698  * @entries: pointer to an array of MSI-X entries
 699  * @nvec: number of MSI-X irqs requested for allocation by device driver
 700  *
 701  * Setup the MSI-X capability structure of device function with the number
 702  * of requested irqs upon its software driver call to request for
 703  * MSI-X mode enabled on its hardware device function. A return of zero
 704  * indicates the successful configuration of MSI-X capability structure
 705  * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 706  * Or a return of > 0 indicates that driver request is exceeding the number
 707  * of irqs or MSI-X vectors available. Driver should use the returned value to
 708  * re-send its request.
 709  **/
 710 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
 711 {
 712         int status, nr_entries;
 713         int i, j;
 714
 715         if (!entries)
 716                 return -EINVAL;
 717
 718         status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
 719         if (status)
 720                 return status;
 721
 722         nr_entries = pci_msix_table_size(dev);
 723         if (nvec > nr_entries)
 724                 return nr_entries;
 725
 726         /* Check for any invalid entries */
 727         for (i = 0; i < nvec; i++) {
 728                 if (entries[i].entry >= nr_entries)
 729                         return -EINVAL;         /* invalid entry */
 730                 for (j = i + 1; j < nvec; j++) {
 731                         if (entries[i].entry == entries[j].entry)
 732                                 return -EINVAL; /* duplicate entry */
 733                 }
 734         }
 735         WARN_ON(!!dev->msix_enabled);
 736
 737         /* Check whether driver already requested for MSI irq */
 738         if (dev->msi_enabled) {
 739                 dev_info(&dev->dev, "can't enable MSI-X "
 740                        "(MSI IRQ already assigned)\n");
 741                 return -EINVAL;
 742         }
 743         status = msix_capability_init(dev, entries, nvec);
 744         return status;
 745 }
 746 EXPORT_SYMBOL(pci_enable_msix);
 747
 748 void pci_msix_shutdown(struct pci_dev* dev)
 749 {
 750         struct msi_desc *entry;
 751
 752         if (!pci_msi_enable || !dev || !dev->msix_enabled)
 753                 return;
 754
 755         /* Return the device with MSI-X masked as initial states */
 756         list_for_each_entry(entry, &dev->msi_list, list) {
 757                 /* Keep cached states to be restored */
 758                 __msix_mask_irq(entry, 1);
 759         }
 760
 761         msix_set_enable(dev, 0);
 762         pci_intx_for_msi(dev, 1);
 763         dev->msix_enabled = 0;
 764 }
 765
 766 void pci_disable_msix(struct pci_dev* dev)
 767 {
 768         if (!pci_msi_enable || !dev || !dev->msix_enabled)
 769                 return;
 770
 771         pci_msix_shutdown(dev);
 772         free_msi_irqs(dev);
 773 }
 774 EXPORT_SYMBOL(pci_disable_msix);
 775
 776 /**
 777  * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 778  * @dev: pointer to the pci_dev data structure of MSI(X) device function
 779  *
 780  * Being called during hotplug remove, from which the device function
 781  * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 782  * allocated for this device function, are reclaimed to unused state,
 783  * which may be used later on.
 784  **/
 785 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
 786 {
 787         if (!pci_msi_enable || !dev)
 788                 return;
 789
 790         if (dev->msi_enabled || dev->msix_enabled)
 791                 free_msi_irqs(dev);
 792 }
 793
 794 void pci_no_msi(void)
 795 {
 796         pci_msi_enable = 0;
 797 }
 798
 799 /**
 800  * pci_msi_enabled - is MSI enabled?
 801  *
 802  * Returns true if MSI has not been disabled by the command-line option
 803  * pci=nomsi.
 804  **/
 805 int pci_msi_enabled(void)
 806 {
 807         return pci_msi_enable;
 808 }
 809 EXPORT_SYMBOL(pci_msi_enabled);
 810
 811 void pci_msi_init_pci_dev(struct pci_dev *dev)
 812 {
 813         INIT_LIST_HEAD(&dev->msi_list);
 814 }