2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
9 #define PCI_MSIX_ENTRY_SIZE 16
10 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
11 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
12 #define PCI_MSIX_ENTRY_DATA 8
13 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
15 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
16 #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
17 #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
18 #define msi_data_reg(base, is64bit) \
19 (base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32))
20 #define msi_mask_reg(base, is64bit) \
21 (base + ((is64bit == 1) ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32))
22 #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
23 #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
25 #define msix_table_offset_reg(base) (base + 0x04)
26 #define msix_pba_offset_reg(base) (base + 0x08)
27 #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
28 #define multi_msix_capable(control) msix_table_size((control))
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