2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 unsigned int pci_pm_d3_delay
= 10;
27 #ifdef CONFIG_PCI_DOMAINS
28 int pci_domains_supported
= 1;
31 #define DEFAULT_CARDBUS_IO_SIZE (256)
32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
34 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
35 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
39 * @bus: pointer to PCI bus structure to search
41 * Given a PCI bus, returns the highest PCI bus number present in the set
42 * including the given PCI bus and its list of child PCI buses.
44 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
46 struct list_head
*tmp
;
49 max
= bus
->subordinate
;
50 list_for_each(tmp
, &bus
->children
) {
51 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
61 * pci_max_busnr - returns maximum PCI bus number
63 * Returns the highest PCI bus number present in the system global list of
66 unsigned char __devinit
69 struct pci_bus
*bus
= NULL
;
73 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
74 n
= pci_bus_max_busnr(bus
);
83 #define PCI_FIND_CAP_TTL 48
85 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
86 u8 pos
, int cap
, int *ttl
)
91 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
95 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
101 pos
+= PCI_CAP_LIST_NEXT
;
106 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
109 int ttl
= PCI_FIND_CAP_TTL
;
111 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
114 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
116 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
117 pos
+ PCI_CAP_LIST_NEXT
, cap
);
119 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
121 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
122 unsigned int devfn
, u8 hdr_type
)
126 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
127 if (!(status
& PCI_STATUS_CAP_LIST
))
131 case PCI_HEADER_TYPE_NORMAL
:
132 case PCI_HEADER_TYPE_BRIDGE
:
133 return PCI_CAPABILITY_LIST
;
134 case PCI_HEADER_TYPE_CARDBUS
:
135 return PCI_CB_CAPABILITY_LIST
;
144 * pci_find_capability - query for devices' capabilities
145 * @dev: PCI device to query
146 * @cap: capability code
148 * Tell if a device supports a given PCI capability.
149 * Returns the address of the requested capability structure within the
150 * device's PCI configuration space or 0 in case the device does not
151 * support it. Possible values for @cap:
153 * %PCI_CAP_ID_PM Power Management
154 * %PCI_CAP_ID_AGP Accelerated Graphics Port
155 * %PCI_CAP_ID_VPD Vital Product Data
156 * %PCI_CAP_ID_SLOTID Slot Identification
157 * %PCI_CAP_ID_MSI Message Signalled Interrupts
158 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
159 * %PCI_CAP_ID_PCIX PCI-X
160 * %PCI_CAP_ID_EXP PCI Express
162 int pci_find_capability(struct pci_dev
*dev
, int cap
)
166 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
168 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
174 * pci_bus_find_capability - query for devices' capabilities
175 * @bus: the PCI bus to query
176 * @devfn: PCI device to query
177 * @cap: capability code
179 * Like pci_find_capability() but works for pci devices that do not have a
180 * pci_dev structure set up yet.
182 * Returns the address of the requested capability structure within the
183 * device's PCI configuration space or 0 in case the device does not
186 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
191 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
193 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
195 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
201 * pci_find_ext_capability - Find an extended capability
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Returns the address of the requested extended capability structure
206 * within the device's PCI configuration space or 0 if the device does
207 * not support it. Possible values for @cap:
209 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
210 * %PCI_EXT_CAP_ID_VC Virtual Channel
211 * %PCI_EXT_CAP_ID_DSN Device Serial Number
212 * %PCI_EXT_CAP_ID_PWR Power Budgeting
214 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
218 int pos
= PCI_CFG_SPACE_SIZE
;
220 /* minimum 8 bytes per capability */
221 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
223 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
226 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
230 * If we have no capabilities, this is indicated by cap ID,
231 * cap version and next pointer all being 0.
237 if (PCI_EXT_CAP_ID(header
) == cap
)
240 pos
= PCI_EXT_CAP_NEXT(header
);
241 if (pos
< PCI_CFG_SPACE_SIZE
)
244 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
250 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
252 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
254 int rc
, ttl
= PCI_FIND_CAP_TTL
;
257 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
258 mask
= HT_3BIT_CAP_MASK
;
260 mask
= HT_5BIT_CAP_MASK
;
262 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
263 PCI_CAP_ID_HT
, &ttl
);
265 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
266 if (rc
!= PCIBIOS_SUCCESSFUL
)
269 if ((cap
& mask
) == ht_cap
)
272 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
273 pos
+ PCI_CAP_LIST_NEXT
,
274 PCI_CAP_ID_HT
, &ttl
);
280 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
281 * @dev: PCI device to query
282 * @pos: Position from which to continue searching
283 * @ht_cap: Hypertransport capability code
285 * To be used in conjunction with pci_find_ht_capability() to search for
286 * all capabilities matching @ht_cap. @pos should always be a value returned
287 * from pci_find_ht_capability().
289 * NB. To be 100% safe against broken PCI devices, the caller should take
290 * steps to avoid an infinite loop.
292 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
294 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
296 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
299 * pci_find_ht_capability - query a device's Hypertransport capabilities
300 * @dev: PCI device to query
301 * @ht_cap: Hypertransport capability code
303 * Tell if a device supports a given Hypertransport capability.
304 * Returns an address within the device's PCI configuration space
305 * or 0 in case the device does not support the request capability.
306 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
307 * which has a Hypertransport capability matching @ht_cap.
309 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
313 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
315 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
319 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
322 * pci_find_parent_resource - return resource region of parent bus of given region
323 * @dev: PCI device structure contains resources to be searched
324 * @res: child resource record for which parent is sought
326 * For given resource region of given device, return the resource
327 * region of parent bus the given region is contained in or where
328 * it should be allocated from.
331 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
333 const struct pci_bus
*bus
= dev
->bus
;
335 struct resource
*best
= NULL
;
337 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
338 struct resource
*r
= bus
->resource
[i
];
341 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
342 continue; /* Not contained */
343 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
344 continue; /* Wrong type */
345 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
346 return r
; /* Exact match */
347 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
348 best
= r
; /* Approximating prefetchable by non-prefetchable */
354 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
355 * @dev: PCI device to have its BARs restored
357 * Restore the BAR values for a given device, so as to make it
358 * accessible by its driver.
361 pci_restore_bars(struct pci_dev
*dev
)
365 switch (dev
->hdr_type
) {
366 case PCI_HEADER_TYPE_NORMAL
:
369 case PCI_HEADER_TYPE_BRIDGE
:
372 case PCI_HEADER_TYPE_CARDBUS
:
376 /* Should never get here, but just in case... */
380 for (i
= 0; i
< numres
; i
++)
381 pci_update_resource(dev
, &dev
->resource
[i
], i
);
384 static struct pci_platform_pm_ops
*pci_platform_pm
;
386 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
388 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
389 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
391 pci_platform_pm
= ops
;
395 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
397 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
400 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
403 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
406 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
408 return pci_platform_pm
?
409 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
412 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
414 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
417 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
419 return pci_platform_pm
?
420 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
424 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
426 * @dev: PCI device to handle.
427 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
430 * -EINVAL if the requested state is invalid.
431 * -EIO if device does not support PCI PM or its PM capabilities register has a
432 * wrong version, or device doesn't support the requested state.
433 * 0 if device already is in the requested state.
434 * 0 if device's power state has been successfully changed.
437 pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
440 bool need_restore
= false;
445 if (state
< PCI_D0
|| state
> PCI_D3hot
)
448 /* Validate current state:
449 * Can enter D0 from any state, but if we can only go deeper
450 * to sleep if we're already in a low power state
452 if (dev
->current_state
== state
) {
453 /* we're already there */
455 } else if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
456 && dev
->current_state
> state
) {
457 dev_err(&dev
->dev
, "invalid power transition "
458 "(from state %d to %d)\n", dev
->current_state
, state
);
462 /* check if this device supports the desired state */
463 if ((state
== PCI_D1
&& !dev
->d1_support
)
464 || (state
== PCI_D2
&& !dev
->d2_support
))
467 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
469 /* If we're (effectively) in D3, force entire word to 0.
470 * This doesn't affect PME_Status, disables PME_En, and
471 * sets PowerState to 0.
473 switch (dev
->current_state
) {
477 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
480 case PCI_UNKNOWN
: /* Boot-up */
481 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
482 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
484 /* Fall-through: force to D0 */
490 /* enter specified state */
491 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
493 /* Mandatory power management transition delays */
494 /* see PCI PM 1.1 5.6.1 table 18 */
495 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
496 msleep(pci_pm_d3_delay
);
497 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
500 dev
->current_state
= state
;
502 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
503 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
504 * from D3hot to D0 _may_ perform an internal reset, thereby
505 * going to "D0 Uninitialized" rather than "D0 Initialized".
506 * For example, at least some versions of the 3c905B and the
507 * 3c556B exhibit this behaviour.
509 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
510 * devices in a D3hot state at boot. Consequently, we need to
511 * restore at least the BARs so that the device will be
512 * accessible to its driver.
515 pci_restore_bars(dev
);
518 pcie_aspm_pm_state_change(dev
->bus
->self
);
524 * pci_update_current_state - Read PCI power state of given device from its
525 * PCI PM registers and cache it
526 * @dev: PCI device to handle.
528 static void pci_update_current_state(struct pci_dev
*dev
)
533 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
534 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
539 * pci_set_power_state - Set the power state of a PCI device
540 * @dev: PCI device to handle.
541 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
543 * Transition a device to a new power state, using the platform formware and/or
544 * the device's PCI PM registers.
547 * -EINVAL if the requested state is invalid.
548 * -EIO if device does not support PCI PM or its PM capabilities register has a
549 * wrong version, or device doesn't support the requested state.
550 * 0 if device already is in the requested state.
551 * 0 if device's power state has been successfully changed.
553 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
557 /* bound the state we're entering */
558 if (state
> PCI_D3hot
)
560 else if (state
< PCI_D0
)
562 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
564 * If the device or the parent bridge do not support PCI PM,
565 * ignore the request if we're doing anything other than putting
566 * it into D0 (which would only happen on boot).
570 if (state
== PCI_D0
&& platform_pci_power_manageable(dev
)) {
572 * Allow the platform to change the state, for example via ACPI
573 * _PR0, _PS0 and some such, but do not trust it.
575 int ret
= platform_pci_set_power_state(dev
, PCI_D0
);
577 pci_update_current_state(dev
);
579 /* This device is quirked not to be put into D3, so
580 don't put it in D3 */
581 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
584 error
= pci_raw_set_power_state(dev
, state
);
586 if (state
> PCI_D0
&& platform_pci_power_manageable(dev
)) {
587 /* Allow the platform to finalize the transition */
588 int ret
= platform_pci_set_power_state(dev
, state
);
590 pci_update_current_state(dev
);
599 * pci_choose_state - Choose the power state of a PCI device
600 * @dev: PCI device to be suspended
601 * @state: target sleep state for the whole system. This is the value
602 * that is passed to suspend() function.
604 * Returns PCI power state suitable for given device and given system
608 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
612 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
615 ret
= platform_pci_choose_state(dev
);
616 if (ret
!= PCI_POWER_ERROR
)
619 switch (state
.event
) {
622 case PM_EVENT_FREEZE
:
623 case PM_EVENT_PRETHAW
:
624 /* REVISIT both freeze and pre-thaw "should" use D0 */
625 case PM_EVENT_SUSPEND
:
626 case PM_EVENT_HIBERNATE
:
629 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
636 EXPORT_SYMBOL(pci_choose_state
);
638 static int pci_save_pcie_state(struct pci_dev
*dev
)
641 struct pci_cap_saved_state
*save_state
;
644 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
648 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
650 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
653 cap
= (u16
*)&save_state
->data
[0];
655 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
656 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
657 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
658 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
663 static void pci_restore_pcie_state(struct pci_dev
*dev
)
666 struct pci_cap_saved_state
*save_state
;
669 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
670 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
671 if (!save_state
|| pos
<= 0)
673 cap
= (u16
*)&save_state
->data
[0];
675 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
676 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
677 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
678 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
682 static int pci_save_pcix_state(struct pci_dev
*dev
)
685 struct pci_cap_saved_state
*save_state
;
687 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
691 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
693 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
697 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
702 static void pci_restore_pcix_state(struct pci_dev
*dev
)
705 struct pci_cap_saved_state
*save_state
;
708 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
709 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
710 if (!save_state
|| pos
<= 0)
712 cap
= (u16
*)&save_state
->data
[0];
714 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
719 * pci_save_state - save the PCI configuration space of a device before suspending
720 * @dev: - PCI device that we're dealing with
723 pci_save_state(struct pci_dev
*dev
)
726 /* XXX: 100% dword access ok here? */
727 for (i
= 0; i
< 16; i
++)
728 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
729 if ((i
= pci_save_pcie_state(dev
)) != 0)
731 if ((i
= pci_save_pcix_state(dev
)) != 0)
737 * pci_restore_state - Restore the saved state of a PCI device
738 * @dev: - PCI device that we're dealing with
741 pci_restore_state(struct pci_dev
*dev
)
746 /* PCI Express register must be restored first */
747 pci_restore_pcie_state(dev
);
750 * The Base Address register should be programmed before the command
753 for (i
= 15; i
>= 0; i
--) {
754 pci_read_config_dword(dev
, i
* 4, &val
);
755 if (val
!= dev
->saved_config_space
[i
]) {
756 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
757 "space at offset %#x (was %#x, writing %#x)\n",
758 i
, val
, (int)dev
->saved_config_space
[i
]);
759 pci_write_config_dword(dev
,i
* 4,
760 dev
->saved_config_space
[i
]);
763 pci_restore_pcix_state(dev
);
764 pci_restore_msi_state(dev
);
769 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
773 err
= pci_set_power_state(dev
, PCI_D0
);
774 if (err
< 0 && err
!= -EIO
)
776 err
= pcibios_enable_device(dev
, bars
);
779 pci_fixup_device(pci_fixup_enable
, dev
);
785 * pci_reenable_device - Resume abandoned device
786 * @dev: PCI device to be resumed
788 * Note this function is a backend of pci_default_resume and is not supposed
789 * to be called by normal code, write proper resume handler and use it instead.
791 int pci_reenable_device(struct pci_dev
*dev
)
793 if (atomic_read(&dev
->enable_cnt
))
794 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
798 static int __pci_enable_device_flags(struct pci_dev
*dev
,
799 resource_size_t flags
)
804 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
805 return 0; /* already enabled */
807 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
808 if (dev
->resource
[i
].flags
& flags
)
811 err
= do_pci_enable_device(dev
, bars
);
813 atomic_dec(&dev
->enable_cnt
);
818 * pci_enable_device_io - Initialize a device for use with IO space
819 * @dev: PCI device to be initialized
821 * Initialize device before it's used by a driver. Ask low-level code
822 * to enable I/O resources. Wake up the device if it was suspended.
823 * Beware, this function can fail.
825 int pci_enable_device_io(struct pci_dev
*dev
)
827 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
831 * pci_enable_device_mem - Initialize a device for use with Memory space
832 * @dev: PCI device to be initialized
834 * Initialize device before it's used by a driver. Ask low-level code
835 * to enable Memory resources. Wake up the device if it was suspended.
836 * Beware, this function can fail.
838 int pci_enable_device_mem(struct pci_dev
*dev
)
840 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
844 * pci_enable_device - Initialize device before it's used by a driver.
845 * @dev: PCI device to be initialized
847 * Initialize device before it's used by a driver. Ask low-level code
848 * to enable I/O and memory. Wake up the device if it was suspended.
849 * Beware, this function can fail.
851 * Note we don't actually enable the device many times if we call
852 * this function repeatedly (we just increment the count).
854 int pci_enable_device(struct pci_dev
*dev
)
856 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
860 * Managed PCI resources. This manages device on/off, intx/msi/msix
861 * on/off and BAR regions. pci_dev itself records msi/msix status, so
862 * there's no need to track it separately. pci_devres is initialized
863 * when a device is enabled using managed PCI device enable interface.
866 unsigned int enabled
:1;
867 unsigned int pinned
:1;
868 unsigned int orig_intx
:1;
869 unsigned int restore_intx
:1;
873 static void pcim_release(struct device
*gendev
, void *res
)
875 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
876 struct pci_devres
*this = res
;
879 if (dev
->msi_enabled
)
880 pci_disable_msi(dev
);
881 if (dev
->msix_enabled
)
882 pci_disable_msix(dev
);
884 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
885 if (this->region_mask
& (1 << i
))
886 pci_release_region(dev
, i
);
888 if (this->restore_intx
)
889 pci_intx(dev
, this->orig_intx
);
891 if (this->enabled
&& !this->pinned
)
892 pci_disable_device(dev
);
895 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
897 struct pci_devres
*dr
, *new_dr
;
899 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
903 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
906 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
909 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
911 if (pci_is_managed(pdev
))
912 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
917 * pcim_enable_device - Managed pci_enable_device()
918 * @pdev: PCI device to be initialized
920 * Managed pci_enable_device().
922 int pcim_enable_device(struct pci_dev
*pdev
)
924 struct pci_devres
*dr
;
927 dr
= get_pci_dr(pdev
);
933 rc
= pci_enable_device(pdev
);
935 pdev
->is_managed
= 1;
942 * pcim_pin_device - Pin managed PCI device
943 * @pdev: PCI device to pin
945 * Pin managed PCI device @pdev. Pinned device won't be disabled on
946 * driver detach. @pdev must have been enabled with
947 * pcim_enable_device().
949 void pcim_pin_device(struct pci_dev
*pdev
)
951 struct pci_devres
*dr
;
953 dr
= find_pci_dr(pdev
);
954 WARN_ON(!dr
|| !dr
->enabled
);
960 * pcibios_disable_device - disable arch specific PCI resources for device dev
961 * @dev: the PCI device to disable
963 * Disables architecture specific PCI resources for the device. This
964 * is the default implementation. Architecture implementations can
967 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
970 * pci_disable_device - Disable PCI device after use
971 * @dev: PCI device to be disabled
973 * Signal to the system that the PCI device is not in use by the system
974 * anymore. This only involves disabling PCI bus-mastering, if active.
976 * Note we don't actually disable the device until all callers of
977 * pci_device_enable() have called pci_device_disable().
980 pci_disable_device(struct pci_dev
*dev
)
982 struct pci_devres
*dr
;
985 dr
= find_pci_dr(dev
);
989 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
992 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
993 if (pci_command
& PCI_COMMAND_MASTER
) {
994 pci_command
&= ~PCI_COMMAND_MASTER
;
995 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
997 dev
->is_busmaster
= 0;
999 pcibios_disable_device(dev
);
1003 * pcibios_set_pcie_reset_state - set reset state for device dev
1004 * @dev: the PCI-E device reset
1005 * @state: Reset state to enter into
1008 * Sets the PCI-E reset state for the device. This is the default
1009 * implementation. Architecture implementations can override this.
1011 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1012 enum pcie_reset_state state
)
1018 * pci_set_pcie_reset_state - set reset state for device dev
1019 * @dev: the PCI-E device reset
1020 * @state: Reset state to enter into
1023 * Sets the PCI reset state for the device.
1025 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1027 return pcibios_set_pcie_reset_state(dev
, state
);
1031 * pci_pme_capable - check the capability of PCI device to generate PME#
1032 * @dev: PCI device to handle.
1033 * @state: PCI state from which device will issue PME#.
1035 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1040 return !!(dev
->pme_support
& (1 << state
));
1044 * pci_pme_active - enable or disable PCI device's PME# function
1045 * @dev: PCI device to handle.
1046 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1048 * The caller must verify that the device is capable of generating PME# before
1049 * calling this function with @enable equal to 'true'.
1051 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1058 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1059 /* Clear PME_Status by writing 1 to it and enable PME# */
1060 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1062 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1064 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1066 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1067 enable
? "enabled" : "disabled");
1071 * pci_enable_wake - enable PCI device as wakeup event source
1072 * @dev: PCI device affected
1073 * @state: PCI state from which device will issue wakeup events
1074 * @enable: True to enable event generation; false to disable
1076 * This enables the device as a wakeup event source, or disables it.
1077 * When such events involves platform-specific hooks, those hooks are
1078 * called automatically by this routine.
1080 * Devices with legacy power management (no standard PCI PM capabilities)
1081 * always require such platform hooks.
1084 * 0 is returned on success
1085 * -EINVAL is returned if device is not supposed to wake up the system
1086 * Error code depending on the platform is returned if both the platform and
1087 * the native mechanism fail to enable the generation of wake-up events
1089 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1092 bool pme_done
= false;
1094 if (enable
&& !device_may_wakeup(&dev
->dev
))
1098 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1099 * Anderson we should be doing PME# wake enable followed by ACPI wake
1100 * enable. To disable wake-up we call the platform first, for symmetry.
1103 if (!enable
&& platform_pci_can_wakeup(dev
))
1104 error
= platform_pci_sleep_wake(dev
, false);
1106 if (!enable
|| pci_pme_capable(dev
, state
)) {
1107 pci_pme_active(dev
, enable
);
1111 if (enable
&& platform_pci_can_wakeup(dev
))
1112 error
= platform_pci_sleep_wake(dev
, true);
1114 return pme_done
? 0 : error
;
1118 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1119 * @dev: PCI device to prepare
1120 * @enable: True to enable wake-up event generation; false to disable
1122 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1123 * and this function allows them to set that up cleanly - pci_enable_wake()
1124 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1125 * ordering constraints.
1127 * This function only returns error code if the device is not capable of
1128 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1129 * enable wake-up power for it.
1131 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1133 return pci_pme_capable(dev
, PCI_D3cold
) ?
1134 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1135 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1139 * pci_target_state - find an appropriate low power state for a given PCI dev
1142 * Use underlying platform code to find a supported low power state for @dev.
1143 * If the platform can't manage @dev, return the deepest state from which it
1144 * can generate wake events, based on any available PME info.
1146 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1148 pci_power_t target_state
= PCI_D3hot
;
1150 if (platform_pci_power_manageable(dev
)) {
1152 * Call the platform to choose the target state of the device
1153 * and enable wake-up from this state if supported.
1155 pci_power_t state
= platform_pci_choose_state(dev
);
1158 case PCI_POWER_ERROR
:
1163 if (pci_no_d1d2(dev
))
1166 target_state
= state
;
1168 } else if (device_may_wakeup(&dev
->dev
)) {
1170 * Find the deepest state from which the device can generate
1171 * wake-up events, make it the target state and enable device
1175 return PCI_POWER_ERROR
;
1177 if (dev
->pme_support
) {
1179 && !(dev
->pme_support
& (1 << target_state
)))
1184 return target_state
;
1188 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1189 * @dev: Device to handle.
1191 * Choose the power state appropriate for the device depending on whether
1192 * it can wake up the system and/or is power manageable by the platform
1193 * (PCI_D3hot is the default) and put the device into that state.
1195 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1197 pci_power_t target_state
= pci_target_state(dev
);
1200 if (target_state
== PCI_POWER_ERROR
)
1203 pci_enable_wake(dev
, target_state
, true);
1205 error
= pci_set_power_state(dev
, target_state
);
1208 pci_enable_wake(dev
, target_state
, false);
1214 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1215 * @dev: Device to handle.
1217 * Disable device's sytem wake-up capability and put it into D0.
1219 int pci_back_from_sleep(struct pci_dev
*dev
)
1221 pci_enable_wake(dev
, PCI_D0
, false);
1222 return pci_set_power_state(dev
, PCI_D0
);
1226 * pci_pm_init - Initialize PM functions of given PCI device
1227 * @dev: PCI device to handle.
1229 void pci_pm_init(struct pci_dev
*dev
)
1236 /* find PCI PM capability in list */
1237 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1240 /* Check device's ability to generate PME# */
1241 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1243 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1244 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1245 pmc
& PCI_PM_CAP_VER_MASK
);
1251 dev
->d1_support
= false;
1252 dev
->d2_support
= false;
1253 if (!pci_no_d1d2(dev
)) {
1254 if (pmc
& PCI_PM_CAP_D1
)
1255 dev
->d1_support
= true;
1256 if (pmc
& PCI_PM_CAP_D2
)
1257 dev
->d2_support
= true;
1259 if (dev
->d1_support
|| dev
->d2_support
)
1260 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1261 dev
->d1_support
? " D1" : "",
1262 dev
->d2_support
? " D2" : "");
1265 pmc
&= PCI_PM_CAP_PME_MASK
;
1267 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1268 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1269 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1270 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1271 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1272 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1273 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1275 * Make device's PM flags reflect the wake-up capability, but
1276 * let the user space enable it to wake up the system as needed.
1278 device_set_wakeup_capable(&dev
->dev
, true);
1279 device_set_wakeup_enable(&dev
->dev
, false);
1280 /* Disable the PME# generation functionality */
1281 pci_pme_active(dev
, false);
1283 dev
->pme_support
= 0;
1288 * pci_add_save_buffer - allocate buffer for saving given capability registers
1289 * @dev: the PCI device
1290 * @cap: the capability to allocate the buffer for
1291 * @size: requested size of the buffer
1293 static int pci_add_cap_save_buffer(
1294 struct pci_dev
*dev
, char cap
, unsigned int size
)
1297 struct pci_cap_saved_state
*save_state
;
1299 pos
= pci_find_capability(dev
, cap
);
1303 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1307 save_state
->cap_nr
= cap
;
1308 pci_add_saved_cap(dev
, save_state
);
1314 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1315 * @dev: the PCI device
1317 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1321 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
, 4 * sizeof(u16
));
1324 "unable to preallocate PCI Express save buffer\n");
1326 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1329 "unable to preallocate PCI-X save buffer\n");
1333 * pci_enable_ari - enable ARI forwarding if hardware support it
1334 * @dev: the PCI device
1336 void pci_enable_ari(struct pci_dev
*dev
)
1341 struct pci_dev
*bridge
;
1343 if (!dev
->is_pcie
|| dev
->devfn
)
1346 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1350 bridge
= dev
->bus
->self
;
1351 if (!bridge
|| !bridge
->is_pcie
)
1354 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1358 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1359 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1362 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1363 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1364 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1366 bridge
->ari_enabled
= 1;
1370 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1371 * @dev: the PCI device
1372 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1374 * Perform INTx swizzling for a device behind one level of bridge. This is
1375 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1376 * behind bridges on add-in cards.
1378 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1380 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1384 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1392 while (dev
->bus
->self
) {
1393 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1394 dev
= dev
->bus
->self
;
1401 * pci_release_region - Release a PCI bar
1402 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1403 * @bar: BAR to release
1405 * Releases the PCI I/O and memory resources previously reserved by a
1406 * successful call to pci_request_region. Call this function only
1407 * after all use of the PCI regions has ceased.
1409 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1411 struct pci_devres
*dr
;
1413 if (pci_resource_len(pdev
, bar
) == 0)
1415 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1416 release_region(pci_resource_start(pdev
, bar
),
1417 pci_resource_len(pdev
, bar
));
1418 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1419 release_mem_region(pci_resource_start(pdev
, bar
),
1420 pci_resource_len(pdev
, bar
));
1422 dr
= find_pci_dr(pdev
);
1424 dr
->region_mask
&= ~(1 << bar
);
1428 * pci_request_region - Reserved PCI I/O and memory resource
1429 * @pdev: PCI device whose resources are to be reserved
1430 * @bar: BAR to be reserved
1431 * @res_name: Name to be associated with resource.
1433 * Mark the PCI region associated with PCI device @pdev BR @bar as
1434 * being reserved by owner @res_name. Do not access any
1435 * address inside the PCI regions unless this call returns
1438 * Returns 0 on success, or %EBUSY on error. A warning
1439 * message is also printed on failure.
1441 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1444 struct pci_devres
*dr
;
1446 if (pci_resource_len(pdev
, bar
) == 0)
1449 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1450 if (!request_region(pci_resource_start(pdev
, bar
),
1451 pci_resource_len(pdev
, bar
), res_name
))
1454 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1455 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1456 pci_resource_len(pdev
, bar
), res_name
,
1461 dr
= find_pci_dr(pdev
);
1463 dr
->region_mask
|= 1 << bar
;
1468 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1470 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1471 &pdev
->resource
[bar
]);
1476 * pci_request_region - Reserved PCI I/O and memory resource
1477 * @pdev: PCI device whose resources are to be reserved
1478 * @bar: BAR to be reserved
1479 * @res_name: Name to be associated with resource.
1481 * Mark the PCI region associated with PCI device @pdev BR @bar as
1482 * being reserved by owner @res_name. Do not access any
1483 * address inside the PCI regions unless this call returns
1486 * Returns 0 on success, or %EBUSY on error. A warning
1487 * message is also printed on failure.
1489 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1491 return __pci_request_region(pdev
, bar
, res_name
, 0);
1495 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1496 * @pdev: PCI device whose resources are to be reserved
1497 * @bar: BAR to be reserved
1498 * @res_name: Name to be associated with resource.
1500 * Mark the PCI region associated with PCI device @pdev BR @bar as
1501 * being reserved by owner @res_name. Do not access any
1502 * address inside the PCI regions unless this call returns
1505 * Returns 0 on success, or %EBUSY on error. A warning
1506 * message is also printed on failure.
1508 * The key difference that _exclusive makes it that userspace is
1509 * explicitly not allowed to map the resource via /dev/mem or
1512 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1514 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1517 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1518 * @pdev: PCI device whose resources were previously reserved
1519 * @bars: Bitmask of BARs to be released
1521 * Release selected PCI I/O and memory resources previously reserved.
1522 * Call this function only after all use of the PCI regions has ceased.
1524 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1528 for (i
= 0; i
< 6; i
++)
1529 if (bars
& (1 << i
))
1530 pci_release_region(pdev
, i
);
1533 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1534 const char *res_name
, int excl
)
1538 for (i
= 0; i
< 6; i
++)
1539 if (bars
& (1 << i
))
1540 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1546 if (bars
& (1 << i
))
1547 pci_release_region(pdev
, i
);
1554 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1555 * @pdev: PCI device whose resources are to be reserved
1556 * @bars: Bitmask of BARs to be requested
1557 * @res_name: Name to be associated with resource
1559 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1560 const char *res_name
)
1562 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1565 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1566 int bars
, const char *res_name
)
1568 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1569 IORESOURCE_EXCLUSIVE
);
1573 * pci_release_regions - Release reserved PCI I/O and memory resources
1574 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1576 * Releases all PCI I/O and memory resources previously reserved by a
1577 * successful call to pci_request_regions. Call this function only
1578 * after all use of the PCI regions has ceased.
1581 void pci_release_regions(struct pci_dev
*pdev
)
1583 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1587 * pci_request_regions - Reserved PCI I/O and memory resources
1588 * @pdev: PCI device whose resources are to be reserved
1589 * @res_name: Name to be associated with resource.
1591 * Mark all PCI regions associated with PCI device @pdev as
1592 * being reserved by owner @res_name. Do not access any
1593 * address inside the PCI regions unless this call returns
1596 * Returns 0 on success, or %EBUSY on error. A warning
1597 * message is also printed on failure.
1599 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1601 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1605 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1606 * @pdev: PCI device whose resources are to be reserved
1607 * @res_name: Name to be associated with resource.
1609 * Mark all PCI regions associated with PCI device @pdev as
1610 * being reserved by owner @res_name. Do not access any
1611 * address inside the PCI regions unless this call returns
1614 * pci_request_regions_exclusive() will mark the region so that
1615 * /dev/mem and the sysfs MMIO access will not be allowed.
1617 * Returns 0 on success, or %EBUSY on error. A warning
1618 * message is also printed on failure.
1620 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1622 return pci_request_selected_regions_exclusive(pdev
,
1623 ((1 << 6) - 1), res_name
);
1628 * pci_set_master - enables bus-mastering for device dev
1629 * @dev: the PCI device to enable
1631 * Enables bus-mastering on the device and calls pcibios_set_master()
1632 * to do the needed arch specific settings.
1635 pci_set_master(struct pci_dev
*dev
)
1639 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1640 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1641 dev_dbg(&dev
->dev
, "enabling bus mastering\n");
1642 cmd
|= PCI_COMMAND_MASTER
;
1643 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1645 dev
->is_busmaster
= 1;
1646 pcibios_set_master(dev
);
1649 #ifdef PCI_DISABLE_MWI
1650 int pci_set_mwi(struct pci_dev
*dev
)
1655 int pci_try_set_mwi(struct pci_dev
*dev
)
1660 void pci_clear_mwi(struct pci_dev
*dev
)
1666 #ifndef PCI_CACHE_LINE_BYTES
1667 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1670 /* This can be overridden by arch code. */
1671 /* Don't forget this is measured in 32-bit words, not bytes */
1672 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1675 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1676 * @dev: the PCI device for which MWI is to be enabled
1678 * Helper function for pci_set_mwi.
1679 * Originally copied from drivers/net/acenic.c.
1680 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1682 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1685 pci_set_cacheline_size(struct pci_dev
*dev
)
1689 if (!pci_cache_line_size
)
1690 return -EINVAL
; /* The system doesn't support MWI. */
1692 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1693 equal to or multiple of the right value. */
1694 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1695 if (cacheline_size
>= pci_cache_line_size
&&
1696 (cacheline_size
% pci_cache_line_size
) == 0)
1699 /* Write the correct value. */
1700 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1702 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1703 if (cacheline_size
== pci_cache_line_size
)
1706 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1707 "supported\n", pci_cache_line_size
<< 2);
1713 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1714 * @dev: the PCI device for which MWI is enabled
1716 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1718 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1721 pci_set_mwi(struct pci_dev
*dev
)
1726 rc
= pci_set_cacheline_size(dev
);
1730 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1731 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1732 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1733 cmd
|= PCI_COMMAND_INVALIDATE
;
1734 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1741 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1742 * @dev: the PCI device for which MWI is enabled
1744 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1745 * Callers are not required to check the return value.
1747 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1749 int pci_try_set_mwi(struct pci_dev
*dev
)
1751 int rc
= pci_set_mwi(dev
);
1756 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1757 * @dev: the PCI device to disable
1759 * Disables PCI Memory-Write-Invalidate transaction on the device
1762 pci_clear_mwi(struct pci_dev
*dev
)
1766 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1767 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1768 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1769 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1772 #endif /* ! PCI_DISABLE_MWI */
1775 * pci_intx - enables/disables PCI INTx for device dev
1776 * @pdev: the PCI device to operate on
1777 * @enable: boolean: whether to enable or disable PCI INTx
1779 * Enables/disables PCI INTx for device dev
1782 pci_intx(struct pci_dev
*pdev
, int enable
)
1784 u16 pci_command
, new;
1786 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1789 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1791 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1794 if (new != pci_command
) {
1795 struct pci_devres
*dr
;
1797 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1799 dr
= find_pci_dr(pdev
);
1800 if (dr
&& !dr
->restore_intx
) {
1801 dr
->restore_intx
= 1;
1802 dr
->orig_intx
= !enable
;
1808 * pci_msi_off - disables any msi or msix capabilities
1809 * @dev: the PCI device to operate on
1811 * If you want to use msi see pci_enable_msi and friends.
1812 * This is a lower level primitive that allows us to disable
1813 * msi operation at the device level.
1815 void pci_msi_off(struct pci_dev
*dev
)
1820 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1822 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1823 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1824 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1826 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1828 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1829 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1830 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1834 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1836 * These can be overridden by arch-specific implementations
1839 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1841 if (!pci_dma_supported(dev
, mask
))
1844 dev
->dma_mask
= mask
;
1850 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1852 if (!pci_dma_supported(dev
, mask
))
1855 dev
->dev
.coherent_dma_mask
= mask
;
1861 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1862 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
1864 return dma_set_max_seg_size(&dev
->dev
, size
);
1866 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
1869 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1870 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
1872 return dma_set_seg_boundary(&dev
->dev
, mask
);
1874 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
1877 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
1881 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1885 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
1886 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
1892 pci_block_user_cfg_access(dev
);
1894 /* Wait for Transaction Pending bit clean */
1896 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1897 if (status
& PCI_EXP_DEVSTA_TRPND
) {
1898 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
1899 "sleeping for 1 second\n");
1901 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1902 if (status
& PCI_EXP_DEVSTA_TRPND
)
1903 dev_info(&dev
->dev
, "Still busy after 1s; "
1904 "proceeding with reset anyway\n");
1907 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
1908 PCI_EXP_DEVCTL_BCR_FLR
);
1911 pci_unblock_user_cfg_access(dev
);
1915 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
1917 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
1923 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
1924 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
1930 pci_block_user_cfg_access(dev
);
1932 /* Wait for Transaction Pending bit clean */
1934 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
1935 if (status
& PCI_AF_STATUS_TP
) {
1936 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
1937 " reset; sleeping for 1 second\n");
1939 pci_read_config_byte(dev
,
1940 cappos
+ PCI_AF_STATUS
, &status
);
1941 if (status
& PCI_AF_STATUS_TP
)
1942 dev_info(&dev
->dev
, "Still busy after 1s; "
1943 "proceeding with reset anyway\n");
1945 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
1948 pci_unblock_user_cfg_access(dev
);
1952 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
1956 res
= __pcie_flr(pdev
, probe
);
1960 res
= __pci_af_flr(pdev
, probe
);
1968 * pci_execute_reset_function() - Reset a PCI device function
1969 * @dev: Device function to reset
1971 * Some devices allow an individual function to be reset without affecting
1972 * other functions in the same device. The PCI device must be responsive
1973 * to PCI config space in order to use this function.
1975 * The device function is presumed to be unused when this function is called.
1976 * Resetting the device will make the contents of PCI configuration space
1977 * random, so any caller of this must be prepared to reinitialise the
1978 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
1981 * Returns 0 if the device function was successfully reset or -ENOTTY if the
1982 * device doesn't support resetting a single function.
1984 int pci_execute_reset_function(struct pci_dev
*dev
)
1986 return __pci_reset_function(dev
, 0);
1988 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
1991 * pci_reset_function() - quiesce and reset a PCI device function
1992 * @dev: Device function to reset
1994 * Some devices allow an individual function to be reset without affecting
1995 * other functions in the same device. The PCI device must be responsive
1996 * to PCI config space in order to use this function.
1998 * This function does not just reset the PCI portion of a device, but
1999 * clears all the state associated with the device. This function differs
2000 * from pci_execute_reset_function in that it saves and restores device state
2003 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2004 * device doesn't support resetting a single function.
2006 int pci_reset_function(struct pci_dev
*dev
)
2008 int r
= __pci_reset_function(dev
, 1);
2013 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2014 disable_irq(dev
->irq
);
2015 pci_save_state(dev
);
2017 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2019 r
= pci_execute_reset_function(dev
);
2021 pci_restore_state(dev
);
2022 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2023 enable_irq(dev
->irq
);
2027 EXPORT_SYMBOL_GPL(pci_reset_function
);
2030 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2031 * @dev: PCI device to query
2033 * Returns mmrbc: maximum designed memory read count in bytes
2034 * or appropriate error value.
2036 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2041 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2045 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2049 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2051 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2054 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2055 * @dev: PCI device to query
2057 * Returns mmrbc: maximum memory read count in bytes
2058 * or appropriate error value.
2060 int pcix_get_mmrbc(struct pci_dev
*dev
)
2065 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2069 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2071 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2075 EXPORT_SYMBOL(pcix_get_mmrbc
);
2078 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2079 * @dev: PCI device to query
2080 * @mmrbc: maximum memory read count in bytes
2081 * valid values are 512, 1024, 2048, 4096
2083 * If possible sets maximum memory read byte count, some bridges have erratas
2084 * that prevent this.
2086 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2088 int cap
, err
= -EINVAL
;
2089 u32 stat
, cmd
, v
, o
;
2091 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2094 v
= ffs(mmrbc
) - 10;
2096 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2100 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2104 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2107 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2111 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2113 if (v
> o
&& dev
->bus
&&
2114 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2117 cmd
&= ~PCI_X_CMD_MAX_READ
;
2119 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2124 EXPORT_SYMBOL(pcix_set_mmrbc
);
2127 * pcie_get_readrq - get PCI Express read request size
2128 * @dev: PCI device to query
2130 * Returns maximum memory read request in bytes
2131 * or appropriate error value.
2133 int pcie_get_readrq(struct pci_dev
*dev
)
2138 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2142 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2144 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2148 EXPORT_SYMBOL(pcie_get_readrq
);
2151 * pcie_set_readrq - set PCI Express maximum memory read request
2152 * @dev: PCI device to query
2153 * @rq: maximum memory read count in bytes
2154 * valid values are 128, 256, 512, 1024, 2048, 4096
2156 * If possible sets maximum read byte count
2158 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2160 int cap
, err
= -EINVAL
;
2163 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2166 v
= (ffs(rq
) - 8) << 12;
2168 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2172 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2176 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2177 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2179 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2185 EXPORT_SYMBOL(pcie_set_readrq
);
2188 * pci_select_bars - Make BAR mask from the type of resource
2189 * @dev: the PCI device for which BAR mask is made
2190 * @flags: resource type mask to be selected
2192 * This helper routine makes bar mask from the type of resource.
2194 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2197 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2198 if (pci_resource_flags(dev
, i
) & flags
)
2203 static void __devinit
pci_no_domains(void)
2205 #ifdef CONFIG_PCI_DOMAINS
2206 pci_domains_supported
= 0;
2211 * pci_ext_cfg_enabled - can we access extended PCI config space?
2212 * @dev: The PCI device of the root bridge.
2214 * Returns 1 if we can access PCI extended config space (offsets
2215 * greater than 0xff). This is the default implementation. Architecture
2216 * implementations can override this.
2218 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2223 static int __devinit
pci_init(void)
2225 struct pci_dev
*dev
= NULL
;
2227 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2228 pci_fixup_device(pci_fixup_final
, dev
);
2234 static int __init
pci_setup(char *str
)
2237 char *k
= strchr(str
, ',');
2240 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2241 if (!strcmp(str
, "nomsi")) {
2243 } else if (!strcmp(str
, "noaer")) {
2245 } else if (!strcmp(str
, "nodomains")) {
2247 } else if (!strncmp(str
, "cbiosize=", 9)) {
2248 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2249 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2250 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2252 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2260 early_param("pci", pci_setup
);
2262 device_initcall(pci_init
);
2264 EXPORT_SYMBOL(pci_reenable_device
);
2265 EXPORT_SYMBOL(pci_enable_device_io
);
2266 EXPORT_SYMBOL(pci_enable_device_mem
);
2267 EXPORT_SYMBOL(pci_enable_device
);
2268 EXPORT_SYMBOL(pcim_enable_device
);
2269 EXPORT_SYMBOL(pcim_pin_device
);
2270 EXPORT_SYMBOL(pci_disable_device
);
2271 EXPORT_SYMBOL(pci_find_capability
);
2272 EXPORT_SYMBOL(pci_bus_find_capability
);
2273 EXPORT_SYMBOL(pci_release_regions
);
2274 EXPORT_SYMBOL(pci_request_regions
);
2275 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2276 EXPORT_SYMBOL(pci_release_region
);
2277 EXPORT_SYMBOL(pci_request_region
);
2278 EXPORT_SYMBOL(pci_request_region_exclusive
);
2279 EXPORT_SYMBOL(pci_release_selected_regions
);
2280 EXPORT_SYMBOL(pci_request_selected_regions
);
2281 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2282 EXPORT_SYMBOL(pci_set_master
);
2283 EXPORT_SYMBOL(pci_set_mwi
);
2284 EXPORT_SYMBOL(pci_try_set_mwi
);
2285 EXPORT_SYMBOL(pci_clear_mwi
);
2286 EXPORT_SYMBOL_GPL(pci_intx
);
2287 EXPORT_SYMBOL(pci_set_dma_mask
);
2288 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2289 EXPORT_SYMBOL(pci_assign_resource
);
2290 EXPORT_SYMBOL(pci_find_parent_resource
);
2291 EXPORT_SYMBOL(pci_select_bars
);
2293 EXPORT_SYMBOL(pci_set_power_state
);
2294 EXPORT_SYMBOL(pci_save_state
);
2295 EXPORT_SYMBOL(pci_restore_state
);
2296 EXPORT_SYMBOL(pci_pme_capable
);
2297 EXPORT_SYMBOL(pci_pme_active
);
2298 EXPORT_SYMBOL(pci_enable_wake
);
2299 EXPORT_SYMBOL(pci_wake_from_d3
);
2300 EXPORT_SYMBOL(pci_target_state
);
2301 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2302 EXPORT_SYMBOL(pci_back_from_sleep
);
2303 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);