drivers/pci/pci.c

   1 /*
   2  *      $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
   3  *
   4  *      PCI Bus Services, see include/linux/pci.h for further explanation.
   5  *
   6  *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  *
   9  *      Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/delay.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/module.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/string.h>
  19 #include <asm/dma.h>    /* isa_dma_bridge_buggy */
  20 #include "pci.h"
  21
  22
  23 /**
  24  * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  25  * @bus: pointer to PCI bus structure to search
  26  *
  27  * Given a PCI bus, returns the highest PCI bus number present in the set
  28  * including the given PCI bus and its list of child PCI buses.
  29  */
  30 unsigned char __devinit
  31 pci_bus_max_busnr(struct pci_bus* bus)
  32 {
  33         struct list_head *tmp;
  34         unsigned char max, n;
  35
  36         max = bus->subordinate;
  37         list_for_each(tmp, &bus->children) {
  38                 n = pci_bus_max_busnr(pci_bus_b(tmp));
  39                 if(n > max)
  40                         max = n;
  41         }
  42         return max;
  43 }
  44 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
  45
  46 #if 0
  47 /**
  48  * pci_max_busnr - returns maximum PCI bus number
  49  *
  50  * Returns the highest PCI bus number present in the system global list of
  51  * PCI buses.
  52  */
  53 unsigned char __devinit
  54 pci_max_busnr(void)
  55 {
  56         struct pci_bus *bus = NULL;
  57         unsigned char max, n;
  58
  59         max = 0;
  60         while ((bus = pci_find_next_bus(bus)) != NULL) {
  61                 n = pci_bus_max_busnr(bus);
  62                 if(n > max)
  63                         max = n;
  64         }
  65         return max;
  66 }
  67
  68 #endif  /*  0  */
  69
  70 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
  71 {
  72         u8 id;
  73         int ttl = 48;
  74
  75         while (ttl--) {
  76                 pci_bus_read_config_byte(bus, devfn, pos, &pos);
  77                 if (pos < 0x40)
  78                         break;
  79                 pos &= ~3;
  80                 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
  81                                          &id);
  82                 if (id == 0xff)
  83                         break;
  84                 if (id == cap)
  85                         return pos;
  86                 pos += PCI_CAP_LIST_NEXT;
  87         }
  88         return 0;
  89 }
  90
  91 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
  92 {
  93         return __pci_find_next_cap(dev->bus, dev->devfn,
  94                                    pos + PCI_CAP_LIST_NEXT, cap);
  95 }
  96 EXPORT_SYMBOL_GPL(pci_find_next_capability);
  97
  98 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
  99 {
 100         u16 status;
 101         u8 pos;
 102
 103         pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
 104         if (!(status & PCI_STATUS_CAP_LIST))
 105                 return 0;
 106
 107         switch (hdr_type) {
 108         case PCI_HEADER_TYPE_NORMAL:
 109         case PCI_HEADER_TYPE_BRIDGE:
 110                 pos = PCI_CAPABILITY_LIST;
 111                 break;
 112         case PCI_HEADER_TYPE_CARDBUS:
 113                 pos = PCI_CB_CAPABILITY_LIST;
 114                 break;
 115         default:
 116                 return 0;
 117         }
 118         return __pci_find_next_cap(bus, devfn, pos, cap);
 119 }
 120
 121 /**
 122  * pci_find_capability - query for devices' capabilities
 123  * @dev: PCI device to query
 124  * @cap: capability code
 125  *
 126  * Tell if a device supports a given PCI capability.
 127  * Returns the address of the requested capability structure within the
 128  * device's PCI configuration space or 0 in case the device does not
 129  * support it.  Possible values for @cap:
 130  *
 131  *  %PCI_CAP_ID_PM           Power Management
 132  *  %PCI_CAP_ID_AGP          Accelerated Graphics Port
 133  *  %PCI_CAP_ID_VPD          Vital Product Data
 134  *  %PCI_CAP_ID_SLOTID       Slot Identification
 135  *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
 136  *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap
 137  *  %PCI_CAP_ID_PCIX         PCI-X
 138  *  %PCI_CAP_ID_EXP          PCI Express
 139  */
 140 int pci_find_capability(struct pci_dev *dev, int cap)
 141 {
 142         return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
 143 }
 144
 145 /**
 146  * pci_bus_find_capability - query for devices' capabilities
 147  * @bus:   the PCI bus to query
 148  * @devfn: PCI device to query
 149  * @cap:   capability code
 150  *
 151  * Like pci_find_capability() but works for pci devices that do not have a
 152  * pci_dev structure set up yet.
 153  *
 154  * Returns the address of the requested capability structure within the
 155  * device's PCI configuration space or 0 in case the device does not
 156  * support it.
 157  */
 158 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
 159 {
 160         u8 hdr_type;
 161
 162         pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
 163
 164         return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
 165 }
 166
 167 #if 0
 168 /**
 169  * pci_find_ext_capability - Find an extended capability
 170  * @dev: PCI device to query
 171  * @cap: capability code
 172  *
 173  * Returns the address of the requested extended capability structure
 174  * within the device's PCI configuration space or 0 if the device does
 175  * not support it.  Possible values for @cap:
 176  *
 177  *  %PCI_EXT_CAP_ID_ERR         Advanced Error Reporting
 178  *  %PCI_EXT_CAP_ID_VC          Virtual Channel
 179  *  %PCI_EXT_CAP_ID_DSN         Device Serial Number
 180  *  %PCI_EXT_CAP_ID_PWR         Power Budgeting
 181  */
 182 int pci_find_ext_capability(struct pci_dev *dev, int cap)
 183 {
 184         u32 header;
 185         int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
 186         int pos = 0x100;
 187
 188         if (dev->cfg_size <= 256)
 189                 return 0;
 190
 191         if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
 192                 return 0;
 193
 194         /*
 195          * If we have no capabilities, this is indicated by cap ID,
 196          * cap version and next pointer all being 0.
 197          */
 198         if (header == 0)
 199                 return 0;
 200
 201         while (ttl-- > 0) {
 202                 if (PCI_EXT_CAP_ID(header) == cap)
 203                         return pos;
 204
 205                 pos = PCI_EXT_CAP_NEXT(header);
 206                 if (pos < 0x100)
 207                         break;
 208
 209                 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
 210                         break;
 211         }
 212
 213         return 0;
 214 }
 215 #endif  /*  0  */
 216
 217 /**
 218  * pci_find_parent_resource - return resource region of parent bus of given region
 219  * @dev: PCI device structure contains resources to be searched
 220  * @res: child resource record for which parent is sought
 221  *
 222  *  For given resource region of given device, return the resource
 223  *  region of parent bus the given region is contained in or where
 224  *  it should be allocated from.
 225  */
 226 struct resource *
 227 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
 228 {
 229         const struct pci_bus *bus = dev->bus;
 230         int i;
 231         struct resource *best = NULL;
 232
 233         for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
 234                 struct resource *r = bus->resource[i];
 235                 if (!r)
 236                         continue;
 237                 if (res->start && !(res->start >= r->start && res->end <= r->end))
 238                         continue;       /* Not contained */
 239                 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
 240                         continue;       /* Wrong type */
 241                 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
 242                         return r;       /* Exact match */
 243                 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
 244                         best = r;       /* Approximating prefetchable by non-prefetchable */
 245         }
 246         return best;
 247 }
 248
 249 /**
 250  * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
 251  * @dev: PCI device to have its BARs restored
 252  *
 253  * Restore the BAR values for a given device, so as to make it
 254  * accessible by its driver.
 255  */
 256 void
 257 pci_restore_bars(struct pci_dev *dev)
 258 {
 259         int i, numres;
 260
 261         switch (dev->hdr_type) {
 262         case PCI_HEADER_TYPE_NORMAL:
 263                 numres = 6;
 264                 break;
 265         case PCI_HEADER_TYPE_BRIDGE:
 266                 numres = 2;
 267                 break;
 268         case PCI_HEADER_TYPE_CARDBUS:
 269                 numres = 1;
 270                 break;
 271         default:
 272                 /* Should never get here, but just in case... */
 273                 return;
 274         }
 275
 276         for (i = 0; i < numres; i ++)
 277                 pci_update_resource(dev, &dev->resource[i], i);
 278 }
 279
 280 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
 281
 282 /**
 283  * pci_set_power_state - Set the power state of a PCI device
 284  * @dev: PCI device to be suspended
 285  * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
 286  *
 287  * Transition a device to a new power state, using the Power Management
 288  * Capabilities in the device's config space.
 289  *
 290  * RETURN VALUE:
 291  * -EINVAL if trying to enter a lower state than we're already in.
 292  * 0 if we're already in the requested state.
 293  * -EIO if device does not support PCI PM.
 294  * 0 if we can successfully change the power state.
 295  */
 296 int
 297 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
 298 {
 299         int pm, need_restore = 0;
 300         u16 pmcsr, pmc;
 301
 302         /* bound the state we're entering */
 303         if (state > PCI_D3hot)
 304                 state = PCI_D3hot;
 305
 306         /* Validate current state:
 307          * Can enter D0 from any state, but if we can only go deeper
 308          * to sleep if we're already in a low power state
 309          */
 310         if (state != PCI_D0 && dev->current_state > state)
 311                 return -EINVAL;
 312         else if (dev->current_state == state)
 313                 return 0;        /* we're already there */
 314
 315         /* find PCI PM capability in list */
 316         pm = pci_find_capability(dev, PCI_CAP_ID_PM);
 317
 318         /* abort if the device doesn't support PM capabilities */
 319         if (!pm)
 320                 return -EIO;
 321
 322         pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
 323         if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
 324                 printk(KERN_DEBUG
 325                        "PCI: %s has unsupported PM cap regs version (%u)\n",
 326                        pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
 327                 return -EIO;
 328         }
 329
 330         /* check if this device supports the desired state */
 331         if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
 332                 return -EIO;
 333         else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
 334                 return -EIO;
 335
 336         pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
 337
 338         /* If we're (effectively) in D3, force entire word to 0.
 339          * This doesn't affect PME_Status, disables PME_En, and
 340          * sets PowerState to 0.
 341          */
 342         switch (dev->current_state) {
 343         case PCI_D0:
 344         case PCI_D1:
 345         case PCI_D2:
 346                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
 347                 pmcsr |= state;
 348                 break;
 349         case PCI_UNKNOWN: /* Boot-up */
 350                 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
 351                  && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
 352                         need_restore = 1;
 353                 /* Fall-through: force to D0 */
 354         default:
 355                 pmcsr = 0;
 356                 break;
 357         }
 358
 359         /* enter specified state */
 360         pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
 361
 362         /* Mandatory power management transition delays */
 363         /* see PCI PM 1.1 5.6.1 table 18 */
 364         if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
 365                 msleep(10);
 366         else if (state == PCI_D2 || dev->current_state == PCI_D2)
 367                 udelay(200);
 368
 369         /*
 370          * Give firmware a chance to be called, such as ACPI _PRx, _PSx
 371          * Firmware method after natice method ?
 372          */
 373         if (platform_pci_set_power_state)
 374                 platform_pci_set_power_state(dev, state);
 375
 376         dev->current_state = state;
 377
 378         /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
 379          * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
 380          * from D3hot to D0 _may_ perform an internal reset, thereby
 381          * going to "D0 Uninitialized" rather than "D0 Initialized".
 382          * For example, at least some versions of the 3c905B and the
 383          * 3c556B exhibit this behaviour.
 384          *
 385          * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
 386          * devices in a D3hot state at boot.  Consequently, we need to
 387          * restore at least the BARs so that the device will be
 388          * accessible to its driver.
 389          */
 390         if (need_restore)
 391                 pci_restore_bars(dev);
 392
 393         return 0;
 394 }
 395
 396 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
 397
 398 /**
 399  * pci_choose_state - Choose the power state of a PCI device
 400  * @dev: PCI device to be suspended
 401  * @state: target sleep state for the whole system. This is the value
 402  *      that is passed to suspend() function.
 403  *
 404  * Returns PCI power state suitable for given device and given system
 405  * message.
 406  */
 407
 408 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
 409 {
 410         int ret;
 411
 412         if (!pci_find_capability(dev, PCI_CAP_ID_PM))
 413                 return PCI_D0;
 414
 415         if (platform_pci_choose_state) {
 416                 ret = platform_pci_choose_state(dev, state);
 417                 if (ret >= 0)
 418                         state.event = ret;
 419         }
 420
 421         switch (state.event) {
 422         case PM_EVENT_ON:
 423                 return PCI_D0;
 424         case PM_EVENT_FREEZE:
 425         case PM_EVENT_SUSPEND:
 426                 return PCI_D3hot;
 427         default:
 428                 printk("They asked me for state %d\n", state.event);
 429                 BUG();
 430         }
 431         return PCI_D0;
 432 }
 433
 434 EXPORT_SYMBOL(pci_choose_state);
 435
 436 /**
 437  * pci_save_state - save the PCI configuration space of a device before suspending
 438  * @dev: - PCI device that we're dealing with
 439  */
 440 int
 441 pci_save_state(struct pci_dev *dev)
 442 {
 443         int i;
 444         /* XXX: 100% dword access ok here? */
 445         for (i = 0; i < 16; i++)
 446                 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
 447         if ((i = pci_save_msi_state(dev)) != 0)
 448                 return i;
 449         if ((i = pci_save_msix_state(dev)) != 0)
 450                 return i;
 451         return 0;
 452 }
 453
 454 /**
 455  * pci_restore_state - Restore the saved state of a PCI device
 456  * @dev: - PCI device that we're dealing with
 457  */
 458 int
 459 pci_restore_state(struct pci_dev *dev)
 460 {
 461         int i;
 462
 463         for (i = 0; i < 16; i++)
 464                 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
 465         pci_restore_msi_state(dev);
 466         pci_restore_msix_state(dev);
 467         return 0;
 468 }
 469
 470 /**
 471  * pci_enable_device_bars - Initialize some of a device for use
 472  * @dev: PCI device to be initialized
 473  * @bars: bitmask of BAR's that must be configured
 474  *
 475  *  Initialize device before it's used by a driver. Ask low-level code
 476  *  to enable selected I/O and memory resources. Wake up the device if it
 477  *  was suspended. Beware, this function can fail.
 478  */
 479
 480 int
 481 pci_enable_device_bars(struct pci_dev *dev, int bars)
 482 {
 483         int err;
 484
 485         err = pci_set_power_state(dev, PCI_D0);
 486         if (err < 0 && err != -EIO)
 487                 return err;
 488         err = pcibios_enable_device(dev, bars);
 489         if (err < 0)
 490                 return err;
 491         return 0;
 492 }
 493
 494 /**
 495  * pci_enable_device - Initialize device before it's used by a driver.
 496  * @dev: PCI device to be initialized
 497  *
 498  *  Initialize device before it's used by a driver. Ask low-level code
 499  *  to enable I/O and memory. Wake up the device if it was suspended.
 500  *  Beware, this function can fail.
 501  */
 502 int
 503 pci_enable_device(struct pci_dev *dev)
 504 {
 505         int err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
 506         if (err)
 507                 return err;
 508         pci_fixup_device(pci_fixup_enable, dev);
 509         dev->is_enabled = 1;
 510         return 0;
 511 }
 512
 513 /**
 514  * pcibios_disable_device - disable arch specific PCI resources for device dev
 515  * @dev: the PCI device to disable
 516  *
 517  * Disables architecture specific PCI resources for the device. This
 518  * is the default implementation. Architecture implementations can
 519  * override this.
 520  */
 521 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
 522
 523 /**
 524  * pci_disable_device - Disable PCI device after use
 525  * @dev: PCI device to be disabled
 526  *
 527  * Signal to the system that the PCI device is not in use by the system
 528  * anymore.  This only involves disabling PCI bus-mastering, if active.
 529  */
 530 void
 531 pci_disable_device(struct pci_dev *dev)
 532 {
 533         u16 pci_command;
 534
 535         pci_read_config_word(dev, PCI_COMMAND, &pci_command);
 536         if (pci_command & PCI_COMMAND_MASTER) {
 537                 pci_command &= ~PCI_COMMAND_MASTER;
 538                 pci_write_config_word(dev, PCI_COMMAND, pci_command);
 539         }
 540         dev->is_busmaster = 0;
 541
 542         pcibios_disable_device(dev);
 543         dev->is_enabled = 0;
 544 }
 545
 546 /**
 547  * pci_enable_wake - enable device to generate PME# when suspended
 548  * @dev: - PCI device to operate on
 549  * @state: - Current state of device.
 550  * @enable: - Flag to enable or disable generation
 551  *
 552  * Set the bits in the device's PM Capabilities to generate PME# when
 553  * the system is suspended.
 554  *
 555  * -EIO is returned if device doesn't have PM Capabilities.
 556  * -EINVAL is returned if device supports it, but can't generate wake events.
 557  * 0 if operation is successful.
 558  *
 559  */
 560 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
 561 {
 562         int pm;
 563         u16 value;
 564
 565         /* find PCI PM capability in list */
 566         pm = pci_find_capability(dev, PCI_CAP_ID_PM);
 567
 568         /* If device doesn't support PM Capabilities, but request is to disable
 569          * wake events, it's a nop; otherwise fail */
 570         if (!pm)
 571                 return enable ? -EIO : 0;
 572
 573         /* Check device's ability to generate PME# */
 574         pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
 575
 576         value &= PCI_PM_CAP_PME_MASK;
 577         value >>= ffs(PCI_PM_CAP_PME_MASK) - 1;   /* First bit of mask */
 578
 579         /* Check if it can generate PME# from requested state. */
 580         if (!value || !(value & (1 << state)))
 581                 return enable ? -EINVAL : 0;
 582
 583         pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
 584
 585         /* Clear PME_Status by writing 1 to it and enable PME# */
 586         value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
 587
 588         if (!enable)
 589                 value &= ~PCI_PM_CTRL_PME_ENABLE;
 590
 591         pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
 592
 593         return 0;
 594 }
 595
 596 int
 597 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
 598 {
 599         u8 pin;
 600
 601         pin = dev->pin;
 602         if (!pin)
 603                 return -1;
 604         pin--;
 605         while (dev->bus->self) {
 606                 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
 607                 dev = dev->bus->self;
 608         }
 609         *bridge = dev;
 610         return pin;
 611 }
 612
 613 /**
 614  *      pci_release_region - Release a PCI bar
 615  *      @pdev: PCI device whose resources were previously reserved by pci_request_region
 616  *      @bar: BAR to release
 617  *
 618  *      Releases the PCI I/O and memory resources previously reserved by a
 619  *      successful call to pci_request_region.  Call this function only
 620  *      after all use of the PCI regions has ceased.
 621  */
 622 void pci_release_region(struct pci_dev *pdev, int bar)
 623 {
 624         if (pci_resource_len(pdev, bar) == 0)
 625                 return;
 626         if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
 627                 release_region(pci_resource_start(pdev, bar),
 628                                 pci_resource_len(pdev, bar));
 629         else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
 630                 release_mem_region(pci_resource_start(pdev, bar),
 631                                 pci_resource_len(pdev, bar));
 632 }
 633
 634 /**
 635  *      pci_request_region - Reserved PCI I/O and memory resource
 636  *      @pdev: PCI device whose resources are to be reserved
 637  *      @bar: BAR to be reserved
 638  *      @res_name: Name to be associated with resource.
 639  *
 640  *      Mark the PCI region associated with PCI device @pdev BR @bar as
 641  *      being reserved by owner @res_name.  Do not access any
 642  *      address inside the PCI regions unless this call returns
 643  *      successfully.
 644  *
 645  *      Returns 0 on success, or %EBUSY on error.  A warning
 646  *      message is also printed on failure.
 647  */
 648 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
 649 {
 650         if (pci_resource_len(pdev, bar) == 0)
 651                 return 0;
 652
 653         if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
 654                 if (!request_region(pci_resource_start(pdev, bar),
 655                             pci_resource_len(pdev, bar), res_name))
 656                         goto err_out;
 657         }
 658         else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 659                 if (!request_mem_region(pci_resource_start(pdev, bar),
 660                                         pci_resource_len(pdev, bar), res_name))
 661                         goto err_out;
 662         }
 663
 664         return 0;
 665
 666 err_out:
 667         printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
 668                 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
 669                 bar + 1, /* PCI BAR # */
 670                 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
 671                 pci_name(pdev));
 672         return -EBUSY;
 673 }
 674
 675
 676 /**
 677  *      pci_release_regions - Release reserved PCI I/O and memory resources
 678  *      @pdev: PCI device whose resources were previously reserved by pci_request_regions
 679  *
 680  *      Releases all PCI I/O and memory resources previously reserved by a
 681  *      successful call to pci_request_regions.  Call this function only
 682  *      after all use of the PCI regions has ceased.
 683  */
 684
 685 void pci_release_regions(struct pci_dev *pdev)
 686 {
 687         int i;
 688
 689         for (i = 0; i < 6; i++)
 690                 pci_release_region(pdev, i);
 691 }
 692
 693 /**
 694  *      pci_request_regions - Reserved PCI I/O and memory resources
 695  *      @pdev: PCI device whose resources are to be reserved
 696  *      @res_name: Name to be associated with resource.
 697  *
 698  *      Mark all PCI regions associated with PCI device @pdev as
 699  *      being reserved by owner @res_name.  Do not access any
 700  *      address inside the PCI regions unless this call returns
 701  *      successfully.
 702  *
 703  *      Returns 0 on success, or %EBUSY on error.  A warning
 704  *      message is also printed on failure.
 705  */
 706 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
 707 {
 708         int i;
 709
 710         for (i = 0; i < 6; i++)
 711                 if(pci_request_region(pdev, i, res_name))
 712                         goto err_out;
 713         return 0;
 714
 715 err_out:
 716         while(--i >= 0)
 717                 pci_release_region(pdev, i);
 718
 719         return -EBUSY;
 720 }
 721
 722 /**
 723  * pci_set_master - enables bus-mastering for device dev
 724  * @dev: the PCI device to enable
 725  *
 726  * Enables bus-mastering on the device and calls pcibios_set_master()
 727  * to do the needed arch specific settings.
 728  */
 729 void
 730 pci_set_master(struct pci_dev *dev)
 731 {
 732         u16 cmd;
 733
 734         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 735         if (! (cmd & PCI_COMMAND_MASTER)) {
 736                 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
 737                 cmd |= PCI_COMMAND_MASTER;
 738                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 739         }
 740         dev->is_busmaster = 1;
 741         pcibios_set_master(dev);
 742 }
 743
 744 #ifndef HAVE_ARCH_PCI_MWI
 745 /* This can be overridden by arch code. */
 746 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
 747
 748 /**
 749  * pci_generic_prep_mwi - helper function for pci_set_mwi
 750  * @dev: the PCI device for which MWI is enabled
 751  *
 752  * Helper function for generic implementation of pcibios_prep_mwi
 753  * function.  Originally copied from drivers/net/acenic.c.
 754  * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
 755  *
 756  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 757  */
 758 static int
 759 pci_generic_prep_mwi(struct pci_dev *dev)
 760 {
 761         u8 cacheline_size;
 762
 763         if (!pci_cache_line_size)
 764                 return -EINVAL;         /* The system doesn't support MWI. */
 765
 766         /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
 767            equal to or multiple of the right value. */
 768         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
 769         if (cacheline_size >= pci_cache_line_size &&
 770             (cacheline_size % pci_cache_line_size) == 0)
 771                 return 0;
 772
 773         /* Write the correct value. */
 774         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
 775         /* Read it back. */
 776         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
 777         if (cacheline_size == pci_cache_line_size)
 778                 return 0;
 779
 780         printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
 781                "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
 782
 783         return -EINVAL;
 784 }
 785 #endif /* !HAVE_ARCH_PCI_MWI */
 786
 787 /**
 788  * pci_set_mwi - enables memory-write-invalidate PCI transaction
 789  * @dev: the PCI device for which MWI is enabled
 790  *
 791  * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
 792  * and then calls @pcibios_set_mwi to do the needed arch specific
 793  * operations or a generic mwi-prep function.
 794  *
 795  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 796  */
 797 int
 798 pci_set_mwi(struct pci_dev *dev)
 799 {
 800         int rc;
 801         u16 cmd;
 802
 803 #ifdef HAVE_ARCH_PCI_MWI
 804         rc = pcibios_prep_mwi(dev);
 805 #else
 806         rc = pci_generic_prep_mwi(dev);
 807 #endif
 808
 809         if (rc)
 810                 return rc;
 811
 812         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 813         if (! (cmd & PCI_COMMAND_INVALIDATE)) {
 814                 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
 815                 cmd |= PCI_COMMAND_INVALIDATE;
 816                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 817         }
 818
 819         return 0;
 820 }
 821
 822 /**
 823  * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
 824  * @dev: the PCI device to disable
 825  *
 826  * Disables PCI Memory-Write-Invalidate transaction on the device
 827  */
 828 void
 829 pci_clear_mwi(struct pci_dev *dev)
 830 {
 831         u16 cmd;
 832
 833         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 834         if (cmd & PCI_COMMAND_INVALIDATE) {
 835                 cmd &= ~PCI_COMMAND_INVALIDATE;
 836                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 837         }
 838 }
 839
 840 /**
 841  * pci_intx - enables/disables PCI INTx for device dev
 842  * @pdev: the PCI device to operate on
 843  * @enable: boolean: whether to enable or disable PCI INTx
 844  *
 845  * Enables/disables PCI INTx for device dev
 846  */
 847 void
 848 pci_intx(struct pci_dev *pdev, int enable)
 849 {
 850         u16 pci_command, new;
 851
 852         pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
 853
 854         if (enable) {
 855                 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
 856         } else {
 857                 new = pci_command | PCI_COMMAND_INTX_DISABLE;
 858         }
 859
 860         if (new != pci_command) {
 861                 pci_write_config_word(pdev, PCI_COMMAND, new);
 862         }
 863 }
 864
 865 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
 866 /*
 867  * These can be overridden by arch-specific implementations
 868  */
 869 int
 870 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
 871 {
 872         if (!pci_dma_supported(dev, mask))
 873                 return -EIO;
 874
 875         dev->dma_mask = mask;
 876
 877         return 0;
 878 }
 879
 880 int
 881 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
 882 {
 883         if (!pci_dma_supported(dev, mask))
 884                 return -EIO;
 885
 886         dev->dev.coherent_dma_mask = mask;
 887
 888         return 0;
 889 }
 890 #endif
 891
 892 static int __devinit pci_init(void)
 893 {
 894         struct pci_dev *dev = NULL;
 895
 896         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
 897                 pci_fixup_device(pci_fixup_final, dev);
 898         }
 899         return 0;
 900 }
 901
 902 static int __devinit pci_setup(char *str)
 903 {
 904         while (str) {
 905                 char *k = strchr(str, ',');
 906                 if (k)
 907                         *k++ = 0;
 908                 if (*str && (str = pcibios_setup(str)) && *str) {
 909                         if (!strcmp(str, "nomsi")) {
 910                                 pci_no_msi();
 911                         } else {
 912                                 printk(KERN_ERR "PCI: Unknown option `%s'\n",
 913                                                 str);
 914                         }
 915                 }
 916                 str = k;
 917         }
 918         return 1;
 919 }
 920
 921 device_initcall(pci_init);
 922
 923 __setup("pci=", pci_setup);
 924
 925 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 926 /* FIXME: Some boxes have multiple ISA bridges! */
 927 struct pci_dev *isa_bridge;
 928 EXPORT_SYMBOL(isa_bridge);
 929 #endif
 930
 931 EXPORT_SYMBOL_GPL(pci_restore_bars);
 932 EXPORT_SYMBOL(pci_enable_device_bars);
 933 EXPORT_SYMBOL(pci_enable_device);
 934 EXPORT_SYMBOL(pci_disable_device);
 935 EXPORT_SYMBOL(pci_find_capability);
 936 EXPORT_SYMBOL(pci_bus_find_capability);
 937 EXPORT_SYMBOL(pci_release_regions);
 938 EXPORT_SYMBOL(pci_request_regions);
 939 EXPORT_SYMBOL(pci_release_region);
 940 EXPORT_SYMBOL(pci_request_region);
 941 EXPORT_SYMBOL(pci_set_master);
 942 EXPORT_SYMBOL(pci_set_mwi);
 943 EXPORT_SYMBOL(pci_clear_mwi);
 944 EXPORT_SYMBOL_GPL(pci_intx);
 945 EXPORT_SYMBOL(pci_set_dma_mask);
 946 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
 947 EXPORT_SYMBOL(pci_assign_resource);
 948 EXPORT_SYMBOL(pci_find_parent_resource);
 949
 950 EXPORT_SYMBOL(pci_set_power_state);
 951 EXPORT_SYMBOL(pci_save_state);
 952 EXPORT_SYMBOL(pci_restore_state);
 953 EXPORT_SYMBOL(pci_enable_wake);
 954
 955 /* Quirk info */
 956
 957 EXPORT_SYMBOL(isa_dma_bridge_buggy);
 958 EXPORT_SYMBOL(pci_pci_problems);