2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names
[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names
);
33 int isa_dma_bridge_buggy
;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
37 EXPORT_SYMBOL(pci_pci_problems
);
39 unsigned int pci_pm_d3_delay
;
41 static void pci_pme_list_scan(struct work_struct
*work
);
43 static LIST_HEAD(pci_pme_list
);
44 static DEFINE_MUTEX(pci_pme_list_mutex
);
45 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
47 struct pci_pme_device
{
48 struct list_head list
;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
56 unsigned int delay
= dev
->d3_delay
;
58 if (delay
< pci_pm_d3_delay
)
59 delay
= pci_pm_d3_delay
;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported
= 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
72 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
78 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
81 * The default CLS is used if arch didn't set CLS explicitly and not
82 * all pci devices agree on the same value. Arch can override either
83 * the dfl or actual value as it sees fit. Don't forget this is
84 * measured in 32-bit words, not bytes.
86 u8 pci_dfl_cache_line_size __devinitdata
= L1_CACHE_BYTES
>> 2;
87 u8 pci_cache_line_size
;
90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
91 * @bus: pointer to PCI bus structure to search
93 * Given a PCI bus, returns the highest PCI bus number present in the set
94 * including the given PCI bus and its list of child PCI buses.
96 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
98 struct list_head
*tmp
;
101 max
= bus
->subordinate
;
102 list_for_each(tmp
, &bus
->children
) {
103 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
109 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
111 #ifdef CONFIG_HAS_IOMEM
112 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
115 * Make sure the BAR is actually a memory resource, not an IO resource
117 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
121 return ioremap_nocache(pci_resource_start(pdev
, bar
),
122 pci_resource_len(pdev
, bar
));
124 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
129 * pci_max_busnr - returns maximum PCI bus number
131 * Returns the highest PCI bus number present in the system global list of
134 unsigned char __devinit
137 struct pci_bus
*bus
= NULL
;
138 unsigned char max
, n
;
141 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
142 n
= pci_bus_max_busnr(bus
);
151 #define PCI_FIND_CAP_TTL 48
153 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
154 u8 pos
, int cap
, int *ttl
)
159 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
163 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
169 pos
+= PCI_CAP_LIST_NEXT
;
174 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
177 int ttl
= PCI_FIND_CAP_TTL
;
179 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
182 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
184 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
185 pos
+ PCI_CAP_LIST_NEXT
, cap
);
187 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
189 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
190 unsigned int devfn
, u8 hdr_type
)
194 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
195 if (!(status
& PCI_STATUS_CAP_LIST
))
199 case PCI_HEADER_TYPE_NORMAL
:
200 case PCI_HEADER_TYPE_BRIDGE
:
201 return PCI_CAPABILITY_LIST
;
202 case PCI_HEADER_TYPE_CARDBUS
:
203 return PCI_CB_CAPABILITY_LIST
;
212 * pci_find_capability - query for devices' capabilities
213 * @dev: PCI device to query
214 * @cap: capability code
216 * Tell if a device supports a given PCI capability.
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it. Possible values for @cap:
221 * %PCI_CAP_ID_PM Power Management
222 * %PCI_CAP_ID_AGP Accelerated Graphics Port
223 * %PCI_CAP_ID_VPD Vital Product Data
224 * %PCI_CAP_ID_SLOTID Slot Identification
225 * %PCI_CAP_ID_MSI Message Signalled Interrupts
226 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
227 * %PCI_CAP_ID_PCIX PCI-X
228 * %PCI_CAP_ID_EXP PCI Express
230 int pci_find_capability(struct pci_dev
*dev
, int cap
)
234 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
236 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
242 * pci_bus_find_capability - query for devices' capabilities
243 * @bus: the PCI bus to query
244 * @devfn: PCI device to query
245 * @cap: capability code
247 * Like pci_find_capability() but works for pci devices that do not have a
248 * pci_dev structure set up yet.
250 * Returns the address of the requested capability structure within the
251 * device's PCI configuration space or 0 in case the device does not
254 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
259 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
261 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
263 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
269 * pci_find_ext_capability - Find an extended capability
270 * @dev: PCI device to query
271 * @cap: capability code
273 * Returns the address of the requested extended capability structure
274 * within the device's PCI configuration space or 0 if the device does
275 * not support it. Possible values for @cap:
277 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
278 * %PCI_EXT_CAP_ID_VC Virtual Channel
279 * %PCI_EXT_CAP_ID_DSN Device Serial Number
280 * %PCI_EXT_CAP_ID_PWR Power Budgeting
282 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
286 int pos
= PCI_CFG_SPACE_SIZE
;
288 /* minimum 8 bytes per capability */
289 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
291 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
294 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
298 * If we have no capabilities, this is indicated by cap ID,
299 * cap version and next pointer all being 0.
305 if (PCI_EXT_CAP_ID(header
) == cap
)
308 pos
= PCI_EXT_CAP_NEXT(header
);
309 if (pos
< PCI_CFG_SPACE_SIZE
)
312 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
318 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
321 * pci_bus_find_ext_capability - find an extended capability
322 * @bus: the PCI bus to query
323 * @devfn: PCI device to query
324 * @cap: capability code
326 * Like pci_find_ext_capability() but works for pci devices that do not have a
327 * pci_dev structure set up yet.
329 * Returns the address of the requested capability structure within the
330 * device's PCI configuration space or 0 in case the device does not
333 int pci_bus_find_ext_capability(struct pci_bus
*bus
, unsigned int devfn
,
338 int pos
= PCI_CFG_SPACE_SIZE
;
340 /* minimum 8 bytes per capability */
341 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
343 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
345 if (header
== 0xffffffff || header
== 0)
349 if (PCI_EXT_CAP_ID(header
) == cap
)
352 pos
= PCI_EXT_CAP_NEXT(header
);
353 if (pos
< PCI_CFG_SPACE_SIZE
)
356 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
363 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
365 int rc
, ttl
= PCI_FIND_CAP_TTL
;
368 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
369 mask
= HT_3BIT_CAP_MASK
;
371 mask
= HT_5BIT_CAP_MASK
;
373 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
374 PCI_CAP_ID_HT
, &ttl
);
376 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
377 if (rc
!= PCIBIOS_SUCCESSFUL
)
380 if ((cap
& mask
) == ht_cap
)
383 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
384 pos
+ PCI_CAP_LIST_NEXT
,
385 PCI_CAP_ID_HT
, &ttl
);
391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
392 * @dev: PCI device to query
393 * @pos: Position from which to continue searching
394 * @ht_cap: Hypertransport capability code
396 * To be used in conjunction with pci_find_ht_capability() to search for
397 * all capabilities matching @ht_cap. @pos should always be a value returned
398 * from pci_find_ht_capability().
400 * NB. To be 100% safe against broken PCI devices, the caller should take
401 * steps to avoid an infinite loop.
403 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
405 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
407 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
410 * pci_find_ht_capability - query a device's Hypertransport capabilities
411 * @dev: PCI device to query
412 * @ht_cap: Hypertransport capability code
414 * Tell if a device supports a given Hypertransport capability.
415 * Returns an address within the device's PCI configuration space
416 * or 0 in case the device does not support the request capability.
417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
418 * which has a Hypertransport capability matching @ht_cap.
420 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
424 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
426 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
430 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
433 * pci_find_parent_resource - return resource region of parent bus of given region
434 * @dev: PCI device structure contains resources to be searched
435 * @res: child resource record for which parent is sought
437 * For given resource region of given device, return the resource
438 * region of parent bus the given region is contained in or where
439 * it should be allocated from.
442 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
444 const struct pci_bus
*bus
= dev
->bus
;
446 struct resource
*best
= NULL
, *r
;
448 pci_bus_for_each_resource(bus
, r
, i
) {
451 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
452 continue; /* Not contained */
453 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
454 continue; /* Wrong type */
455 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
456 return r
; /* Exact match */
457 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
458 if (r
->flags
& IORESOURCE_PREFETCH
)
460 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
469 * @dev: PCI device to have its BARs restored
471 * Restore the BAR values for a given device, so as to make it
472 * accessible by its driver.
475 pci_restore_bars(struct pci_dev
*dev
)
479 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
480 pci_update_resource(dev
, i
);
483 static struct pci_platform_pm_ops
*pci_platform_pm
;
485 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
487 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
488 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
490 pci_platform_pm
= ops
;
494 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
496 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
499 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
502 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
505 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
507 return pci_platform_pm
?
508 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
511 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
513 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
516 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
518 return pci_platform_pm
?
519 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
522 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
524 return pci_platform_pm
?
525 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
531 * @dev: PCI device to handle.
532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
535 * -EINVAL if the requested state is invalid.
536 * -EIO if device does not support PCI PM or its PM capabilities register has a
537 * wrong version, or device doesn't support the requested state.
538 * 0 if device already is in the requested state.
539 * 0 if device's power state has been successfully changed.
541 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
544 bool need_restore
= false;
546 /* Check if we're already there */
547 if (dev
->current_state
== state
)
553 if (state
< PCI_D0
|| state
> PCI_D3hot
)
556 /* Validate current state:
557 * Can enter D0 from any state, but if we can only go deeper
558 * to sleep if we're already in a low power state
560 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
561 && dev
->current_state
> state
) {
562 dev_err(&dev
->dev
, "invalid power transition "
563 "(from state %d to %d)\n", dev
->current_state
, state
);
567 /* check if this device supports the desired state */
568 if ((state
== PCI_D1
&& !dev
->d1_support
)
569 || (state
== PCI_D2
&& !dev
->d2_support
))
572 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
574 /* If we're (effectively) in D3, force entire word to 0.
575 * This doesn't affect PME_Status, disables PME_En, and
576 * sets PowerState to 0.
578 switch (dev
->current_state
) {
582 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
587 case PCI_UNKNOWN
: /* Boot-up */
588 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
589 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
591 /* Fall-through: force to D0 */
597 /* enter specified state */
598 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
600 /* Mandatory power management transition delays */
601 /* see PCI PM 1.1 5.6.1 table 18 */
602 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
603 pci_dev_d3_sleep(dev
);
604 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
605 udelay(PCI_PM_D2_DELAY
);
607 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
608 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
609 if (dev
->current_state
!= state
&& printk_ratelimit())
610 dev_info(&dev
->dev
, "Refused to change power state, "
611 "currently in D%d\n", dev
->current_state
);
613 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
614 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
615 * from D3hot to D0 _may_ perform an internal reset, thereby
616 * going to "D0 Uninitialized" rather than "D0 Initialized".
617 * For example, at least some versions of the 3c905B and the
618 * 3c556B exhibit this behaviour.
620 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
621 * devices in a D3hot state at boot. Consequently, we need to
622 * restore at least the BARs so that the device will be
623 * accessible to its driver.
626 pci_restore_bars(dev
);
629 pcie_aspm_pm_state_change(dev
->bus
->self
);
635 * pci_update_current_state - Read PCI power state of given device from its
636 * PCI PM registers and cache it
637 * @dev: PCI device to handle.
638 * @state: State to cache in case the device doesn't have the PM capability
640 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
645 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
646 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
648 dev
->current_state
= state
;
653 * pci_platform_power_transition - Use platform to change device power state
654 * @dev: PCI device to handle.
655 * @state: State to put the device into.
657 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
661 if (platform_pci_power_manageable(dev
)) {
662 error
= platform_pci_set_power_state(dev
, state
);
664 pci_update_current_state(dev
, state
);
667 /* Fall back to PCI_D0 if native PM is not supported */
669 dev
->current_state
= PCI_D0
;
676 * __pci_start_power_transition - Start power transition of a PCI device
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
680 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
683 pci_platform_power_transition(dev
, PCI_D0
);
687 * __pci_complete_power_transition - Complete power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
691 * This function should not be called directly by device drivers.
693 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
695 return state
>= PCI_D0
?
696 pci_platform_power_transition(dev
, state
) : -EINVAL
;
698 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
701 * pci_set_power_state - Set the power state of a PCI device
702 * @dev: PCI device to handle.
703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
705 * Transition a device to a new power state, using the platform firmware and/or
706 * the device's PCI PM registers.
709 * -EINVAL if the requested state is invalid.
710 * -EIO if device does not support PCI PM or its PM capabilities register has a
711 * wrong version, or device doesn't support the requested state.
712 * 0 if device already is in the requested state.
713 * 0 if device's power state has been successfully changed.
715 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
719 /* bound the state we're entering */
720 if (state
> PCI_D3hot
)
722 else if (state
< PCI_D0
)
724 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
726 * If the device or the parent bridge do not support PCI PM,
727 * ignore the request if we're doing anything other than putting
728 * it into D0 (which would only happen on boot).
732 __pci_start_power_transition(dev
, state
);
734 /* This device is quirked not to be put into D3, so
735 don't put it in D3 */
736 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
739 error
= pci_raw_set_power_state(dev
, state
);
741 if (!__pci_complete_power_transition(dev
, state
))
744 * When aspm_policy is "powersave" this call ensures
745 * that ASPM is configured.
747 if (!error
&& dev
->bus
->self
)
748 pcie_aspm_powersave_config_link(dev
->bus
->self
);
754 * pci_choose_state - Choose the power state of a PCI device
755 * @dev: PCI device to be suspended
756 * @state: target sleep state for the whole system. This is the value
757 * that is passed to suspend() function.
759 * Returns PCI power state suitable for given device and given system
763 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
767 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
770 ret
= platform_pci_choose_state(dev
);
771 if (ret
!= PCI_POWER_ERROR
)
774 switch (state
.event
) {
777 case PM_EVENT_FREEZE
:
778 case PM_EVENT_PRETHAW
:
779 /* REVISIT both freeze and pre-thaw "should" use D0 */
780 case PM_EVENT_SUSPEND
:
781 case PM_EVENT_HIBERNATE
:
784 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
791 EXPORT_SYMBOL(pci_choose_state
);
793 #define PCI_EXP_SAVE_REGS 7
795 #define pcie_cap_has_devctl(type, flags) 1
796 #define pcie_cap_has_lnkctl(type, flags) \
797 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
798 (type == PCI_EXP_TYPE_ROOT_PORT || \
799 type == PCI_EXP_TYPE_ENDPOINT || \
800 type == PCI_EXP_TYPE_LEG_END))
801 #define pcie_cap_has_sltctl(type, flags) \
802 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
803 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
804 (type == PCI_EXP_TYPE_DOWNSTREAM && \
805 (flags & PCI_EXP_FLAGS_SLOT))))
806 #define pcie_cap_has_rtctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 (type == PCI_EXP_TYPE_ROOT_PORT || \
809 type == PCI_EXP_TYPE_RC_EC))
810 #define pcie_cap_has_devctl2(type, flags) \
811 ((flags & PCI_EXP_FLAGS_VERS) > 1)
812 #define pcie_cap_has_lnkctl2(type, flags) \
813 ((flags & PCI_EXP_FLAGS_VERS) > 1)
814 #define pcie_cap_has_sltctl2(type, flags) \
815 ((flags & PCI_EXP_FLAGS_VERS) > 1)
817 static int pci_save_pcie_state(struct pci_dev
*dev
)
820 struct pci_cap_saved_state
*save_state
;
824 pos
= pci_pcie_cap(dev
);
828 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
830 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
833 cap
= (u16
*)&save_state
->cap
.data
[0];
835 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
837 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
838 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
839 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
840 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
841 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
842 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
843 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
844 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
845 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
846 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
847 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
848 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
849 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
850 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
855 static void pci_restore_pcie_state(struct pci_dev
*dev
)
858 struct pci_cap_saved_state
*save_state
;
862 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
863 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
864 if (!save_state
|| pos
<= 0)
866 cap
= (u16
*)&save_state
->cap
.data
[0];
868 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
870 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
871 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
872 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
873 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
874 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
875 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
876 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
877 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
878 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
879 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
880 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
881 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
882 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
883 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
887 static int pci_save_pcix_state(struct pci_dev
*dev
)
890 struct pci_cap_saved_state
*save_state
;
892 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
896 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
898 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
902 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
903 (u16
*)save_state
->cap
.data
);
908 static void pci_restore_pcix_state(struct pci_dev
*dev
)
911 struct pci_cap_saved_state
*save_state
;
914 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
915 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
916 if (!save_state
|| pos
<= 0)
918 cap
= (u16
*)&save_state
->cap
.data
[0];
920 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
925 * pci_save_state - save the PCI configuration space of a device before suspending
926 * @dev: - PCI device that we're dealing with
929 pci_save_state(struct pci_dev
*dev
)
932 /* XXX: 100% dword access ok here? */
933 for (i
= 0; i
< 16; i
++)
934 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
935 dev
->state_saved
= true;
936 if ((i
= pci_save_pcie_state(dev
)) != 0)
938 if ((i
= pci_save_pcix_state(dev
)) != 0)
944 * pci_restore_state - Restore the saved state of a PCI device
945 * @dev: - PCI device that we're dealing with
947 void pci_restore_state(struct pci_dev
*dev
)
952 if (!dev
->state_saved
)
955 /* PCI Express register must be restored first */
956 pci_restore_pcie_state(dev
);
959 * The Base Address register should be programmed before the command
962 for (i
= 15; i
>= 0; i
--) {
963 pci_read_config_dword(dev
, i
* 4, &val
);
964 if (val
!= dev
->saved_config_space
[i
]) {
965 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
966 "space at offset %#x (was %#x, writing %#x)\n",
967 i
, val
, (int)dev
->saved_config_space
[i
]);
968 pci_write_config_dword(dev
,i
* 4,
969 dev
->saved_config_space
[i
]);
972 pci_restore_pcix_state(dev
);
973 pci_restore_msi_state(dev
);
974 pci_restore_iov_state(dev
);
976 dev
->state_saved
= false;
979 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
983 err
= pci_set_power_state(dev
, PCI_D0
);
984 if (err
< 0 && err
!= -EIO
)
986 err
= pcibios_enable_device(dev
, bars
);
989 pci_fixup_device(pci_fixup_enable
, dev
);
995 * pci_reenable_device - Resume abandoned device
996 * @dev: PCI device to be resumed
998 * Note this function is a backend of pci_default_resume and is not supposed
999 * to be called by normal code, write proper resume handler and use it instead.
1001 int pci_reenable_device(struct pci_dev
*dev
)
1003 if (pci_is_enabled(dev
))
1004 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1008 static int __pci_enable_device_flags(struct pci_dev
*dev
,
1009 resource_size_t flags
)
1015 * Power state could be unknown at this point, either due to a fresh
1016 * boot or a device removal call. So get the current power state
1017 * so that things like MSI message writing will behave as expected
1018 * (e.g. if the device really is in D0 at enable time).
1022 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1023 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1026 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
1027 return 0; /* already enabled */
1029 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1030 if (dev
->resource
[i
].flags
& flags
)
1033 err
= do_pci_enable_device(dev
, bars
);
1035 atomic_dec(&dev
->enable_cnt
);
1040 * pci_enable_device_io - Initialize a device for use with IO space
1041 * @dev: PCI device to be initialized
1043 * Initialize device before it's used by a driver. Ask low-level code
1044 * to enable I/O resources. Wake up the device if it was suspended.
1045 * Beware, this function can fail.
1047 int pci_enable_device_io(struct pci_dev
*dev
)
1049 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
1053 * pci_enable_device_mem - Initialize a device for use with Memory space
1054 * @dev: PCI device to be initialized
1056 * Initialize device before it's used by a driver. Ask low-level code
1057 * to enable Memory resources. Wake up the device if it was suspended.
1058 * Beware, this function can fail.
1060 int pci_enable_device_mem(struct pci_dev
*dev
)
1062 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1066 * pci_enable_device - Initialize device before it's used by a driver.
1067 * @dev: PCI device to be initialized
1069 * Initialize device before it's used by a driver. Ask low-level code
1070 * to enable I/O and memory. Wake up the device if it was suspended.
1071 * Beware, this function can fail.
1073 * Note we don't actually enable the device many times if we call
1074 * this function repeatedly (we just increment the count).
1076 int pci_enable_device(struct pci_dev
*dev
)
1078 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1082 * Managed PCI resources. This manages device on/off, intx/msi/msix
1083 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1084 * there's no need to track it separately. pci_devres is initialized
1085 * when a device is enabled using managed PCI device enable interface.
1088 unsigned int enabled
:1;
1089 unsigned int pinned
:1;
1090 unsigned int orig_intx
:1;
1091 unsigned int restore_intx
:1;
1095 static void pcim_release(struct device
*gendev
, void *res
)
1097 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1098 struct pci_devres
*this = res
;
1101 if (dev
->msi_enabled
)
1102 pci_disable_msi(dev
);
1103 if (dev
->msix_enabled
)
1104 pci_disable_msix(dev
);
1106 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1107 if (this->region_mask
& (1 << i
))
1108 pci_release_region(dev
, i
);
1110 if (this->restore_intx
)
1111 pci_intx(dev
, this->orig_intx
);
1113 if (this->enabled
&& !this->pinned
)
1114 pci_disable_device(dev
);
1117 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1119 struct pci_devres
*dr
, *new_dr
;
1121 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1125 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1128 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1131 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1133 if (pci_is_managed(pdev
))
1134 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1139 * pcim_enable_device - Managed pci_enable_device()
1140 * @pdev: PCI device to be initialized
1142 * Managed pci_enable_device().
1144 int pcim_enable_device(struct pci_dev
*pdev
)
1146 struct pci_devres
*dr
;
1149 dr
= get_pci_dr(pdev
);
1155 rc
= pci_enable_device(pdev
);
1157 pdev
->is_managed
= 1;
1164 * pcim_pin_device - Pin managed PCI device
1165 * @pdev: PCI device to pin
1167 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1168 * driver detach. @pdev must have been enabled with
1169 * pcim_enable_device().
1171 void pcim_pin_device(struct pci_dev
*pdev
)
1173 struct pci_devres
*dr
;
1175 dr
= find_pci_dr(pdev
);
1176 WARN_ON(!dr
|| !dr
->enabled
);
1182 * pcibios_disable_device - disable arch specific PCI resources for device dev
1183 * @dev: the PCI device to disable
1185 * Disables architecture specific PCI resources for the device. This
1186 * is the default implementation. Architecture implementations can
1189 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1191 static void do_pci_disable_device(struct pci_dev
*dev
)
1195 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1196 if (pci_command
& PCI_COMMAND_MASTER
) {
1197 pci_command
&= ~PCI_COMMAND_MASTER
;
1198 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1201 pcibios_disable_device(dev
);
1205 * pci_disable_enabled_device - Disable device without updating enable_cnt
1206 * @dev: PCI device to disable
1208 * NOTE: This function is a backend of PCI power management routines and is
1209 * not supposed to be called drivers.
1211 void pci_disable_enabled_device(struct pci_dev
*dev
)
1213 if (pci_is_enabled(dev
))
1214 do_pci_disable_device(dev
);
1218 * pci_disable_device - Disable PCI device after use
1219 * @dev: PCI device to be disabled
1221 * Signal to the system that the PCI device is not in use by the system
1222 * anymore. This only involves disabling PCI bus-mastering, if active.
1224 * Note we don't actually disable the device until all callers of
1225 * pci_enable_device() have called pci_disable_device().
1228 pci_disable_device(struct pci_dev
*dev
)
1230 struct pci_devres
*dr
;
1232 dr
= find_pci_dr(dev
);
1236 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1239 do_pci_disable_device(dev
);
1241 dev
->is_busmaster
= 0;
1245 * pcibios_set_pcie_reset_state - set reset state for device dev
1246 * @dev: the PCIe device reset
1247 * @state: Reset state to enter into
1250 * Sets the PCIe reset state for the device. This is the default
1251 * implementation. Architecture implementations can override this.
1253 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1254 enum pcie_reset_state state
)
1260 * pci_set_pcie_reset_state - set reset state for device dev
1261 * @dev: the PCIe device reset
1262 * @state: Reset state to enter into
1265 * Sets the PCI reset state for the device.
1267 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1269 return pcibios_set_pcie_reset_state(dev
, state
);
1273 * pci_check_pme_status - Check if given device has generated PME.
1274 * @dev: Device to check.
1276 * Check the PME status of the device and if set, clear it and clear PME enable
1277 * (if set). Return 'true' if PME status and PME enable were both set or
1278 * 'false' otherwise.
1280 bool pci_check_pme_status(struct pci_dev
*dev
)
1289 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1290 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1291 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1294 /* Clear PME status. */
1295 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1296 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1297 /* Disable PME to avoid interrupt flood. */
1298 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1302 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1308 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1309 * @dev: Device to handle.
1312 * Check if @dev has generated PME and queue a resume request for it in that
1315 static int pci_pme_wakeup(struct pci_dev
*dev
, void *ign
)
1317 if (pci_check_pme_status(dev
)) {
1318 pci_wakeup_event(dev
);
1319 pm_request_resume(&dev
->dev
);
1325 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1326 * @bus: Top bus of the subtree to walk.
1328 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1331 pci_walk_bus(bus
, pci_pme_wakeup
, NULL
);
1335 * pci_pme_capable - check the capability of PCI device to generate PME#
1336 * @dev: PCI device to handle.
1337 * @state: PCI state from which device will issue PME#.
1339 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1344 return !!(dev
->pme_support
& (1 << state
));
1347 static void pci_pme_list_scan(struct work_struct
*work
)
1349 struct pci_pme_device
*pme_dev
;
1351 mutex_lock(&pci_pme_list_mutex
);
1352 if (!list_empty(&pci_pme_list
)) {
1353 list_for_each_entry(pme_dev
, &pci_pme_list
, list
)
1354 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1355 schedule_delayed_work(&pci_pme_work
, msecs_to_jiffies(PME_TIMEOUT
));
1357 mutex_unlock(&pci_pme_list_mutex
);
1361 * pci_external_pme - is a device an external PCI PME source?
1362 * @dev: PCI device to check
1366 static bool pci_external_pme(struct pci_dev
*dev
)
1368 if (pci_is_pcie(dev
) || dev
->bus
->number
== 0)
1374 * pci_pme_active - enable or disable PCI device's PME# function
1375 * @dev: PCI device to handle.
1376 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1378 * The caller must verify that the device is capable of generating PME# before
1379 * calling this function with @enable equal to 'true'.
1381 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1388 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1389 /* Clear PME_Status by writing 1 to it and enable PME# */
1390 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1392 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1394 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1396 /* PCI (as opposed to PCIe) PME requires that the device have
1397 its PME# line hooked up correctly. Not all hardware vendors
1398 do this, so the PME never gets delivered and the device
1399 remains asleep. The easiest way around this is to
1400 periodically walk the list of suspended devices and check
1401 whether any have their PME flag set. The assumption is that
1402 we'll wake up often enough anyway that this won't be a huge
1403 hit, and the power savings from the devices will still be a
1406 if (pci_external_pme(dev
)) {
1407 struct pci_pme_device
*pme_dev
;
1409 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1414 mutex_lock(&pci_pme_list_mutex
);
1415 list_add(&pme_dev
->list
, &pci_pme_list
);
1416 if (list_is_singular(&pci_pme_list
))
1417 schedule_delayed_work(&pci_pme_work
,
1418 msecs_to_jiffies(PME_TIMEOUT
));
1419 mutex_unlock(&pci_pme_list_mutex
);
1421 mutex_lock(&pci_pme_list_mutex
);
1422 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1423 if (pme_dev
->dev
== dev
) {
1424 list_del(&pme_dev
->list
);
1429 mutex_unlock(&pci_pme_list_mutex
);
1434 dev_printk(KERN_DEBUG
, &dev
->dev
, "PME# %s\n",
1435 enable
? "enabled" : "disabled");
1439 * __pci_enable_wake - enable PCI device as wakeup event source
1440 * @dev: PCI device affected
1441 * @state: PCI state from which device will issue wakeup events
1442 * @runtime: True if the events are to be generated at run time
1443 * @enable: True to enable event generation; false to disable
1445 * This enables the device as a wakeup event source, or disables it.
1446 * When such events involves platform-specific hooks, those hooks are
1447 * called automatically by this routine.
1449 * Devices with legacy power management (no standard PCI PM capabilities)
1450 * always require such platform hooks.
1453 * 0 is returned on success
1454 * -EINVAL is returned if device is not supposed to wake up the system
1455 * Error code depending on the platform is returned if both the platform and
1456 * the native mechanism fail to enable the generation of wake-up events
1458 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1459 bool runtime
, bool enable
)
1463 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1466 /* Don't do the same thing twice in a row for one device. */
1467 if (!!enable
== !!dev
->wakeup_prepared
)
1471 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1472 * Anderson we should be doing PME# wake enable followed by ACPI wake
1473 * enable. To disable wake-up we call the platform first, for symmetry.
1479 if (pci_pme_capable(dev
, state
))
1480 pci_pme_active(dev
, true);
1483 error
= runtime
? platform_pci_run_wake(dev
, true) :
1484 platform_pci_sleep_wake(dev
, true);
1488 dev
->wakeup_prepared
= true;
1491 platform_pci_run_wake(dev
, false);
1493 platform_pci_sleep_wake(dev
, false);
1494 pci_pme_active(dev
, false);
1495 dev
->wakeup_prepared
= false;
1500 EXPORT_SYMBOL(__pci_enable_wake
);
1503 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1504 * @dev: PCI device to prepare
1505 * @enable: True to enable wake-up event generation; false to disable
1507 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1508 * and this function allows them to set that up cleanly - pci_enable_wake()
1509 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1510 * ordering constraints.
1512 * This function only returns error code if the device is not capable of
1513 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1514 * enable wake-up power for it.
1516 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1518 return pci_pme_capable(dev
, PCI_D3cold
) ?
1519 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1520 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1524 * pci_target_state - find an appropriate low power state for a given PCI dev
1527 * Use underlying platform code to find a supported low power state for @dev.
1528 * If the platform can't manage @dev, return the deepest state from which it
1529 * can generate wake events, based on any available PME info.
1531 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1533 pci_power_t target_state
= PCI_D3hot
;
1535 if (platform_pci_power_manageable(dev
)) {
1537 * Call the platform to choose the target state of the device
1538 * and enable wake-up from this state if supported.
1540 pci_power_t state
= platform_pci_choose_state(dev
);
1543 case PCI_POWER_ERROR
:
1548 if (pci_no_d1d2(dev
))
1551 target_state
= state
;
1553 } else if (!dev
->pm_cap
) {
1554 target_state
= PCI_D0
;
1555 } else if (device_may_wakeup(&dev
->dev
)) {
1557 * Find the deepest state from which the device can generate
1558 * wake-up events, make it the target state and enable device
1561 if (dev
->pme_support
) {
1563 && !(dev
->pme_support
& (1 << target_state
)))
1568 return target_state
;
1572 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1573 * @dev: Device to handle.
1575 * Choose the power state appropriate for the device depending on whether
1576 * it can wake up the system and/or is power manageable by the platform
1577 * (PCI_D3hot is the default) and put the device into that state.
1579 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1581 pci_power_t target_state
= pci_target_state(dev
);
1584 if (target_state
== PCI_POWER_ERROR
)
1587 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1589 error
= pci_set_power_state(dev
, target_state
);
1592 pci_enable_wake(dev
, target_state
, false);
1598 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1599 * @dev: Device to handle.
1601 * Disable device's system wake-up capability and put it into D0.
1603 int pci_back_from_sleep(struct pci_dev
*dev
)
1605 pci_enable_wake(dev
, PCI_D0
, false);
1606 return pci_set_power_state(dev
, PCI_D0
);
1610 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1611 * @dev: PCI device being suspended.
1613 * Prepare @dev to generate wake-up events at run time and put it into a low
1616 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1618 pci_power_t target_state
= pci_target_state(dev
);
1621 if (target_state
== PCI_POWER_ERROR
)
1624 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1626 error
= pci_set_power_state(dev
, target_state
);
1629 __pci_enable_wake(dev
, target_state
, true, false);
1635 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1636 * @dev: Device to check.
1638 * Return true if the device itself is cabable of generating wake-up events
1639 * (through the platform or using the native PCIe PME) or if the device supports
1640 * PME and one of its upstream bridges can generate wake-up events.
1642 bool pci_dev_run_wake(struct pci_dev
*dev
)
1644 struct pci_bus
*bus
= dev
->bus
;
1646 if (device_run_wake(&dev
->dev
))
1649 if (!dev
->pme_support
)
1652 while (bus
->parent
) {
1653 struct pci_dev
*bridge
= bus
->self
;
1655 if (device_run_wake(&bridge
->dev
))
1661 /* We have reached the root bus. */
1663 return device_run_wake(bus
->bridge
);
1667 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
1670 * pci_pm_init - Initialize PM functions of given PCI device
1671 * @dev: PCI device to handle.
1673 void pci_pm_init(struct pci_dev
*dev
)
1678 pm_runtime_forbid(&dev
->dev
);
1679 device_enable_async_suspend(&dev
->dev
);
1680 dev
->wakeup_prepared
= false;
1684 /* find PCI PM capability in list */
1685 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1688 /* Check device's ability to generate PME# */
1689 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1691 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1692 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1693 pmc
& PCI_PM_CAP_VER_MASK
);
1698 dev
->d3_delay
= PCI_PM_D3_WAIT
;
1700 dev
->d1_support
= false;
1701 dev
->d2_support
= false;
1702 if (!pci_no_d1d2(dev
)) {
1703 if (pmc
& PCI_PM_CAP_D1
)
1704 dev
->d1_support
= true;
1705 if (pmc
& PCI_PM_CAP_D2
)
1706 dev
->d2_support
= true;
1708 if (dev
->d1_support
|| dev
->d2_support
)
1709 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1710 dev
->d1_support
? " D1" : "",
1711 dev
->d2_support
? " D2" : "");
1714 pmc
&= PCI_PM_CAP_PME_MASK
;
1716 dev_printk(KERN_DEBUG
, &dev
->dev
,
1717 "PME# supported from%s%s%s%s%s\n",
1718 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1719 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1720 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1721 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1722 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1723 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1725 * Make device's PM flags reflect the wake-up capability, but
1726 * let the user space enable it to wake up the system as needed.
1728 device_set_wakeup_capable(&dev
->dev
, true);
1729 /* Disable the PME# generation functionality */
1730 pci_pme_active(dev
, false);
1732 dev
->pme_support
= 0;
1737 * platform_pci_wakeup_init - init platform wakeup if present
1740 * Some devices don't have PCI PM caps but can still generate wakeup
1741 * events through platform methods (like ACPI events). If @dev supports
1742 * platform wakeup events, set the device flag to indicate as much. This
1743 * may be redundant if the device also supports PCI PM caps, but double
1744 * initialization should be safe in that case.
1746 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1748 if (!platform_pci_can_wakeup(dev
))
1751 device_set_wakeup_capable(&dev
->dev
, true);
1752 platform_pci_sleep_wake(dev
, false);
1756 * pci_add_save_buffer - allocate buffer for saving given capability registers
1757 * @dev: the PCI device
1758 * @cap: the capability to allocate the buffer for
1759 * @size: requested size of the buffer
1761 static int pci_add_cap_save_buffer(
1762 struct pci_dev
*dev
, char cap
, unsigned int size
)
1765 struct pci_cap_saved_state
*save_state
;
1767 pos
= pci_find_capability(dev
, cap
);
1771 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1775 save_state
->cap
.cap_nr
= cap
;
1776 save_state
->cap
.size
= size
;
1777 pci_add_saved_cap(dev
, save_state
);
1783 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1784 * @dev: the PCI device
1786 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1790 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1791 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1794 "unable to preallocate PCI Express save buffer\n");
1796 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1799 "unable to preallocate PCI-X save buffer\n");
1803 * pci_enable_ari - enable ARI forwarding if hardware support it
1804 * @dev: the PCI device
1806 void pci_enable_ari(struct pci_dev
*dev
)
1811 struct pci_dev
*bridge
;
1813 if (!pci_is_pcie(dev
) || dev
->devfn
)
1816 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1820 bridge
= dev
->bus
->self
;
1821 if (!bridge
|| !pci_is_pcie(bridge
))
1824 pos
= pci_pcie_cap(bridge
);
1828 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1829 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1832 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1833 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1834 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1836 bridge
->ari_enabled
= 1;
1840 * pci_enable_ido - enable ID-based ordering on a device
1841 * @dev: the PCI device
1842 * @type: which types of IDO to enable
1844 * Enable ID-based ordering on @dev. @type can contain the bits
1845 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1846 * which types of transactions are allowed to be re-ordered.
1848 void pci_enable_ido(struct pci_dev
*dev
, unsigned long type
)
1853 pos
= pci_pcie_cap(dev
);
1857 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1858 if (type
& PCI_EXP_IDO_REQUEST
)
1859 ctrl
|= PCI_EXP_IDO_REQ_EN
;
1860 if (type
& PCI_EXP_IDO_COMPLETION
)
1861 ctrl
|= PCI_EXP_IDO_CMP_EN
;
1862 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1864 EXPORT_SYMBOL(pci_enable_ido
);
1867 * pci_disable_ido - disable ID-based ordering on a device
1868 * @dev: the PCI device
1869 * @type: which types of IDO to disable
1871 void pci_disable_ido(struct pci_dev
*dev
, unsigned long type
)
1876 if (!pci_is_pcie(dev
))
1879 pos
= pci_pcie_cap(dev
);
1883 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1884 if (type
& PCI_EXP_IDO_REQUEST
)
1885 ctrl
&= ~PCI_EXP_IDO_REQ_EN
;
1886 if (type
& PCI_EXP_IDO_COMPLETION
)
1887 ctrl
&= ~PCI_EXP_IDO_CMP_EN
;
1888 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1890 EXPORT_SYMBOL(pci_disable_ido
);
1893 * pci_enable_obff - enable optimized buffer flush/fill
1895 * @type: type of signaling to use
1897 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
1898 * signaling if possible, falling back to message signaling only if
1899 * WAKE# isn't supported. @type should indicate whether the PCIe link
1900 * be brought out of L0s or L1 to send the message. It should be either
1901 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
1903 * If your device can benefit from receiving all messages, even at the
1904 * power cost of bringing the link back up from a low power state, use
1905 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
1909 * Zero on success, appropriate error number on failure.
1911 int pci_enable_obff(struct pci_dev
*dev
, enum pci_obff_signal_type type
)
1918 if (!pci_is_pcie(dev
))
1921 pos
= pci_pcie_cap(dev
);
1925 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1926 if (!(cap
& PCI_EXP_OBFF_MASK
))
1927 return -ENOTSUPP
; /* no OBFF support at all */
1929 /* Make sure the topology supports OBFF as well */
1931 ret
= pci_enable_obff(dev
->bus
->self
, type
);
1936 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1937 if (cap
& PCI_EXP_OBFF_WAKE
)
1938 ctrl
|= PCI_EXP_OBFF_WAKE_EN
;
1941 case PCI_EXP_OBFF_SIGNAL_L0
:
1942 if (!(ctrl
& PCI_EXP_OBFF_WAKE_EN
))
1943 ctrl
|= PCI_EXP_OBFF_MSGA_EN
;
1945 case PCI_EXP_OBFF_SIGNAL_ALWAYS
:
1946 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
1947 ctrl
|= PCI_EXP_OBFF_MSGB_EN
;
1950 WARN(1, "bad OBFF signal type\n");
1954 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1958 EXPORT_SYMBOL(pci_enable_obff
);
1961 * pci_disable_obff - disable optimized buffer flush/fill
1964 * Disable OBFF on @dev.
1966 void pci_disable_obff(struct pci_dev
*dev
)
1971 if (!pci_is_pcie(dev
))
1974 pos
= pci_pcie_cap(dev
);
1978 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1979 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
1980 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1982 EXPORT_SYMBOL(pci_disable_obff
);
1985 * pci_ltr_supported - check whether a device supports LTR
1989 * True if @dev supports latency tolerance reporting, false otherwise.
1991 bool pci_ltr_supported(struct pci_dev
*dev
)
1996 if (!pci_is_pcie(dev
))
1999 pos
= pci_pcie_cap(dev
);
2003 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2005 return cap
& PCI_EXP_DEVCAP2_LTR
;
2007 EXPORT_SYMBOL(pci_ltr_supported
);
2010 * pci_enable_ltr - enable latency tolerance reporting
2013 * Enable LTR on @dev if possible, which means enabling it first on
2017 * Zero on success, errno on failure.
2019 int pci_enable_ltr(struct pci_dev
*dev
)
2025 if (!pci_ltr_supported(dev
))
2028 pos
= pci_pcie_cap(dev
);
2032 /* Only primary function can enable/disable LTR */
2033 if (PCI_FUNC(dev
->devfn
) != 0)
2036 /* Enable upstream ports first */
2038 ret
= pci_enable_ltr(dev
->bus
->self
);
2043 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2044 ctrl
|= PCI_EXP_LTR_EN
;
2045 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2049 EXPORT_SYMBOL(pci_enable_ltr
);
2052 * pci_disable_ltr - disable latency tolerance reporting
2055 void pci_disable_ltr(struct pci_dev
*dev
)
2060 if (!pci_ltr_supported(dev
))
2063 pos
= pci_pcie_cap(dev
);
2067 /* Only primary function can enable/disable LTR */
2068 if (PCI_FUNC(dev
->devfn
) != 0)
2071 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2072 ctrl
&= ~PCI_EXP_LTR_EN
;
2073 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2075 EXPORT_SYMBOL(pci_disable_ltr
);
2077 static int __pci_ltr_scale(int *val
)
2081 while (*val
> 1023) {
2082 *val
= (*val
+ 31) / 32;
2089 * pci_set_ltr - set LTR latency values
2091 * @snoop_lat_ns: snoop latency in nanoseconds
2092 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2094 * Figure out the scale and set the LTR values accordingly.
2096 int pci_set_ltr(struct pci_dev
*dev
, int snoop_lat_ns
, int nosnoop_lat_ns
)
2098 int pos
, ret
, snoop_scale
, nosnoop_scale
;
2101 if (!pci_ltr_supported(dev
))
2104 snoop_scale
= __pci_ltr_scale(&snoop_lat_ns
);
2105 nosnoop_scale
= __pci_ltr_scale(&nosnoop_lat_ns
);
2107 if (snoop_lat_ns
> PCI_LTR_VALUE_MASK
||
2108 nosnoop_lat_ns
> PCI_LTR_VALUE_MASK
)
2111 if ((snoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)) ||
2112 (nosnoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)))
2115 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
2119 val
= (snoop_scale
<< PCI_LTR_SCALE_SHIFT
) | snoop_lat_ns
;
2120 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_SNOOP_LAT
, val
);
2124 val
= (nosnoop_scale
<< PCI_LTR_SCALE_SHIFT
) | nosnoop_lat_ns
;
2125 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_NOSNOOP_LAT
, val
);
2131 EXPORT_SYMBOL(pci_set_ltr
);
2133 static int pci_acs_enable
;
2136 * pci_request_acs - ask for ACS to be enabled if supported
2138 void pci_request_acs(void)
2144 * pci_enable_acs - enable ACS if hardware support it
2145 * @dev: the PCI device
2147 void pci_enable_acs(struct pci_dev
*dev
)
2153 if (!pci_acs_enable
)
2156 if (!pci_is_pcie(dev
))
2159 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2163 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2164 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2166 /* Source Validation */
2167 ctrl
|= (cap
& PCI_ACS_SV
);
2169 /* P2P Request Redirect */
2170 ctrl
|= (cap
& PCI_ACS_RR
);
2172 /* P2P Completion Redirect */
2173 ctrl
|= (cap
& PCI_ACS_CR
);
2175 /* Upstream Forwarding */
2176 ctrl
|= (cap
& PCI_ACS_UF
);
2178 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2182 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2183 * @dev: the PCI device
2184 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2186 * Perform INTx swizzling for a device behind one level of bridge. This is
2187 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2188 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2189 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2190 * the PCI Express Base Specification, Revision 2.1)
2192 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
2196 if (pci_ari_enabled(dev
->bus
))
2199 slot
= PCI_SLOT(dev
->devfn
);
2201 return (((pin
- 1) + slot
) % 4) + 1;
2205 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2213 while (!pci_is_root_bus(dev
->bus
)) {
2214 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2215 dev
= dev
->bus
->self
;
2222 * pci_common_swizzle - swizzle INTx all the way to root bridge
2223 * @dev: the PCI device
2224 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2226 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2227 * bridges all the way up to a PCI root bus.
2229 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2233 while (!pci_is_root_bus(dev
->bus
)) {
2234 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2235 dev
= dev
->bus
->self
;
2238 return PCI_SLOT(dev
->devfn
);
2242 * pci_release_region - Release a PCI bar
2243 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2244 * @bar: BAR to release
2246 * Releases the PCI I/O and memory resources previously reserved by a
2247 * successful call to pci_request_region. Call this function only
2248 * after all use of the PCI regions has ceased.
2250 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2252 struct pci_devres
*dr
;
2254 if (pci_resource_len(pdev
, bar
) == 0)
2256 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2257 release_region(pci_resource_start(pdev
, bar
),
2258 pci_resource_len(pdev
, bar
));
2259 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2260 release_mem_region(pci_resource_start(pdev
, bar
),
2261 pci_resource_len(pdev
, bar
));
2263 dr
= find_pci_dr(pdev
);
2265 dr
->region_mask
&= ~(1 << bar
);
2269 * __pci_request_region - Reserved PCI I/O and memory resource
2270 * @pdev: PCI device whose resources are to be reserved
2271 * @bar: BAR to be reserved
2272 * @res_name: Name to be associated with resource.
2273 * @exclusive: whether the region access is exclusive or not
2275 * Mark the PCI region associated with PCI device @pdev BR @bar as
2276 * being reserved by owner @res_name. Do not access any
2277 * address inside the PCI regions unless this call returns
2280 * If @exclusive is set, then the region is marked so that userspace
2281 * is explicitly not allowed to map the resource via /dev/mem or
2282 * sysfs MMIO access.
2284 * Returns 0 on success, or %EBUSY on error. A warning
2285 * message is also printed on failure.
2287 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
2290 struct pci_devres
*dr
;
2292 if (pci_resource_len(pdev
, bar
) == 0)
2295 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2296 if (!request_region(pci_resource_start(pdev
, bar
),
2297 pci_resource_len(pdev
, bar
), res_name
))
2300 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2301 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2302 pci_resource_len(pdev
, bar
), res_name
,
2307 dr
= find_pci_dr(pdev
);
2309 dr
->region_mask
|= 1 << bar
;
2314 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2315 &pdev
->resource
[bar
]);
2320 * pci_request_region - Reserve PCI I/O and memory resource
2321 * @pdev: PCI device whose resources are to be reserved
2322 * @bar: BAR to be reserved
2323 * @res_name: Name to be associated with resource
2325 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2326 * being reserved by owner @res_name. Do not access any
2327 * address inside the PCI regions unless this call returns
2330 * Returns 0 on success, or %EBUSY on error. A warning
2331 * message is also printed on failure.
2333 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2335 return __pci_request_region(pdev
, bar
, res_name
, 0);
2339 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2340 * @pdev: PCI device whose resources are to be reserved
2341 * @bar: BAR to be reserved
2342 * @res_name: Name to be associated with resource.
2344 * Mark the PCI region associated with PCI device @pdev BR @bar as
2345 * being reserved by owner @res_name. Do not access any
2346 * address inside the PCI regions unless this call returns
2349 * Returns 0 on success, or %EBUSY on error. A warning
2350 * message is also printed on failure.
2352 * The key difference that _exclusive makes it that userspace is
2353 * explicitly not allowed to map the resource via /dev/mem or
2356 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2358 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2361 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2362 * @pdev: PCI device whose resources were previously reserved
2363 * @bars: Bitmask of BARs to be released
2365 * Release selected PCI I/O and memory resources previously reserved.
2366 * Call this function only after all use of the PCI regions has ceased.
2368 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2372 for (i
= 0; i
< 6; i
++)
2373 if (bars
& (1 << i
))
2374 pci_release_region(pdev
, i
);
2377 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2378 const char *res_name
, int excl
)
2382 for (i
= 0; i
< 6; i
++)
2383 if (bars
& (1 << i
))
2384 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2390 if (bars
& (1 << i
))
2391 pci_release_region(pdev
, i
);
2398 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2399 * @pdev: PCI device whose resources are to be reserved
2400 * @bars: Bitmask of BARs to be requested
2401 * @res_name: Name to be associated with resource
2403 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2404 const char *res_name
)
2406 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2409 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
2410 int bars
, const char *res_name
)
2412 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2413 IORESOURCE_EXCLUSIVE
);
2417 * pci_release_regions - Release reserved PCI I/O and memory resources
2418 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2420 * Releases all PCI I/O and memory resources previously reserved by a
2421 * successful call to pci_request_regions. Call this function only
2422 * after all use of the PCI regions has ceased.
2425 void pci_release_regions(struct pci_dev
*pdev
)
2427 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2431 * pci_request_regions - Reserved PCI I/O and memory resources
2432 * @pdev: PCI device whose resources are to be reserved
2433 * @res_name: Name to be associated with resource.
2435 * Mark all PCI regions associated with PCI device @pdev as
2436 * being reserved by owner @res_name. Do not access any
2437 * address inside the PCI regions unless this call returns
2440 * Returns 0 on success, or %EBUSY on error. A warning
2441 * message is also printed on failure.
2443 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2445 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2449 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2450 * @pdev: PCI device whose resources are to be reserved
2451 * @res_name: Name to be associated with resource.
2453 * Mark all PCI regions associated with PCI device @pdev as
2454 * being reserved by owner @res_name. Do not access any
2455 * address inside the PCI regions unless this call returns
2458 * pci_request_regions_exclusive() will mark the region so that
2459 * /dev/mem and the sysfs MMIO access will not be allowed.
2461 * Returns 0 on success, or %EBUSY on error. A warning
2462 * message is also printed on failure.
2464 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2466 return pci_request_selected_regions_exclusive(pdev
,
2467 ((1 << 6) - 1), res_name
);
2470 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2474 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2476 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2478 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2479 if (cmd
!= old_cmd
) {
2480 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2481 enable
? "enabling" : "disabling");
2482 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2484 dev
->is_busmaster
= enable
;
2488 * pci_set_master - enables bus-mastering for device dev
2489 * @dev: the PCI device to enable
2491 * Enables bus-mastering on the device and calls pcibios_set_master()
2492 * to do the needed arch specific settings.
2494 void pci_set_master(struct pci_dev
*dev
)
2496 __pci_set_master(dev
, true);
2497 pcibios_set_master(dev
);
2501 * pci_clear_master - disables bus-mastering for device dev
2502 * @dev: the PCI device to disable
2504 void pci_clear_master(struct pci_dev
*dev
)
2506 __pci_set_master(dev
, false);
2510 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2511 * @dev: the PCI device for which MWI is to be enabled
2513 * Helper function for pci_set_mwi.
2514 * Originally copied from drivers/net/acenic.c.
2515 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2517 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2519 int pci_set_cacheline_size(struct pci_dev
*dev
)
2523 if (!pci_cache_line_size
)
2526 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2527 equal to or multiple of the right value. */
2528 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2529 if (cacheline_size
>= pci_cache_line_size
&&
2530 (cacheline_size
% pci_cache_line_size
) == 0)
2533 /* Write the correct value. */
2534 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2536 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2537 if (cacheline_size
== pci_cache_line_size
)
2540 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
2541 "supported\n", pci_cache_line_size
<< 2);
2545 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2547 #ifdef PCI_DISABLE_MWI
2548 int pci_set_mwi(struct pci_dev
*dev
)
2553 int pci_try_set_mwi(struct pci_dev
*dev
)
2558 void pci_clear_mwi(struct pci_dev
*dev
)
2565 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2566 * @dev: the PCI device for which MWI is enabled
2568 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2570 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2573 pci_set_mwi(struct pci_dev
*dev
)
2578 rc
= pci_set_cacheline_size(dev
);
2582 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2583 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
2584 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2585 cmd
|= PCI_COMMAND_INVALIDATE
;
2586 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2593 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2594 * @dev: the PCI device for which MWI is enabled
2596 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2597 * Callers are not required to check the return value.
2599 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2601 int pci_try_set_mwi(struct pci_dev
*dev
)
2603 int rc
= pci_set_mwi(dev
);
2608 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2609 * @dev: the PCI device to disable
2611 * Disables PCI Memory-Write-Invalidate transaction on the device
2614 pci_clear_mwi(struct pci_dev
*dev
)
2618 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2619 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2620 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2621 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2624 #endif /* ! PCI_DISABLE_MWI */
2627 * pci_intx - enables/disables PCI INTx for device dev
2628 * @pdev: the PCI device to operate on
2629 * @enable: boolean: whether to enable or disable PCI INTx
2631 * Enables/disables PCI INTx for device dev
2634 pci_intx(struct pci_dev
*pdev
, int enable
)
2636 u16 pci_command
, new;
2638 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2641 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2643 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2646 if (new != pci_command
) {
2647 struct pci_devres
*dr
;
2649 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2651 dr
= find_pci_dr(pdev
);
2652 if (dr
&& !dr
->restore_intx
) {
2653 dr
->restore_intx
= 1;
2654 dr
->orig_intx
= !enable
;
2660 * pci_msi_off - disables any msi or msix capabilities
2661 * @dev: the PCI device to operate on
2663 * If you want to use msi see pci_enable_msi and friends.
2664 * This is a lower level primitive that allows us to disable
2665 * msi operation at the device level.
2667 void pci_msi_off(struct pci_dev
*dev
)
2672 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2674 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2675 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2676 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2678 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2680 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2681 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2682 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2685 EXPORT_SYMBOL_GPL(pci_msi_off
);
2687 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2689 return dma_set_max_seg_size(&dev
->dev
, size
);
2691 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2693 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2695 return dma_set_seg_boundary(&dev
->dev
, mask
);
2697 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2699 static int pcie_flr(struct pci_dev
*dev
, int probe
)
2704 u16 status
, control
;
2706 pos
= pci_pcie_cap(dev
);
2710 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
2711 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2717 /* Wait for Transaction Pending bit clean */
2718 for (i
= 0; i
< 4; i
++) {
2720 msleep((1 << (i
- 1)) * 100);
2722 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
2723 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2727 dev_err(&dev
->dev
, "transaction is not cleared; "
2728 "proceeding with reset anyway\n");
2731 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &control
);
2732 control
|= PCI_EXP_DEVCTL_BCR_FLR
;
2733 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, control
);
2740 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
2747 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2751 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
2752 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2758 /* Wait for Transaction Pending bit clean */
2759 for (i
= 0; i
< 4; i
++) {
2761 msleep((1 << (i
- 1)) * 100);
2763 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
2764 if (!(status
& PCI_AF_STATUS_TP
))
2768 dev_err(&dev
->dev
, "transaction is not cleared; "
2769 "proceeding with reset anyway\n");
2772 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2779 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2780 * @dev: Device to reset.
2781 * @probe: If set, only check if the device can be reset this way.
2783 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2784 * unset, it will be reinitialized internally when going from PCI_D3hot to
2785 * PCI_D0. If that's the case and the device is not in a low-power state
2786 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2788 * NOTE: This causes the caller to sleep for twice the device power transition
2789 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2790 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2791 * Moreover, only devices in D0 can be reset by this function.
2793 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
2800 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
2801 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
2807 if (dev
->current_state
!= PCI_D0
)
2810 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2812 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2813 pci_dev_d3_sleep(dev
);
2815 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2817 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2818 pci_dev_d3_sleep(dev
);
2823 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
2826 struct pci_dev
*pdev
;
2828 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
2831 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
2838 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
2839 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
2840 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2843 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
2844 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2850 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
2857 pci_block_user_cfg_access(dev
);
2858 /* block PM suspend, driver probe, etc. */
2859 device_lock(&dev
->dev
);
2862 rc
= pci_dev_specific_reset(dev
, probe
);
2866 rc
= pcie_flr(dev
, probe
);
2870 rc
= pci_af_flr(dev
, probe
);
2874 rc
= pci_pm_reset(dev
, probe
);
2878 rc
= pci_parent_bus_reset(dev
, probe
);
2881 device_unlock(&dev
->dev
);
2882 pci_unblock_user_cfg_access(dev
);
2889 * __pci_reset_function - reset a PCI device function
2890 * @dev: PCI device to reset
2892 * Some devices allow an individual function to be reset without affecting
2893 * other functions in the same device. The PCI device must be responsive
2894 * to PCI config space in order to use this function.
2896 * The device function is presumed to be unused when this function is called.
2897 * Resetting the device will make the contents of PCI configuration space
2898 * random, so any caller of this must be prepared to reinitialise the
2899 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2902 * Returns 0 if the device function was successfully reset or negative if the
2903 * device doesn't support resetting a single function.
2905 int __pci_reset_function(struct pci_dev
*dev
)
2907 return pci_dev_reset(dev
, 0);
2909 EXPORT_SYMBOL_GPL(__pci_reset_function
);
2912 * pci_probe_reset_function - check whether the device can be safely reset
2913 * @dev: PCI device to reset
2915 * Some devices allow an individual function to be reset without affecting
2916 * other functions in the same device. The PCI device must be responsive
2917 * to PCI config space in order to use this function.
2919 * Returns 0 if the device function can be reset or negative if the
2920 * device doesn't support resetting a single function.
2922 int pci_probe_reset_function(struct pci_dev
*dev
)
2924 return pci_dev_reset(dev
, 1);
2928 * pci_reset_function - quiesce and reset a PCI device function
2929 * @dev: PCI device to reset
2931 * Some devices allow an individual function to be reset without affecting
2932 * other functions in the same device. The PCI device must be responsive
2933 * to PCI config space in order to use this function.
2935 * This function does not just reset the PCI portion of a device, but
2936 * clears all the state associated with the device. This function differs
2937 * from __pci_reset_function in that it saves and restores device state
2940 * Returns 0 if the device function was successfully reset or negative if the
2941 * device doesn't support resetting a single function.
2943 int pci_reset_function(struct pci_dev
*dev
)
2947 rc
= pci_dev_reset(dev
, 1);
2951 pci_save_state(dev
);
2954 * both INTx and MSI are disabled after the Interrupt Disable bit
2955 * is set and the Bus Master bit is cleared.
2957 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2959 rc
= pci_dev_reset(dev
, 0);
2961 pci_restore_state(dev
);
2965 EXPORT_SYMBOL_GPL(pci_reset_function
);
2968 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2969 * @dev: PCI device to query
2971 * Returns mmrbc: maximum designed memory read count in bytes
2972 * or appropriate error value.
2974 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2979 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2983 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
2986 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
2988 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2991 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2992 * @dev: PCI device to query
2994 * Returns mmrbc: maximum memory read count in bytes
2995 * or appropriate error value.
2997 int pcix_get_mmrbc(struct pci_dev
*dev
)
3002 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3006 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3009 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
3011 EXPORT_SYMBOL(pcix_get_mmrbc
);
3014 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3015 * @dev: PCI device to query
3016 * @mmrbc: maximum memory read count in bytes
3017 * valid values are 512, 1024, 2048, 4096
3019 * If possible sets maximum memory read byte count, some bridges have erratas
3020 * that prevent this.
3022 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
3028 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
3031 v
= ffs(mmrbc
) - 10;
3033 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3037 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3040 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
3043 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3046 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
3048 if (v
> o
&& dev
->bus
&&
3049 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
3052 cmd
&= ~PCI_X_CMD_MAX_READ
;
3054 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
3059 EXPORT_SYMBOL(pcix_set_mmrbc
);
3062 * pcie_get_readrq - get PCI Express read request size
3063 * @dev: PCI device to query
3065 * Returns maximum memory read request in bytes
3066 * or appropriate error value.
3068 int pcie_get_readrq(struct pci_dev
*dev
)
3073 cap
= pci_pcie_cap(dev
);
3077 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3079 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
3083 EXPORT_SYMBOL(pcie_get_readrq
);
3086 * pcie_set_readrq - set PCI Express maximum memory read request
3087 * @dev: PCI device to query
3088 * @rq: maximum memory read count in bytes
3089 * valid values are 128, 256, 512, 1024, 2048, 4096
3091 * If possible sets maximum read byte count
3093 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
3095 int cap
, err
= -EINVAL
;
3098 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
3101 v
= (ffs(rq
) - 8) << 12;
3103 cap
= pci_pcie_cap(dev
);
3107 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3111 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
3112 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
3114 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3120 EXPORT_SYMBOL(pcie_set_readrq
);
3123 * pci_select_bars - Make BAR mask from the type of resource
3124 * @dev: the PCI device for which BAR mask is made
3125 * @flags: resource type mask to be selected
3127 * This helper routine makes bar mask from the type of resource.
3129 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
3132 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
3133 if (pci_resource_flags(dev
, i
) & flags
)
3139 * pci_resource_bar - get position of the BAR associated with a resource
3140 * @dev: the PCI device
3141 * @resno: the resource number
3142 * @type: the BAR type to be filled in
3144 * Returns BAR position in config space, or 0 if the BAR is invalid.
3146 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
3150 if (resno
< PCI_ROM_RESOURCE
) {
3151 *type
= pci_bar_unknown
;
3152 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
3153 } else if (resno
== PCI_ROM_RESOURCE
) {
3154 *type
= pci_bar_mem32
;
3155 return dev
->rom_base_reg
;
3156 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
3157 /* device specific resource */
3158 reg
= pci_iov_resource_bar(dev
, resno
, type
);
3163 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
3167 /* Some architectures require additional programming to enable VGA */
3168 static arch_set_vga_state_t arch_set_vga_state
;
3170 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
3172 arch_set_vga_state
= func
; /* NULL disables */
3175 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
3176 unsigned int command_bits
, bool change_bridge
)
3178 if (arch_set_vga_state
)
3179 return arch_set_vga_state(dev
, decode
, command_bits
,
3185 * pci_set_vga_state - set VGA decode state on device and parents if requested
3186 * @dev: the PCI device
3187 * @decode: true = enable decoding, false = disable decoding
3188 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3189 * @change_bridge: traverse ancestors and change bridges
3191 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
3192 unsigned int command_bits
, bool change_bridge
)
3194 struct pci_bus
*bus
;
3195 struct pci_dev
*bridge
;
3199 WARN_ON(command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
));
3201 /* ARCH specific VGA enables */
3202 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, change_bridge
);
3206 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3208 cmd
|= command_bits
;
3210 cmd
&= ~command_bits
;
3211 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3213 if (change_bridge
== false)
3220 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3223 cmd
|= PCI_BRIDGE_CTL_VGA
;
3225 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
3226 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3234 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3235 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
3236 static DEFINE_SPINLOCK(resource_alignment_lock
);
3239 * pci_specified_resource_alignment - get resource alignment specified by user.
3240 * @dev: the PCI device to get
3242 * RETURNS: Resource alignment if it is specified.
3243 * Zero if it is not specified.
3245 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
3247 int seg
, bus
, slot
, func
, align_order
, count
;
3248 resource_size_t align
= 0;
3251 spin_lock(&resource_alignment_lock
);
3252 p
= resource_alignment_param
;
3255 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
3261 if (sscanf(p
, "%x:%x:%x.%x%n",
3262 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
3264 if (sscanf(p
, "%x:%x.%x%n",
3265 &bus
, &slot
, &func
, &count
) != 3) {
3266 /* Invalid format */
3267 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
3273 if (seg
== pci_domain_nr(dev
->bus
) &&
3274 bus
== dev
->bus
->number
&&
3275 slot
== PCI_SLOT(dev
->devfn
) &&
3276 func
== PCI_FUNC(dev
->devfn
)) {
3277 if (align_order
== -1) {
3280 align
= 1 << align_order
;
3285 if (*p
!= ';' && *p
!= ',') {
3286 /* End of param or invalid format */
3291 spin_unlock(&resource_alignment_lock
);
3296 * pci_is_reassigndev - check if specified PCI is target device to reassign
3297 * @dev: the PCI device to check
3299 * RETURNS: non-zero for PCI device is a target device to reassign,
3302 int pci_is_reassigndev(struct pci_dev
*dev
)
3304 return (pci_specified_resource_alignment(dev
) != 0);
3307 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
3309 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
3310 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
3311 spin_lock(&resource_alignment_lock
);
3312 strncpy(resource_alignment_param
, buf
, count
);
3313 resource_alignment_param
[count
] = '\0';
3314 spin_unlock(&resource_alignment_lock
);
3318 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
3321 spin_lock(&resource_alignment_lock
);
3322 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
3323 spin_unlock(&resource_alignment_lock
);
3327 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
3329 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
3332 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
3333 const char *buf
, size_t count
)
3335 return pci_set_resource_alignment_param(buf
, count
);
3338 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
3339 pci_resource_alignment_store
);
3341 static int __init
pci_resource_alignment_sysfs_init(void)
3343 return bus_create_file(&pci_bus_type
,
3344 &bus_attr_resource_alignment
);
3347 late_initcall(pci_resource_alignment_sysfs_init
);
3349 static void __devinit
pci_no_domains(void)
3351 #ifdef CONFIG_PCI_DOMAINS
3352 pci_domains_supported
= 0;
3357 * pci_ext_cfg_enabled - can we access extended PCI config space?
3358 * @dev: The PCI device of the root bridge.
3360 * Returns 1 if we can access PCI extended config space (offsets
3361 * greater than 0xff). This is the default implementation. Architecture
3362 * implementations can override this.
3364 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
3369 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
3372 EXPORT_SYMBOL(pci_fixup_cardbus
);
3374 static int __init
pci_setup(char *str
)
3377 char *k
= strchr(str
, ',');
3380 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
3381 if (!strcmp(str
, "nomsi")) {
3383 } else if (!strcmp(str
, "noaer")) {
3385 } else if (!strcmp(str
, "nodomains")) {
3387 } else if (!strncmp(str
, "cbiosize=", 9)) {
3388 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
3389 } else if (!strncmp(str
, "cbmemsize=", 10)) {
3390 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
3391 } else if (!strncmp(str
, "resource_alignment=", 19)) {
3392 pci_set_resource_alignment_param(str
+ 19,
3394 } else if (!strncmp(str
, "ecrc=", 5)) {
3395 pcie_ecrc_get_policy(str
+ 5);
3396 } else if (!strncmp(str
, "hpiosize=", 9)) {
3397 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
3398 } else if (!strncmp(str
, "hpmemsize=", 10)) {
3399 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
3401 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
3409 early_param("pci", pci_setup
);
3411 EXPORT_SYMBOL(pci_reenable_device
);
3412 EXPORT_SYMBOL(pci_enable_device_io
);
3413 EXPORT_SYMBOL(pci_enable_device_mem
);
3414 EXPORT_SYMBOL(pci_enable_device
);
3415 EXPORT_SYMBOL(pcim_enable_device
);
3416 EXPORT_SYMBOL(pcim_pin_device
);
3417 EXPORT_SYMBOL(pci_disable_device
);
3418 EXPORT_SYMBOL(pci_find_capability
);
3419 EXPORT_SYMBOL(pci_bus_find_capability
);
3420 EXPORT_SYMBOL(pci_release_regions
);
3421 EXPORT_SYMBOL(pci_request_regions
);
3422 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3423 EXPORT_SYMBOL(pci_release_region
);
3424 EXPORT_SYMBOL(pci_request_region
);
3425 EXPORT_SYMBOL(pci_request_region_exclusive
);
3426 EXPORT_SYMBOL(pci_release_selected_regions
);
3427 EXPORT_SYMBOL(pci_request_selected_regions
);
3428 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3429 EXPORT_SYMBOL(pci_set_master
);
3430 EXPORT_SYMBOL(pci_clear_master
);
3431 EXPORT_SYMBOL(pci_set_mwi
);
3432 EXPORT_SYMBOL(pci_try_set_mwi
);
3433 EXPORT_SYMBOL(pci_clear_mwi
);
3434 EXPORT_SYMBOL_GPL(pci_intx
);
3435 EXPORT_SYMBOL(pci_assign_resource
);
3436 EXPORT_SYMBOL(pci_find_parent_resource
);
3437 EXPORT_SYMBOL(pci_select_bars
);
3439 EXPORT_SYMBOL(pci_set_power_state
);
3440 EXPORT_SYMBOL(pci_save_state
);
3441 EXPORT_SYMBOL(pci_restore_state
);
3442 EXPORT_SYMBOL(pci_pme_capable
);
3443 EXPORT_SYMBOL(pci_pme_active
);
3444 EXPORT_SYMBOL(pci_wake_from_d3
);
3445 EXPORT_SYMBOL(pci_target_state
);
3446 EXPORT_SYMBOL(pci_prepare_to_sleep
);
3447 EXPORT_SYMBOL(pci_back_from_sleep
);
3448 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);