drivers/pci/pci.h

   1 #ifndef DRIVERS_PCI_H
   2 #define DRIVERS_PCI_H
   3
   4 #include <linux/workqueue.h>
   5
   6 #define PCI_CFG_SPACE_SIZE      256
   7 #define PCI_CFG_SPACE_EXP_SIZE  4096
   8
   9 /* Functions internal to the PCI core code */
  10
  11 extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
  12 extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  13 extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  14 #ifndef CONFIG_DMI
  15 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  16 { return; }
  17 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  18 { return; }
  19 #else
  20 extern void pci_create_firmware_label_files(struct pci_dev *pdev);
  21 extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
  22 #endif
  23 extern void pci_cleanup_rom(struct pci_dev *dev);
  24 #ifdef HAVE_PCI_MMAP
  25 extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
  26                          struct vm_area_struct *vma);
  27 #endif
  28 int pci_probe_reset_function(struct pci_dev *dev);
  29
  30 /**
  31  * struct pci_platform_pm_ops - Firmware PM callbacks
  32  *
  33  * @is_manageable: returns 'true' if given device is power manageable by the
  34  *                 platform firmware
  35  *
  36  * @set_state: invokes the platform firmware to set the device's power state
  37  *
  38  * @choose_state: returns PCI power state of given device preferred by the
  39  *                platform; to be used during system-wide transitions from a
  40  *                sleeping state to the working state and vice versa
  41  *
  42  * @can_wakeup: returns 'true' if given device is capable of waking up the
  43  *              system from a sleeping state
  44  *
  45  * @sleep_wake: enables/disables the system wake up capability of given device
  46  *
  47  * @run_wake: enables/disables the platform to generate run-time wake-up events
  48  *              for given device (the device's wake-up capability has to be
  49  *              enabled by @sleep_wake for this feature to work)
  50  *
  51  * If given platform is generally capable of power managing PCI devices, all of
  52  * these callbacks are mandatory.
  53  */
  54 struct pci_platform_pm_ops {
  55         bool (*is_manageable)(struct pci_dev *dev);
  56         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  57         pci_power_t (*choose_state)(struct pci_dev *dev);
  58         bool (*can_wakeup)(struct pci_dev *dev);
  59         int (*sleep_wake)(struct pci_dev *dev, bool enable);
  60         int (*run_wake)(struct pci_dev *dev, bool enable);
  61 };
  62
  63 extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
  64 extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  65 extern void pci_disable_enabled_device(struct pci_dev *dev);
  66 extern bool pci_check_pme_status(struct pci_dev *dev);
  67 extern int pci_finish_runtime_suspend(struct pci_dev *dev);
  68 extern void pci_wakeup_event(struct pci_dev *dev);
  69 extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  70 extern void pci_pme_wakeup_bus(struct pci_bus *bus);
  71 extern void pci_pm_init(struct pci_dev *dev);
  72 extern void platform_pci_wakeup_init(struct pci_dev *dev);
  73 extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  74
  75 static inline bool pci_is_bridge(struct pci_dev *pci_dev)
  76 {
  77         return !!(pci_dev->subordinate);
  78 }
  79
  80 extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
  81 extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
  82 extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
  83 extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
  84 extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
  85 extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
  86
  87 struct pci_vpd_ops {
  88         ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
  89         ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
  90         void (*release)(struct pci_dev *dev);
  91 };
  92
  93 struct pci_vpd {
  94         unsigned int len;
  95         const struct pci_vpd_ops *ops;
  96         struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
  97 };
  98
  99 extern int pci_vpd_pci22_init(struct pci_dev *dev);
 100 static inline void pci_vpd_release(struct pci_dev *dev)
 101 {
 102         if (dev->vpd)
 103                 dev->vpd->ops->release(dev);
 104 }
 105
 106 /* PCI /proc functions */
 107 #ifdef CONFIG_PROC_FS
 108 extern int pci_proc_attach_device(struct pci_dev *dev);
 109 extern int pci_proc_detach_device(struct pci_dev *dev);
 110 extern int pci_proc_detach_bus(struct pci_bus *bus);
 111 #else
 112 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 113 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 114 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 115 #endif
 116
 117 /* Functions for PCI Hotplug drivers to use */
 118 extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
 119
 120 #ifdef HAVE_PCI_LEGACY
 121 extern void pci_create_legacy_files(struct pci_bus *bus);
 122 extern void pci_remove_legacy_files(struct pci_bus *bus);
 123 #else
 124 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 125 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 126 #endif
 127
 128 /* Lock for read/write access to pci device and bus lists */
 129 extern struct rw_semaphore pci_bus_sem;
 130
 131 extern unsigned int pci_pm_d3_delay;
 132
 133 #ifdef CONFIG_PCI_MSI
 134 void pci_no_msi(void);
 135 extern void pci_msi_init_pci_dev(struct pci_dev *dev);
 136 #else
 137 static inline void pci_no_msi(void) { }
 138 static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
 139 #endif
 140
 141 #ifdef CONFIG_PCIEAER
 142 void pci_no_aer(void);
 143 #else
 144 static inline void pci_no_aer(void) { }
 145 #endif
 146
 147 static inline int pci_no_d1d2(struct pci_dev *dev)
 148 {
 149         unsigned int parent_dstates = 0;
 150
 151         if (dev->bus->self)
 152                 parent_dstates = dev->bus->self->no_d1d2;
 153         return (dev->no_d1d2 || parent_dstates);
 154
 155 }
 156 extern struct device_attribute pci_dev_attrs[];
 157 extern struct device_attribute dev_attr_cpuaffinity;
 158 extern struct device_attribute dev_attr_cpulistaffinity;
 159 #ifdef CONFIG_HOTPLUG
 160 extern struct bus_attribute pci_bus_attrs[];
 161 #else
 162 #define pci_bus_attrs   NULL
 163 #endif
 164
 165
 166 /**
 167  * pci_match_one_device - Tell if a PCI device structure has a matching
 168  *                        PCI device id structure
 169  * @id: single PCI device id structure to match
 170  * @dev: the PCI device structure to match against
 171  *
 172  * Returns the matching pci_device_id structure or %NULL if there is no match.
 173  */
 174 static inline const struct pci_device_id *
 175 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 176 {
 177         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 178             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 179             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 180             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 181             !((id->class ^ dev->class) & id->class_mask))
 182                 return id;
 183         return NULL;
 184 }
 185
 186 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
 187
 188 /* PCI slot sysfs helper code */
 189 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 190
 191 extern struct kset *pci_slots_kset;
 192
 193 struct pci_slot_attribute {
 194         struct attribute attr;
 195         ssize_t (*show)(struct pci_slot *, char *);
 196         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 197 };
 198 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 199
 200 enum pci_bar_type {
 201         pci_bar_unknown,        /* Standard PCI BAR probe */
 202         pci_bar_io,             /* An io port BAR */
 203         pci_bar_mem32,          /* A 32-bit memory BAR */
 204         pci_bar_mem64,          /* A 64-bit memory BAR */
 205 };
 206
 207 extern int pci_setup_device(struct pci_dev *dev);
 208 extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 209                                 struct resource *res, unsigned int reg);
 210 extern int pci_resource_bar(struct pci_dev *dev, int resno,
 211                             enum pci_bar_type *type);
 212 extern int pci_bus_add_child(struct pci_bus *bus);
 213 extern void pci_enable_ari(struct pci_dev *dev);
 214 /**
 215  * pci_ari_enabled - query ARI forwarding status
 216  * @bus: the PCI bus
 217  *
 218  * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 219  */
 220 static inline int pci_ari_enabled(struct pci_bus *bus)
 221 {
 222         return bus->self && bus->self->ari_enabled;
 223 }
 224
 225 #ifdef CONFIG_PCI_QUIRKS
 226 extern int pci_is_reassigndev(struct pci_dev *dev);
 227 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
 228 extern void pci_disable_bridge_window(struct pci_dev *dev);
 229 #endif
 230
 231 /* Single Root I/O Virtualization */
 232 struct pci_sriov {
 233         int pos;                /* capability position */
 234         int nres;               /* number of resources */
 235         u32 cap;                /* SR-IOV Capabilities */
 236         u16 ctrl;               /* SR-IOV Control */
 237         u16 total;              /* total VFs associated with the PF */
 238         u16 initial;            /* initial VFs associated with the PF */
 239         u16 nr_virtfn;          /* number of VFs available */
 240         u16 offset;             /* first VF Routing ID offset */
 241         u16 stride;             /* following VF stride */
 242         u32 pgsz;               /* page size for BAR alignment */
 243         u8 link;                /* Function Dependency Link */
 244         struct pci_dev *dev;    /* lowest numbered PF */
 245         struct pci_dev *self;   /* this PF */
 246         struct mutex lock;      /* lock for VF bus */
 247         struct work_struct mtask; /* VF Migration task */
 248         u8 __iomem *mstate;     /* VF Migration State Array */
 249 };
 250
 251 /* Address Translation Service */
 252 struct pci_ats {
 253         int pos;        /* capability position */
 254         int stu;        /* Smallest Translation Unit */
 255         int qdep;       /* Invalidate Queue Depth */
 256         int ref_cnt;    /* Physical Function reference count */
 257         unsigned int is_enabled:1;      /* Enable bit is set */
 258 };
 259
 260 #ifdef CONFIG_PCI_IOV
 261 extern int pci_iov_init(struct pci_dev *dev);
 262 extern void pci_iov_release(struct pci_dev *dev);
 263 extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
 264                                 enum pci_bar_type *type);
 265 extern int pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 266 extern void pci_restore_iov_state(struct pci_dev *dev);
 267 extern int pci_iov_bus_range(struct pci_bus *bus);
 268
 269 extern int pci_enable_ats(struct pci_dev *dev, int ps);
 270 extern void pci_disable_ats(struct pci_dev *dev);
 271 extern int pci_ats_queue_depth(struct pci_dev *dev);
 272 /**
 273  * pci_ats_enabled - query the ATS status
 274  * @dev: the PCI device
 275  *
 276  * Returns 1 if ATS capability is enabled, or 0 if not.
 277  */
 278 static inline int pci_ats_enabled(struct pci_dev *dev)
 279 {
 280         return dev->ats && dev->ats->is_enabled;
 281 }
 282 #else
 283 static inline int pci_iov_init(struct pci_dev *dev)
 284 {
 285         return -ENODEV;
 286 }
 287 static inline void pci_iov_release(struct pci_dev *dev)
 288
 289 {
 290 }
 291 static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
 292                                        enum pci_bar_type *type)
 293 {
 294         return 0;
 295 }
 296 static inline void pci_restore_iov_state(struct pci_dev *dev)
 297 {
 298 }
 299 static inline int pci_iov_bus_range(struct pci_bus *bus)
 300 {
 301         return 0;
 302 }
 303
 304 static inline int pci_enable_ats(struct pci_dev *dev, int ps)
 305 {
 306         return -ENODEV;
 307 }
 308 static inline void pci_disable_ats(struct pci_dev *dev)
 309 {
 310 }
 311 static inline int pci_ats_queue_depth(struct pci_dev *dev)
 312 {
 313         return -ENODEV;
 314 }
 315 static inline int pci_ats_enabled(struct pci_dev *dev)
 316 {
 317         return 0;
 318 }
 319 #endif /* CONFIG_PCI_IOV */
 320
 321 static inline int pci_resource_alignment(struct pci_dev *dev,
 322                                          struct resource *res)
 323 {
 324 #ifdef CONFIG_PCI_IOV
 325         int resno = res - dev->resource;
 326
 327         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 328                 return pci_sriov_resource_alignment(dev, resno);
 329 #endif
 330         return resource_alignment(res);
 331 }
 332
 333 extern void pci_enable_acs(struct pci_dev *dev);
 334
 335 struct pci_dev_reset_methods {
 336         u16 vendor;
 337         u16 device;
 338         int (*reset)(struct pci_dev *dev, int probe);
 339 };
 340
 341 #ifdef CONFIG_PCI_QUIRKS
 342 extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 343 #else
 344 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 345 {
 346         return -ENOTTY;
 347 }
 348 #endif
 349
 350 #endif /* DRIVERS_PCI_H */