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PCI: print resources consistently with %pRt
[deliverable/linux.git] / drivers / pci / probe.c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
21
22
23 static int find_anything(struct device *dev, void *data)
24 {
25 return 1;
26 }
27
28 /*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33 int no_pci_devices(void)
34 {
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42 }
43 EXPORT_SYMBOL(no_pci_devices);
44
45 /*
46 * PCI Bus Class Devices
47 */
48 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
49 int type,
50 struct device_attribute *attr,
51 char *buf)
52 {
53 int ret;
54 const struct cpumask *cpumask;
55
56 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
57 ret = type?
58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
60 buf[ret++] = '\n';
61 buf[ret] = '\0';
62 return ret;
63 }
64
65 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
67 char *buf)
68 {
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
70 }
71
72 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
74 char *buf)
75 {
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
77 }
78
79 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
81
82 /*
83 * PCI Bus Class
84 */
85 static void release_pcibus_dev(struct device *dev)
86 {
87 struct pci_bus *pci_bus = to_pci_bus(dev);
88
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
91 kfree(pci_bus);
92 }
93
94 static struct class pcibus_class = {
95 .name = "pci_bus",
96 .dev_release = &release_pcibus_dev,
97 };
98
99 static int __init pcibus_class_init(void)
100 {
101 return class_register(&pcibus_class);
102 }
103 postcore_initcall(pcibus_class_init);
104
105 /*
106 * Translate the low bits of the PCI base
107 * to the resource type
108 */
109 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
110 {
111 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
112 return IORESOURCE_IO;
113
114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
115 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
116
117 return IORESOURCE_MEM;
118 }
119
120 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
121 {
122 u64 size = mask & maxbase; /* Find the significant bits */
123 if (!size)
124 return 0;
125
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size = (size & ~(size-1)) - 1;
129
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base == maxbase && ((base | size) & mask) != mask)
133 return 0;
134
135 return size;
136 }
137
138 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
139 {
140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
141 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
142 return pci_bar_io;
143 }
144
145 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
146
147 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
148 return pci_bar_mem64;
149 return pci_bar_mem32;
150 }
151
152 /**
153 * pci_read_base - read a PCI BAR
154 * @dev: the PCI device
155 * @type: type of the BAR
156 * @res: resource buffer to be filled in
157 * @pos: BAR position in the config space
158 *
159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
160 */
161 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
162 struct resource *res, unsigned int pos)
163 {
164 u32 l, sz, mask;
165
166 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
167
168 res->name = pci_name(dev);
169
170 pci_read_config_dword(dev, pos, &l);
171 pci_write_config_dword(dev, pos, mask);
172 pci_read_config_dword(dev, pos, &sz);
173 pci_write_config_dword(dev, pos, l);
174
175 /*
176 * All bits set in sz means the device isn't working properly.
177 * If the BAR isn't implemented, all bits must be 0. If it's a
178 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
179 * 1 must be clear.
180 */
181 if (!sz || sz == 0xffffffff)
182 goto fail;
183
184 /*
185 * I don't know how l can have all bits set. Copied from old code.
186 * Maybe it fixes a bug on some ancient platform.
187 */
188 if (l == 0xffffffff)
189 l = 0;
190
191 if (type == pci_bar_unknown) {
192 type = decode_bar(res, l);
193 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
194 if (type == pci_bar_io) {
195 l &= PCI_BASE_ADDRESS_IO_MASK;
196 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
197 } else {
198 l &= PCI_BASE_ADDRESS_MEM_MASK;
199 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
200 }
201 } else {
202 res->flags |= (l & IORESOURCE_ROM_ENABLE);
203 l &= PCI_ROM_ADDRESS_MASK;
204 mask = (u32)PCI_ROM_ADDRESS_MASK;
205 }
206
207 if (type == pci_bar_mem64) {
208 u64 l64 = l;
209 u64 sz64 = sz;
210 u64 mask64 = mask | (u64)~0 << 32;
211
212 pci_read_config_dword(dev, pos + 4, &l);
213 pci_write_config_dword(dev, pos + 4, ~0);
214 pci_read_config_dword(dev, pos + 4, &sz);
215 pci_write_config_dword(dev, pos + 4, l);
216
217 l64 |= ((u64)l << 32);
218 sz64 |= ((u64)sz << 32);
219
220 sz64 = pci_size(l64, sz64, mask64);
221
222 if (!sz64)
223 goto fail;
224
225 res->flags |= IORESOURCE_MEM_64;
226
227 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
228 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
229 goto fail;
230 } else if ((sizeof(resource_size_t) < 8) && l) {
231 /* Address above 32-bit boundary; disable the BAR */
232 pci_write_config_dword(dev, pos, 0);
233 pci_write_config_dword(dev, pos + 4, 0);
234 res->start = 0;
235 res->end = sz64;
236 } else {
237 res->start = l64;
238 res->end = l64 + sz64;
239 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pRt\n",
240 pos, res);
241 }
242 } else {
243 sz = pci_size(l, sz, mask);
244
245 if (!sz)
246 goto fail;
247
248 res->start = l;
249 res->end = l + sz;
250
251 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pRt\n", pos, res);
252 }
253
254 out:
255 return (type == pci_bar_mem64) ? 1 : 0;
256 fail:
257 res->flags = 0;
258 goto out;
259 }
260
261 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
262 {
263 unsigned int pos, reg;
264
265 for (pos = 0; pos < howmany; pos++) {
266 struct resource *res = &dev->resource[pos];
267 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
268 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
269 }
270
271 if (rom) {
272 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
273 dev->rom_base_reg = rom;
274 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
275 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
276 IORESOURCE_SIZEALIGN;
277 __pci_read_base(dev, pci_bar_mem32, res, rom);
278 }
279 }
280
281 void __devinit pci_read_bridge_bases(struct pci_bus *child)
282 {
283 struct pci_dev *dev = child->self;
284 u8 io_base_lo, io_limit_lo;
285 u16 mem_base_lo, mem_limit_lo;
286 unsigned long base, limit;
287 struct resource *res;
288 int i;
289
290 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
291 return;
292
293 if (dev->transparent) {
294 dev_info(&dev->dev, "transparent bridge\n");
295 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
296 child->resource[i] = child->parent->resource[i - 3];
297 }
298
299 res = child->resource[0];
300 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
301 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
302 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
303 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
304
305 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
306 u16 io_base_hi, io_limit_hi;
307 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
308 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
309 base |= (io_base_hi << 16);
310 limit |= (io_limit_hi << 16);
311 }
312
313 if (base <= limit) {
314 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
315 if (!res->start)
316 res->start = base;
317 if (!res->end)
318 res->end = limit + 0xfff;
319 dev_printk(KERN_DEBUG, &dev->dev, "bridge window: %pRt\n", res);
320 }
321
322 res = child->resource[1];
323 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
324 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
325 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
326 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
327 if (base <= limit) {
328 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
329 res->start = base;
330 res->end = limit + 0xfffff;
331 dev_printk(KERN_DEBUG, &dev->dev, "bridge window: %pRt\n", res);
332 }
333
334 res = child->resource[2];
335 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
336 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
337 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
338 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
339
340 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
341 u32 mem_base_hi, mem_limit_hi;
342 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
343 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
344
345 /*
346 * Some bridges set the base > limit by default, and some
347 * (broken) BIOSes do not initialize them. If we find
348 * this, just assume they are not being used.
349 */
350 if (mem_base_hi <= mem_limit_hi) {
351 #if BITS_PER_LONG == 64
352 base |= ((long) mem_base_hi) << 32;
353 limit |= ((long) mem_limit_hi) << 32;
354 #else
355 if (mem_base_hi || mem_limit_hi) {
356 dev_err(&dev->dev, "can't handle 64-bit "
357 "address space for bridge\n");
358 return;
359 }
360 #endif
361 }
362 }
363 if (base <= limit) {
364 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
365 IORESOURCE_MEM | IORESOURCE_PREFETCH;
366 if (res->flags & PCI_PREF_RANGE_TYPE_64)
367 res->flags |= IORESOURCE_MEM_64;
368 res->start = base;
369 res->end = limit + 0xfffff;
370 dev_printk(KERN_DEBUG, &dev->dev, "bridge window: %pRt\n", res);
371 }
372 }
373
374 static struct pci_bus * pci_alloc_bus(void)
375 {
376 struct pci_bus *b;
377
378 b = kzalloc(sizeof(*b), GFP_KERNEL);
379 if (b) {
380 INIT_LIST_HEAD(&b->node);
381 INIT_LIST_HEAD(&b->children);
382 INIT_LIST_HEAD(&b->devices);
383 INIT_LIST_HEAD(&b->slots);
384 }
385 return b;
386 }
387
388 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
389 struct pci_dev *bridge, int busnr)
390 {
391 struct pci_bus *child;
392 int i;
393
394 /*
395 * Allocate a new bus, and inherit stuff from the parent..
396 */
397 child = pci_alloc_bus();
398 if (!child)
399 return NULL;
400
401 child->parent = parent;
402 child->ops = parent->ops;
403 child->sysdata = parent->sysdata;
404 child->bus_flags = parent->bus_flags;
405
406 /* initialize some portions of the bus device, but don't register it
407 * now as the parent is not properly set up yet. This device will get
408 * registered later in pci_bus_add_devices()
409 */
410 child->dev.class = &pcibus_class;
411 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
412
413 /*
414 * Set up the primary, secondary and subordinate
415 * bus numbers.
416 */
417 child->number = child->secondary = busnr;
418 child->primary = parent->secondary;
419 child->subordinate = 0xff;
420
421 if (!bridge)
422 return child;
423
424 child->self = bridge;
425 child->bridge = get_device(&bridge->dev);
426
427 /* Set up default resource pointers and names.. */
428 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
429 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
430 child->resource[i]->name = child->name;
431 }
432 bridge->subordinate = child;
433
434 return child;
435 }
436
437 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
438 {
439 struct pci_bus *child;
440
441 child = pci_alloc_child_bus(parent, dev, busnr);
442 if (child) {
443 down_write(&pci_bus_sem);
444 list_add_tail(&child->node, &parent->children);
445 up_write(&pci_bus_sem);
446 }
447 return child;
448 }
449
450 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
451 {
452 struct pci_bus *parent = child->parent;
453
454 /* Attempts to fix that up are really dangerous unless
455 we're going to re-assign all bus numbers. */
456 if (!pcibios_assign_all_busses())
457 return;
458
459 while (parent->parent && parent->subordinate < max) {
460 parent->subordinate = max;
461 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
462 parent = parent->parent;
463 }
464 }
465
466 /*
467 * If it's a bridge, configure it and scan the bus behind it.
468 * For CardBus bridges, we don't scan behind as the devices will
469 * be handled by the bridge driver itself.
470 *
471 * We need to process bridges in two passes -- first we scan those
472 * already configured by the BIOS and after we are done with all of
473 * them, we proceed to assigning numbers to the remaining buses in
474 * order to avoid overlaps between old and new bus numbers.
475 */
476 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
477 {
478 struct pci_bus *child;
479 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
480 u32 buses, i, j = 0;
481 u16 bctl;
482 int broken = 0;
483
484 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
485
486 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
487 buses & 0xffffff, pass);
488
489 /* Check if setup is sensible at all */
490 if (!pass &&
491 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
492 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
493 broken = 1;
494 }
495
496 /* Disable MasterAbortMode during probing to avoid reporting
497 of bus errors (in some architectures) */
498 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
499 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
500 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
501
502 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
503 unsigned int cmax, busnr;
504 /*
505 * Bus already configured by firmware, process it in the first
506 * pass and just note the configuration.
507 */
508 if (pass)
509 goto out;
510 busnr = (buses >> 8) & 0xFF;
511
512 /*
513 * If we already got to this bus through a different bridge,
514 * don't re-add it. This can happen with the i450NX chipset.
515 *
516 * However, we continue to descend down the hierarchy and
517 * scan remaining child buses.
518 */
519 child = pci_find_bus(pci_domain_nr(bus), busnr);
520 if (!child) {
521 child = pci_add_new_bus(bus, dev, busnr);
522 if (!child)
523 goto out;
524 child->primary = buses & 0xFF;
525 child->subordinate = (buses >> 16) & 0xFF;
526 child->bridge_ctl = bctl;
527 }
528
529 cmax = pci_scan_child_bus(child);
530 if (cmax > max)
531 max = cmax;
532 if (child->subordinate > max)
533 max = child->subordinate;
534 } else {
535 /*
536 * We need to assign a number to this bus which we always
537 * do in the second pass.
538 */
539 if (!pass) {
540 if (pcibios_assign_all_busses() || broken)
541 /* Temporarily disable forwarding of the
542 configuration cycles on all bridges in
543 this bus segment to avoid possible
544 conflicts in the second pass between two
545 bridges programmed with overlapping
546 bus ranges. */
547 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
548 buses & ~0xffffff);
549 goto out;
550 }
551
552 /* Clear errors */
553 pci_write_config_word(dev, PCI_STATUS, 0xffff);
554
555 /* Prevent assigning a bus number that already exists.
556 * This can happen when a bridge is hot-plugged */
557 if (pci_find_bus(pci_domain_nr(bus), max+1))
558 goto out;
559 child = pci_add_new_bus(bus, dev, ++max);
560 buses = (buses & 0xff000000)
561 | ((unsigned int)(child->primary) << 0)
562 | ((unsigned int)(child->secondary) << 8)
563 | ((unsigned int)(child->subordinate) << 16);
564
565 /*
566 * yenta.c forces a secondary latency timer of 176.
567 * Copy that behaviour here.
568 */
569 if (is_cardbus) {
570 buses &= ~0xff000000;
571 buses |= CARDBUS_LATENCY_TIMER << 24;
572 }
573
574 /*
575 * We need to blast all three values with a single write.
576 */
577 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
578
579 if (!is_cardbus) {
580 child->bridge_ctl = bctl;
581 /*
582 * Adjust subordinate busnr in parent buses.
583 * We do this before scanning for children because
584 * some devices may not be detected if the bios
585 * was lazy.
586 */
587 pci_fixup_parent_subordinate_busnr(child, max);
588 /* Now we can scan all subordinate buses... */
589 max = pci_scan_child_bus(child);
590 /*
591 * now fix it up again since we have found
592 * the real value of max.
593 */
594 pci_fixup_parent_subordinate_busnr(child, max);
595 } else {
596 /*
597 * For CardBus bridges, we leave 4 bus numbers
598 * as cards with a PCI-to-PCI bridge can be
599 * inserted later.
600 */
601 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
602 struct pci_bus *parent = bus;
603 if (pci_find_bus(pci_domain_nr(bus),
604 max+i+1))
605 break;
606 while (parent->parent) {
607 if ((!pcibios_assign_all_busses()) &&
608 (parent->subordinate > max) &&
609 (parent->subordinate <= max+i)) {
610 j = 1;
611 }
612 parent = parent->parent;
613 }
614 if (j) {
615 /*
616 * Often, there are two cardbus bridges
617 * -- try to leave one valid bus number
618 * for each one.
619 */
620 i /= 2;
621 break;
622 }
623 }
624 max += i;
625 pci_fixup_parent_subordinate_busnr(child, max);
626 }
627 /*
628 * Set the subordinate bus number to its real value.
629 */
630 child->subordinate = max;
631 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
632 }
633
634 sprintf(child->name,
635 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
636 pci_domain_nr(bus), child->number);
637
638 /* Has only triggered on CardBus, fixup is in yenta_socket */
639 while (bus->parent) {
640 if ((child->subordinate > bus->subordinate) ||
641 (child->number > bus->subordinate) ||
642 (child->number < bus->number) ||
643 (child->subordinate < bus->number)) {
644 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
645 "hidden behind%s bridge #%02x (-#%02x)\n",
646 child->number, child->subordinate,
647 (bus->number > child->subordinate &&
648 bus->subordinate < child->number) ?
649 "wholly" : "partially",
650 bus->self->transparent ? " transparent" : "",
651 bus->number, bus->subordinate);
652 }
653 bus = bus->parent;
654 }
655
656 out:
657 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
658
659 return max;
660 }
661
662 /*
663 * Read interrupt line and base address registers.
664 * The architecture-dependent code can tweak these, of course.
665 */
666 static void pci_read_irq(struct pci_dev *dev)
667 {
668 unsigned char irq;
669
670 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
671 dev->pin = irq;
672 if (irq)
673 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
674 dev->irq = irq;
675 }
676
677 static void set_pcie_port_type(struct pci_dev *pdev)
678 {
679 int pos;
680 u16 reg16;
681
682 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
683 if (!pos)
684 return;
685 pdev->is_pcie = 1;
686 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
687 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
688 }
689
690 static void set_pcie_hotplug_bridge(struct pci_dev *pdev)
691 {
692 int pos;
693 u16 reg16;
694 u32 reg32;
695
696 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
697 if (!pos)
698 return;
699 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
700 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
701 return;
702 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
703 if (reg32 & PCI_EXP_SLTCAP_HPC)
704 pdev->is_hotplug_bridge = 1;
705 }
706
707 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
708
709 /**
710 * pci_setup_device - fill in class and map information of a device
711 * @dev: the device structure to fill
712 *
713 * Initialize the device structure with information about the device's
714 * vendor,class,memory and IO-space addresses,IRQ lines etc.
715 * Called at initialisation of the PCI subsystem and by CardBus services.
716 * Returns 0 on success and negative if unknown type of device (not normal,
717 * bridge or CardBus).
718 */
719 int pci_setup_device(struct pci_dev *dev)
720 {
721 u32 class;
722 u8 hdr_type;
723 struct pci_slot *slot;
724
725 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
726 return -EIO;
727
728 dev->sysdata = dev->bus->sysdata;
729 dev->dev.parent = dev->bus->bridge;
730 dev->dev.bus = &pci_bus_type;
731 dev->hdr_type = hdr_type & 0x7f;
732 dev->multifunction = !!(hdr_type & 0x80);
733 dev->error_state = pci_channel_io_normal;
734 set_pcie_port_type(dev);
735
736 list_for_each_entry(slot, &dev->bus->slots, list)
737 if (PCI_SLOT(dev->devfn) == slot->number)
738 dev->slot = slot;
739
740 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
741 set this higher, assuming the system even supports it. */
742 dev->dma_mask = 0xffffffff;
743
744 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
745 dev->bus->number, PCI_SLOT(dev->devfn),
746 PCI_FUNC(dev->devfn));
747
748 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
749 dev->revision = class & 0xff;
750 class >>= 8; /* upper 3 bytes */
751 dev->class = class;
752 class >>= 8;
753
754 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
755 dev->vendor, dev->device, class, dev->hdr_type);
756
757 /* need to have dev->class ready */
758 dev->cfg_size = pci_cfg_space_size(dev);
759
760 /* "Unknown power state" */
761 dev->current_state = PCI_UNKNOWN;
762
763 /* Early fixups, before probing the BARs */
764 pci_fixup_device(pci_fixup_early, dev);
765 /* device class may be changed after fixup */
766 class = dev->class >> 8;
767
768 switch (dev->hdr_type) { /* header type */
769 case PCI_HEADER_TYPE_NORMAL: /* standard header */
770 if (class == PCI_CLASS_BRIDGE_PCI)
771 goto bad;
772 pci_read_irq(dev);
773 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
774 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
775 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
776
777 /*
778 * Do the ugly legacy mode stuff here rather than broken chip
779 * quirk code. Legacy mode ATA controllers have fixed
780 * addresses. These are not always echoed in BAR0-3, and
781 * BAR0-3 in a few cases contain junk!
782 */
783 if (class == PCI_CLASS_STORAGE_IDE) {
784 u8 progif;
785 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
786 if ((progif & 1) == 0) {
787 dev->resource[0].start = 0x1F0;
788 dev->resource[0].end = 0x1F7;
789 dev->resource[0].flags = LEGACY_IO_RESOURCE;
790 dev->resource[1].start = 0x3F6;
791 dev->resource[1].end = 0x3F6;
792 dev->resource[1].flags = LEGACY_IO_RESOURCE;
793 }
794 if ((progif & 4) == 0) {
795 dev->resource[2].start = 0x170;
796 dev->resource[2].end = 0x177;
797 dev->resource[2].flags = LEGACY_IO_RESOURCE;
798 dev->resource[3].start = 0x376;
799 dev->resource[3].end = 0x376;
800 dev->resource[3].flags = LEGACY_IO_RESOURCE;
801 }
802 }
803 break;
804
805 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
806 if (class != PCI_CLASS_BRIDGE_PCI)
807 goto bad;
808 /* The PCI-to-PCI bridge spec requires that subtractive
809 decoding (i.e. transparent) bridge must have programming
810 interface code of 0x01. */
811 pci_read_irq(dev);
812 dev->transparent = ((dev->class & 0xff) == 1);
813 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
814 set_pcie_hotplug_bridge(dev);
815 break;
816
817 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
818 if (class != PCI_CLASS_BRIDGE_CARDBUS)
819 goto bad;
820 pci_read_irq(dev);
821 pci_read_bases(dev, 1, 0);
822 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
823 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
824 break;
825
826 default: /* unknown header */
827 dev_err(&dev->dev, "unknown header type %02x, "
828 "ignoring device\n", dev->hdr_type);
829 return -EIO;
830
831 bad:
832 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
833 "type %02x)\n", class, dev->hdr_type);
834 dev->class = PCI_CLASS_NOT_DEFINED;
835 }
836
837 /* We found a fine healthy device, go go go... */
838 return 0;
839 }
840
841 static void pci_release_capabilities(struct pci_dev *dev)
842 {
843 pci_vpd_release(dev);
844 pci_iov_release(dev);
845 }
846
847 /**
848 * pci_release_dev - free a pci device structure when all users of it are finished.
849 * @dev: device that's been disconnected
850 *
851 * Will be called only by the device core when all users of this pci device are
852 * done.
853 */
854 static void pci_release_dev(struct device *dev)
855 {
856 struct pci_dev *pci_dev;
857
858 pci_dev = to_pci_dev(dev);
859 pci_release_capabilities(pci_dev);
860 kfree(pci_dev);
861 }
862
863 /**
864 * pci_cfg_space_size - get the configuration space size of the PCI device.
865 * @dev: PCI device
866 *
867 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
868 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
869 * access it. Maybe we don't have a way to generate extended config space
870 * accesses, or the device is behind a reverse Express bridge. So we try
871 * reading the dword at 0x100 which must either be 0 or a valid extended
872 * capability header.
873 */
874 int pci_cfg_space_size_ext(struct pci_dev *dev)
875 {
876 u32 status;
877 int pos = PCI_CFG_SPACE_SIZE;
878
879 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
880 goto fail;
881 if (status == 0xffffffff)
882 goto fail;
883
884 return PCI_CFG_SPACE_EXP_SIZE;
885
886 fail:
887 return PCI_CFG_SPACE_SIZE;
888 }
889
890 int pci_cfg_space_size(struct pci_dev *dev)
891 {
892 int pos;
893 u32 status;
894 u16 class;
895
896 class = dev->class >> 8;
897 if (class == PCI_CLASS_BRIDGE_HOST)
898 return pci_cfg_space_size_ext(dev);
899
900 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
901 if (!pos) {
902 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
903 if (!pos)
904 goto fail;
905
906 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
907 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
908 goto fail;
909 }
910
911 return pci_cfg_space_size_ext(dev);
912
913 fail:
914 return PCI_CFG_SPACE_SIZE;
915 }
916
917 static void pci_release_bus_bridge_dev(struct device *dev)
918 {
919 kfree(dev);
920 }
921
922 struct pci_dev *alloc_pci_dev(void)
923 {
924 struct pci_dev *dev;
925
926 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
927 if (!dev)
928 return NULL;
929
930 INIT_LIST_HEAD(&dev->bus_list);
931
932 return dev;
933 }
934 EXPORT_SYMBOL(alloc_pci_dev);
935
936 /*
937 * Read the config data for a PCI device, sanity-check it
938 * and fill in the dev structure...
939 */
940 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
941 {
942 struct pci_dev *dev;
943 u32 l;
944 int delay = 1;
945
946 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
947 return NULL;
948
949 /* some broken boards return 0 or ~0 if a slot is empty: */
950 if (l == 0xffffffff || l == 0x00000000 ||
951 l == 0x0000ffff || l == 0xffff0000)
952 return NULL;
953
954 /* Configuration request Retry Status */
955 while (l == 0xffff0001) {
956 msleep(delay);
957 delay *= 2;
958 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
959 return NULL;
960 /* Card hasn't responded in 60 seconds? Must be stuck. */
961 if (delay > 60 * 1000) {
962 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
963 "responding\n", pci_domain_nr(bus),
964 bus->number, PCI_SLOT(devfn),
965 PCI_FUNC(devfn));
966 return NULL;
967 }
968 }
969
970 dev = alloc_pci_dev();
971 if (!dev)
972 return NULL;
973
974 dev->bus = bus;
975 dev->devfn = devfn;
976 dev->vendor = l & 0xffff;
977 dev->device = (l >> 16) & 0xffff;
978
979 if (pci_setup_device(dev)) {
980 kfree(dev);
981 return NULL;
982 }
983
984 return dev;
985 }
986
987 static void pci_init_capabilities(struct pci_dev *dev)
988 {
989 /* MSI/MSI-X list */
990 pci_msi_init_pci_dev(dev);
991
992 /* Buffers for saving PCIe and PCI-X capabilities */
993 pci_allocate_cap_save_buffers(dev);
994
995 /* Power Management */
996 pci_pm_init(dev);
997 platform_pci_wakeup_init(dev);
998
999 /* Vital Product Data */
1000 pci_vpd_pci22_init(dev);
1001
1002 /* Alternative Routing-ID Forwarding */
1003 pci_enable_ari(dev);
1004
1005 /* Single Root I/O Virtualization */
1006 pci_iov_init(dev);
1007 }
1008
1009 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1010 {
1011 device_initialize(&dev->dev);
1012 dev->dev.release = pci_release_dev;
1013 pci_dev_get(dev);
1014
1015 dev->dev.dma_mask = &dev->dma_mask;
1016 dev->dev.dma_parms = &dev->dma_parms;
1017 dev->dev.coherent_dma_mask = 0xffffffffull;
1018
1019 pci_set_dma_max_seg_size(dev, 65536);
1020 pci_set_dma_seg_boundary(dev, 0xffffffff);
1021
1022 /* Fix up broken headers */
1023 pci_fixup_device(pci_fixup_header, dev);
1024
1025 /* Clear the state_saved flag. */
1026 dev->state_saved = false;
1027
1028 /* Initialize various capabilities */
1029 pci_init_capabilities(dev);
1030
1031 /*
1032 * Add the device to our list of discovered devices
1033 * and the bus list for fixup functions, etc.
1034 */
1035 down_write(&pci_bus_sem);
1036 list_add_tail(&dev->bus_list, &bus->devices);
1037 up_write(&pci_bus_sem);
1038 }
1039
1040 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1041 {
1042 struct pci_dev *dev;
1043
1044 dev = pci_get_slot(bus, devfn);
1045 if (dev) {
1046 pci_dev_put(dev);
1047 return dev;
1048 }
1049
1050 dev = pci_scan_device(bus, devfn);
1051 if (!dev)
1052 return NULL;
1053
1054 pci_device_add(dev, bus);
1055
1056 return dev;
1057 }
1058 EXPORT_SYMBOL(pci_scan_single_device);
1059
1060 /**
1061 * pci_scan_slot - scan a PCI slot on a bus for devices.
1062 * @bus: PCI bus to scan
1063 * @devfn: slot number to scan (must have zero function.)
1064 *
1065 * Scan a PCI slot on the specified PCI bus for devices, adding
1066 * discovered devices to the @bus->devices list. New devices
1067 * will not have is_added set.
1068 *
1069 * Returns the number of new devices found.
1070 */
1071 int pci_scan_slot(struct pci_bus *bus, int devfn)
1072 {
1073 int fn, nr = 0;
1074 struct pci_dev *dev;
1075
1076 dev = pci_scan_single_device(bus, devfn);
1077 if (dev && !dev->is_added) /* new device? */
1078 nr++;
1079
1080 if (dev && dev->multifunction) {
1081 for (fn = 1; fn < 8; fn++) {
1082 dev = pci_scan_single_device(bus, devfn + fn);
1083 if (dev) {
1084 if (!dev->is_added)
1085 nr++;
1086 dev->multifunction = 1;
1087 }
1088 }
1089 }
1090
1091 /* only one slot has pcie device */
1092 if (bus->self && nr)
1093 pcie_aspm_init_link_state(bus->self);
1094
1095 return nr;
1096 }
1097
1098 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1099 {
1100 unsigned int devfn, pass, max = bus->secondary;
1101 struct pci_dev *dev;
1102
1103 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1104
1105 /* Go find them, Rover! */
1106 for (devfn = 0; devfn < 0x100; devfn += 8)
1107 pci_scan_slot(bus, devfn);
1108
1109 /* Reserve buses for SR-IOV capability. */
1110 max += pci_iov_bus_range(bus);
1111
1112 /*
1113 * After performing arch-dependent fixup of the bus, look behind
1114 * all PCI-to-PCI bridges on this bus.
1115 */
1116 if (!bus->is_added) {
1117 pr_debug("PCI: Fixups for bus %04x:%02x\n",
1118 pci_domain_nr(bus), bus->number);
1119 pcibios_fixup_bus(bus);
1120 if (pci_is_root_bus(bus))
1121 bus->is_added = 1;
1122 }
1123
1124 for (pass=0; pass < 2; pass++)
1125 list_for_each_entry(dev, &bus->devices, bus_list) {
1126 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1127 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1128 max = pci_scan_bridge(bus, dev, max, pass);
1129 }
1130
1131 /*
1132 * We've scanned the bus and so we know all about what's on
1133 * the other side of any bridges that may be on this bus plus
1134 * any devices.
1135 *
1136 * Return how far we've got finding sub-buses.
1137 */
1138 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1139 pci_domain_nr(bus), bus->number, max);
1140 return max;
1141 }
1142
1143 struct pci_bus * pci_create_bus(struct device *parent,
1144 int bus, struct pci_ops *ops, void *sysdata)
1145 {
1146 int error;
1147 struct pci_bus *b;
1148 struct device *dev;
1149
1150 b = pci_alloc_bus();
1151 if (!b)
1152 return NULL;
1153
1154 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1155 if (!dev){
1156 kfree(b);
1157 return NULL;
1158 }
1159
1160 b->sysdata = sysdata;
1161 b->ops = ops;
1162
1163 if (pci_find_bus(pci_domain_nr(b), bus)) {
1164 /* If we already got to this bus through a different bridge, ignore it */
1165 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1166 goto err_out;
1167 }
1168
1169 down_write(&pci_bus_sem);
1170 list_add_tail(&b->node, &pci_root_buses);
1171 up_write(&pci_bus_sem);
1172
1173 dev->parent = parent;
1174 dev->release = pci_release_bus_bridge_dev;
1175 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1176 error = device_register(dev);
1177 if (error)
1178 goto dev_reg_err;
1179 b->bridge = get_device(dev);
1180
1181 if (!parent)
1182 set_dev_node(b->bridge, pcibus_to_node(b));
1183
1184 b->dev.class = &pcibus_class;
1185 b->dev.parent = b->bridge;
1186 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1187 error = device_register(&b->dev);
1188 if (error)
1189 goto class_dev_reg_err;
1190 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1191 if (error)
1192 goto dev_create_file_err;
1193
1194 /* Create legacy_io and legacy_mem files for this bus */
1195 pci_create_legacy_files(b);
1196
1197 b->number = b->secondary = bus;
1198 b->resource[0] = &ioport_resource;
1199 b->resource[1] = &iomem_resource;
1200
1201 return b;
1202
1203 dev_create_file_err:
1204 device_unregister(&b->dev);
1205 class_dev_reg_err:
1206 device_unregister(dev);
1207 dev_reg_err:
1208 down_write(&pci_bus_sem);
1209 list_del(&b->node);
1210 up_write(&pci_bus_sem);
1211 err_out:
1212 kfree(dev);
1213 kfree(b);
1214 return NULL;
1215 }
1216
1217 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1218 int bus, struct pci_ops *ops, void *sysdata)
1219 {
1220 struct pci_bus *b;
1221
1222 b = pci_create_bus(parent, bus, ops, sysdata);
1223 if (b)
1224 b->subordinate = pci_scan_child_bus(b);
1225 return b;
1226 }
1227 EXPORT_SYMBOL(pci_scan_bus_parented);
1228
1229 #ifdef CONFIG_HOTPLUG
1230 /**
1231 * pci_rescan_bus - scan a PCI bus for devices.
1232 * @bus: PCI bus to scan
1233 *
1234 * Scan a PCI bus and child buses for new devices, adds them,
1235 * and enables them.
1236 *
1237 * Returns the max number of subordinate bus discovered.
1238 */
1239 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1240 {
1241 unsigned int max;
1242 struct pci_dev *dev;
1243
1244 max = pci_scan_child_bus(bus);
1245
1246 down_read(&pci_bus_sem);
1247 list_for_each_entry(dev, &bus->devices, bus_list)
1248 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1249 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1250 if (dev->subordinate)
1251 pci_bus_size_bridges(dev->subordinate);
1252 up_read(&pci_bus_sem);
1253
1254 pci_bus_assign_resources(bus);
1255 pci_enable_bridges(bus);
1256 pci_bus_add_devices(bus);
1257
1258 return max;
1259 }
1260 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1261
1262 EXPORT_SYMBOL(pci_add_new_bus);
1263 EXPORT_SYMBOL(pci_scan_slot);
1264 EXPORT_SYMBOL(pci_scan_bridge);
1265 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1266 #endif
1267
1268 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1269 {
1270 const struct pci_dev *a = to_pci_dev(d_a);
1271 const struct pci_dev *b = to_pci_dev(d_b);
1272
1273 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1274 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1275
1276 if (a->bus->number < b->bus->number) return -1;
1277 else if (a->bus->number > b->bus->number) return 1;
1278
1279 if (a->devfn < b->devfn) return -1;
1280 else if (a->devfn > b->devfn) return 1;
1281
1282 return 0;
1283 }
1284
1285 void __init pci_sort_breadthfirst(void)
1286 {
1287 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1288 }
Linux kernel - Deliverables
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