2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <linux/iommu.h>
14 #include <acpi/acpi_hest.h>
18 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
19 #define CARDBUS_RESERVE_BUSNR 3
21 /* Ugh. Need to stop exporting this to modules. */
22 LIST_HEAD(pci_root_buses
);
23 EXPORT_SYMBOL(pci_root_buses
);
26 static int find_anything(struct device
*dev
, void *data
)
32 * Some device drivers need know if pci is initiated.
33 * Basically, we think pci is not initiated when there
34 * is no device to be found on the pci_bus_type.
36 int no_pci_devices(void)
41 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
42 no_devices
= (dev
== NULL
);
46 EXPORT_SYMBOL(no_pci_devices
);
49 * PCI Bus Class Devices
51 static ssize_t
pci_bus_show_cpuaffinity(struct device
*dev
,
53 struct device_attribute
*attr
,
57 const struct cpumask
*cpumask
;
59 cpumask
= cpumask_of_pcibus(to_pci_bus(dev
));
61 cpulist_scnprintf(buf
, PAGE_SIZE
-2, cpumask
) :
62 cpumask_scnprintf(buf
, PAGE_SIZE
-2, cpumask
);
68 static ssize_t
inline pci_bus_show_cpumaskaffinity(struct device
*dev
,
69 struct device_attribute
*attr
,
72 return pci_bus_show_cpuaffinity(dev
, 0, attr
, buf
);
75 static ssize_t
inline pci_bus_show_cpulistaffinity(struct device
*dev
,
76 struct device_attribute
*attr
,
79 return pci_bus_show_cpuaffinity(dev
, 1, attr
, buf
);
82 DEVICE_ATTR(cpuaffinity
, S_IRUGO
, pci_bus_show_cpumaskaffinity
, NULL
);
83 DEVICE_ATTR(cpulistaffinity
, S_IRUGO
, pci_bus_show_cpulistaffinity
, NULL
);
88 static void release_pcibus_dev(struct device
*dev
)
90 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
93 put_device(pci_bus
->bridge
);
97 static struct class pcibus_class
= {
99 .dev_release
= &release_pcibus_dev
,
102 static int __init
pcibus_class_init(void)
104 return class_register(&pcibus_class
);
106 postcore_initcall(pcibus_class_init
);
109 * Translate the low bits of the PCI base
110 * to the resource type
112 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
114 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
115 return IORESOURCE_IO
;
117 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
118 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
120 return IORESOURCE_MEM
;
123 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
125 u64 size
= mask
& maxbase
; /* Find the significant bits */
129 /* Get the lowest of them to find the decode size, and
130 from that the extent. */
131 size
= (size
& ~(size
-1)) - 1;
133 /* base == maxbase can be valid only if the BAR has
134 already been programmed with all 1s. */
135 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
141 static inline enum pci_bar_type
decode_bar(struct resource
*res
, u32 bar
)
143 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
144 res
->flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
148 res
->flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
150 if (res
->flags
& PCI_BASE_ADDRESS_MEM_TYPE_64
)
151 return pci_bar_mem64
;
152 return pci_bar_mem32
;
156 * pci_read_base - read a PCI BAR
157 * @dev: the PCI device
158 * @type: type of the BAR
159 * @res: resource buffer to be filled in
160 * @pos: BAR position in the config space
162 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
164 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
165 struct resource
*res
, unsigned int pos
)
169 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
171 res
->name
= pci_name(dev
);
173 pci_read_config_dword(dev
, pos
, &l
);
174 pci_write_config_dword(dev
, pos
, l
| mask
);
175 pci_read_config_dword(dev
, pos
, &sz
);
176 pci_write_config_dword(dev
, pos
, l
);
179 * All bits set in sz means the device isn't working properly.
180 * If the BAR isn't implemented, all bits must be 0. If it's a
181 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
184 if (!sz
|| sz
== 0xffffffff)
188 * I don't know how l can have all bits set. Copied from old code.
189 * Maybe it fixes a bug on some ancient platform.
194 if (type
== pci_bar_unknown
) {
195 type
= decode_bar(res
, l
);
196 res
->flags
|= pci_calc_resource_flags(l
) | IORESOURCE_SIZEALIGN
;
197 if (type
== pci_bar_io
) {
198 l
&= PCI_BASE_ADDRESS_IO_MASK
;
199 mask
= PCI_BASE_ADDRESS_IO_MASK
& IO_SPACE_LIMIT
;
201 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
202 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
205 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
206 l
&= PCI_ROM_ADDRESS_MASK
;
207 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
210 if (type
== pci_bar_mem64
) {
213 u64 mask64
= mask
| (u64
)~0 << 32;
215 pci_read_config_dword(dev
, pos
+ 4, &l
);
216 pci_write_config_dword(dev
, pos
+ 4, ~0);
217 pci_read_config_dword(dev
, pos
+ 4, &sz
);
218 pci_write_config_dword(dev
, pos
+ 4, l
);
220 l64
|= ((u64
)l
<< 32);
221 sz64
|= ((u64
)sz
<< 32);
223 sz64
= pci_size(l64
, sz64
, mask64
);
228 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
229 dev_err(&dev
->dev
, "can't handle 64-bit BAR\n");
233 res
->flags
|= IORESOURCE_MEM_64
;
234 if ((sizeof(resource_size_t
) < 8) && l
) {
235 /* Address above 32-bit boundary; disable the BAR */
236 pci_write_config_dword(dev
, pos
, 0);
237 pci_write_config_dword(dev
, pos
+ 4, 0);
242 res
->end
= l64
+ sz64
;
243 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n",
247 sz
= pci_size(l
, sz
, mask
);
255 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n", pos
, res
);
259 return (type
== pci_bar_mem64
) ? 1 : 0;
265 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
267 unsigned int pos
, reg
;
269 for (pos
= 0; pos
< howmany
; pos
++) {
270 struct resource
*res
= &dev
->resource
[pos
];
271 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
272 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
276 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
277 dev
->rom_base_reg
= rom
;
278 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
279 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
280 IORESOURCE_SIZEALIGN
;
281 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
285 void __devinit
pci_read_bridge_bases(struct pci_bus
*child
)
287 struct pci_dev
*dev
= child
->self
;
288 u8 io_base_lo
, io_limit_lo
;
289 u16 mem_base_lo
, mem_limit_lo
;
290 unsigned long base
, limit
;
291 struct resource
*res
;
294 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
297 if (dev
->transparent
) {
298 dev_info(&dev
->dev
, "transparent bridge\n");
299 for(i
= 3; i
< PCI_BUS_NUM_RESOURCES
; i
++)
300 child
->resource
[i
] = child
->parent
->resource
[i
- 3];
303 res
= child
->resource
[0];
304 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
305 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
306 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
307 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
309 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
310 u16 io_base_hi
, io_limit_hi
;
311 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
312 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
313 base
|= (io_base_hi
<< 16);
314 limit
|= (io_limit_hi
<< 16);
318 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
322 res
->end
= limit
+ 0xfff;
323 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
326 res
= child
->resource
[1];
327 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
328 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
329 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
330 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
332 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
334 res
->end
= limit
+ 0xfffff;
335 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
338 res
= child
->resource
[2];
339 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
340 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
341 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
342 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
344 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
345 u32 mem_base_hi
, mem_limit_hi
;
346 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
347 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
350 * Some bridges set the base > limit by default, and some
351 * (broken) BIOSes do not initialize them. If we find
352 * this, just assume they are not being used.
354 if (mem_base_hi
<= mem_limit_hi
) {
355 #if BITS_PER_LONG == 64
356 base
|= ((long) mem_base_hi
) << 32;
357 limit
|= ((long) mem_limit_hi
) << 32;
359 if (mem_base_hi
|| mem_limit_hi
) {
360 dev_err(&dev
->dev
, "can't handle 64-bit "
361 "address space for bridge\n");
368 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
369 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
370 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
371 res
->flags
|= IORESOURCE_MEM_64
;
373 res
->end
= limit
+ 0xfffff;
374 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
378 static struct pci_bus
* pci_alloc_bus(void)
382 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
384 INIT_LIST_HEAD(&b
->node
);
385 INIT_LIST_HEAD(&b
->children
);
386 INIT_LIST_HEAD(&b
->devices
);
387 INIT_LIST_HEAD(&b
->slots
);
392 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
393 struct pci_dev
*bridge
, int busnr
)
395 struct pci_bus
*child
;
399 * Allocate a new bus, and inherit stuff from the parent..
401 child
= pci_alloc_bus();
405 child
->parent
= parent
;
406 child
->ops
= parent
->ops
;
407 child
->sysdata
= parent
->sysdata
;
408 child
->bus_flags
= parent
->bus_flags
;
410 /* initialize some portions of the bus device, but don't register it
411 * now as the parent is not properly set up yet. This device will get
412 * registered later in pci_bus_add_devices()
414 child
->dev
.class = &pcibus_class
;
415 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
418 * Set up the primary, secondary and subordinate
421 child
->number
= child
->secondary
= busnr
;
422 child
->primary
= parent
->secondary
;
423 child
->subordinate
= 0xff;
428 child
->self
= bridge
;
429 child
->bridge
= get_device(&bridge
->dev
);
431 /* Set up default resource pointers and names.. */
432 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
433 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
434 child
->resource
[i
]->name
= child
->name
;
436 bridge
->subordinate
= child
;
441 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
443 struct pci_bus
*child
;
445 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
447 down_write(&pci_bus_sem
);
448 list_add_tail(&child
->node
, &parent
->children
);
449 up_write(&pci_bus_sem
);
454 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
456 struct pci_bus
*parent
= child
->parent
;
458 /* Attempts to fix that up are really dangerous unless
459 we're going to re-assign all bus numbers. */
460 if (!pcibios_assign_all_busses())
463 while (parent
->parent
&& parent
->subordinate
< max
) {
464 parent
->subordinate
= max
;
465 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
466 parent
= parent
->parent
;
471 * If it's a bridge, configure it and scan the bus behind it.
472 * For CardBus bridges, we don't scan behind as the devices will
473 * be handled by the bridge driver itself.
475 * We need to process bridges in two passes -- first we scan those
476 * already configured by the BIOS and after we are done with all of
477 * them, we proceed to assigning numbers to the remaining buses in
478 * order to avoid overlaps between old and new bus numbers.
480 int __devinit
pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
482 struct pci_bus
*child
;
483 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
488 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
490 dev_dbg(&dev
->dev
, "scanning behind bridge, config %06x, pass %d\n",
491 buses
& 0xffffff, pass
);
493 /* Check if setup is sensible at all */
495 ((buses
& 0xff) != bus
->number
|| ((buses
>> 8) & 0xff) <= bus
->number
)) {
496 dev_dbg(&dev
->dev
, "bus configuration invalid, reconfiguring\n");
500 /* Disable MasterAbortMode during probing to avoid reporting
501 of bus errors (in some architectures) */
502 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
503 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
504 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
506 if ((buses
& 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus
&& !broken
) {
507 unsigned int cmax
, busnr
;
509 * Bus already configured by firmware, process it in the first
510 * pass and just note the configuration.
514 busnr
= (buses
>> 8) & 0xFF;
517 * If we already got to this bus through a different bridge,
518 * don't re-add it. This can happen with the i450NX chipset.
520 * However, we continue to descend down the hierarchy and
521 * scan remaining child buses.
523 child
= pci_find_bus(pci_domain_nr(bus
), busnr
);
525 child
= pci_add_new_bus(bus
, dev
, busnr
);
528 child
->primary
= buses
& 0xFF;
529 child
->subordinate
= (buses
>> 16) & 0xFF;
530 child
->bridge_ctl
= bctl
;
533 cmax
= pci_scan_child_bus(child
);
536 if (child
->subordinate
> max
)
537 max
= child
->subordinate
;
540 * We need to assign a number to this bus which we always
541 * do in the second pass.
544 if (pcibios_assign_all_busses() || broken
)
545 /* Temporarily disable forwarding of the
546 configuration cycles on all bridges in
547 this bus segment to avoid possible
548 conflicts in the second pass between two
549 bridges programmed with overlapping
551 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
557 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
559 /* Prevent assigning a bus number that already exists.
560 * This can happen when a bridge is hot-plugged */
561 if (pci_find_bus(pci_domain_nr(bus
), max
+1))
563 child
= pci_add_new_bus(bus
, dev
, ++max
);
564 buses
= (buses
& 0xff000000)
565 | ((unsigned int)(child
->primary
) << 0)
566 | ((unsigned int)(child
->secondary
) << 8)
567 | ((unsigned int)(child
->subordinate
) << 16);
570 * yenta.c forces a secondary latency timer of 176.
571 * Copy that behaviour here.
574 buses
&= ~0xff000000;
575 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
579 * We need to blast all three values with a single write.
581 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
584 child
->bridge_ctl
= bctl
;
586 * Adjust subordinate busnr in parent buses.
587 * We do this before scanning for children because
588 * some devices may not be detected if the bios
591 pci_fixup_parent_subordinate_busnr(child
, max
);
592 /* Now we can scan all subordinate buses... */
593 max
= pci_scan_child_bus(child
);
595 * now fix it up again since we have found
596 * the real value of max.
598 pci_fixup_parent_subordinate_busnr(child
, max
);
601 * For CardBus bridges, we leave 4 bus numbers
602 * as cards with a PCI-to-PCI bridge can be
605 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
606 struct pci_bus
*parent
= bus
;
607 if (pci_find_bus(pci_domain_nr(bus
),
610 while (parent
->parent
) {
611 if ((!pcibios_assign_all_busses()) &&
612 (parent
->subordinate
> max
) &&
613 (parent
->subordinate
<= max
+i
)) {
616 parent
= parent
->parent
;
620 * Often, there are two cardbus bridges
621 * -- try to leave one valid bus number
629 pci_fixup_parent_subordinate_busnr(child
, max
);
632 * Set the subordinate bus number to its real value.
634 child
->subordinate
= max
;
635 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
639 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
640 pci_domain_nr(bus
), child
->number
);
642 /* Has only triggered on CardBus, fixup is in yenta_socket */
643 while (bus
->parent
) {
644 if ((child
->subordinate
> bus
->subordinate
) ||
645 (child
->number
> bus
->subordinate
) ||
646 (child
->number
< bus
->number
) ||
647 (child
->subordinate
< bus
->number
)) {
648 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
649 "hidden behind%s bridge #%02x (-#%02x)\n",
650 child
->number
, child
->subordinate
,
651 (bus
->number
> child
->subordinate
&&
652 bus
->subordinate
< child
->number
) ?
653 "wholly" : "partially",
654 bus
->self
->transparent
? " transparent" : "",
655 bus
->number
, bus
->subordinate
);
661 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
667 * Read interrupt line and base address registers.
668 * The architecture-dependent code can tweak these, of course.
670 static void pci_read_irq(struct pci_dev
*dev
)
674 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
677 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
681 static void set_pcie_port_type(struct pci_dev
*pdev
)
686 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
690 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
691 pdev
->pcie_type
= (reg16
& PCI_EXP_FLAGS_TYPE
) >> 4;
694 static void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
700 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
703 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
704 if (!(reg16
& PCI_EXP_FLAGS_SLOT
))
706 pci_read_config_dword(pdev
, pos
+ PCI_EXP_SLTCAP
, ®32
);
707 if (reg32
& PCI_EXP_SLTCAP_HPC
)
708 pdev
->is_hotplug_bridge
= 1;
711 static void set_pci_aer_firmware_first(struct pci_dev
*pdev
)
713 if (acpi_hest_firmware_first_pci(pdev
))
714 pdev
->aer_firmware_first
= 1;
717 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
720 * pci_setup_device - fill in class and map information of a device
721 * @dev: the device structure to fill
723 * Initialize the device structure with information about the device's
724 * vendor,class,memory and IO-space addresses,IRQ lines etc.
725 * Called at initialisation of the PCI subsystem and by CardBus services.
726 * Returns 0 on success and negative if unknown type of device (not normal,
727 * bridge or CardBus).
729 int pci_setup_device(struct pci_dev
*dev
)
733 struct pci_slot
*slot
;
736 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
739 dev
->sysdata
= dev
->bus
->sysdata
;
740 dev
->dev
.parent
= dev
->bus
->bridge
;
741 dev
->dev
.bus
= &pci_bus_type
;
742 dev
->hdr_type
= hdr_type
& 0x7f;
743 dev
->multifunction
= !!(hdr_type
& 0x80);
744 dev
->error_state
= pci_channel_io_normal
;
745 set_pcie_port_type(dev
);
746 set_pci_aer_firmware_first(dev
);
748 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
749 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
752 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
753 set this higher, assuming the system even supports it. */
754 dev
->dma_mask
= 0xffffffff;
756 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
757 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
758 PCI_FUNC(dev
->devfn
));
760 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
761 dev
->revision
= class & 0xff;
762 class >>= 8; /* upper 3 bytes */
766 dev_dbg(&dev
->dev
, "found [%04x:%04x] class %06x header type %02x\n",
767 dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
769 /* need to have dev->class ready */
770 dev
->cfg_size
= pci_cfg_space_size(dev
);
772 /* "Unknown power state" */
773 dev
->current_state
= PCI_UNKNOWN
;
775 /* Early fixups, before probing the BARs */
776 pci_fixup_device(pci_fixup_early
, dev
);
777 /* device class may be changed after fixup */
778 class = dev
->class >> 8;
780 switch (dev
->hdr_type
) { /* header type */
781 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
782 if (class == PCI_CLASS_BRIDGE_PCI
)
785 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
786 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
787 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
790 * Do the ugly legacy mode stuff here rather than broken chip
791 * quirk code. Legacy mode ATA controllers have fixed
792 * addresses. These are not always echoed in BAR0-3, and
793 * BAR0-3 in a few cases contain junk!
795 if (class == PCI_CLASS_STORAGE_IDE
) {
797 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
798 if ((progif
& 1) == 0) {
799 dev
->resource
[0].start
= 0x1F0;
800 dev
->resource
[0].end
= 0x1F7;
801 dev
->resource
[0].flags
= LEGACY_IO_RESOURCE
;
802 dev
->resource
[1].start
= 0x3F6;
803 dev
->resource
[1].end
= 0x3F6;
804 dev
->resource
[1].flags
= LEGACY_IO_RESOURCE
;
806 if ((progif
& 4) == 0) {
807 dev
->resource
[2].start
= 0x170;
808 dev
->resource
[2].end
= 0x177;
809 dev
->resource
[2].flags
= LEGACY_IO_RESOURCE
;
810 dev
->resource
[3].start
= 0x376;
811 dev
->resource
[3].end
= 0x376;
812 dev
->resource
[3].flags
= LEGACY_IO_RESOURCE
;
817 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
818 if (class != PCI_CLASS_BRIDGE_PCI
)
820 /* The PCI-to-PCI bridge spec requires that subtractive
821 decoding (i.e. transparent) bridge must have programming
822 interface code of 0x01. */
824 dev
->transparent
= ((dev
->class & 0xff) == 1);
825 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
826 set_pcie_hotplug_bridge(dev
);
827 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
829 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
830 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
834 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
835 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
838 pci_read_bases(dev
, 1, 0);
839 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
840 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
843 default: /* unknown header */
844 dev_err(&dev
->dev
, "unknown header type %02x, "
845 "ignoring device\n", dev
->hdr_type
);
849 dev_err(&dev
->dev
, "ignoring class %02x (doesn't match header "
850 "type %02x)\n", class, dev
->hdr_type
);
851 dev
->class = PCI_CLASS_NOT_DEFINED
;
854 /* We found a fine healthy device, go go go... */
858 static void pci_release_capabilities(struct pci_dev
*dev
)
860 pci_vpd_release(dev
);
861 pci_iov_release(dev
);
865 * pci_release_dev - free a pci device structure when all users of it are finished.
866 * @dev: device that's been disconnected
868 * Will be called only by the device core when all users of this pci device are
871 static void pci_release_dev(struct device
*dev
)
873 struct pci_dev
*pci_dev
;
875 pci_dev
= to_pci_dev(dev
);
876 pci_release_capabilities(pci_dev
);
881 * pci_cfg_space_size - get the configuration space size of the PCI device.
884 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
885 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
886 * access it. Maybe we don't have a way to generate extended config space
887 * accesses, or the device is behind a reverse Express bridge. So we try
888 * reading the dword at 0x100 which must either be 0 or a valid extended
891 int pci_cfg_space_size_ext(struct pci_dev
*dev
)
894 int pos
= PCI_CFG_SPACE_SIZE
;
896 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
898 if (status
== 0xffffffff)
901 return PCI_CFG_SPACE_EXP_SIZE
;
904 return PCI_CFG_SPACE_SIZE
;
907 int pci_cfg_space_size(struct pci_dev
*dev
)
913 class = dev
->class >> 8;
914 if (class == PCI_CLASS_BRIDGE_HOST
)
915 return pci_cfg_space_size_ext(dev
);
917 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
919 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
923 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
924 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
928 return pci_cfg_space_size_ext(dev
);
931 return PCI_CFG_SPACE_SIZE
;
934 static void pci_release_bus_bridge_dev(struct device
*dev
)
939 struct pci_dev
*alloc_pci_dev(void)
943 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
947 INIT_LIST_HEAD(&dev
->bus_list
);
951 EXPORT_SYMBOL(alloc_pci_dev
);
954 * Read the config data for a PCI device, sanity-check it
955 * and fill in the dev structure...
957 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
963 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
966 /* some broken boards return 0 or ~0 if a slot is empty: */
967 if (l
== 0xffffffff || l
== 0x00000000 ||
968 l
== 0x0000ffff || l
== 0xffff0000)
971 /* Configuration request Retry Status */
972 while (l
== 0xffff0001) {
975 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
977 /* Card hasn't responded in 60 seconds? Must be stuck. */
978 if (delay
> 60 * 1000) {
979 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
980 "responding\n", pci_domain_nr(bus
),
981 bus
->number
, PCI_SLOT(devfn
),
987 dev
= alloc_pci_dev();
993 dev
->vendor
= l
& 0xffff;
994 dev
->device
= (l
>> 16) & 0xffff;
996 if (pci_setup_device(dev
)) {
1004 static void pci_init_capabilities(struct pci_dev
*dev
)
1006 /* MSI/MSI-X list */
1007 pci_msi_init_pci_dev(dev
);
1009 /* Buffers for saving PCIe and PCI-X capabilities */
1010 pci_allocate_cap_save_buffers(dev
);
1012 /* Power Management */
1014 platform_pci_wakeup_init(dev
);
1016 /* Vital Product Data */
1017 pci_vpd_pci22_init(dev
);
1019 /* Alternative Routing-ID Forwarding */
1020 pci_enable_ari(dev
);
1022 /* Single Root I/O Virtualization */
1025 /* Enable ACS P2P upstream forwarding */
1026 if (iommu_found() || xen_initial_domain())
1027 pci_enable_acs(dev
);
1030 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1032 device_initialize(&dev
->dev
);
1033 dev
->dev
.release
= pci_release_dev
;
1036 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1037 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1038 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1040 pci_set_dma_max_seg_size(dev
, 65536);
1041 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1043 /* Fix up broken headers */
1044 pci_fixup_device(pci_fixup_header
, dev
);
1046 /* Clear the state_saved flag. */
1047 dev
->state_saved
= false;
1049 /* Initialize various capabilities */
1050 pci_init_capabilities(dev
);
1053 * Add the device to our list of discovered devices
1054 * and the bus list for fixup functions, etc.
1056 down_write(&pci_bus_sem
);
1057 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1058 up_write(&pci_bus_sem
);
1061 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1063 struct pci_dev
*dev
;
1065 dev
= pci_get_slot(bus
, devfn
);
1071 dev
= pci_scan_device(bus
, devfn
);
1075 pci_device_add(dev
, bus
);
1079 EXPORT_SYMBOL(pci_scan_single_device
);
1082 * pci_scan_slot - scan a PCI slot on a bus for devices.
1083 * @bus: PCI bus to scan
1084 * @devfn: slot number to scan (must have zero function.)
1086 * Scan a PCI slot on the specified PCI bus for devices, adding
1087 * discovered devices to the @bus->devices list. New devices
1088 * will not have is_added set.
1090 * Returns the number of new devices found.
1092 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1095 struct pci_dev
*dev
;
1097 dev
= pci_scan_single_device(bus
, devfn
);
1098 if (dev
&& !dev
->is_added
) /* new device? */
1101 if (dev
&& dev
->multifunction
) {
1102 for (fn
= 1; fn
< 8; fn
++) {
1103 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1107 dev
->multifunction
= 1;
1112 /* only one slot has pcie device */
1113 if (bus
->self
&& nr
)
1114 pcie_aspm_init_link_state(bus
->self
);
1119 unsigned int __devinit
pci_scan_child_bus(struct pci_bus
*bus
)
1121 unsigned int devfn
, pass
, max
= bus
->secondary
;
1122 struct pci_dev
*dev
;
1124 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus
), bus
->number
);
1126 /* Go find them, Rover! */
1127 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1128 pci_scan_slot(bus
, devfn
);
1130 /* Reserve buses for SR-IOV capability. */
1131 max
+= pci_iov_bus_range(bus
);
1134 * After performing arch-dependent fixup of the bus, look behind
1135 * all PCI-to-PCI bridges on this bus.
1137 if (!bus
->is_added
) {
1138 pr_debug("PCI: Fixups for bus %04x:%02x\n",
1139 pci_domain_nr(bus
), bus
->number
);
1140 pcibios_fixup_bus(bus
);
1141 if (pci_is_root_bus(bus
))
1145 for (pass
=0; pass
< 2; pass
++)
1146 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1147 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1148 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1149 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1153 * We've scanned the bus and so we know all about what's on
1154 * the other side of any bridges that may be on this bus plus
1157 * Return how far we've got finding sub-buses.
1159 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1160 pci_domain_nr(bus
), bus
->number
, max
);
1164 struct pci_bus
* pci_create_bus(struct device
*parent
,
1165 int bus
, struct pci_ops
*ops
, void *sysdata
)
1171 b
= pci_alloc_bus();
1175 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1181 b
->sysdata
= sysdata
;
1184 if (pci_find_bus(pci_domain_nr(b
), bus
)) {
1185 /* If we already got to this bus through a different bridge, ignore it */
1186 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b
), bus
);
1190 down_write(&pci_bus_sem
);
1191 list_add_tail(&b
->node
, &pci_root_buses
);
1192 up_write(&pci_bus_sem
);
1194 dev
->parent
= parent
;
1195 dev
->release
= pci_release_bus_bridge_dev
;
1196 dev_set_name(dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1197 error
= device_register(dev
);
1200 b
->bridge
= get_device(dev
);
1203 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1205 b
->dev
.class = &pcibus_class
;
1206 b
->dev
.parent
= b
->bridge
;
1207 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1208 error
= device_register(&b
->dev
);
1210 goto class_dev_reg_err
;
1211 error
= device_create_file(&b
->dev
, &dev_attr_cpuaffinity
);
1213 goto dev_create_file_err
;
1215 /* Create legacy_io and legacy_mem files for this bus */
1216 pci_create_legacy_files(b
);
1218 b
->number
= b
->secondary
= bus
;
1219 b
->resource
[0] = &ioport_resource
;
1220 b
->resource
[1] = &iomem_resource
;
1224 dev_create_file_err
:
1225 device_unregister(&b
->dev
);
1227 device_unregister(dev
);
1229 down_write(&pci_bus_sem
);
1231 up_write(&pci_bus_sem
);
1238 struct pci_bus
* __devinit
pci_scan_bus_parented(struct device
*parent
,
1239 int bus
, struct pci_ops
*ops
, void *sysdata
)
1243 b
= pci_create_bus(parent
, bus
, ops
, sysdata
);
1245 b
->subordinate
= pci_scan_child_bus(b
);
1248 EXPORT_SYMBOL(pci_scan_bus_parented
);
1250 #ifdef CONFIG_HOTPLUG
1252 * pci_rescan_bus - scan a PCI bus for devices.
1253 * @bus: PCI bus to scan
1255 * Scan a PCI bus and child buses for new devices, adds them,
1258 * Returns the max number of subordinate bus discovered.
1260 unsigned int __ref
pci_rescan_bus(struct pci_bus
*bus
)
1263 struct pci_dev
*dev
;
1265 max
= pci_scan_child_bus(bus
);
1267 down_read(&pci_bus_sem
);
1268 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1269 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1270 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1271 if (dev
->subordinate
)
1272 pci_bus_size_bridges(dev
->subordinate
);
1273 up_read(&pci_bus_sem
);
1275 pci_bus_assign_resources(bus
);
1276 pci_enable_bridges(bus
);
1277 pci_bus_add_devices(bus
);
1281 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
1283 EXPORT_SYMBOL(pci_add_new_bus
);
1284 EXPORT_SYMBOL(pci_scan_slot
);
1285 EXPORT_SYMBOL(pci_scan_bridge
);
1286 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1289 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
1291 const struct pci_dev
*a
= to_pci_dev(d_a
);
1292 const struct pci_dev
*b
= to_pci_dev(d_b
);
1294 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
1295 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
1297 if (a
->bus
->number
< b
->bus
->number
) return -1;
1298 else if (a
->bus
->number
> b
->bus
->number
) return 1;
1300 if (a
->devfn
< b
->devfn
) return -1;
1301 else if (a
->devfn
> b
->devfn
) return 1;
1306 void __init
pci_sort_breadthfirst(void)
1308 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);