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Merge branches 'pci/aer', 'pci/hotplug', 'pci/misc', 'pci/msi', 'pci/resource' and...
[deliverable/linux.git] / drivers / pci / probe.c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci_hotplug.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/cpumask.h>
14 #include <linux/pci-aspm.h>
15 #include <linux/aer.h>
16 #include <asm-generic/pci-bridge.h>
17 #include "pci.h"
18
19 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
20 #define CARDBUS_RESERVE_BUSNR 3
21
22 static struct resource busn_resource = {
23 .name = "PCI busn",
24 .start = 0,
25 .end = 255,
26 .flags = IORESOURCE_BUS,
27 };
28
29 /* Ugh. Need to stop exporting this to modules. */
30 LIST_HEAD(pci_root_buses);
31 EXPORT_SYMBOL(pci_root_buses);
32
33 static LIST_HEAD(pci_domain_busn_res_list);
34
35 struct pci_domain_busn_res {
36 struct list_head list;
37 struct resource res;
38 int domain_nr;
39 };
40
41 static struct resource *get_pci_domain_busn_res(int domain_nr)
42 {
43 struct pci_domain_busn_res *r;
44
45 list_for_each_entry(r, &pci_domain_busn_res_list, list)
46 if (r->domain_nr == domain_nr)
47 return &r->res;
48
49 r = kzalloc(sizeof(*r), GFP_KERNEL);
50 if (!r)
51 return NULL;
52
53 r->domain_nr = domain_nr;
54 r->res.start = 0;
55 r->res.end = 0xff;
56 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
57
58 list_add_tail(&r->list, &pci_domain_busn_res_list);
59
60 return &r->res;
61 }
62
63 static int find_anything(struct device *dev, void *data)
64 {
65 return 1;
66 }
67
68 /*
69 * Some device drivers need know if pci is initiated.
70 * Basically, we think pci is not initiated when there
71 * is no device to be found on the pci_bus_type.
72 */
73 int no_pci_devices(void)
74 {
75 struct device *dev;
76 int no_devices;
77
78 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82 }
83 EXPORT_SYMBOL(no_pci_devices);
84
85 /*
86 * PCI Bus Class
87 */
88 static void release_pcibus_dev(struct device *dev)
89 {
90 struct pci_bus *pci_bus = to_pci_bus(dev);
91
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
96 }
97
98 static struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
102 };
103
104 static int __init pcibus_class_init(void)
105 {
106 return class_register(&pcibus_class);
107 }
108 postcore_initcall(pcibus_class_init);
109
110 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111 {
112 u64 size = mask & maxbase; /* Find the significant bits */
113 if (!size)
114 return 0;
115
116 /* Get the lowest of them to find the decode size, and
117 from that the extent. */
118 size = (size & ~(size-1)) - 1;
119
120 /* base == maxbase can be valid only if the BAR has
121 already been programmed with all 1s. */
122 if (base == maxbase && ((base | size) & mask) != mask)
123 return 0;
124
125 return size;
126 }
127
128 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
129 {
130 u32 mem_type;
131 unsigned long flags;
132
133 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
134 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
135 flags |= IORESOURCE_IO;
136 return flags;
137 }
138
139 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
140 flags |= IORESOURCE_MEM;
141 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
142 flags |= IORESOURCE_PREFETCH;
143
144 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
145 switch (mem_type) {
146 case PCI_BASE_ADDRESS_MEM_TYPE_32:
147 break;
148 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
149 /* 1M mem BAR treated as 32-bit BAR */
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_64:
152 flags |= IORESOURCE_MEM_64;
153 break;
154 default:
155 /* mem unknown type treated as 32-bit BAR */
156 break;
157 }
158 return flags;
159 }
160
161 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
162
163 /**
164 * pci_read_base - read a PCI BAR
165 * @dev: the PCI device
166 * @type: type of the BAR
167 * @res: resource buffer to be filled in
168 * @pos: BAR position in the config space
169 *
170 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
171 */
172 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
173 struct resource *res, unsigned int pos)
174 {
175 u32 l, sz, mask;
176 u64 l64, sz64, mask64;
177 u16 orig_cmd;
178 struct pci_bus_region region, inverted_region;
179
180 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
181
182 /* No printks while decoding is disabled! */
183 if (!dev->mmio_always_on) {
184 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
185 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
186 pci_write_config_word(dev, PCI_COMMAND,
187 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
188 }
189 }
190
191 res->name = pci_name(dev);
192
193 pci_read_config_dword(dev, pos, &l);
194 pci_write_config_dword(dev, pos, l | mask);
195 pci_read_config_dword(dev, pos, &sz);
196 pci_write_config_dword(dev, pos, l);
197
198 /*
199 * All bits set in sz means the device isn't working properly.
200 * If the BAR isn't implemented, all bits must be 0. If it's a
201 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
202 * 1 must be clear.
203 */
204 if (sz == 0xffffffff)
205 sz = 0;
206
207 /*
208 * I don't know how l can have all bits set. Copied from old code.
209 * Maybe it fixes a bug on some ancient platform.
210 */
211 if (l == 0xffffffff)
212 l = 0;
213
214 if (type == pci_bar_unknown) {
215 res->flags = decode_bar(dev, l);
216 res->flags |= IORESOURCE_SIZEALIGN;
217 if (res->flags & IORESOURCE_IO) {
218 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
219 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
220 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
221 } else {
222 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
224 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
225 }
226 } else {
227 res->flags |= (l & IORESOURCE_ROM_ENABLE);
228 l64 = l & PCI_ROM_ADDRESS_MASK;
229 sz64 = sz & PCI_ROM_ADDRESS_MASK;
230 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
231 }
232
233 if (res->flags & IORESOURCE_MEM_64) {
234 pci_read_config_dword(dev, pos + 4, &l);
235 pci_write_config_dword(dev, pos + 4, ~0);
236 pci_read_config_dword(dev, pos + 4, &sz);
237 pci_write_config_dword(dev, pos + 4, l);
238
239 l64 |= ((u64)l << 32);
240 sz64 |= ((u64)sz << 32);
241 mask64 |= ((u64)~0 << 32);
242 }
243
244 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
245 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
246
247 if (!sz64)
248 goto fail;
249
250 sz64 = pci_size(l64, sz64, mask64);
251 if (!sz64) {
252 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
253 pos);
254 goto fail;
255 }
256
257 if (res->flags & IORESOURCE_MEM_64) {
258 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
259 && sz64 > 0x100000000ULL) {
260 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
261 res->start = 0;
262 res->end = 0;
263 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
264 pos, (unsigned long long)sz64);
265 goto out;
266 }
267
268 if ((sizeof(pci_bus_addr_t) < 8) && l) {
269 /* Above 32-bit boundary; try to reallocate */
270 res->flags |= IORESOURCE_UNSET;
271 res->start = 0;
272 res->end = sz64;
273 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
274 pos, (unsigned long long)l64);
275 goto out;
276 }
277 }
278
279 region.start = l64;
280 region.end = l64 + sz64;
281
282 pcibios_bus_to_resource(dev->bus, res, &region);
283 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
284
285 /*
286 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
287 * the corresponding resource address (the physical address used by
288 * the CPU. Converting that resource address back to a bus address
289 * should yield the original BAR value:
290 *
291 * resource_to_bus(bus_to_resource(A)) == A
292 *
293 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
294 * be claimed by the device.
295 */
296 if (inverted_region.start != region.start) {
297 res->flags |= IORESOURCE_UNSET;
298 res->start = 0;
299 res->end = region.end - region.start;
300 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
301 pos, (unsigned long long)region.start);
302 }
303
304 goto out;
305
306
307 fail:
308 res->flags = 0;
309 out:
310 if (res->flags)
311 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
312
313 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
314 }
315
316 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
317 {
318 unsigned int pos, reg;
319
320 for (pos = 0; pos < howmany; pos++) {
321 struct resource *res = &dev->resource[pos];
322 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
323 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
324 }
325
326 if (rom) {
327 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
328 dev->rom_base_reg = rom;
329 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
330 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
331 __pci_read_base(dev, pci_bar_mem32, res, rom);
332 }
333 }
334
335 static void pci_read_bridge_io(struct pci_bus *child)
336 {
337 struct pci_dev *dev = child->self;
338 u8 io_base_lo, io_limit_lo;
339 unsigned long io_mask, io_granularity, base, limit;
340 struct pci_bus_region region;
341 struct resource *res;
342
343 io_mask = PCI_IO_RANGE_MASK;
344 io_granularity = 0x1000;
345 if (dev->io_window_1k) {
346 /* Support 1K I/O space granularity */
347 io_mask = PCI_IO_1K_RANGE_MASK;
348 io_granularity = 0x400;
349 }
350
351 res = child->resource[0];
352 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
353 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
354 base = (io_base_lo & io_mask) << 8;
355 limit = (io_limit_lo & io_mask) << 8;
356
357 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
358 u16 io_base_hi, io_limit_hi;
359
360 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
361 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
362 base |= ((unsigned long) io_base_hi << 16);
363 limit |= ((unsigned long) io_limit_hi << 16);
364 }
365
366 if (base <= limit) {
367 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
368 region.start = base;
369 region.end = limit + io_granularity - 1;
370 pcibios_bus_to_resource(dev->bus, res, &region);
371 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
372 }
373 }
374
375 static void pci_read_bridge_mmio(struct pci_bus *child)
376 {
377 struct pci_dev *dev = child->self;
378 u16 mem_base_lo, mem_limit_lo;
379 unsigned long base, limit;
380 struct pci_bus_region region;
381 struct resource *res;
382
383 res = child->resource[1];
384 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
385 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
386 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
387 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
388 if (base <= limit) {
389 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
390 region.start = base;
391 region.end = limit + 0xfffff;
392 pcibios_bus_to_resource(dev->bus, res, &region);
393 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
394 }
395 }
396
397 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
398 {
399 struct pci_dev *dev = child->self;
400 u16 mem_base_lo, mem_limit_lo;
401 u64 base64, limit64;
402 pci_bus_addr_t base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
405
406 res = child->resource[2];
407 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
408 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
409 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
410 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
411
412 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
413 u32 mem_base_hi, mem_limit_hi;
414
415 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
416 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
417
418 /*
419 * Some bridges set the base > limit by default, and some
420 * (broken) BIOSes do not initialize them. If we find
421 * this, just assume they are not being used.
422 */
423 if (mem_base_hi <= mem_limit_hi) {
424 base64 |= (u64) mem_base_hi << 32;
425 limit64 |= (u64) mem_limit_hi << 32;
426 }
427 }
428
429 base = (pci_bus_addr_t) base64;
430 limit = (pci_bus_addr_t) limit64;
431
432 if (base != base64) {
433 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
434 (unsigned long long) base64);
435 return;
436 }
437
438 if (base <= limit) {
439 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
440 IORESOURCE_MEM | IORESOURCE_PREFETCH;
441 if (res->flags & PCI_PREF_RANGE_TYPE_64)
442 res->flags |= IORESOURCE_MEM_64;
443 region.start = base;
444 region.end = limit + 0xfffff;
445 pcibios_bus_to_resource(dev->bus, res, &region);
446 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
447 }
448 }
449
450 void pci_read_bridge_bases(struct pci_bus *child)
451 {
452 struct pci_dev *dev = child->self;
453 struct resource *res;
454 int i;
455
456 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
457 return;
458
459 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
460 &child->busn_res,
461 dev->transparent ? " (subtractive decode)" : "");
462
463 pci_bus_remove_resources(child);
464 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
465 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
466
467 pci_read_bridge_io(child);
468 pci_read_bridge_mmio(child);
469 pci_read_bridge_mmio_pref(child);
470
471 if (dev->transparent) {
472 pci_bus_for_each_resource(child->parent, res, i) {
473 if (res && res->flags) {
474 pci_bus_add_resource(child, res,
475 PCI_SUBTRACTIVE_DECODE);
476 dev_printk(KERN_DEBUG, &dev->dev,
477 " bridge window %pR (subtractive decode)\n",
478 res);
479 }
480 }
481 }
482 }
483
484 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
485 {
486 struct pci_bus *b;
487
488 b = kzalloc(sizeof(*b), GFP_KERNEL);
489 if (!b)
490 return NULL;
491
492 INIT_LIST_HEAD(&b->node);
493 INIT_LIST_HEAD(&b->children);
494 INIT_LIST_HEAD(&b->devices);
495 INIT_LIST_HEAD(&b->slots);
496 INIT_LIST_HEAD(&b->resources);
497 b->max_bus_speed = PCI_SPEED_UNKNOWN;
498 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
499 #ifdef CONFIG_PCI_DOMAINS_GENERIC
500 if (parent)
501 b->domain_nr = parent->domain_nr;
502 #endif
503 return b;
504 }
505
506 static void pci_release_host_bridge_dev(struct device *dev)
507 {
508 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
509
510 if (bridge->release_fn)
511 bridge->release_fn(bridge);
512
513 pci_free_resource_list(&bridge->windows);
514
515 kfree(bridge);
516 }
517
518 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
519 {
520 struct pci_host_bridge *bridge;
521
522 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
523 if (!bridge)
524 return NULL;
525
526 INIT_LIST_HEAD(&bridge->windows);
527 bridge->bus = b;
528 return bridge;
529 }
530
531 static const unsigned char pcix_bus_speed[] = {
532 PCI_SPEED_UNKNOWN, /* 0 */
533 PCI_SPEED_66MHz_PCIX, /* 1 */
534 PCI_SPEED_100MHz_PCIX, /* 2 */
535 PCI_SPEED_133MHz_PCIX, /* 3 */
536 PCI_SPEED_UNKNOWN, /* 4 */
537 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
538 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
539 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
540 PCI_SPEED_UNKNOWN, /* 8 */
541 PCI_SPEED_66MHz_PCIX_266, /* 9 */
542 PCI_SPEED_100MHz_PCIX_266, /* A */
543 PCI_SPEED_133MHz_PCIX_266, /* B */
544 PCI_SPEED_UNKNOWN, /* C */
545 PCI_SPEED_66MHz_PCIX_533, /* D */
546 PCI_SPEED_100MHz_PCIX_533, /* E */
547 PCI_SPEED_133MHz_PCIX_533 /* F */
548 };
549
550 const unsigned char pcie_link_speed[] = {
551 PCI_SPEED_UNKNOWN, /* 0 */
552 PCIE_SPEED_2_5GT, /* 1 */
553 PCIE_SPEED_5_0GT, /* 2 */
554 PCIE_SPEED_8_0GT, /* 3 */
555 PCI_SPEED_UNKNOWN, /* 4 */
556 PCI_SPEED_UNKNOWN, /* 5 */
557 PCI_SPEED_UNKNOWN, /* 6 */
558 PCI_SPEED_UNKNOWN, /* 7 */
559 PCI_SPEED_UNKNOWN, /* 8 */
560 PCI_SPEED_UNKNOWN, /* 9 */
561 PCI_SPEED_UNKNOWN, /* A */
562 PCI_SPEED_UNKNOWN, /* B */
563 PCI_SPEED_UNKNOWN, /* C */
564 PCI_SPEED_UNKNOWN, /* D */
565 PCI_SPEED_UNKNOWN, /* E */
566 PCI_SPEED_UNKNOWN /* F */
567 };
568
569 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
570 {
571 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
572 }
573 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
574
575 static unsigned char agp_speeds[] = {
576 AGP_UNKNOWN,
577 AGP_1X,
578 AGP_2X,
579 AGP_4X,
580 AGP_8X
581 };
582
583 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
584 {
585 int index = 0;
586
587 if (agpstat & 4)
588 index = 3;
589 else if (agpstat & 2)
590 index = 2;
591 else if (agpstat & 1)
592 index = 1;
593 else
594 goto out;
595
596 if (agp3) {
597 index += 2;
598 if (index == 5)
599 index = 0;
600 }
601
602 out:
603 return agp_speeds[index];
604 }
605
606 static void pci_set_bus_speed(struct pci_bus *bus)
607 {
608 struct pci_dev *bridge = bus->self;
609 int pos;
610
611 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
612 if (!pos)
613 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
614 if (pos) {
615 u32 agpstat, agpcmd;
616
617 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
618 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
619
620 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
621 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
622 }
623
624 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
625 if (pos) {
626 u16 status;
627 enum pci_bus_speed max;
628
629 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
630 &status);
631
632 if (status & PCI_X_SSTATUS_533MHZ) {
633 max = PCI_SPEED_133MHz_PCIX_533;
634 } else if (status & PCI_X_SSTATUS_266MHZ) {
635 max = PCI_SPEED_133MHz_PCIX_266;
636 } else if (status & PCI_X_SSTATUS_133MHZ) {
637 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
638 max = PCI_SPEED_133MHz_PCIX_ECC;
639 else
640 max = PCI_SPEED_133MHz_PCIX;
641 } else {
642 max = PCI_SPEED_66MHz_PCIX;
643 }
644
645 bus->max_bus_speed = max;
646 bus->cur_bus_speed = pcix_bus_speed[
647 (status & PCI_X_SSTATUS_FREQ) >> 6];
648
649 return;
650 }
651
652 if (pci_is_pcie(bridge)) {
653 u32 linkcap;
654 u16 linksta;
655
656 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
657 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
658
659 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
660 pcie_update_link_speed(bus, linksta);
661 }
662 }
663
664 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
665 {
666 struct irq_domain *d;
667
668 /*
669 * Any firmware interface that can resolve the msi_domain
670 * should be called from here.
671 */
672 d = pci_host_bridge_of_msi_domain(bus);
673
674 return d;
675 }
676
677 static void pci_set_bus_msi_domain(struct pci_bus *bus)
678 {
679 struct irq_domain *d;
680
681 /*
682 * Either bus is the root, and we must obtain it from the
683 * firmware, or we inherit it from the bridge device.
684 */
685 if (pci_is_root_bus(bus))
686 d = pci_host_bridge_msi_domain(bus);
687 else
688 d = dev_get_msi_domain(&bus->self->dev);
689
690 dev_set_msi_domain(&bus->dev, d);
691 }
692
693 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
694 struct pci_dev *bridge, int busnr)
695 {
696 struct pci_bus *child;
697 int i;
698 int ret;
699
700 /*
701 * Allocate a new bus, and inherit stuff from the parent..
702 */
703 child = pci_alloc_bus(parent);
704 if (!child)
705 return NULL;
706
707 child->parent = parent;
708 child->ops = parent->ops;
709 child->msi = parent->msi;
710 child->sysdata = parent->sysdata;
711 child->bus_flags = parent->bus_flags;
712
713 /* initialize some portions of the bus device, but don't register it
714 * now as the parent is not properly set up yet.
715 */
716 child->dev.class = &pcibus_class;
717 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
718
719 /*
720 * Set up the primary, secondary and subordinate
721 * bus numbers.
722 */
723 child->number = child->busn_res.start = busnr;
724 child->primary = parent->busn_res.start;
725 child->busn_res.end = 0xff;
726
727 if (!bridge) {
728 child->dev.parent = parent->bridge;
729 goto add_dev;
730 }
731
732 child->self = bridge;
733 child->bridge = get_device(&bridge->dev);
734 child->dev.parent = child->bridge;
735 pci_set_bus_of_node(child);
736 pci_set_bus_speed(child);
737
738 /* Set up default resource pointers and names.. */
739 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
740 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
741 child->resource[i]->name = child->name;
742 }
743 bridge->subordinate = child;
744
745 add_dev:
746 pci_set_bus_msi_domain(child);
747 ret = device_register(&child->dev);
748 WARN_ON(ret < 0);
749
750 pcibios_add_bus(child);
751
752 /* Create legacy_io and legacy_mem files for this bus */
753 pci_create_legacy_files(child);
754
755 return child;
756 }
757
758 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
759 int busnr)
760 {
761 struct pci_bus *child;
762
763 child = pci_alloc_child_bus(parent, dev, busnr);
764 if (child) {
765 down_write(&pci_bus_sem);
766 list_add_tail(&child->node, &parent->children);
767 up_write(&pci_bus_sem);
768 }
769 return child;
770 }
771 EXPORT_SYMBOL(pci_add_new_bus);
772
773 static void pci_enable_crs(struct pci_dev *pdev)
774 {
775 u16 root_cap = 0;
776
777 /* Enable CRS Software Visibility if supported */
778 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
779 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
780 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
781 PCI_EXP_RTCTL_CRSSVE);
782 }
783
784 /*
785 * If it's a bridge, configure it and scan the bus behind it.
786 * For CardBus bridges, we don't scan behind as the devices will
787 * be handled by the bridge driver itself.
788 *
789 * We need to process bridges in two passes -- first we scan those
790 * already configured by the BIOS and after we are done with all of
791 * them, we proceed to assigning numbers to the remaining buses in
792 * order to avoid overlaps between old and new bus numbers.
793 */
794 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
795 {
796 struct pci_bus *child;
797 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
798 u32 buses, i, j = 0;
799 u16 bctl;
800 u8 primary, secondary, subordinate;
801 int broken = 0;
802
803 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
804 primary = buses & 0xFF;
805 secondary = (buses >> 8) & 0xFF;
806 subordinate = (buses >> 16) & 0xFF;
807
808 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
809 secondary, subordinate, pass);
810
811 if (!primary && (primary != bus->number) && secondary && subordinate) {
812 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
813 primary = bus->number;
814 }
815
816 /* Check if setup is sensible at all */
817 if (!pass &&
818 (primary != bus->number || secondary <= bus->number ||
819 secondary > subordinate)) {
820 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
821 secondary, subordinate);
822 broken = 1;
823 }
824
825 /* Disable MasterAbortMode during probing to avoid reporting
826 of bus errors (in some architectures) */
827 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
828 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
829 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
830
831 pci_enable_crs(dev);
832
833 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
834 !is_cardbus && !broken) {
835 unsigned int cmax;
836 /*
837 * Bus already configured by firmware, process it in the first
838 * pass and just note the configuration.
839 */
840 if (pass)
841 goto out;
842
843 /*
844 * The bus might already exist for two reasons: Either we are
845 * rescanning the bus or the bus is reachable through more than
846 * one bridge. The second case can happen with the i450NX
847 * chipset.
848 */
849 child = pci_find_bus(pci_domain_nr(bus), secondary);
850 if (!child) {
851 child = pci_add_new_bus(bus, dev, secondary);
852 if (!child)
853 goto out;
854 child->primary = primary;
855 pci_bus_insert_busn_res(child, secondary, subordinate);
856 child->bridge_ctl = bctl;
857 }
858
859 /* Read and initialize bridge resources */
860 pci_read_bridge_bases(child);
861
862 cmax = pci_scan_child_bus(child);
863 if (cmax > subordinate)
864 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
865 subordinate, cmax);
866 /* subordinate should equal child->busn_res.end */
867 if (subordinate > max)
868 max = subordinate;
869 } else {
870 /*
871 * We need to assign a number to this bus which we always
872 * do in the second pass.
873 */
874 if (!pass) {
875 if (pcibios_assign_all_busses() || broken || is_cardbus)
876 /* Temporarily disable forwarding of the
877 configuration cycles on all bridges in
878 this bus segment to avoid possible
879 conflicts in the second pass between two
880 bridges programmed with overlapping
881 bus ranges. */
882 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
883 buses & ~0xffffff);
884 goto out;
885 }
886
887 /* Clear errors */
888 pci_write_config_word(dev, PCI_STATUS, 0xffff);
889
890 /* Prevent assigning a bus number that already exists.
891 * This can happen when a bridge is hot-plugged, so in
892 * this case we only re-scan this bus. */
893 child = pci_find_bus(pci_domain_nr(bus), max+1);
894 if (!child) {
895 child = pci_add_new_bus(bus, dev, max+1);
896 if (!child)
897 goto out;
898 pci_bus_insert_busn_res(child, max+1, 0xff);
899 }
900 max++;
901 buses = (buses & 0xff000000)
902 | ((unsigned int)(child->primary) << 0)
903 | ((unsigned int)(child->busn_res.start) << 8)
904 | ((unsigned int)(child->busn_res.end) << 16);
905
906 /*
907 * yenta.c forces a secondary latency timer of 176.
908 * Copy that behaviour here.
909 */
910 if (is_cardbus) {
911 buses &= ~0xff000000;
912 buses |= CARDBUS_LATENCY_TIMER << 24;
913 }
914
915 /*
916 * We need to blast all three values with a single write.
917 */
918 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
919
920 if (!is_cardbus) {
921 child->bridge_ctl = bctl;
922
923 /* Read and initialize bridge resources */
924 pci_read_bridge_bases(child);
925 max = pci_scan_child_bus(child);
926 } else {
927 /*
928 * For CardBus bridges, we leave 4 bus numbers
929 * as cards with a PCI-to-PCI bridge can be
930 * inserted later.
931 */
932 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
933 struct pci_bus *parent = bus;
934 if (pci_find_bus(pci_domain_nr(bus),
935 max+i+1))
936 break;
937 while (parent->parent) {
938 if ((!pcibios_assign_all_busses()) &&
939 (parent->busn_res.end > max) &&
940 (parent->busn_res.end <= max+i)) {
941 j = 1;
942 }
943 parent = parent->parent;
944 }
945 if (j) {
946 /*
947 * Often, there are two cardbus bridges
948 * -- try to leave one valid bus number
949 * for each one.
950 */
951 i /= 2;
952 break;
953 }
954 }
955 max += i;
956 }
957 /*
958 * Set the subordinate bus number to its real value.
959 */
960 pci_bus_update_busn_res_end(child, max);
961 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
962 }
963
964 sprintf(child->name,
965 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
966 pci_domain_nr(bus), child->number);
967
968 /* Has only triggered on CardBus, fixup is in yenta_socket */
969 while (bus->parent) {
970 if ((child->busn_res.end > bus->busn_res.end) ||
971 (child->number > bus->busn_res.end) ||
972 (child->number < bus->number) ||
973 (child->busn_res.end < bus->number)) {
974 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
975 &child->busn_res,
976 (bus->number > child->busn_res.end &&
977 bus->busn_res.end < child->number) ?
978 "wholly" : "partially",
979 bus->self->transparent ? " transparent" : "",
980 dev_name(&bus->dev),
981 &bus->busn_res);
982 }
983 bus = bus->parent;
984 }
985
986 out:
987 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
988
989 return max;
990 }
991 EXPORT_SYMBOL(pci_scan_bridge);
992
993 /*
994 * Read interrupt line and base address registers.
995 * The architecture-dependent code can tweak these, of course.
996 */
997 static void pci_read_irq(struct pci_dev *dev)
998 {
999 unsigned char irq;
1000
1001 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1002 dev->pin = irq;
1003 if (irq)
1004 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1005 dev->irq = irq;
1006 }
1007
1008 void set_pcie_port_type(struct pci_dev *pdev)
1009 {
1010 int pos;
1011 u16 reg16;
1012 int type;
1013 struct pci_dev *parent;
1014
1015 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1016 if (!pos)
1017 return;
1018 pdev->pcie_cap = pos;
1019 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1020 pdev->pcie_flags_reg = reg16;
1021 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1022 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1023
1024 /*
1025 * A Root Port is always the upstream end of a Link. No PCIe
1026 * component has two Links. Two Links are connected by a Switch
1027 * that has a Port on each Link and internal logic to connect the
1028 * two Ports.
1029 */
1030 type = pci_pcie_type(pdev);
1031 if (type == PCI_EXP_TYPE_ROOT_PORT)
1032 pdev->has_secondary_link = 1;
1033 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1034 type == PCI_EXP_TYPE_DOWNSTREAM) {
1035 parent = pci_upstream_bridge(pdev);
1036
1037 /*
1038 * Usually there's an upstream device (Root Port or Switch
1039 * Downstream Port), but we can't assume one exists.
1040 */
1041 if (parent && !parent->has_secondary_link)
1042 pdev->has_secondary_link = 1;
1043 }
1044 }
1045
1046 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1047 {
1048 u32 reg32;
1049
1050 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1051 if (reg32 & PCI_EXP_SLTCAP_HPC)
1052 pdev->is_hotplug_bridge = 1;
1053 }
1054
1055 /**
1056 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1057 * @dev: PCI device
1058 *
1059 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1060 * when forwarding a type1 configuration request the bridge must check that
1061 * the extended register address field is zero. The bridge is not permitted
1062 * to forward the transactions and must handle it as an Unsupported Request.
1063 * Some bridges do not follow this rule and simply drop the extended register
1064 * bits, resulting in the standard config space being aliased, every 256
1065 * bytes across the entire configuration space. Test for this condition by
1066 * comparing the first dword of each potential alias to the vendor/device ID.
1067 * Known offenders:
1068 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1069 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1070 */
1071 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1072 {
1073 #ifdef CONFIG_PCI_QUIRKS
1074 int pos;
1075 u32 header, tmp;
1076
1077 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1078
1079 for (pos = PCI_CFG_SPACE_SIZE;
1080 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1081 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1082 || header != tmp)
1083 return false;
1084 }
1085
1086 return true;
1087 #else
1088 return false;
1089 #endif
1090 }
1091
1092 /**
1093 * pci_cfg_space_size - get the configuration space size of the PCI device.
1094 * @dev: PCI device
1095 *
1096 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1097 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1098 * access it. Maybe we don't have a way to generate extended config space
1099 * accesses, or the device is behind a reverse Express bridge. So we try
1100 * reading the dword at 0x100 which must either be 0 or a valid extended
1101 * capability header.
1102 */
1103 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1104 {
1105 u32 status;
1106 int pos = PCI_CFG_SPACE_SIZE;
1107
1108 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1109 goto fail;
1110 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1111 goto fail;
1112
1113 return PCI_CFG_SPACE_EXP_SIZE;
1114
1115 fail:
1116 return PCI_CFG_SPACE_SIZE;
1117 }
1118
1119 int pci_cfg_space_size(struct pci_dev *dev)
1120 {
1121 int pos;
1122 u32 status;
1123 u16 class;
1124
1125 class = dev->class >> 8;
1126 if (class == PCI_CLASS_BRIDGE_HOST)
1127 return pci_cfg_space_size_ext(dev);
1128
1129 if (!pci_is_pcie(dev)) {
1130 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1131 if (!pos)
1132 goto fail;
1133
1134 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1135 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1136 goto fail;
1137 }
1138
1139 return pci_cfg_space_size_ext(dev);
1140
1141 fail:
1142 return PCI_CFG_SPACE_SIZE;
1143 }
1144
1145 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1146
1147 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1148 {
1149 /*
1150 * Disable the MSI hardware to avoid screaming interrupts
1151 * during boot. This is the power on reset default so
1152 * usually this should be a noop.
1153 */
1154 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1155 if (dev->msi_cap)
1156 pci_msi_set_enable(dev, 0);
1157
1158 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1159 if (dev->msix_cap)
1160 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1161 }
1162
1163 /**
1164 * pci_setup_device - fill in class and map information of a device
1165 * @dev: the device structure to fill
1166 *
1167 * Initialize the device structure with information about the device's
1168 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1169 * Called at initialisation of the PCI subsystem and by CardBus services.
1170 * Returns 0 on success and negative if unknown type of device (not normal,
1171 * bridge or CardBus).
1172 */
1173 int pci_setup_device(struct pci_dev *dev)
1174 {
1175 u32 class;
1176 u8 hdr_type;
1177 int pos = 0;
1178 struct pci_bus_region region;
1179 struct resource *res;
1180
1181 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1182 return -EIO;
1183
1184 dev->sysdata = dev->bus->sysdata;
1185 dev->dev.parent = dev->bus->bridge;
1186 dev->dev.bus = &pci_bus_type;
1187 dev->hdr_type = hdr_type & 0x7f;
1188 dev->multifunction = !!(hdr_type & 0x80);
1189 dev->error_state = pci_channel_io_normal;
1190 set_pcie_port_type(dev);
1191
1192 pci_dev_assign_slot(dev);
1193 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1194 set this higher, assuming the system even supports it. */
1195 dev->dma_mask = 0xffffffff;
1196
1197 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1198 dev->bus->number, PCI_SLOT(dev->devfn),
1199 PCI_FUNC(dev->devfn));
1200
1201 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1202 dev->revision = class & 0xff;
1203 dev->class = class >> 8; /* upper 3 bytes */
1204
1205 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1206 dev->vendor, dev->device, dev->hdr_type, dev->class);
1207
1208 /* need to have dev->class ready */
1209 dev->cfg_size = pci_cfg_space_size(dev);
1210
1211 /* "Unknown power state" */
1212 dev->current_state = PCI_UNKNOWN;
1213
1214 pci_msi_setup_pci_dev(dev);
1215
1216 /* Early fixups, before probing the BARs */
1217 pci_fixup_device(pci_fixup_early, dev);
1218 /* device class may be changed after fixup */
1219 class = dev->class >> 8;
1220
1221 switch (dev->hdr_type) { /* header type */
1222 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1223 if (class == PCI_CLASS_BRIDGE_PCI)
1224 goto bad;
1225 pci_read_irq(dev);
1226 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1227 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1228 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1229
1230 /*
1231 * Do the ugly legacy mode stuff here rather than broken chip
1232 * quirk code. Legacy mode ATA controllers have fixed
1233 * addresses. These are not always echoed in BAR0-3, and
1234 * BAR0-3 in a few cases contain junk!
1235 */
1236 if (class == PCI_CLASS_STORAGE_IDE) {
1237 u8 progif;
1238 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1239 if ((progif & 1) == 0) {
1240 region.start = 0x1F0;
1241 region.end = 0x1F7;
1242 res = &dev->resource[0];
1243 res->flags = LEGACY_IO_RESOURCE;
1244 pcibios_bus_to_resource(dev->bus, res, &region);
1245 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1246 res);
1247 region.start = 0x3F6;
1248 region.end = 0x3F6;
1249 res = &dev->resource[1];
1250 res->flags = LEGACY_IO_RESOURCE;
1251 pcibios_bus_to_resource(dev->bus, res, &region);
1252 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1253 res);
1254 }
1255 if ((progif & 4) == 0) {
1256 region.start = 0x170;
1257 region.end = 0x177;
1258 res = &dev->resource[2];
1259 res->flags = LEGACY_IO_RESOURCE;
1260 pcibios_bus_to_resource(dev->bus, res, &region);
1261 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1262 res);
1263 region.start = 0x376;
1264 region.end = 0x376;
1265 res = &dev->resource[3];
1266 res->flags = LEGACY_IO_RESOURCE;
1267 pcibios_bus_to_resource(dev->bus, res, &region);
1268 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1269 res);
1270 }
1271 }
1272 break;
1273
1274 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1275 if (class != PCI_CLASS_BRIDGE_PCI)
1276 goto bad;
1277 /* The PCI-to-PCI bridge spec requires that subtractive
1278 decoding (i.e. transparent) bridge must have programming
1279 interface code of 0x01. */
1280 pci_read_irq(dev);
1281 dev->transparent = ((dev->class & 0xff) == 1);
1282 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1283 set_pcie_hotplug_bridge(dev);
1284 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1285 if (pos) {
1286 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1287 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1288 }
1289 break;
1290
1291 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1292 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1293 goto bad;
1294 pci_read_irq(dev);
1295 pci_read_bases(dev, 1, 0);
1296 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1297 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1298 break;
1299
1300 default: /* unknown header */
1301 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1302 dev->hdr_type);
1303 return -EIO;
1304
1305 bad:
1306 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1307 dev->class, dev->hdr_type);
1308 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1309 }
1310
1311 /* We found a fine healthy device, go go go... */
1312 return 0;
1313 }
1314
1315 static void pci_configure_mps(struct pci_dev *dev)
1316 {
1317 struct pci_dev *bridge = pci_upstream_bridge(dev);
1318 int mps, p_mps, rc;
1319
1320 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1321 return;
1322
1323 mps = pcie_get_mps(dev);
1324 p_mps = pcie_get_mps(bridge);
1325
1326 if (mps == p_mps)
1327 return;
1328
1329 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1330 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1331 mps, pci_name(bridge), p_mps);
1332 return;
1333 }
1334
1335 /*
1336 * Fancier MPS configuration is done later by
1337 * pcie_bus_configure_settings()
1338 */
1339 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1340 return;
1341
1342 rc = pcie_set_mps(dev, p_mps);
1343 if (rc) {
1344 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1345 p_mps);
1346 return;
1347 }
1348
1349 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1350 p_mps, mps, 128 << dev->pcie_mpss);
1351 }
1352
1353 static struct hpp_type0 pci_default_type0 = {
1354 .revision = 1,
1355 .cache_line_size = 8,
1356 .latency_timer = 0x40,
1357 .enable_serr = 0,
1358 .enable_perr = 0,
1359 };
1360
1361 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1362 {
1363 u16 pci_cmd, pci_bctl;
1364
1365 if (!hpp)
1366 hpp = &pci_default_type0;
1367
1368 if (hpp->revision > 1) {
1369 dev_warn(&dev->dev,
1370 "PCI settings rev %d not supported; using defaults\n",
1371 hpp->revision);
1372 hpp = &pci_default_type0;
1373 }
1374
1375 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1376 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1377 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1378 if (hpp->enable_serr)
1379 pci_cmd |= PCI_COMMAND_SERR;
1380 if (hpp->enable_perr)
1381 pci_cmd |= PCI_COMMAND_PARITY;
1382 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1383
1384 /* Program bridge control value */
1385 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1386 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1387 hpp->latency_timer);
1388 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1389 if (hpp->enable_serr)
1390 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1391 if (hpp->enable_perr)
1392 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1393 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1394 }
1395 }
1396
1397 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1398 {
1399 if (hpp)
1400 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1401 }
1402
1403 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1404 {
1405 int pos;
1406 u32 reg32;
1407
1408 if (!hpp)
1409 return;
1410
1411 if (hpp->revision > 1) {
1412 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1413 hpp->revision);
1414 return;
1415 }
1416
1417 /*
1418 * Don't allow _HPX to change MPS or MRRS settings. We manage
1419 * those to make sure they're consistent with the rest of the
1420 * platform.
1421 */
1422 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1423 PCI_EXP_DEVCTL_READRQ;
1424 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1425 PCI_EXP_DEVCTL_READRQ);
1426
1427 /* Initialize Device Control Register */
1428 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1429 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1430
1431 /* Initialize Link Control Register */
1432 if (pcie_cap_has_lnkctl(dev))
1433 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1434 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1435
1436 /* Find Advanced Error Reporting Enhanced Capability */
1437 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1438 if (!pos)
1439 return;
1440
1441 /* Initialize Uncorrectable Error Mask Register */
1442 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1443 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1444 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1445
1446 /* Initialize Uncorrectable Error Severity Register */
1447 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1448 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1449 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1450
1451 /* Initialize Correctable Error Mask Register */
1452 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1453 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1454 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1455
1456 /* Initialize Advanced Error Capabilities and Control Register */
1457 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1458 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1459 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1460
1461 /*
1462 * FIXME: The following two registers are not supported yet.
1463 *
1464 * o Secondary Uncorrectable Error Severity Register
1465 * o Secondary Uncorrectable Error Mask Register
1466 */
1467 }
1468
1469 static void pci_configure_device(struct pci_dev *dev)
1470 {
1471 struct hotplug_params hpp;
1472 int ret;
1473
1474 pci_configure_mps(dev);
1475
1476 memset(&hpp, 0, sizeof(hpp));
1477 ret = pci_get_hp_params(dev, &hpp);
1478 if (ret)
1479 return;
1480
1481 program_hpp_type2(dev, hpp.t2);
1482 program_hpp_type1(dev, hpp.t1);
1483 program_hpp_type0(dev, hpp.t0);
1484 }
1485
1486 static void pci_release_capabilities(struct pci_dev *dev)
1487 {
1488 pci_vpd_release(dev);
1489 pci_iov_release(dev);
1490 pci_free_cap_save_buffers(dev);
1491 }
1492
1493 /**
1494 * pci_release_dev - free a pci device structure when all users of it are finished.
1495 * @dev: device that's been disconnected
1496 *
1497 * Will be called only by the device core when all users of this pci device are
1498 * done.
1499 */
1500 static void pci_release_dev(struct device *dev)
1501 {
1502 struct pci_dev *pci_dev;
1503
1504 pci_dev = to_pci_dev(dev);
1505 pci_release_capabilities(pci_dev);
1506 pci_release_of_node(pci_dev);
1507 pcibios_release_device(pci_dev);
1508 pci_bus_put(pci_dev->bus);
1509 kfree(pci_dev->driver_override);
1510 kfree(pci_dev);
1511 }
1512
1513 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1514 {
1515 struct pci_dev *dev;
1516
1517 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1518 if (!dev)
1519 return NULL;
1520
1521 INIT_LIST_HEAD(&dev->bus_list);
1522 dev->dev.type = &pci_dev_type;
1523 dev->bus = pci_bus_get(bus);
1524
1525 return dev;
1526 }
1527 EXPORT_SYMBOL(pci_alloc_dev);
1528
1529 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1530 int crs_timeout)
1531 {
1532 int delay = 1;
1533
1534 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1535 return false;
1536
1537 /* some broken boards return 0 or ~0 if a slot is empty: */
1538 if (*l == 0xffffffff || *l == 0x00000000 ||
1539 *l == 0x0000ffff || *l == 0xffff0000)
1540 return false;
1541
1542 /*
1543 * Configuration Request Retry Status. Some root ports return the
1544 * actual device ID instead of the synthetic ID (0xFFFF) required
1545 * by the PCIe spec. Ignore the device ID and only check for
1546 * (vendor id == 1).
1547 */
1548 while ((*l & 0xffff) == 0x0001) {
1549 if (!crs_timeout)
1550 return false;
1551
1552 msleep(delay);
1553 delay *= 2;
1554 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1555 return false;
1556 /* Card hasn't responded in 60 seconds? Must be stuck. */
1557 if (delay > crs_timeout) {
1558 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1559 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1560 PCI_FUNC(devfn));
1561 return false;
1562 }
1563 }
1564
1565 return true;
1566 }
1567 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1568
1569 /*
1570 * Read the config data for a PCI device, sanity-check it
1571 * and fill in the dev structure...
1572 */
1573 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1574 {
1575 struct pci_dev *dev;
1576 u32 l;
1577
1578 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1579 return NULL;
1580
1581 dev = pci_alloc_dev(bus);
1582 if (!dev)
1583 return NULL;
1584
1585 dev->devfn = devfn;
1586 dev->vendor = l & 0xffff;
1587 dev->device = (l >> 16) & 0xffff;
1588
1589 pci_set_of_node(dev);
1590
1591 if (pci_setup_device(dev)) {
1592 pci_bus_put(dev->bus);
1593 kfree(dev);
1594 return NULL;
1595 }
1596
1597 return dev;
1598 }
1599
1600 static void pci_init_capabilities(struct pci_dev *dev)
1601 {
1602 /* Enhanced Allocation */
1603 pci_ea_init(dev);
1604
1605 /* MSI/MSI-X list */
1606 pci_msi_init_pci_dev(dev);
1607
1608 /* Buffers for saving PCIe and PCI-X capabilities */
1609 pci_allocate_cap_save_buffers(dev);
1610
1611 /* Power Management */
1612 pci_pm_init(dev);
1613
1614 /* Vital Product Data */
1615 pci_vpd_pci22_init(dev);
1616
1617 /* Alternative Routing-ID Forwarding */
1618 pci_configure_ari(dev);
1619
1620 /* Single Root I/O Virtualization */
1621 pci_iov_init(dev);
1622
1623 /* Address Translation Services */
1624 pci_ats_init(dev);
1625
1626 /* Enable ACS P2P upstream forwarding */
1627 pci_enable_acs(dev);
1628
1629 pci_cleanup_aer_error_status_regs(dev);
1630 }
1631
1632 static void pci_set_msi_domain(struct pci_dev *dev)
1633 {
1634 /*
1635 * If no domain has been set through the pcibios_add_device
1636 * callback, inherit the default from the bus device.
1637 */
1638 if (!dev_get_msi_domain(&dev->dev))
1639 dev_set_msi_domain(&dev->dev,
1640 dev_get_msi_domain(&dev->bus->dev));
1641 }
1642
1643 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1644 {
1645 int ret;
1646
1647 pci_configure_device(dev);
1648
1649 device_initialize(&dev->dev);
1650 dev->dev.release = pci_release_dev;
1651
1652 set_dev_node(&dev->dev, pcibus_to_node(bus));
1653 dev->dev.dma_mask = &dev->dma_mask;
1654 dev->dev.dma_parms = &dev->dma_parms;
1655 dev->dev.coherent_dma_mask = 0xffffffffull;
1656 of_pci_dma_configure(dev);
1657
1658 pci_set_dma_max_seg_size(dev, 65536);
1659 pci_set_dma_seg_boundary(dev, 0xffffffff);
1660
1661 /* Fix up broken headers */
1662 pci_fixup_device(pci_fixup_header, dev);
1663
1664 /* moved out from quirk header fixup code */
1665 pci_reassigndev_resource_alignment(dev);
1666
1667 /* Clear the state_saved flag. */
1668 dev->state_saved = false;
1669
1670 /* Initialize various capabilities */
1671 pci_init_capabilities(dev);
1672
1673 /*
1674 * Add the device to our list of discovered devices
1675 * and the bus list for fixup functions, etc.
1676 */
1677 down_write(&pci_bus_sem);
1678 list_add_tail(&dev->bus_list, &bus->devices);
1679 up_write(&pci_bus_sem);
1680
1681 ret = pcibios_add_device(dev);
1682 WARN_ON(ret < 0);
1683
1684 /* Setup MSI irq domain */
1685 pci_set_msi_domain(dev);
1686
1687 /* Notifier could use PCI capabilities */
1688 dev->match_driver = false;
1689 ret = device_add(&dev->dev);
1690 WARN_ON(ret < 0);
1691 }
1692
1693 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1694 {
1695 struct pci_dev *dev;
1696
1697 dev = pci_get_slot(bus, devfn);
1698 if (dev) {
1699 pci_dev_put(dev);
1700 return dev;
1701 }
1702
1703 dev = pci_scan_device(bus, devfn);
1704 if (!dev)
1705 return NULL;
1706
1707 pci_device_add(dev, bus);
1708
1709 return dev;
1710 }
1711 EXPORT_SYMBOL(pci_scan_single_device);
1712
1713 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1714 {
1715 int pos;
1716 u16 cap = 0;
1717 unsigned next_fn;
1718
1719 if (pci_ari_enabled(bus)) {
1720 if (!dev)
1721 return 0;
1722 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1723 if (!pos)
1724 return 0;
1725
1726 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1727 next_fn = PCI_ARI_CAP_NFN(cap);
1728 if (next_fn <= fn)
1729 return 0; /* protect against malformed list */
1730
1731 return next_fn;
1732 }
1733
1734 /* dev may be NULL for non-contiguous multifunction devices */
1735 if (!dev || dev->multifunction)
1736 return (fn + 1) % 8;
1737
1738 return 0;
1739 }
1740
1741 static int only_one_child(struct pci_bus *bus)
1742 {
1743 struct pci_dev *parent = bus->self;
1744
1745 if (!parent || !pci_is_pcie(parent))
1746 return 0;
1747 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1748 return 1;
1749 if (parent->has_secondary_link &&
1750 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1751 return 1;
1752 return 0;
1753 }
1754
1755 /**
1756 * pci_scan_slot - scan a PCI slot on a bus for devices.
1757 * @bus: PCI bus to scan
1758 * @devfn: slot number to scan (must have zero function.)
1759 *
1760 * Scan a PCI slot on the specified PCI bus for devices, adding
1761 * discovered devices to the @bus->devices list. New devices
1762 * will not have is_added set.
1763 *
1764 * Returns the number of new devices found.
1765 */
1766 int pci_scan_slot(struct pci_bus *bus, int devfn)
1767 {
1768 unsigned fn, nr = 0;
1769 struct pci_dev *dev;
1770
1771 if (only_one_child(bus) && (devfn > 0))
1772 return 0; /* Already scanned the entire slot */
1773
1774 dev = pci_scan_single_device(bus, devfn);
1775 if (!dev)
1776 return 0;
1777 if (!dev->is_added)
1778 nr++;
1779
1780 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1781 dev = pci_scan_single_device(bus, devfn + fn);
1782 if (dev) {
1783 if (!dev->is_added)
1784 nr++;
1785 dev->multifunction = 1;
1786 }
1787 }
1788
1789 /* only one slot has pcie device */
1790 if (bus->self && nr)
1791 pcie_aspm_init_link_state(bus->self);
1792
1793 return nr;
1794 }
1795 EXPORT_SYMBOL(pci_scan_slot);
1796
1797 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1798 {
1799 u8 *smpss = data;
1800
1801 if (!pci_is_pcie(dev))
1802 return 0;
1803
1804 /*
1805 * We don't have a way to change MPS settings on devices that have
1806 * drivers attached. A hot-added device might support only the minimum
1807 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1808 * where devices may be hot-added, we limit the fabric MPS to 128 so
1809 * hot-added devices will work correctly.
1810 *
1811 * However, if we hot-add a device to a slot directly below a Root
1812 * Port, it's impossible for there to be other existing devices below
1813 * the port. We don't limit the MPS in this case because we can
1814 * reconfigure MPS on both the Root Port and the hot-added device,
1815 * and there are no other devices involved.
1816 *
1817 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1818 */
1819 if (dev->is_hotplug_bridge &&
1820 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1821 *smpss = 0;
1822
1823 if (*smpss > dev->pcie_mpss)
1824 *smpss = dev->pcie_mpss;
1825
1826 return 0;
1827 }
1828
1829 static void pcie_write_mps(struct pci_dev *dev, int mps)
1830 {
1831 int rc;
1832
1833 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1834 mps = 128 << dev->pcie_mpss;
1835
1836 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1837 dev->bus->self)
1838 /* For "Performance", the assumption is made that
1839 * downstream communication will never be larger than
1840 * the MRRS. So, the MPS only needs to be configured
1841 * for the upstream communication. This being the case,
1842 * walk from the top down and set the MPS of the child
1843 * to that of the parent bus.
1844 *
1845 * Configure the device MPS with the smaller of the
1846 * device MPSS or the bridge MPS (which is assumed to be
1847 * properly configured at this point to the largest
1848 * allowable MPS based on its parent bus).
1849 */
1850 mps = min(mps, pcie_get_mps(dev->bus->self));
1851 }
1852
1853 rc = pcie_set_mps(dev, mps);
1854 if (rc)
1855 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1856 }
1857
1858 static void pcie_write_mrrs(struct pci_dev *dev)
1859 {
1860 int rc, mrrs;
1861
1862 /* In the "safe" case, do not configure the MRRS. There appear to be
1863 * issues with setting MRRS to 0 on a number of devices.
1864 */
1865 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1866 return;
1867
1868 /* For Max performance, the MRRS must be set to the largest supported
1869 * value. However, it cannot be configured larger than the MPS the
1870 * device or the bus can support. This should already be properly
1871 * configured by a prior call to pcie_write_mps.
1872 */
1873 mrrs = pcie_get_mps(dev);
1874
1875 /* MRRS is a R/W register. Invalid values can be written, but a
1876 * subsequent read will verify if the value is acceptable or not.
1877 * If the MRRS value provided is not acceptable (e.g., too large),
1878 * shrink the value until it is acceptable to the HW.
1879 */
1880 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1881 rc = pcie_set_readrq(dev, mrrs);
1882 if (!rc)
1883 break;
1884
1885 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1886 mrrs /= 2;
1887 }
1888
1889 if (mrrs < 128)
1890 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1891 }
1892
1893 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1894 {
1895 int mps, orig_mps;
1896
1897 if (!pci_is_pcie(dev))
1898 return 0;
1899
1900 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1901 pcie_bus_config == PCIE_BUS_DEFAULT)
1902 return 0;
1903
1904 mps = 128 << *(u8 *)data;
1905 orig_mps = pcie_get_mps(dev);
1906
1907 pcie_write_mps(dev, mps);
1908 pcie_write_mrrs(dev);
1909
1910 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1911 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1912 orig_mps, pcie_get_readrq(dev));
1913
1914 return 0;
1915 }
1916
1917 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1918 * parents then children fashion. If this changes, then this code will not
1919 * work as designed.
1920 */
1921 void pcie_bus_configure_settings(struct pci_bus *bus)
1922 {
1923 u8 smpss = 0;
1924
1925 if (!bus->self)
1926 return;
1927
1928 if (!pci_is_pcie(bus->self))
1929 return;
1930
1931 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1932 * to be aware of the MPS of the destination. To work around this,
1933 * simply force the MPS of the entire system to the smallest possible.
1934 */
1935 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1936 smpss = 0;
1937
1938 if (pcie_bus_config == PCIE_BUS_SAFE) {
1939 smpss = bus->self->pcie_mpss;
1940
1941 pcie_find_smpss(bus->self, &smpss);
1942 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1943 }
1944
1945 pcie_bus_configure_set(bus->self, &smpss);
1946 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1947 }
1948 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1949
1950 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1951 {
1952 unsigned int devfn, pass, max = bus->busn_res.start;
1953 struct pci_dev *dev;
1954
1955 dev_dbg(&bus->dev, "scanning bus\n");
1956
1957 /* Go find them, Rover! */
1958 for (devfn = 0; devfn < 0x100; devfn += 8)
1959 pci_scan_slot(bus, devfn);
1960
1961 /* Reserve buses for SR-IOV capability. */
1962 max += pci_iov_bus_range(bus);
1963
1964 /*
1965 * After performing arch-dependent fixup of the bus, look behind
1966 * all PCI-to-PCI bridges on this bus.
1967 */
1968 if (!bus->is_added) {
1969 dev_dbg(&bus->dev, "fixups for bus\n");
1970 pcibios_fixup_bus(bus);
1971 bus->is_added = 1;
1972 }
1973
1974 for (pass = 0; pass < 2; pass++)
1975 list_for_each_entry(dev, &bus->devices, bus_list) {
1976 if (pci_is_bridge(dev))
1977 max = pci_scan_bridge(bus, dev, max, pass);
1978 }
1979
1980 /*
1981 * We've scanned the bus and so we know all about what's on
1982 * the other side of any bridges that may be on this bus plus
1983 * any devices.
1984 *
1985 * Return how far we've got finding sub-buses.
1986 */
1987 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1988 return max;
1989 }
1990 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1991
1992 /**
1993 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1994 * @bridge: Host bridge to set up.
1995 *
1996 * Default empty implementation. Replace with an architecture-specific setup
1997 * routine, if necessary.
1998 */
1999 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2000 {
2001 return 0;
2002 }
2003
2004 void __weak pcibios_add_bus(struct pci_bus *bus)
2005 {
2006 }
2007
2008 void __weak pcibios_remove_bus(struct pci_bus *bus)
2009 {
2010 }
2011
2012 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2013 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2014 {
2015 int error;
2016 struct pci_host_bridge *bridge;
2017 struct pci_bus *b, *b2;
2018 struct resource_entry *window, *n;
2019 struct resource *res;
2020 resource_size_t offset;
2021 char bus_addr[64];
2022 char *fmt;
2023
2024 b = pci_alloc_bus(NULL);
2025 if (!b)
2026 return NULL;
2027
2028 b->sysdata = sysdata;
2029 b->ops = ops;
2030 b->number = b->busn_res.start = bus;
2031 pci_bus_assign_domain_nr(b, parent);
2032 b2 = pci_find_bus(pci_domain_nr(b), bus);
2033 if (b2) {
2034 /* If we already got to this bus through a different bridge, ignore it */
2035 dev_dbg(&b2->dev, "bus already known\n");
2036 goto err_out;
2037 }
2038
2039 bridge = pci_alloc_host_bridge(b);
2040 if (!bridge)
2041 goto err_out;
2042
2043 bridge->dev.parent = parent;
2044 bridge->dev.release = pci_release_host_bridge_dev;
2045 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2046 error = pcibios_root_bridge_prepare(bridge);
2047 if (error) {
2048 kfree(bridge);
2049 goto err_out;
2050 }
2051
2052 error = device_register(&bridge->dev);
2053 if (error) {
2054 put_device(&bridge->dev);
2055 goto err_out;
2056 }
2057 b->bridge = get_device(&bridge->dev);
2058 device_enable_async_suspend(b->bridge);
2059 pci_set_bus_of_node(b);
2060 pci_set_bus_msi_domain(b);
2061
2062 if (!parent)
2063 set_dev_node(b->bridge, pcibus_to_node(b));
2064
2065 b->dev.class = &pcibus_class;
2066 b->dev.parent = b->bridge;
2067 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2068 error = device_register(&b->dev);
2069 if (error)
2070 goto class_dev_reg_err;
2071
2072 pcibios_add_bus(b);
2073
2074 /* Create legacy_io and legacy_mem files for this bus */
2075 pci_create_legacy_files(b);
2076
2077 if (parent)
2078 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2079 else
2080 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2081
2082 /* Add initial resources to the bus */
2083 resource_list_for_each_entry_safe(window, n, resources) {
2084 list_move_tail(&window->node, &bridge->windows);
2085 res = window->res;
2086 offset = window->offset;
2087 if (res->flags & IORESOURCE_BUS)
2088 pci_bus_insert_busn_res(b, bus, res->end);
2089 else
2090 pci_bus_add_resource(b, res, 0);
2091 if (offset) {
2092 if (resource_type(res) == IORESOURCE_IO)
2093 fmt = " (bus address [%#06llx-%#06llx])";
2094 else
2095 fmt = " (bus address [%#010llx-%#010llx])";
2096 snprintf(bus_addr, sizeof(bus_addr), fmt,
2097 (unsigned long long) (res->start - offset),
2098 (unsigned long long) (res->end - offset));
2099 } else
2100 bus_addr[0] = '\0';
2101 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2102 }
2103
2104 down_write(&pci_bus_sem);
2105 list_add_tail(&b->node, &pci_root_buses);
2106 up_write(&pci_bus_sem);
2107
2108 return b;
2109
2110 class_dev_reg_err:
2111 put_device(&bridge->dev);
2112 device_unregister(&bridge->dev);
2113 err_out:
2114 kfree(b);
2115 return NULL;
2116 }
2117 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2118
2119 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2120 {
2121 struct resource *res = &b->busn_res;
2122 struct resource *parent_res, *conflict;
2123
2124 res->start = bus;
2125 res->end = bus_max;
2126 res->flags = IORESOURCE_BUS;
2127
2128 if (!pci_is_root_bus(b))
2129 parent_res = &b->parent->busn_res;
2130 else {
2131 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2132 res->flags |= IORESOURCE_PCI_FIXED;
2133 }
2134
2135 conflict = request_resource_conflict(parent_res, res);
2136
2137 if (conflict)
2138 dev_printk(KERN_DEBUG, &b->dev,
2139 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2140 res, pci_is_root_bus(b) ? "domain " : "",
2141 parent_res, conflict->name, conflict);
2142
2143 return conflict == NULL;
2144 }
2145
2146 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2147 {
2148 struct resource *res = &b->busn_res;
2149 struct resource old_res = *res;
2150 resource_size_t size;
2151 int ret;
2152
2153 if (res->start > bus_max)
2154 return -EINVAL;
2155
2156 size = bus_max - res->start + 1;
2157 ret = adjust_resource(res, res->start, size);
2158 dev_printk(KERN_DEBUG, &b->dev,
2159 "busn_res: %pR end %s updated to %02x\n",
2160 &old_res, ret ? "can not be" : "is", bus_max);
2161
2162 if (!ret && !res->parent)
2163 pci_bus_insert_busn_res(b, res->start, res->end);
2164
2165 return ret;
2166 }
2167
2168 void pci_bus_release_busn_res(struct pci_bus *b)
2169 {
2170 struct resource *res = &b->busn_res;
2171 int ret;
2172
2173 if (!res->flags || !res->parent)
2174 return;
2175
2176 ret = release_resource(res);
2177 dev_printk(KERN_DEBUG, &b->dev,
2178 "busn_res: %pR %s released\n",
2179 res, ret ? "can not be" : "is");
2180 }
2181
2182 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2183 struct pci_ops *ops, void *sysdata,
2184 struct list_head *resources, struct msi_controller *msi)
2185 {
2186 struct resource_entry *window;
2187 bool found = false;
2188 struct pci_bus *b;
2189 int max;
2190
2191 resource_list_for_each_entry(window, resources)
2192 if (window->res->flags & IORESOURCE_BUS) {
2193 found = true;
2194 break;
2195 }
2196
2197 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2198 if (!b)
2199 return NULL;
2200
2201 b->msi = msi;
2202
2203 if (!found) {
2204 dev_info(&b->dev,
2205 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2206 bus);
2207 pci_bus_insert_busn_res(b, bus, 255);
2208 }
2209
2210 max = pci_scan_child_bus(b);
2211
2212 if (!found)
2213 pci_bus_update_busn_res_end(b, max);
2214
2215 return b;
2216 }
2217
2218 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2219 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2220 {
2221 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2222 NULL);
2223 }
2224 EXPORT_SYMBOL(pci_scan_root_bus);
2225
2226 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2227 void *sysdata)
2228 {
2229 LIST_HEAD(resources);
2230 struct pci_bus *b;
2231
2232 pci_add_resource(&resources, &ioport_resource);
2233 pci_add_resource(&resources, &iomem_resource);
2234 pci_add_resource(&resources, &busn_resource);
2235 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2236 if (b) {
2237 pci_scan_child_bus(b);
2238 } else {
2239 pci_free_resource_list(&resources);
2240 }
2241 return b;
2242 }
2243 EXPORT_SYMBOL(pci_scan_bus);
2244
2245 /**
2246 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2247 * @bridge: PCI bridge for the bus to scan
2248 *
2249 * Scan a PCI bus and child buses for new devices, add them,
2250 * and enable them, resizing bridge mmio/io resource if necessary
2251 * and possible. The caller must ensure the child devices are already
2252 * removed for resizing to occur.
2253 *
2254 * Returns the max number of subordinate bus discovered.
2255 */
2256 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2257 {
2258 unsigned int max;
2259 struct pci_bus *bus = bridge->subordinate;
2260
2261 max = pci_scan_child_bus(bus);
2262
2263 pci_assign_unassigned_bridge_resources(bridge);
2264
2265 pci_bus_add_devices(bus);
2266
2267 return max;
2268 }
2269
2270 /**
2271 * pci_rescan_bus - scan a PCI bus for devices.
2272 * @bus: PCI bus to scan
2273 *
2274 * Scan a PCI bus and child buses for new devices, adds them,
2275 * and enables them.
2276 *
2277 * Returns the max number of subordinate bus discovered.
2278 */
2279 unsigned int pci_rescan_bus(struct pci_bus *bus)
2280 {
2281 unsigned int max;
2282
2283 max = pci_scan_child_bus(bus);
2284 pci_assign_unassigned_bus_resources(bus);
2285 pci_bus_add_devices(bus);
2286
2287 return max;
2288 }
2289 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2290
2291 /*
2292 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2293 * routines should always be executed under this mutex.
2294 */
2295 static DEFINE_MUTEX(pci_rescan_remove_lock);
2296
2297 void pci_lock_rescan_remove(void)
2298 {
2299 mutex_lock(&pci_rescan_remove_lock);
2300 }
2301 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2302
2303 void pci_unlock_rescan_remove(void)
2304 {
2305 mutex_unlock(&pci_rescan_remove_lock);
2306 }
2307 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2308
2309 static int __init pci_sort_bf_cmp(const struct device *d_a,
2310 const struct device *d_b)
2311 {
2312 const struct pci_dev *a = to_pci_dev(d_a);
2313 const struct pci_dev *b = to_pci_dev(d_b);
2314
2315 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2316 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2317
2318 if (a->bus->number < b->bus->number) return -1;
2319 else if (a->bus->number > b->bus->number) return 1;
2320
2321 if (a->devfn < b->devfn) return -1;
2322 else if (a->devfn > b->devfn) return 1;
2323
2324 return 0;
2325 }
2326
2327 void __init pci_sort_breadthfirst(void)
2328 {
2329 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2330 }
Linux kernel - Deliverables
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