2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses
);
22 EXPORT_SYMBOL(pci_root_buses
);
25 static int find_anything(struct device
*dev
, void *data
)
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
35 int no_pci_devices(void)
40 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
41 no_devices
= (dev
== NULL
);
45 EXPORT_SYMBOL(no_pci_devices
);
47 #ifdef HAVE_PCI_LEGACY
49 * pci_create_legacy_files - create legacy I/O port and memory files
50 * @b: bus to create files under
52 * Some platforms allow access to legacy I/O port and ISA memory space on
53 * a per-bus basis. This routine creates the files and ties them into
54 * their associated read, write and mmap files from pci-sysfs.c
56 * On error unwind, but don't propogate the error to the caller
57 * as it is ok to set up the PCI bus without these files.
59 static void pci_create_legacy_files(struct pci_bus
*b
)
63 b
->legacy_io
= kzalloc(sizeof(struct bin_attribute
) * 2,
68 b
->legacy_io
->attr
.name
= "legacy_io";
69 b
->legacy_io
->size
= 0xffff;
70 b
->legacy_io
->attr
.mode
= S_IRUSR
| S_IWUSR
;
71 b
->legacy_io
->read
= pci_read_legacy_io
;
72 b
->legacy_io
->write
= pci_write_legacy_io
;
73 error
= device_create_bin_file(&b
->dev
, b
->legacy_io
);
77 /* Allocated above after the legacy_io struct */
78 b
->legacy_mem
= b
->legacy_io
+ 1;
79 b
->legacy_mem
->attr
.name
= "legacy_mem";
80 b
->legacy_mem
->size
= 1024*1024;
81 b
->legacy_mem
->attr
.mode
= S_IRUSR
| S_IWUSR
;
82 b
->legacy_mem
->mmap
= pci_mmap_legacy_mem
;
83 error
= device_create_bin_file(&b
->dev
, b
->legacy_mem
);
90 device_remove_bin_file(&b
->dev
, b
->legacy_io
);
95 printk(KERN_WARNING
"pci: warning: could not create legacy I/O port "
96 "and ISA memory resources to sysfs\n");
100 void pci_remove_legacy_files(struct pci_bus
*b
)
103 device_remove_bin_file(&b
->dev
, b
->legacy_io
);
104 device_remove_bin_file(&b
->dev
, b
->legacy_mem
);
105 kfree(b
->legacy_io
); /* both are allocated here */
108 #else /* !HAVE_PCI_LEGACY */
109 static inline void pci_create_legacy_files(struct pci_bus
*bus
) { return; }
110 void pci_remove_legacy_files(struct pci_bus
*bus
) { return; }
111 #endif /* HAVE_PCI_LEGACY */
114 * PCI Bus Class Devices
116 static ssize_t
pci_bus_show_cpuaffinity(struct device
*dev
,
118 struct device_attribute
*attr
,
124 cpumask
= pcibus_to_cpumask(to_pci_bus(dev
));
126 cpulist_scnprintf(buf
, PAGE_SIZE
-2, cpumask
):
127 cpumask_scnprintf(buf
, PAGE_SIZE
-2, cpumask
);
133 static ssize_t
inline pci_bus_show_cpumaskaffinity(struct device
*dev
,
134 struct device_attribute
*attr
,
137 return pci_bus_show_cpuaffinity(dev
, 0, attr
, buf
);
140 static ssize_t
inline pci_bus_show_cpulistaffinity(struct device
*dev
,
141 struct device_attribute
*attr
,
144 return pci_bus_show_cpuaffinity(dev
, 1, attr
, buf
);
147 DEVICE_ATTR(cpuaffinity
, S_IRUGO
, pci_bus_show_cpumaskaffinity
, NULL
);
148 DEVICE_ATTR(cpulistaffinity
, S_IRUGO
, pci_bus_show_cpulistaffinity
, NULL
);
153 static void release_pcibus_dev(struct device
*dev
)
155 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
158 put_device(pci_bus
->bridge
);
162 static struct class pcibus_class
= {
164 .dev_release
= &release_pcibus_dev
,
167 static int __init
pcibus_class_init(void)
169 return class_register(&pcibus_class
);
171 postcore_initcall(pcibus_class_init
);
174 * Translate the low bits of the PCI base
175 * to the resource type
177 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
179 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
180 return IORESOURCE_IO
;
182 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
183 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
185 return IORESOURCE_MEM
;
188 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
190 u64 size
= mask
& maxbase
; /* Find the significant bits */
194 /* Get the lowest of them to find the decode size, and
195 from that the extent. */
196 size
= (size
& ~(size
-1)) - 1;
198 /* base == maxbase can be valid only if the BAR has
199 already been programmed with all 1s. */
200 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
207 pci_bar_unknown
, /* Standard PCI BAR probe */
208 pci_bar_io
, /* An io port BAR */
209 pci_bar_mem32
, /* A 32-bit memory BAR */
210 pci_bar_mem64
, /* A 64-bit memory BAR */
213 static inline enum pci_bar_type
decode_bar(struct resource
*res
, u32 bar
)
215 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
216 res
->flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
220 res
->flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
222 if (res
->flags
== PCI_BASE_ADDRESS_MEM_TYPE_64
)
223 return pci_bar_mem64
;
224 return pci_bar_mem32
;
228 * If the type is not unknown, we assume that the lowest bit is 'enable'.
229 * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
231 static int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
232 struct resource
*res
, unsigned int pos
)
236 mask
= type
? ~PCI_ROM_ADDRESS_ENABLE
: ~0;
238 res
->name
= pci_name(dev
);
240 pci_read_config_dword(dev
, pos
, &l
);
241 pci_write_config_dword(dev
, pos
, mask
);
242 pci_read_config_dword(dev
, pos
, &sz
);
243 pci_write_config_dword(dev
, pos
, l
);
246 * All bits set in sz means the device isn't working properly.
247 * If the BAR isn't implemented, all bits must be 0. If it's a
248 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
251 if (!sz
|| sz
== 0xffffffff)
255 * I don't know how l can have all bits set. Copied from old code.
256 * Maybe it fixes a bug on some ancient platform.
261 if (type
== pci_bar_unknown
) {
262 type
= decode_bar(res
, l
);
263 res
->flags
|= pci_calc_resource_flags(l
) | IORESOURCE_SIZEALIGN
;
264 if (type
== pci_bar_io
) {
265 l
&= PCI_BASE_ADDRESS_IO_MASK
;
266 mask
= PCI_BASE_ADDRESS_IO_MASK
& 0xffff;
268 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
269 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
272 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
273 l
&= PCI_ROM_ADDRESS_MASK
;
274 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
277 if (type
== pci_bar_mem64
) {
280 u64 mask64
= mask
| (u64
)~0 << 32;
282 pci_read_config_dword(dev
, pos
+ 4, &l
);
283 pci_write_config_dword(dev
, pos
+ 4, ~0);
284 pci_read_config_dword(dev
, pos
+ 4, &sz
);
285 pci_write_config_dword(dev
, pos
+ 4, l
);
287 l64
|= ((u64
)l
<< 32);
288 sz64
|= ((u64
)sz
<< 32);
290 sz64
= pci_size(l64
, sz64
, mask64
);
295 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
296 dev_err(&dev
->dev
, "can't handle 64-bit BAR\n");
298 } else if ((sizeof(resource_size_t
) < 8) && l
) {
299 /* Address above 32-bit boundary; disable the BAR */
300 pci_write_config_dword(dev
, pos
, 0);
301 pci_write_config_dword(dev
, pos
+ 4, 0);
306 res
->end
= l64
+ sz64
;
307 printk(KERN_DEBUG
"PCI: %s reg %x 64bit mmio: %pR\n",
308 pci_name(dev
), pos
, res
);
311 sz
= pci_size(l
, sz
, mask
);
318 printk(KERN_DEBUG
"PCI: %s reg %x %s: %pR\n",
320 (res
->flags
& IORESOURCE_IO
) ? "io port":"32bit mmio",
325 return (type
== pci_bar_mem64
) ? 1 : 0;
331 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
333 unsigned int pos
, reg
;
335 for (pos
= 0; pos
< howmany
; pos
++) {
336 struct resource
*res
= &dev
->resource
[pos
];
337 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
338 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
342 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
343 dev
->rom_base_reg
= rom
;
344 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
345 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
346 IORESOURCE_SIZEALIGN
;
347 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
351 void __devinit
pci_read_bridge_bases(struct pci_bus
*child
)
353 struct pci_dev
*dev
= child
->self
;
354 u8 io_base_lo
, io_limit_lo
;
355 u16 mem_base_lo
, mem_limit_lo
;
356 unsigned long base
, limit
;
357 struct resource
*res
;
360 if (!dev
) /* It's a host bus, nothing to read */
363 if (dev
->transparent
) {
364 dev_info(&dev
->dev
, "transparent bridge\n");
365 for(i
= 3; i
< PCI_BUS_NUM_RESOURCES
; i
++)
366 child
->resource
[i
] = child
->parent
->resource
[i
- 3];
370 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
372 res
= child
->resource
[0];
373 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
374 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
375 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
376 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
378 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
379 u16 io_base_hi
, io_limit_hi
;
380 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
381 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
382 base
|= (io_base_hi
<< 16);
383 limit
|= (io_limit_hi
<< 16);
387 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
391 res
->end
= limit
+ 0xfff;
392 printk(KERN_DEBUG
"PCI: bridge %s io port: %pR\n",
396 res
= child
->resource
[1];
397 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
398 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
399 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
400 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
402 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
404 res
->end
= limit
+ 0xfffff;
405 printk(KERN_DEBUG
"PCI: bridge %s 32bit mmio: %pR\n",
409 res
= child
->resource
[2];
410 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
411 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
412 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
413 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
415 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
416 u32 mem_base_hi
, mem_limit_hi
;
417 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
418 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
421 * Some bridges set the base > limit by default, and some
422 * (broken) BIOSes do not initialize them. If we find
423 * this, just assume they are not being used.
425 if (mem_base_hi
<= mem_limit_hi
) {
426 #if BITS_PER_LONG == 64
427 base
|= ((long) mem_base_hi
) << 32;
428 limit
|= ((long) mem_limit_hi
) << 32;
430 if (mem_base_hi
|| mem_limit_hi
) {
431 dev_err(&dev
->dev
, "can't handle 64-bit "
432 "address space for bridge\n");
439 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
441 res
->end
= limit
+ 0xfffff;
442 printk(KERN_DEBUG
"PCI: bridge %s %sbit mmio pref: %pR\n",
444 (res
->flags
& PCI_PREF_RANGE_TYPE_64
) ? "64":"32", res
);
448 static struct pci_bus
* pci_alloc_bus(void)
452 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
454 INIT_LIST_HEAD(&b
->node
);
455 INIT_LIST_HEAD(&b
->children
);
456 INIT_LIST_HEAD(&b
->devices
);
457 INIT_LIST_HEAD(&b
->slots
);
462 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
463 struct pci_dev
*bridge
, int busnr
)
465 struct pci_bus
*child
;
469 * Allocate a new bus, and inherit stuff from the parent..
471 child
= pci_alloc_bus();
475 child
->self
= bridge
;
476 child
->parent
= parent
;
477 child
->ops
= parent
->ops
;
478 child
->sysdata
= parent
->sysdata
;
479 child
->bus_flags
= parent
->bus_flags
;
480 child
->bridge
= get_device(&bridge
->dev
);
482 /* initialize some portions of the bus device, but don't register it
483 * now as the parent is not properly set up yet. This device will get
484 * registered later in pci_bus_add_devices()
486 child
->dev
.class = &pcibus_class
;
487 sprintf(child
->dev
.bus_id
, "%04x:%02x", pci_domain_nr(child
), busnr
);
490 * Set up the primary, secondary and subordinate
493 child
->number
= child
->secondary
= busnr
;
494 child
->primary
= parent
->secondary
;
495 child
->subordinate
= 0xff;
497 /* Set up default resource pointers and names.. */
498 for (i
= 0; i
< 4; i
++) {
499 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
500 child
->resource
[i
]->name
= child
->name
;
502 bridge
->subordinate
= child
;
507 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
509 struct pci_bus
*child
;
511 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
513 down_write(&pci_bus_sem
);
514 list_add_tail(&child
->node
, &parent
->children
);
515 up_write(&pci_bus_sem
);
520 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
522 struct pci_bus
*parent
= child
->parent
;
524 /* Attempts to fix that up are really dangerous unless
525 we're going to re-assign all bus numbers. */
526 if (!pcibios_assign_all_busses())
529 while (parent
->parent
&& parent
->subordinate
< max
) {
530 parent
->subordinate
= max
;
531 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
532 parent
= parent
->parent
;
537 * If it's a bridge, configure it and scan the bus behind it.
538 * For CardBus bridges, we don't scan behind as the devices will
539 * be handled by the bridge driver itself.
541 * We need to process bridges in two passes -- first we scan those
542 * already configured by the BIOS and after we are done with all of
543 * them, we proceed to assigning numbers to the remaining buses in
544 * order to avoid overlaps between old and new bus numbers.
546 int __devinit
pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
548 struct pci_bus
*child
;
549 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
553 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
555 dev_dbg(&dev
->dev
, "scanning behind bridge, config %06x, pass %d\n",
556 buses
& 0xffffff, pass
);
558 /* Disable MasterAbortMode during probing to avoid reporting
559 of bus errors (in some architectures) */
560 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
561 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
562 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
564 if ((buses
& 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus
) {
565 unsigned int cmax
, busnr
;
567 * Bus already configured by firmware, process it in the first
568 * pass and just note the configuration.
572 busnr
= (buses
>> 8) & 0xFF;
575 * If we already got to this bus through a different bridge,
576 * ignore it. This can happen with the i450NX chipset.
578 if (pci_find_bus(pci_domain_nr(bus
), busnr
)) {
579 dev_info(&dev
->dev
, "bus %04x:%02x already known\n",
580 pci_domain_nr(bus
), busnr
);
584 child
= pci_add_new_bus(bus
, dev
, busnr
);
587 child
->primary
= buses
& 0xFF;
588 child
->subordinate
= (buses
>> 16) & 0xFF;
589 child
->bridge_ctl
= bctl
;
591 cmax
= pci_scan_child_bus(child
);
594 if (child
->subordinate
> max
)
595 max
= child
->subordinate
;
598 * We need to assign a number to this bus which we always
599 * do in the second pass.
602 if (pcibios_assign_all_busses())
603 /* Temporarily disable forwarding of the
604 configuration cycles on all bridges in
605 this bus segment to avoid possible
606 conflicts in the second pass between two
607 bridges programmed with overlapping
609 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
615 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
617 /* Prevent assigning a bus number that already exists.
618 * This can happen when a bridge is hot-plugged */
619 if (pci_find_bus(pci_domain_nr(bus
), max
+1))
621 child
= pci_add_new_bus(bus
, dev
, ++max
);
622 buses
= (buses
& 0xff000000)
623 | ((unsigned int)(child
->primary
) << 0)
624 | ((unsigned int)(child
->secondary
) << 8)
625 | ((unsigned int)(child
->subordinate
) << 16);
628 * yenta.c forces a secondary latency timer of 176.
629 * Copy that behaviour here.
632 buses
&= ~0xff000000;
633 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
637 * We need to blast all three values with a single write.
639 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
642 child
->bridge_ctl
= bctl
;
644 * Adjust subordinate busnr in parent buses.
645 * We do this before scanning for children because
646 * some devices may not be detected if the bios
649 pci_fixup_parent_subordinate_busnr(child
, max
);
650 /* Now we can scan all subordinate buses... */
651 max
= pci_scan_child_bus(child
);
653 * now fix it up again since we have found
654 * the real value of max.
656 pci_fixup_parent_subordinate_busnr(child
, max
);
659 * For CardBus bridges, we leave 4 bus numbers
660 * as cards with a PCI-to-PCI bridge can be
663 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
664 struct pci_bus
*parent
= bus
;
665 if (pci_find_bus(pci_domain_nr(bus
),
668 while (parent
->parent
) {
669 if ((!pcibios_assign_all_busses()) &&
670 (parent
->subordinate
> max
) &&
671 (parent
->subordinate
<= max
+i
)) {
674 parent
= parent
->parent
;
678 * Often, there are two cardbus bridges
679 * -- try to leave one valid bus number
687 pci_fixup_parent_subordinate_busnr(child
, max
);
690 * Set the subordinate bus number to its real value.
692 child
->subordinate
= max
;
693 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
697 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
698 pci_domain_nr(bus
), child
->number
);
700 /* Has only triggered on CardBus, fixup is in yenta_socket */
701 while (bus
->parent
) {
702 if ((child
->subordinate
> bus
->subordinate
) ||
703 (child
->number
> bus
->subordinate
) ||
704 (child
->number
< bus
->number
) ||
705 (child
->subordinate
< bus
->number
)) {
706 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
707 "hidden behind%s bridge #%02x (-#%02x)\n",
708 child
->number
, child
->subordinate
,
709 (bus
->number
> child
->subordinate
&&
710 bus
->subordinate
< child
->number
) ?
711 "wholly" : "partially",
712 bus
->self
->transparent
? " transparent" : "",
713 bus
->number
, bus
->subordinate
);
719 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
725 * Read interrupt line and base address registers.
726 * The architecture-dependent code can tweak these, of course.
728 static void pci_read_irq(struct pci_dev
*dev
)
732 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
735 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
739 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
742 * pci_setup_device - fill in class and map information of a device
743 * @dev: the device structure to fill
745 * Initialize the device structure with information about the device's
746 * vendor,class,memory and IO-space addresses,IRQ lines etc.
747 * Called at initialisation of the PCI subsystem and by CardBus services.
748 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
751 static int pci_setup_device(struct pci_dev
* dev
)
755 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
756 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
757 PCI_FUNC(dev
->devfn
));
759 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
760 dev
->revision
= class & 0xff;
761 class >>= 8; /* upper 3 bytes */
765 dev_dbg(&dev
->dev
, "found [%04x/%04x] class %06x header type %02x\n",
766 dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
768 /* "Unknown power state" */
769 dev
->current_state
= PCI_UNKNOWN
;
771 /* Early fixups, before probing the BARs */
772 pci_fixup_device(pci_fixup_early
, dev
);
773 class = dev
->class >> 8;
775 switch (dev
->hdr_type
) { /* header type */
776 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
777 if (class == PCI_CLASS_BRIDGE_PCI
)
780 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
781 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
782 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
785 * Do the ugly legacy mode stuff here rather than broken chip
786 * quirk code. Legacy mode ATA controllers have fixed
787 * addresses. These are not always echoed in BAR0-3, and
788 * BAR0-3 in a few cases contain junk!
790 if (class == PCI_CLASS_STORAGE_IDE
) {
792 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
793 if ((progif
& 1) == 0) {
794 dev
->resource
[0].start
= 0x1F0;
795 dev
->resource
[0].end
= 0x1F7;
796 dev
->resource
[0].flags
= LEGACY_IO_RESOURCE
;
797 dev
->resource
[1].start
= 0x3F6;
798 dev
->resource
[1].end
= 0x3F6;
799 dev
->resource
[1].flags
= LEGACY_IO_RESOURCE
;
801 if ((progif
& 4) == 0) {
802 dev
->resource
[2].start
= 0x170;
803 dev
->resource
[2].end
= 0x177;
804 dev
->resource
[2].flags
= LEGACY_IO_RESOURCE
;
805 dev
->resource
[3].start
= 0x376;
806 dev
->resource
[3].end
= 0x376;
807 dev
->resource
[3].flags
= LEGACY_IO_RESOURCE
;
812 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
813 if (class != PCI_CLASS_BRIDGE_PCI
)
815 /* The PCI-to-PCI bridge spec requires that subtractive
816 decoding (i.e. transparent) bridge must have programming
817 interface code of 0x01. */
819 dev
->transparent
= ((dev
->class & 0xff) == 1);
820 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
823 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
824 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
827 pci_read_bases(dev
, 1, 0);
828 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
829 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
832 default: /* unknown header */
833 dev_err(&dev
->dev
, "unknown header type %02x, "
834 "ignoring device\n", dev
->hdr_type
);
838 dev_err(&dev
->dev
, "ignoring class %02x (doesn't match header "
839 "type %02x)\n", class, dev
->hdr_type
);
840 dev
->class = PCI_CLASS_NOT_DEFINED
;
843 /* We found a fine healthy device, go go go... */
848 * pci_release_dev - free a pci device structure when all users of it are finished.
849 * @dev: device that's been disconnected
851 * Will be called only by the device core when all users of this pci device are
854 static void pci_release_dev(struct device
*dev
)
856 struct pci_dev
*pci_dev
;
858 pci_dev
= to_pci_dev(dev
);
859 pci_vpd_release(pci_dev
);
863 static void set_pcie_port_type(struct pci_dev
*pdev
)
868 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
872 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
873 pdev
->pcie_type
= (reg16
& PCI_EXP_FLAGS_TYPE
) >> 4;
877 * pci_cfg_space_size - get the configuration space size of the PCI device.
880 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
881 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
882 * access it. Maybe we don't have a way to generate extended config space
883 * accesses, or the device is behind a reverse Express bridge. So we try
884 * reading the dword at 0x100 which must either be 0 or a valid extended
887 int pci_cfg_space_size_ext(struct pci_dev
*dev
)
891 if (pci_read_config_dword(dev
, 256, &status
) != PCIBIOS_SUCCESSFUL
)
893 if (status
== 0xffffffff)
896 return PCI_CFG_SPACE_EXP_SIZE
;
899 return PCI_CFG_SPACE_SIZE
;
902 int pci_cfg_space_size(struct pci_dev
*dev
)
907 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
909 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
913 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
914 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
918 return pci_cfg_space_size_ext(dev
);
921 return PCI_CFG_SPACE_SIZE
;
924 static void pci_release_bus_bridge_dev(struct device
*dev
)
929 struct pci_dev
*alloc_pci_dev(void)
933 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
937 INIT_LIST_HEAD(&dev
->bus_list
);
939 pci_msi_init_pci_dev(dev
);
943 EXPORT_SYMBOL(alloc_pci_dev
);
946 * Read the config data for a PCI device, sanity-check it
947 * and fill in the dev structure...
949 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
956 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
959 /* some broken boards return 0 or ~0 if a slot is empty: */
960 if (l
== 0xffffffff || l
== 0x00000000 ||
961 l
== 0x0000ffff || l
== 0xffff0000)
964 /* Configuration request Retry Status */
965 while (l
== 0xffff0001) {
968 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
970 /* Card hasn't responded in 60 seconds? Must be stuck. */
971 if (delay
> 60 * 1000) {
972 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
973 "responding\n", pci_domain_nr(bus
),
974 bus
->number
, PCI_SLOT(devfn
),
980 if (pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
))
983 dev
= alloc_pci_dev();
988 dev
->sysdata
= bus
->sysdata
;
989 dev
->dev
.parent
= bus
->bridge
;
990 dev
->dev
.bus
= &pci_bus_type
;
992 dev
->hdr_type
= hdr_type
& 0x7f;
993 dev
->multifunction
= !!(hdr_type
& 0x80);
994 dev
->vendor
= l
& 0xffff;
995 dev
->device
= (l
>> 16) & 0xffff;
996 dev
->cfg_size
= pci_cfg_space_size(dev
);
997 dev
->error_state
= pci_channel_io_normal
;
998 set_pcie_port_type(dev
);
1000 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1001 set this higher, assuming the system even supports it. */
1002 dev
->dma_mask
= 0xffffffff;
1003 if (pci_setup_device(dev
) < 0) {
1008 pci_vpd_pci22_init(dev
);
1013 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1015 device_initialize(&dev
->dev
);
1016 dev
->dev
.release
= pci_release_dev
;
1019 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1020 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1021 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1023 pci_set_dma_max_seg_size(dev
, 65536);
1024 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1026 /* Fix up broken headers */
1027 pci_fixup_device(pci_fixup_header
, dev
);
1029 /* Initialize power management of the device */
1033 * Add the device to our list of discovered devices
1034 * and the bus list for fixup functions, etc.
1036 down_write(&pci_bus_sem
);
1037 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1038 up_write(&pci_bus_sem
);
1041 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1043 struct pci_dev
*dev
;
1045 dev
= pci_scan_device(bus
, devfn
);
1049 pci_device_add(dev
, bus
);
1053 EXPORT_SYMBOL(pci_scan_single_device
);
1056 * pci_scan_slot - scan a PCI slot on a bus for devices.
1057 * @bus: PCI bus to scan
1058 * @devfn: slot number to scan (must have zero function.)
1060 * Scan a PCI slot on the specified PCI bus for devices, adding
1061 * discovered devices to the @bus->devices list. New devices
1062 * will not have is_added set.
1064 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1069 scan_all_fns
= pcibios_scan_all_fns(bus
, devfn
);
1071 for (func
= 0; func
< 8; func
++, devfn
++) {
1072 struct pci_dev
*dev
;
1074 dev
= pci_scan_single_device(bus
, devfn
);
1079 * If this is a single function device,
1080 * don't scan past the first function.
1082 if (!dev
->multifunction
) {
1084 dev
->multifunction
= 1;
1090 if (func
== 0 && !scan_all_fns
)
1095 /* only one slot has pcie device */
1096 if (bus
->self
&& nr
)
1097 pcie_aspm_init_link_state(bus
->self
);
1102 unsigned int __devinit
pci_scan_child_bus(struct pci_bus
*bus
)
1104 unsigned int devfn
, pass
, max
= bus
->secondary
;
1105 struct pci_dev
*dev
;
1107 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus
), bus
->number
);
1109 /* Go find them, Rover! */
1110 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1111 pci_scan_slot(bus
, devfn
);
1114 * After performing arch-dependent fixup of the bus, look behind
1115 * all PCI-to-PCI bridges on this bus.
1117 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus
), bus
->number
);
1118 pcibios_fixup_bus(bus
);
1119 for (pass
=0; pass
< 2; pass
++)
1120 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1121 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1122 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1123 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1127 * We've scanned the bus and so we know all about what's on
1128 * the other side of any bridges that may be on this bus plus
1131 * Return how far we've got finding sub-buses.
1133 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1134 pci_domain_nr(bus
), bus
->number
, max
);
1138 void __attribute__((weak
)) set_pci_bus_resources_arch_default(struct pci_bus
*b
)
1142 struct pci_bus
* pci_create_bus(struct device
*parent
,
1143 int bus
, struct pci_ops
*ops
, void *sysdata
)
1149 b
= pci_alloc_bus();
1153 dev
= kmalloc(sizeof(*dev
), GFP_KERNEL
);
1159 b
->sysdata
= sysdata
;
1162 if (pci_find_bus(pci_domain_nr(b
), bus
)) {
1163 /* If we already got to this bus through a different bridge, ignore it */
1164 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b
), bus
);
1168 down_write(&pci_bus_sem
);
1169 list_add_tail(&b
->node
, &pci_root_buses
);
1170 up_write(&pci_bus_sem
);
1172 memset(dev
, 0, sizeof(*dev
));
1173 dev
->parent
= parent
;
1174 dev
->release
= pci_release_bus_bridge_dev
;
1175 sprintf(dev
->bus_id
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1176 error
= device_register(dev
);
1179 b
->bridge
= get_device(dev
);
1182 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1184 b
->dev
.class = &pcibus_class
;
1185 b
->dev
.parent
= b
->bridge
;
1186 sprintf(b
->dev
.bus_id
, "%04x:%02x", pci_domain_nr(b
), bus
);
1187 error
= device_register(&b
->dev
);
1189 goto class_dev_reg_err
;
1190 error
= device_create_file(&b
->dev
, &dev_attr_cpuaffinity
);
1192 goto dev_create_file_err
;
1194 /* Create legacy_io and legacy_mem files for this bus */
1195 pci_create_legacy_files(b
);
1197 b
->number
= b
->secondary
= bus
;
1198 b
->resource
[0] = &ioport_resource
;
1199 b
->resource
[1] = &iomem_resource
;
1201 set_pci_bus_resources_arch_default(b
);
1205 dev_create_file_err
:
1206 device_unregister(&b
->dev
);
1208 device_unregister(dev
);
1210 down_write(&pci_bus_sem
);
1212 up_write(&pci_bus_sem
);
1219 struct pci_bus
* __devinit
pci_scan_bus_parented(struct device
*parent
,
1220 int bus
, struct pci_ops
*ops
, void *sysdata
)
1224 b
= pci_create_bus(parent
, bus
, ops
, sysdata
);
1226 b
->subordinate
= pci_scan_child_bus(b
);
1229 EXPORT_SYMBOL(pci_scan_bus_parented
);
1231 #ifdef CONFIG_HOTPLUG
1232 EXPORT_SYMBOL(pci_add_new_bus
);
1233 EXPORT_SYMBOL(pci_scan_slot
);
1234 EXPORT_SYMBOL(pci_scan_bridge
);
1235 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1238 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
1240 const struct pci_dev
*a
= to_pci_dev(d_a
);
1241 const struct pci_dev
*b
= to_pci_dev(d_b
);
1243 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
1244 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
1246 if (a
->bus
->number
< b
->bus
->number
) return -1;
1247 else if (a
->bus
->number
> b
->bus
->number
) return 1;
1249 if (a
->devfn
< b
->devfn
) return -1;
1250 else if (a
->devfn
> b
->devfn
) return 1;
1255 void __init
pci_sort_breadthfirst(void)
1257 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);