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PCI hotplug: acpiphp: remove superfluous _HPP/_HPX evaluation
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/ioport.h>
28 #include "pci.h"
29
30 int isa_dma_bridge_buggy;
31 EXPORT_SYMBOL(isa_dma_bridge_buggy);
32 int pci_pci_problems;
33 EXPORT_SYMBOL(pci_pci_problems);
34
35 #ifdef CONFIG_PCI_QUIRKS
36 /*
37 * This quirk function disables memory decoding and releases memory resources
38 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
39 * It also rounds up size to specified alignment.
40 * Later on, the kernel will assign page-aligned memory resource back
41 * to the device.
42 */
43 static void __devinit quirk_resource_alignment(struct pci_dev *dev)
44 {
45 int i;
46 struct resource *r;
47 resource_size_t align, size;
48 u16 command;
49
50 if (!pci_is_reassigndev(dev))
51 return;
52
53 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
54 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
55 dev_warn(&dev->dev,
56 "Can't reassign resources to host bridge.\n");
57 return;
58 }
59
60 dev_info(&dev->dev,
61 "Disabling memory decoding and releasing memory resources.\n");
62 pci_read_config_word(dev, PCI_COMMAND, &command);
63 command &= ~PCI_COMMAND_MEMORY;
64 pci_write_config_word(dev, PCI_COMMAND, command);
65
66 align = pci_specified_resource_alignment(dev);
67 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
68 r = &dev->resource[i];
69 if (!(r->flags & IORESOURCE_MEM))
70 continue;
71 size = resource_size(r);
72 if (size < align) {
73 size = align;
74 dev_info(&dev->dev,
75 "Rounding up size of resource #%d to %#llx.\n",
76 i, (unsigned long long)size);
77 }
78 r->end = size - 1;
79 r->start = 0;
80 }
81 /* Need to disable bridge's resource window,
82 * to enable the kernel to reassign new resource
83 * window later on.
84 */
85 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
86 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
87 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
88 r = &dev->resource[i];
89 if (!(r->flags & IORESOURCE_MEM))
90 continue;
91 r->end = resource_size(r) - 1;
92 r->start = 0;
93 }
94 pci_disable_bridge_window(dev);
95 }
96 }
97 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
98
99 /* The Mellanox Tavor device gives false positive parity errors
100 * Mark this device with a broken_parity_status, to allow
101 * PCI scanning code to "skip" this now blacklisted device.
102 */
103 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
104 {
105 dev->broken_parity_status = 1; /* This device gives false positives */
106 }
107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
109
110 /* Deal with broken BIOS'es that neglect to enable passive release,
111 which can cause problems in combination with the 82441FX/PPro MTRRs */
112 static void quirk_passive_release(struct pci_dev *dev)
113 {
114 struct pci_dev *d = NULL;
115 unsigned char dlc;
116
117 /* We have to make sure a particular bit is set in the PIIX3
118 ISA bridge, so we have to go out and find it. */
119 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
120 pci_read_config_byte(d, 0x82, &dlc);
121 if (!(dlc & 1<<1)) {
122 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
123 dlc |= 1<<1;
124 pci_write_config_byte(d, 0x82, dlc);
125 }
126 }
127 }
128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
129 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
130
131 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
132 but VIA don't answer queries. If you happen to have good contacts at VIA
133 ask them for me please -- Alan
134
135 This appears to be BIOS not version dependent. So presumably there is a
136 chipset level fix */
137
138 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
139 {
140 if (!isa_dma_bridge_buggy) {
141 isa_dma_bridge_buggy=1;
142 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
143 }
144 }
145 /*
146 * Its not totally clear which chipsets are the problematic ones
147 * We know 82C586 and 82C596 variants are affected.
148 */
149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
156
157 /*
158 * Chipsets where PCI->PCI transfers vanish or hang
159 */
160 static void __devinit quirk_nopcipci(struct pci_dev *dev)
161 {
162 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
163 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
164 pci_pci_problems |= PCIPCI_FAIL;
165 }
166 }
167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
169
170 static void __devinit quirk_nopciamd(struct pci_dev *dev)
171 {
172 u8 rev;
173 pci_read_config_byte(dev, 0x08, &rev);
174 if (rev == 0x13) {
175 /* Erratum 24 */
176 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
177 pci_pci_problems |= PCIAGP_FAIL;
178 }
179 }
180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
181
182 /*
183 * Triton requires workarounds to be used by the drivers
184 */
185 static void __devinit quirk_triton(struct pci_dev *dev)
186 {
187 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
188 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
189 pci_pci_problems |= PCIPCI_TRITON;
190 }
191 }
192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
196
197 /*
198 * VIA Apollo KT133 needs PCI latency patch
199 * Made according to a windows driver based patch by George E. Breese
200 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
201 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
202 * the info on which Mr Breese based his work.
203 *
204 * Updated based on further information from the site and also on
205 * information provided by VIA
206 */
207 static void quirk_vialatency(struct pci_dev *dev)
208 {
209 struct pci_dev *p;
210 u8 busarb;
211 /* Ok we have a potential problem chipset here. Now see if we have
212 a buggy southbridge */
213
214 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
215 if (p!=NULL) {
216 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
217 /* Check for buggy part revisions */
218 if (p->revision < 0x40 || p->revision > 0x42)
219 goto exit;
220 } else {
221 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
222 if (p==NULL) /* No problem parts */
223 goto exit;
224 /* Check for buggy part revisions */
225 if (p->revision < 0x10 || p->revision > 0x12)
226 goto exit;
227 }
228
229 /*
230 * Ok we have the problem. Now set the PCI master grant to
231 * occur every master grant. The apparent bug is that under high
232 * PCI load (quite common in Linux of course) you can get data
233 * loss when the CPU is held off the bus for 3 bus master requests
234 * This happens to include the IDE controllers....
235 *
236 * VIA only apply this fix when an SB Live! is present but under
237 * both Linux and Windows this isnt enough, and we have seen
238 * corruption without SB Live! but with things like 3 UDMA IDE
239 * controllers. So we ignore that bit of the VIA recommendation..
240 */
241
242 pci_read_config_byte(dev, 0x76, &busarb);
243 /* Set bit 4 and bi 5 of byte 76 to 0x01
244 "Master priority rotation on every PCI master grant */
245 busarb &= ~(1<<5);
246 busarb |= (1<<4);
247 pci_write_config_byte(dev, 0x76, busarb);
248 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
249 exit:
250 pci_dev_put(p);
251 }
252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
255 /* Must restore this on a resume from RAM */
256 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
257 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
258 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
259
260 /*
261 * VIA Apollo VP3 needs ETBF on BT848/878
262 */
263 static void __devinit quirk_viaetbf(struct pci_dev *dev)
264 {
265 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
266 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
267 pci_pci_problems |= PCIPCI_VIAETBF;
268 }
269 }
270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
271
272 static void __devinit quirk_vsfx(struct pci_dev *dev)
273 {
274 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
275 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
276 pci_pci_problems |= PCIPCI_VSFX;
277 }
278 }
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
280
281 /*
282 * Ali Magik requires workarounds to be used by the drivers
283 * that DMA to AGP space. Latency must be set to 0xA and triton
284 * workaround applied too
285 * [Info kindly provided by ALi]
286 */
287 static void __init quirk_alimagik(struct pci_dev *dev)
288 {
289 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
290 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
291 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
292 }
293 }
294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
296
297 /*
298 * Natoma has some interesting boundary conditions with Zoran stuff
299 * at least
300 */
301 static void __devinit quirk_natoma(struct pci_dev *dev)
302 {
303 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
305 pci_pci_problems |= PCIPCI_NATOMA;
306 }
307 }
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
314
315 /*
316 * This chip can cause PCI parity errors if config register 0xA0 is read
317 * while DMAs are occurring.
318 */
319 static void __devinit quirk_citrine(struct pci_dev *dev)
320 {
321 dev->cfg_size = 0xA0;
322 }
323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
324
325 /*
326 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
327 * If it's needed, re-allocate the region.
328 */
329 static void __devinit quirk_s3_64M(struct pci_dev *dev)
330 {
331 struct resource *r = &dev->resource[0];
332
333 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
334 r->start = 0;
335 r->end = 0x3ffffff;
336 }
337 }
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
340
341 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
342 unsigned size, int nr, const char *name)
343 {
344 region &= ~(size-1);
345 if (region) {
346 struct pci_bus_region bus_region;
347 struct resource *res = dev->resource + nr;
348
349 res->name = pci_name(dev);
350 res->start = region;
351 res->end = region + size - 1;
352 res->flags = IORESOURCE_IO;
353
354 /* Convert from PCI bus to resource space. */
355 bus_region.start = res->start;
356 bus_region.end = res->end;
357 pcibios_bus_to_resource(dev, res, &bus_region);
358
359 pci_claim_resource(dev, nr);
360 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
361 }
362 }
363
364 /*
365 * ATI Northbridge setups MCE the processor if you even
366 * read somewhere between 0x3b0->0x3bb or read 0x3d3
367 */
368 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
369 {
370 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
371 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
372 request_region(0x3b0, 0x0C, "RadeonIGP");
373 request_region(0x3d3, 0x01, "RadeonIGP");
374 }
375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
376
377 /*
378 * Let's make the southbridge information explicit instead
379 * of having to worry about people probing the ACPI areas,
380 * for example.. (Yes, it happens, and if you read the wrong
381 * ACPI register it will put the machine to sleep with no
382 * way of waking it up again. Bummer).
383 *
384 * ALI M7101: Two IO regions pointed to by words at
385 * 0xE0 (64 bytes of ACPI registers)
386 * 0xE2 (32 bytes of SMB registers)
387 */
388 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
389 {
390 u16 region;
391
392 pci_read_config_word(dev, 0xE0, &region);
393 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
394 pci_read_config_word(dev, 0xE2, &region);
395 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
396 }
397 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
398
399 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
400 {
401 u32 devres;
402 u32 mask, size, base;
403
404 pci_read_config_dword(dev, port, &devres);
405 if ((devres & enable) != enable)
406 return;
407 mask = (devres >> 16) & 15;
408 base = devres & 0xffff;
409 size = 16;
410 for (;;) {
411 unsigned bit = size >> 1;
412 if ((bit & mask) == bit)
413 break;
414 size = bit;
415 }
416 /*
417 * For now we only print it out. Eventually we'll want to
418 * reserve it (at least if it's in the 0x1000+ range), but
419 * let's get enough confirmation reports first.
420 */
421 base &= -size;
422 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
423 }
424
425 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
426 {
427 u32 devres;
428 u32 mask, size, base;
429
430 pci_read_config_dword(dev, port, &devres);
431 if ((devres & enable) != enable)
432 return;
433 base = devres & 0xffff0000;
434 mask = (devres & 0x3f) << 16;
435 size = 128 << 16;
436 for (;;) {
437 unsigned bit = size >> 1;
438 if ((bit & mask) == bit)
439 break;
440 size = bit;
441 }
442 /*
443 * For now we only print it out. Eventually we'll want to
444 * reserve it, but let's get enough confirmation reports first.
445 */
446 base &= -size;
447 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
448 }
449
450 /*
451 * PIIX4 ACPI: Two IO regions pointed to by longwords at
452 * 0x40 (64 bytes of ACPI registers)
453 * 0x90 (16 bytes of SMB registers)
454 * and a few strange programmable PIIX4 device resources.
455 */
456 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
457 {
458 u32 region, res_a;
459
460 pci_read_config_dword(dev, 0x40, &region);
461 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
462 pci_read_config_dword(dev, 0x90, &region);
463 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
464
465 /* Device resource A has enables for some of the other ones */
466 pci_read_config_dword(dev, 0x5c, &res_a);
467
468 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
469 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
470
471 /* Device resource D is just bitfields for static resources */
472
473 /* Device 12 enabled? */
474 if (res_a & (1 << 29)) {
475 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
476 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
477 }
478 /* Device 13 enabled? */
479 if (res_a & (1 << 30)) {
480 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
481 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
482 }
483 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
484 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
485 }
486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
488
489 /*
490 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
491 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
492 * 0x58 (64 bytes of GPIO I/O space)
493 */
494 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
495 {
496 u32 region;
497
498 pci_read_config_dword(dev, 0x40, &region);
499 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
500
501 pci_read_config_dword(dev, 0x58, &region);
502 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
503 }
504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
514
515 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
516 {
517 u32 region;
518
519 pci_read_config_dword(dev, 0x40, &region);
520 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
521
522 pci_read_config_dword(dev, 0x48, &region);
523 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
524 }
525
526 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
527 {
528 u32 val;
529 u32 size, base;
530
531 pci_read_config_dword(dev, reg, &val);
532
533 /* Enabled? */
534 if (!(val & 1))
535 return;
536 base = val & 0xfffc;
537 if (dynsize) {
538 /*
539 * This is not correct. It is 16, 32 or 64 bytes depending on
540 * register D31:F0:ADh bits 5:4.
541 *
542 * But this gets us at least _part_ of it.
543 */
544 size = 16;
545 } else {
546 size = 128;
547 }
548 base &= ~(size-1);
549
550 /* Just print it out for now. We should reserve it after more debugging */
551 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
552 }
553
554 static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
555 {
556 /* Shared ACPI/GPIO decode with all ICH6+ */
557 ich6_lpc_acpi_gpio(dev);
558
559 /* ICH6-specific generic IO decode */
560 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
561 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
562 }
563 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
565
566 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
567 {
568 u32 val;
569 u32 mask, base;
570
571 pci_read_config_dword(dev, reg, &val);
572
573 /* Enabled? */
574 if (!(val & 1))
575 return;
576
577 /*
578 * IO base in bits 15:2, mask in bits 23:18, both
579 * are dword-based
580 */
581 base = val & 0xfffc;
582 mask = (val >> 16) & 0xfc;
583 mask |= 3;
584
585 /* Just print it out for now. We should reserve it after more debugging */
586 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
587 }
588
589 /* ICH7-10 has the same common LPC generic IO decode registers */
590 static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
591 {
592 /* We share the common ACPI/DPIO decode with ICH6 */
593 ich6_lpc_acpi_gpio(dev);
594
595 /* And have 4 ICH7+ generic decodes */
596 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
597 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
598 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
599 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
600 }
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
614
615 /*
616 * VIA ACPI: One IO region pointed to by longword at
617 * 0x48 or 0x20 (256 bytes of ACPI registers)
618 */
619 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
620 {
621 u32 region;
622
623 if (dev->revision & 0x10) {
624 pci_read_config_dword(dev, 0x48, &region);
625 region &= PCI_BASE_ADDRESS_IO_MASK;
626 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
627 }
628 }
629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
630
631 /*
632 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
633 * 0x48 (256 bytes of ACPI registers)
634 * 0x70 (128 bytes of hardware monitoring register)
635 * 0x90 (16 bytes of SMB registers)
636 */
637 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
638 {
639 u16 hm;
640 u32 smb;
641
642 quirk_vt82c586_acpi(dev);
643
644 pci_read_config_word(dev, 0x70, &hm);
645 hm &= PCI_BASE_ADDRESS_IO_MASK;
646 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
647
648 pci_read_config_dword(dev, 0x90, &smb);
649 smb &= PCI_BASE_ADDRESS_IO_MASK;
650 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
651 }
652 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
653
654 /*
655 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
656 * 0x88 (128 bytes of power management registers)
657 * 0xd0 (16 bytes of SMB registers)
658 */
659 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
660 {
661 u16 pm, smb;
662
663 pci_read_config_word(dev, 0x88, &pm);
664 pm &= PCI_BASE_ADDRESS_IO_MASK;
665 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
666
667 pci_read_config_word(dev, 0xd0, &smb);
668 smb &= PCI_BASE_ADDRESS_IO_MASK;
669 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
670 }
671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
672
673
674 #ifdef CONFIG_X86_IO_APIC
675
676 #include <asm/io_apic.h>
677
678 /*
679 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
680 * devices to the external APIC.
681 *
682 * TODO: When we have device-specific interrupt routers,
683 * this code will go away from quirks.
684 */
685 static void quirk_via_ioapic(struct pci_dev *dev)
686 {
687 u8 tmp;
688
689 if (nr_ioapics < 1)
690 tmp = 0; /* nothing routed to external APIC */
691 else
692 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
693
694 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
695 tmp == 0 ? "Disa" : "Ena");
696
697 /* Offset 0x58: External APIC IRQ output control */
698 pci_write_config_byte (dev, 0x58, tmp);
699 }
700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
701 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
702
703 /*
704 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
705 * This leads to doubled level interrupt rates.
706 * Set this bit to get rid of cycle wastage.
707 * Otherwise uncritical.
708 */
709 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
710 {
711 u8 misc_control2;
712 #define BYPASS_APIC_DEASSERT 8
713
714 pci_read_config_byte(dev, 0x5B, &misc_control2);
715 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
716 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
717 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
718 }
719 }
720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
721 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
722
723 /*
724 * The AMD io apic can hang the box when an apic irq is masked.
725 * We check all revs >= B0 (yet not in the pre production!) as the bug
726 * is currently marked NoFix
727 *
728 * We have multiple reports of hangs with this chipset that went away with
729 * noapic specified. For the moment we assume it's the erratum. We may be wrong
730 * of course. However the advice is demonstrably good even if so..
731 */
732 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
733 {
734 if (dev->revision >= 0x02) {
735 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
736 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
737 }
738 }
739 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
740
741 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
742 {
743 if (dev->devfn == 0 && dev->bus->number == 0)
744 sis_apic_bug = 1;
745 }
746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
747 #endif /* CONFIG_X86_IO_APIC */
748
749 /*
750 * Some settings of MMRBC can lead to data corruption so block changes.
751 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
752 */
753 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
754 {
755 if (dev->subordinate && dev->revision <= 0x12) {
756 dev_info(&dev->dev, "AMD8131 rev %x detected; "
757 "disabling PCI-X MMRBC\n", dev->revision);
758 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
759 }
760 }
761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
762
763 /*
764 * FIXME: it is questionable that quirk_via_acpi
765 * is needed. It shows up as an ISA bridge, and does not
766 * support the PCI_INTERRUPT_LINE register at all. Therefore
767 * it seems like setting the pci_dev's 'irq' to the
768 * value of the ACPI SCI interrupt is only done for convenience.
769 * -jgarzik
770 */
771 static void __devinit quirk_via_acpi(struct pci_dev *d)
772 {
773 /*
774 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
775 */
776 u8 irq;
777 pci_read_config_byte(d, 0x42, &irq);
778 irq &= 0xf;
779 if (irq && (irq != 2))
780 d->irq = irq;
781 }
782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
784
785
786 /*
787 * VIA bridges which have VLink
788 */
789
790 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
791
792 static void quirk_via_bridge(struct pci_dev *dev)
793 {
794 /* See what bridge we have and find the device ranges */
795 switch (dev->device) {
796 case PCI_DEVICE_ID_VIA_82C686:
797 /* The VT82C686 is special, it attaches to PCI and can have
798 any device number. All its subdevices are functions of
799 that single device. */
800 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
801 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
802 break;
803 case PCI_DEVICE_ID_VIA_8237:
804 case PCI_DEVICE_ID_VIA_8237A:
805 via_vlink_dev_lo = 15;
806 break;
807 case PCI_DEVICE_ID_VIA_8235:
808 via_vlink_dev_lo = 16;
809 break;
810 case PCI_DEVICE_ID_VIA_8231:
811 case PCI_DEVICE_ID_VIA_8233_0:
812 case PCI_DEVICE_ID_VIA_8233A:
813 case PCI_DEVICE_ID_VIA_8233C_0:
814 via_vlink_dev_lo = 17;
815 break;
816 }
817 }
818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
826
827 /**
828 * quirk_via_vlink - VIA VLink IRQ number update
829 * @dev: PCI device
830 *
831 * If the device we are dealing with is on a PIC IRQ we need to
832 * ensure that the IRQ line register which usually is not relevant
833 * for PCI cards, is actually written so that interrupts get sent
834 * to the right place.
835 * We only do this on systems where a VIA south bridge was detected,
836 * and only for VIA devices on the motherboard (see quirk_via_bridge
837 * above).
838 */
839
840 static void quirk_via_vlink(struct pci_dev *dev)
841 {
842 u8 irq, new_irq;
843
844 /* Check if we have VLink at all */
845 if (via_vlink_dev_lo == -1)
846 return;
847
848 new_irq = dev->irq;
849
850 /* Don't quirk interrupts outside the legacy IRQ range */
851 if (!new_irq || new_irq > 15)
852 return;
853
854 /* Internal device ? */
855 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
856 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
857 return;
858
859 /* This is an internal VLink device on a PIC interrupt. The BIOS
860 ought to have set this but may not have, so we redo it */
861
862 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
863 if (new_irq != irq) {
864 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
865 irq, new_irq);
866 udelay(15); /* unknown if delay really needed */
867 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
868 }
869 }
870 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
871
872 /*
873 * VIA VT82C598 has its device ID settable and many BIOSes
874 * set it to the ID of VT82C597 for backward compatibility.
875 * We need to switch it off to be able to recognize the real
876 * type of the chip.
877 */
878 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
879 {
880 pci_write_config_byte(dev, 0xfc, 0);
881 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
882 }
883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
884
885 /*
886 * CardBus controllers have a legacy base address that enables them
887 * to respond as i82365 pcmcia controllers. We don't want them to
888 * do this even if the Linux CardBus driver is not loaded, because
889 * the Linux i82365 driver does not (and should not) handle CardBus.
890 */
891 static void quirk_cardbus_legacy(struct pci_dev *dev)
892 {
893 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
894 return;
895 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
896 }
897 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
898 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
899
900 /*
901 * Following the PCI ordering rules is optional on the AMD762. I'm not
902 * sure what the designers were smoking but let's not inhale...
903 *
904 * To be fair to AMD, it follows the spec by default, its BIOS people
905 * who turn it off!
906 */
907 static void quirk_amd_ordering(struct pci_dev *dev)
908 {
909 u32 pcic;
910 pci_read_config_dword(dev, 0x4C, &pcic);
911 if ((pcic&6)!=6) {
912 pcic |= 6;
913 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
914 pci_write_config_dword(dev, 0x4C, pcic);
915 pci_read_config_dword(dev, 0x84, &pcic);
916 pcic |= (1<<23); /* Required in this mode */
917 pci_write_config_dword(dev, 0x84, pcic);
918 }
919 }
920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
921 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
922
923 /*
924 * DreamWorks provided workaround for Dunord I-3000 problem
925 *
926 * This card decodes and responds to addresses not apparently
927 * assigned to it. We force a larger allocation to ensure that
928 * nothing gets put too close to it.
929 */
930 static void __devinit quirk_dunord ( struct pci_dev * dev )
931 {
932 struct resource *r = &dev->resource [1];
933 r->start = 0;
934 r->end = 0xffffff;
935 }
936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
937
938 /*
939 * i82380FB mobile docking controller: its PCI-to-PCI bridge
940 * is subtractive decoding (transparent), and does indicate this
941 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
942 * instead of 0x01.
943 */
944 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
945 {
946 dev->transparent = 1;
947 }
948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
949 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
950
951 /*
952 * Common misconfiguration of the MediaGX/Geode PCI master that will
953 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
954 * datasheets found at http://www.national.com/ds/GX for info on what
955 * these bits do. <christer@weinigel.se>
956 */
957 static void quirk_mediagx_master(struct pci_dev *dev)
958 {
959 u8 reg;
960 pci_read_config_byte(dev, 0x41, &reg);
961 if (reg & 2) {
962 reg &= ~2;
963 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
964 pci_write_config_byte(dev, 0x41, reg);
965 }
966 }
967 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
968 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
969
970 /*
971 * Ensure C0 rev restreaming is off. This is normally done by
972 * the BIOS but in the odd case it is not the results are corruption
973 * hence the presence of a Linux check
974 */
975 static void quirk_disable_pxb(struct pci_dev *pdev)
976 {
977 u16 config;
978
979 if (pdev->revision != 0x04) /* Only C0 requires this */
980 return;
981 pci_read_config_word(pdev, 0x40, &config);
982 if (config & (1<<6)) {
983 config &= ~(1<<6);
984 pci_write_config_word(pdev, 0x40, config);
985 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
986 }
987 }
988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
989 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
990
991 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
992 {
993 /* set sb600/sb700/sb800 sata to ahci mode */
994 u8 tmp;
995
996 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
997 if (tmp == 0x01) {
998 pci_read_config_byte(pdev, 0x40, &tmp);
999 pci_write_config_byte(pdev, 0x40, tmp|1);
1000 pci_write_config_byte(pdev, 0x9, 1);
1001 pci_write_config_byte(pdev, 0xa, 6);
1002 pci_write_config_byte(pdev, 0x40, tmp);
1003
1004 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1005 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1006 }
1007 }
1008 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1009 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1010 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1011 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1012
1013 /*
1014 * Serverworks CSB5 IDE does not fully support native mode
1015 */
1016 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1017 {
1018 u8 prog;
1019 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1020 if (prog & 5) {
1021 prog &= ~5;
1022 pdev->class &= ~5;
1023 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1024 /* PCI layer will sort out resources */
1025 }
1026 }
1027 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1028
1029 /*
1030 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1031 */
1032 static void __init quirk_ide_samemode(struct pci_dev *pdev)
1033 {
1034 u8 prog;
1035
1036 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1037
1038 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1039 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1040 prog &= ~5;
1041 pdev->class &= ~5;
1042 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1043 }
1044 }
1045 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1046
1047 /*
1048 * Some ATA devices break if put into D3
1049 */
1050
1051 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1052 {
1053 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1054 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1055 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1056 }
1057 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1058 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1059 /* ALi loses some register settings that we cannot then restore */
1060 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1061 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1062 occur when mode detecting */
1063 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1064
1065 /* This was originally an Alpha specific thing, but it really fits here.
1066 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1067 */
1068 static void __init quirk_eisa_bridge(struct pci_dev *dev)
1069 {
1070 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1071 }
1072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1073
1074
1075 /*
1076 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1077 * is not activated. The myth is that Asus said that they do not want the
1078 * users to be irritated by just another PCI Device in the Win98 device
1079 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1080 * package 2.7.0 for details)
1081 *
1082 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1083 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1084 * becomes necessary to do this tweak in two steps -- the chosen trigger
1085 * is either the Host bridge (preferred) or on-board VGA controller.
1086 *
1087 * Note that we used to unhide the SMBus that way on Toshiba laptops
1088 * (Satellite A40 and Tecra M2) but then found that the thermal management
1089 * was done by SMM code, which could cause unsynchronized concurrent
1090 * accesses to the SMBus registers, with potentially bad effects. Thus you
1091 * should be very careful when adding new entries: if SMM is accessing the
1092 * Intel SMBus, this is a very good reason to leave it hidden.
1093 *
1094 * Likewise, many recent laptops use ACPI for thermal management. If the
1095 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1096 * natively, and keeping the SMBus hidden is the right thing to do. If you
1097 * are about to add an entry in the table below, please first disassemble
1098 * the DSDT and double-check that there is no code accessing the SMBus.
1099 */
1100 static int asus_hides_smbus;
1101
1102 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1103 {
1104 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1105 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1106 switch(dev->subsystem_device) {
1107 case 0x8025: /* P4B-LX */
1108 case 0x8070: /* P4B */
1109 case 0x8088: /* P4B533 */
1110 case 0x1626: /* L3C notebook */
1111 asus_hides_smbus = 1;
1112 }
1113 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1114 switch(dev->subsystem_device) {
1115 case 0x80b1: /* P4GE-V */
1116 case 0x80b2: /* P4PE */
1117 case 0x8093: /* P4B533-V */
1118 asus_hides_smbus = 1;
1119 }
1120 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1121 switch(dev->subsystem_device) {
1122 case 0x8030: /* P4T533 */
1123 asus_hides_smbus = 1;
1124 }
1125 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1126 switch (dev->subsystem_device) {
1127 case 0x8070: /* P4G8X Deluxe */
1128 asus_hides_smbus = 1;
1129 }
1130 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1131 switch (dev->subsystem_device) {
1132 case 0x80c9: /* PU-DLS */
1133 asus_hides_smbus = 1;
1134 }
1135 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1136 switch (dev->subsystem_device) {
1137 case 0x1751: /* M2N notebook */
1138 case 0x1821: /* M5N notebook */
1139 case 0x1897: /* A6L notebook */
1140 asus_hides_smbus = 1;
1141 }
1142 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1143 switch (dev->subsystem_device) {
1144 case 0x184b: /* W1N notebook */
1145 case 0x186a: /* M6Ne notebook */
1146 asus_hides_smbus = 1;
1147 }
1148 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1149 switch (dev->subsystem_device) {
1150 case 0x80f2: /* P4P800-X */
1151 asus_hides_smbus = 1;
1152 }
1153 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1154 switch (dev->subsystem_device) {
1155 case 0x1882: /* M6V notebook */
1156 case 0x1977: /* A6VA notebook */
1157 asus_hides_smbus = 1;
1158 }
1159 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1160 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1161 switch(dev->subsystem_device) {
1162 case 0x088C: /* HP Compaq nc8000 */
1163 case 0x0890: /* HP Compaq nc6000 */
1164 asus_hides_smbus = 1;
1165 }
1166 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1167 switch (dev->subsystem_device) {
1168 case 0x12bc: /* HP D330L */
1169 case 0x12bd: /* HP D530 */
1170 case 0x006a: /* HP Compaq nx9500 */
1171 asus_hides_smbus = 1;
1172 }
1173 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1174 switch (dev->subsystem_device) {
1175 case 0x12bf: /* HP xw4100 */
1176 asus_hides_smbus = 1;
1177 }
1178 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1179 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1180 switch(dev->subsystem_device) {
1181 case 0xC00C: /* Samsung P35 notebook */
1182 asus_hides_smbus = 1;
1183 }
1184 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1185 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1186 switch(dev->subsystem_device) {
1187 case 0x0058: /* Compaq Evo N620c */
1188 asus_hides_smbus = 1;
1189 }
1190 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1191 switch(dev->subsystem_device) {
1192 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1193 /* Motherboard doesn't have Host bridge
1194 * subvendor/subdevice IDs, therefore checking
1195 * its on-board VGA controller */
1196 asus_hides_smbus = 1;
1197 }
1198 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1199 switch(dev->subsystem_device) {
1200 case 0x00b8: /* Compaq Evo D510 CMT */
1201 case 0x00b9: /* Compaq Evo D510 SFF */
1202 case 0x00ba: /* Compaq Evo D510 USDT */
1203 /* Motherboard doesn't have Host bridge
1204 * subvendor/subdevice IDs and on-board VGA
1205 * controller is disabled if an AGP card is
1206 * inserted, therefore checking USB UHCI
1207 * Controller #1 */
1208 asus_hides_smbus = 1;
1209 }
1210 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1211 switch (dev->subsystem_device) {
1212 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1213 /* Motherboard doesn't have host bridge
1214 * subvendor/subdevice IDs, therefore checking
1215 * its on-board VGA controller */
1216 asus_hides_smbus = 1;
1217 }
1218 }
1219 }
1220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1230
1231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1234
1235 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1236 {
1237 u16 val;
1238
1239 if (likely(!asus_hides_smbus))
1240 return;
1241
1242 pci_read_config_word(dev, 0xF2, &val);
1243 if (val & 0x8) {
1244 pci_write_config_word(dev, 0xF2, val & (~0x8));
1245 pci_read_config_word(dev, 0xF2, &val);
1246 if (val & 0x8)
1247 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1248 else
1249 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1250 }
1251 }
1252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1259 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1260 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1261 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1262 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1263 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1264 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1265 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1266
1267 /* It appears we just have one such device. If not, we have a warning */
1268 static void __iomem *asus_rcba_base;
1269 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1270 {
1271 u32 rcba;
1272
1273 if (likely(!asus_hides_smbus))
1274 return;
1275 WARN_ON(asus_rcba_base);
1276
1277 pci_read_config_dword(dev, 0xF0, &rcba);
1278 /* use bits 31:14, 16 kB aligned */
1279 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1280 if (asus_rcba_base == NULL)
1281 return;
1282 }
1283
1284 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1285 {
1286 u32 val;
1287
1288 if (likely(!asus_hides_smbus || !asus_rcba_base))
1289 return;
1290 /* read the Function Disable register, dword mode only */
1291 val = readl(asus_rcba_base + 0x3418);
1292 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1293 }
1294
1295 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1296 {
1297 if (likely(!asus_hides_smbus || !asus_rcba_base))
1298 return;
1299 iounmap(asus_rcba_base);
1300 asus_rcba_base = NULL;
1301 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1302 }
1303
1304 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1305 {
1306 asus_hides_smbus_lpc_ich6_suspend(dev);
1307 asus_hides_smbus_lpc_ich6_resume_early(dev);
1308 asus_hides_smbus_lpc_ich6_resume(dev);
1309 }
1310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1311 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1312 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1313 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1314
1315 /*
1316 * SiS 96x south bridge: BIOS typically hides SMBus device...
1317 */
1318 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1319 {
1320 u8 val = 0;
1321 pci_read_config_byte(dev, 0x77, &val);
1322 if (val & 0x10) {
1323 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1324 pci_write_config_byte(dev, 0x77, val & ~0x10);
1325 }
1326 }
1327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1331 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1332 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1333 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1334 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1335
1336 /*
1337 * ... This is further complicated by the fact that some SiS96x south
1338 * bridges pretend to be 85C503/5513 instead. In that case see if we
1339 * spotted a compatible north bridge to make sure.
1340 * (pci_find_device doesn't work yet)
1341 *
1342 * We can also enable the sis96x bit in the discovery register..
1343 */
1344 #define SIS_DETECT_REGISTER 0x40
1345
1346 static void quirk_sis_503(struct pci_dev *dev)
1347 {
1348 u8 reg;
1349 u16 devid;
1350
1351 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1352 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1353 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1354 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1355 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1356 return;
1357 }
1358
1359 /*
1360 * Ok, it now shows up as a 96x.. run the 96x quirk by
1361 * hand in case it has already been processed.
1362 * (depends on link order, which is apparently not guaranteed)
1363 */
1364 dev->device = devid;
1365 quirk_sis_96x_smbus(dev);
1366 }
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1368 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1369
1370
1371 /*
1372 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1373 * and MC97 modem controller are disabled when a second PCI soundcard is
1374 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1375 * -- bjd
1376 */
1377 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1378 {
1379 u8 val;
1380 int asus_hides_ac97 = 0;
1381
1382 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1383 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1384 asus_hides_ac97 = 1;
1385 }
1386
1387 if (!asus_hides_ac97)
1388 return;
1389
1390 pci_read_config_byte(dev, 0x50, &val);
1391 if (val & 0xc0) {
1392 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1393 pci_read_config_byte(dev, 0x50, &val);
1394 if (val & 0xc0)
1395 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1396 else
1397 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1398 }
1399 }
1400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1401 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1402
1403 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1404
1405 /*
1406 * If we are using libata we can drive this chip properly but must
1407 * do this early on to make the additional device appear during
1408 * the PCI scanning.
1409 */
1410 static void quirk_jmicron_ata(struct pci_dev *pdev)
1411 {
1412 u32 conf1, conf5, class;
1413 u8 hdr;
1414
1415 /* Only poke fn 0 */
1416 if (PCI_FUNC(pdev->devfn))
1417 return;
1418
1419 pci_read_config_dword(pdev, 0x40, &conf1);
1420 pci_read_config_dword(pdev, 0x80, &conf5);
1421
1422 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1423 conf5 &= ~(1 << 24); /* Clear bit 24 */
1424
1425 switch (pdev->device) {
1426 case PCI_DEVICE_ID_JMICRON_JMB360:
1427 /* The controller should be in single function ahci mode */
1428 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1429 break;
1430
1431 case PCI_DEVICE_ID_JMICRON_JMB365:
1432 case PCI_DEVICE_ID_JMICRON_JMB366:
1433 /* Redirect IDE second PATA port to the right spot */
1434 conf5 |= (1 << 24);
1435 /* Fall through */
1436 case PCI_DEVICE_ID_JMICRON_JMB361:
1437 case PCI_DEVICE_ID_JMICRON_JMB363:
1438 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1439 /* Set the class codes correctly and then direct IDE 0 */
1440 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1441 break;
1442
1443 case PCI_DEVICE_ID_JMICRON_JMB368:
1444 /* The controller should be in single function IDE mode */
1445 conf1 |= 0x00C00000; /* Set 22, 23 */
1446 break;
1447 }
1448
1449 pci_write_config_dword(pdev, 0x40, conf1);
1450 pci_write_config_dword(pdev, 0x80, conf5);
1451
1452 /* Update pdev accordingly */
1453 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1454 pdev->hdr_type = hdr & 0x7f;
1455 pdev->multifunction = !!(hdr & 0x80);
1456
1457 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1458 pdev->class = class >> 8;
1459 }
1460 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1461 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1462 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1463 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1464 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1465 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1466 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1467 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1468 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1469 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1470 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1471 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1472
1473 #endif
1474
1475 #ifdef CONFIG_X86_IO_APIC
1476 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1477 {
1478 int i;
1479
1480 if ((pdev->class >> 8) != 0xff00)
1481 return;
1482
1483 /* the first BAR is the location of the IO APIC...we must
1484 * not touch this (and it's already covered by the fixmap), so
1485 * forcibly insert it into the resource tree */
1486 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1487 insert_resource(&iomem_resource, &pdev->resource[0]);
1488
1489 /* The next five BARs all seem to be rubbish, so just clean
1490 * them out */
1491 for (i=1; i < 6; i++) {
1492 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1493 }
1494
1495 }
1496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1497 #endif
1498
1499 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1500 {
1501 pci_msi_off(pdev);
1502 pdev->no_msi = 1;
1503 }
1504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1507
1508
1509 /*
1510 * It's possible for the MSI to get corrupted if shpc and acpi
1511 * are used together on certain PXH-based systems.
1512 */
1513 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1514 {
1515 pci_msi_off(dev);
1516 dev->no_msi = 1;
1517 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1518 }
1519 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1520 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1521 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1522 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1524
1525 /*
1526 * Some Intel PCI Express chipsets have trouble with downstream
1527 * device power management.
1528 */
1529 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1530 {
1531 pci_pm_d3_delay = 120;
1532 dev->no_d1d2 = 1;
1533 }
1534
1535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1556
1557 #ifdef CONFIG_X86_IO_APIC
1558 /*
1559 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1560 * remap the original interrupt in the linux kernel to the boot interrupt, so
1561 * that a PCI device's interrupt handler is installed on the boot interrupt
1562 * line instead.
1563 */
1564 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1565 {
1566 if (noioapicquirk || noioapicreroute)
1567 return;
1568
1569 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1570 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1571 dev->vendor, dev->device);
1572 }
1573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1581 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1582 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1583 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1584 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1585 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1586 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1587 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1588 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1589
1590 /*
1591 * On some chipsets we can disable the generation of legacy INTx boot
1592 * interrupts.
1593 */
1594
1595 /*
1596 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1597 * 300641-004US, section 5.7.3.
1598 */
1599 #define INTEL_6300_IOAPIC_ABAR 0x40
1600 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1601
1602 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1603 {
1604 u16 pci_config_word;
1605
1606 if (noioapicquirk)
1607 return;
1608
1609 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1610 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1611 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1612
1613 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1614 dev->vendor, dev->device);
1615 }
1616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1617 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1618
1619 /*
1620 * disable boot interrupts on HT-1000
1621 */
1622 #define BC_HT1000_FEATURE_REG 0x64
1623 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1624 #define BC_HT1000_MAP_IDX 0xC00
1625 #define BC_HT1000_MAP_DATA 0xC01
1626
1627 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1628 {
1629 u32 pci_config_dword;
1630 u8 irq;
1631
1632 if (noioapicquirk)
1633 return;
1634
1635 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1636 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1637 BC_HT1000_PIC_REGS_ENABLE);
1638
1639 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1640 outb(irq, BC_HT1000_MAP_IDX);
1641 outb(0x00, BC_HT1000_MAP_DATA);
1642 }
1643
1644 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1645
1646 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1647 dev->vendor, dev->device);
1648 }
1649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1650 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1651
1652 /*
1653 * disable boot interrupts on AMD and ATI chipsets
1654 */
1655 /*
1656 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1657 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1658 * (due to an erratum).
1659 */
1660 #define AMD_813X_MISC 0x40
1661 #define AMD_813X_NOIOAMODE (1<<0)
1662 #define AMD_813X_REV_B2 0x13
1663
1664 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1665 {
1666 u32 pci_config_dword;
1667
1668 if (noioapicquirk)
1669 return;
1670 if (dev->revision == AMD_813X_REV_B2)
1671 return;
1672
1673 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1674 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1675 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1676
1677 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1678 dev->vendor, dev->device);
1679 }
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1681 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1682
1683 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1684
1685 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1686 {
1687 u16 pci_config_word;
1688
1689 if (noioapicquirk)
1690 return;
1691
1692 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1693 if (!pci_config_word) {
1694 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1695 "already disabled\n", dev->vendor, dev->device);
1696 return;
1697 }
1698 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1699 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1700 dev->vendor, dev->device);
1701 }
1702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1703 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1704 #endif /* CONFIG_X86_IO_APIC */
1705
1706 /*
1707 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1708 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1709 * Re-allocate the region if needed...
1710 */
1711 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1712 {
1713 struct resource *r = &dev->resource[0];
1714
1715 if (r->start & 0x8) {
1716 r->start = 0;
1717 r->end = 0xf;
1718 }
1719 }
1720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1721 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1722 quirk_tc86c001_ide);
1723
1724 static void __devinit quirk_netmos(struct pci_dev *dev)
1725 {
1726 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1727 unsigned int num_serial = dev->subsystem_device & 0xf;
1728
1729 /*
1730 * These Netmos parts are multiport serial devices with optional
1731 * parallel ports. Even when parallel ports are present, they
1732 * are identified as class SERIAL, which means the serial driver
1733 * will claim them. To prevent this, mark them as class OTHER.
1734 * These combo devices should be claimed by parport_serial.
1735 *
1736 * The subdevice ID is of the form 0x00PS, where <P> is the number
1737 * of parallel ports and <S> is the number of serial ports.
1738 */
1739 switch (dev->device) {
1740 case PCI_DEVICE_ID_NETMOS_9835:
1741 /* Well, this rule doesn't hold for the following 9835 device */
1742 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1743 dev->subsystem_device == 0x0299)
1744 return;
1745 case PCI_DEVICE_ID_NETMOS_9735:
1746 case PCI_DEVICE_ID_NETMOS_9745:
1747 case PCI_DEVICE_ID_NETMOS_9845:
1748 case PCI_DEVICE_ID_NETMOS_9855:
1749 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1750 num_parallel) {
1751 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1752 "%u serial); changing class SERIAL to OTHER "
1753 "(use parport_serial)\n",
1754 dev->device, num_parallel, num_serial);
1755 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1756 (dev->class & 0xff);
1757 }
1758 }
1759 }
1760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1761
1762 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1763 {
1764 u16 command, pmcsr;
1765 u8 __iomem *csr;
1766 u8 cmd_hi;
1767 int pm;
1768
1769 switch (dev->device) {
1770 /* PCI IDs taken from drivers/net/e100.c */
1771 case 0x1029:
1772 case 0x1030 ... 0x1034:
1773 case 0x1038 ... 0x103E:
1774 case 0x1050 ... 0x1057:
1775 case 0x1059:
1776 case 0x1064 ... 0x106B:
1777 case 0x1091 ... 0x1095:
1778 case 0x1209:
1779 case 0x1229:
1780 case 0x2449:
1781 case 0x2459:
1782 case 0x245D:
1783 case 0x27DC:
1784 break;
1785 default:
1786 return;
1787 }
1788
1789 /*
1790 * Some firmware hands off the e100 with interrupts enabled,
1791 * which can cause a flood of interrupts if packets are
1792 * received before the driver attaches to the device. So
1793 * disable all e100 interrupts here. The driver will
1794 * re-enable them when it's ready.
1795 */
1796 pci_read_config_word(dev, PCI_COMMAND, &command);
1797
1798 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1799 return;
1800
1801 /*
1802 * Check that the device is in the D0 power state. If it's not,
1803 * there is no point to look any further.
1804 */
1805 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1806 if (pm) {
1807 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1808 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1809 return;
1810 }
1811
1812 /* Convert from PCI bus to resource space. */
1813 csr = ioremap(pci_resource_start(dev, 0), 8);
1814 if (!csr) {
1815 dev_warn(&dev->dev, "Can't map e100 registers\n");
1816 return;
1817 }
1818
1819 cmd_hi = readb(csr + 3);
1820 if (cmd_hi == 0) {
1821 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1822 "disabling\n");
1823 writeb(1, csr + 3);
1824 }
1825
1826 iounmap(csr);
1827 }
1828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1829
1830 /*
1831 * The 82575 and 82598 may experience data corruption issues when transitioning
1832 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1833 */
1834 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1835 {
1836 dev_info(&dev->dev, "Disabling L0s\n");
1837 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1838 }
1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1853
1854 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1855 {
1856 /* rev 1 ncr53c810 chips don't set the class at all which means
1857 * they don't get their resources remapped. Fix that here.
1858 */
1859
1860 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1861 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1862 dev->class = PCI_CLASS_STORAGE_SCSI;
1863 }
1864 }
1865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1866
1867 /* Enable 1k I/O space granularity on the Intel P64H2 */
1868 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1869 {
1870 u16 en1k;
1871 u8 io_base_lo, io_limit_lo;
1872 unsigned long base, limit;
1873 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1874
1875 pci_read_config_word(dev, 0x40, &en1k);
1876
1877 if (en1k & 0x200) {
1878 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1879
1880 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1881 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1882 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1883 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1884
1885 if (base <= limit) {
1886 res->start = base;
1887 res->end = limit + 0x3ff;
1888 }
1889 }
1890 }
1891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1892
1893 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1894 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1895 * in drivers/pci/setup-bus.c
1896 */
1897 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1898 {
1899 u16 en1k, iobl_adr, iobl_adr_1k;
1900 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1901
1902 pci_read_config_word(dev, 0x40, &en1k);
1903
1904 if (en1k & 0x200) {
1905 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1906
1907 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1908
1909 if (iobl_adr != iobl_adr_1k) {
1910 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1911 iobl_adr,iobl_adr_1k);
1912 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1913 }
1914 }
1915 }
1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1917
1918 /* Under some circumstances, AER is not linked with extended capabilities.
1919 * Force it to be linked by setting the corresponding control bit in the
1920 * config space.
1921 */
1922 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1923 {
1924 uint8_t b;
1925 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1926 if (!(b & 0x20)) {
1927 pci_write_config_byte(dev, 0xf41, b | 0x20);
1928 dev_info(&dev->dev,
1929 "Linking AER extended capability\n");
1930 }
1931 }
1932 }
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1934 quirk_nvidia_ck804_pcie_aer_ext_cap);
1935 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1936 quirk_nvidia_ck804_pcie_aer_ext_cap);
1937
1938 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1939 {
1940 /*
1941 * Disable PCI Bus Parking and PCI Master read caching on CX700
1942 * which causes unspecified timing errors with a VT6212L on the PCI
1943 * bus leading to USB2.0 packet loss. The defaults are that these
1944 * features are turned off but some BIOSes turn them on.
1945 */
1946
1947 uint8_t b;
1948 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1949 if (b & 0x40) {
1950 /* Turn off PCI Bus Parking */
1951 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1952
1953 dev_info(&dev->dev,
1954 "Disabling VIA CX700 PCI parking\n");
1955 }
1956 }
1957
1958 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1959 if (b != 0) {
1960 /* Turn off PCI Master read caching */
1961 pci_write_config_byte(dev, 0x72, 0x0);
1962
1963 /* Set PCI Master Bus time-out to "1x16 PCLK" */
1964 pci_write_config_byte(dev, 0x75, 0x1);
1965
1966 /* Disable "Read FIFO Timer" */
1967 pci_write_config_byte(dev, 0x77, 0x0);
1968
1969 dev_info(&dev->dev,
1970 "Disabling VIA CX700 PCI caching\n");
1971 }
1972 }
1973 }
1974 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1975
1976 /*
1977 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1978 * VPD end tag will hang the device. This problem was initially
1979 * observed when a vpd entry was created in sysfs
1980 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1981 * will dump 32k of data. Reading a full 32k will cause an access
1982 * beyond the VPD end tag causing the device to hang. Once the device
1983 * is hung, the bnx2 driver will not be able to reset the device.
1984 * We believe that it is legal to read beyond the end tag and
1985 * therefore the solution is to limit the read/write length.
1986 */
1987 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1988 {
1989 /*
1990 * Only disable the VPD capability for 5706, 5706S, 5708,
1991 * 5708S and 5709 rev. A
1992 */
1993 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
1994 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
1995 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
1996 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
1997 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1998 (dev->revision & 0xf0) == 0x0)) {
1999 if (dev->vpd)
2000 dev->vpd->len = 0x80;
2001 }
2002 }
2003
2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2005 PCI_DEVICE_ID_NX2_5706,
2006 quirk_brcm_570x_limit_vpd);
2007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2008 PCI_DEVICE_ID_NX2_5706S,
2009 quirk_brcm_570x_limit_vpd);
2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2011 PCI_DEVICE_ID_NX2_5708,
2012 quirk_brcm_570x_limit_vpd);
2013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2014 PCI_DEVICE_ID_NX2_5708S,
2015 quirk_brcm_570x_limit_vpd);
2016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2017 PCI_DEVICE_ID_NX2_5709,
2018 quirk_brcm_570x_limit_vpd);
2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2020 PCI_DEVICE_ID_NX2_5709S,
2021 quirk_brcm_570x_limit_vpd);
2022
2023 /* Originally in EDAC sources for i82875P:
2024 * Intel tells BIOS developers to hide device 6 which
2025 * configures the overflow device access containing
2026 * the DRBs - this is where we expose device 6.
2027 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2028 */
2029 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2030 {
2031 u8 reg;
2032
2033 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2034 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2035 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2036 }
2037 }
2038
2039 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2040 quirk_unhide_mch_dev6);
2041 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2042 quirk_unhide_mch_dev6);
2043
2044
2045 #ifdef CONFIG_PCI_MSI
2046 /* Some chipsets do not support MSI. We cannot easily rely on setting
2047 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2048 * some other busses controlled by the chipset even if Linux is not
2049 * aware of it. Instead of setting the flag on all busses in the
2050 * machine, simply disable MSI globally.
2051 */
2052 static void __init quirk_disable_all_msi(struct pci_dev *dev)
2053 {
2054 pci_no_msi();
2055 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2056 }
2057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2063
2064 /* Disable MSI on chipsets that are known to not support it */
2065 static void __devinit quirk_disable_msi(struct pci_dev *dev)
2066 {
2067 if (dev->subordinate) {
2068 dev_warn(&dev->dev, "MSI quirk detected; "
2069 "subordinate MSI disabled\n");
2070 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2071 }
2072 }
2073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2074
2075 /* Go through the list of Hypertransport capabilities and
2076 * return 1 if a HT MSI capability is found and enabled */
2077 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2078 {
2079 int pos, ttl = 48;
2080
2081 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2082 while (pos && ttl--) {
2083 u8 flags;
2084
2085 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2086 &flags) == 0)
2087 {
2088 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2089 flags & HT_MSI_FLAGS_ENABLE ?
2090 "enabled" : "disabled");
2091 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2092 }
2093
2094 pos = pci_find_next_ht_capability(dev, pos,
2095 HT_CAPTYPE_MSI_MAPPING);
2096 }
2097 return 0;
2098 }
2099
2100 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2101 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2102 {
2103 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2104 dev_warn(&dev->dev, "MSI quirk detected; "
2105 "subordinate MSI disabled\n");
2106 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2107 }
2108 }
2109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2110 quirk_msi_ht_cap);
2111
2112 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2113 * MSI are supported if the MSI capability set in any of these mappings.
2114 */
2115 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2116 {
2117 struct pci_dev *pdev;
2118
2119 if (!dev->subordinate)
2120 return;
2121
2122 /* check HT MSI cap on this chipset and the root one.
2123 * a single one having MSI is enough to be sure that MSI are supported.
2124 */
2125 pdev = pci_get_slot(dev->bus, 0);
2126 if (!pdev)
2127 return;
2128 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2129 dev_warn(&dev->dev, "MSI quirk detected; "
2130 "subordinate MSI disabled\n");
2131 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2132 }
2133 pci_dev_put(pdev);
2134 }
2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2136 quirk_nvidia_ck804_msi_ht_cap);
2137
2138 /* Force enable MSI mapping capability on HT bridges */
2139 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2140 {
2141 int pos, ttl = 48;
2142
2143 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2144 while (pos && ttl--) {
2145 u8 flags;
2146
2147 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2148 &flags) == 0) {
2149 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2150
2151 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2152 flags | HT_MSI_FLAGS_ENABLE);
2153 }
2154 pos = pci_find_next_ht_capability(dev, pos,
2155 HT_CAPTYPE_MSI_MAPPING);
2156 }
2157 }
2158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2159 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2160 ht_enable_msi_mapping);
2161
2162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2163 ht_enable_msi_mapping);
2164
2165 /* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2166 * for the MCP55 NIC. It is not yet determined whether the msi problem
2167 * also affects other devices. As for now, turn off msi for this device.
2168 */
2169 static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2170 {
2171 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2172 dev_info(&dev->dev,
2173 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2174 dev->no_msi = 1;
2175 }
2176 }
2177 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2178 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2179 nvenet_msi_disable);
2180
2181 static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2182 {
2183 int pos, ttl = 48;
2184 int found = 0;
2185
2186 /* check if there is HT MSI cap or enabled on this device */
2187 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2188 while (pos && ttl--) {
2189 u8 flags;
2190
2191 if (found < 1)
2192 found = 1;
2193 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2194 &flags) == 0) {
2195 if (flags & HT_MSI_FLAGS_ENABLE) {
2196 if (found < 2) {
2197 found = 2;
2198 break;
2199 }
2200 }
2201 }
2202 pos = pci_find_next_ht_capability(dev, pos,
2203 HT_CAPTYPE_MSI_MAPPING);
2204 }
2205
2206 return found;
2207 }
2208
2209 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2210 {
2211 struct pci_dev *dev;
2212 int pos;
2213 int i, dev_no;
2214 int found = 0;
2215
2216 dev_no = host_bridge->devfn >> 3;
2217 for (i = dev_no + 1; i < 0x20; i++) {
2218 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2219 if (!dev)
2220 continue;
2221
2222 /* found next host bridge ?*/
2223 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2224 if (pos != 0) {
2225 pci_dev_put(dev);
2226 break;
2227 }
2228
2229 if (ht_check_msi_mapping(dev)) {
2230 found = 1;
2231 pci_dev_put(dev);
2232 break;
2233 }
2234 pci_dev_put(dev);
2235 }
2236
2237 return found;
2238 }
2239
2240 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2241 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2242
2243 static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2244 {
2245 int pos, ctrl_off;
2246 int end = 0;
2247 u16 flags, ctrl;
2248
2249 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2250
2251 if (!pos)
2252 goto out;
2253
2254 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2255
2256 ctrl_off = ((flags >> 10) & 1) ?
2257 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2258 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2259
2260 if (ctrl & (1 << 6))
2261 end = 1;
2262
2263 out:
2264 return end;
2265 }
2266
2267 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2268 {
2269 struct pci_dev *host_bridge;
2270 int pos;
2271 int i, dev_no;
2272 int found = 0;
2273
2274 dev_no = dev->devfn >> 3;
2275 for (i = dev_no; i >= 0; i--) {
2276 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2277 if (!host_bridge)
2278 continue;
2279
2280 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2281 if (pos != 0) {
2282 found = 1;
2283 break;
2284 }
2285 pci_dev_put(host_bridge);
2286 }
2287
2288 if (!found)
2289 return;
2290
2291 /* don't enable end_device/host_bridge with leaf directly here */
2292 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2293 host_bridge_with_leaf(host_bridge))
2294 goto out;
2295
2296 /* root did that ! */
2297 if (msi_ht_cap_enabled(host_bridge))
2298 goto out;
2299
2300 ht_enable_msi_mapping(dev);
2301
2302 out:
2303 pci_dev_put(host_bridge);
2304 }
2305
2306 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2307 {
2308 int pos, ttl = 48;
2309
2310 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2311 while (pos && ttl--) {
2312 u8 flags;
2313
2314 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2315 &flags) == 0) {
2316 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2317
2318 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2319 flags & ~HT_MSI_FLAGS_ENABLE);
2320 }
2321 pos = pci_find_next_ht_capability(dev, pos,
2322 HT_CAPTYPE_MSI_MAPPING);
2323 }
2324 }
2325
2326 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2327 {
2328 struct pci_dev *host_bridge;
2329 int pos;
2330 int found;
2331
2332 /* check if there is HT MSI cap or enabled on this device */
2333 found = ht_check_msi_mapping(dev);
2334
2335 /* no HT MSI CAP */
2336 if (found == 0)
2337 return;
2338
2339 /*
2340 * HT MSI mapping should be disabled on devices that are below
2341 * a non-Hypertransport host bridge. Locate the host bridge...
2342 */
2343 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2344 if (host_bridge == NULL) {
2345 dev_warn(&dev->dev,
2346 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2347 return;
2348 }
2349
2350 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2351 if (pos != 0) {
2352 /* Host bridge is to HT */
2353 if (found == 1) {
2354 /* it is not enabled, try to enable it */
2355 if (all)
2356 ht_enable_msi_mapping(dev);
2357 else
2358 nv_ht_enable_msi_mapping(dev);
2359 }
2360 return;
2361 }
2362
2363 /* HT MSI is not enabled */
2364 if (found == 1)
2365 return;
2366
2367 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2368 ht_disable_msi_mapping(dev);
2369 }
2370
2371 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2372 {
2373 return __nv_msi_ht_cap_quirk(dev, 1);
2374 }
2375
2376 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2377 {
2378 return __nv_msi_ht_cap_quirk(dev, 0);
2379 }
2380
2381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2382 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2383
2384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2385 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2386
2387 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2388 {
2389 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2390 }
2391 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2392 {
2393 struct pci_dev *p;
2394
2395 /* SB700 MSI issue will be fixed at HW level from revision A21,
2396 * we need check PCI REVISION ID of SMBus controller to get SB700
2397 * revision.
2398 */
2399 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2400 NULL);
2401 if (!p)
2402 return;
2403
2404 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2405 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2406 pci_dev_put(p);
2407 }
2408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2409 PCI_DEVICE_ID_TIGON3_5780,
2410 quirk_msi_intx_disable_bug);
2411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2412 PCI_DEVICE_ID_TIGON3_5780S,
2413 quirk_msi_intx_disable_bug);
2414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2415 PCI_DEVICE_ID_TIGON3_5714,
2416 quirk_msi_intx_disable_bug);
2417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2418 PCI_DEVICE_ID_TIGON3_5714S,
2419 quirk_msi_intx_disable_bug);
2420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2421 PCI_DEVICE_ID_TIGON3_5715,
2422 quirk_msi_intx_disable_bug);
2423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2424 PCI_DEVICE_ID_TIGON3_5715S,
2425 quirk_msi_intx_disable_bug);
2426
2427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2428 quirk_msi_intx_disable_ati_bug);
2429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2430 quirk_msi_intx_disable_ati_bug);
2431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2432 quirk_msi_intx_disable_ati_bug);
2433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2434 quirk_msi_intx_disable_ati_bug);
2435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2436 quirk_msi_intx_disable_ati_bug);
2437
2438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2439 quirk_msi_intx_disable_bug);
2440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2441 quirk_msi_intx_disable_bug);
2442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2443 quirk_msi_intx_disable_bug);
2444
2445 #endif /* CONFIG_PCI_MSI */
2446
2447 #ifdef CONFIG_PCI_IOV
2448
2449 /*
2450 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2451 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2452 * old Flash Memory Space.
2453 */
2454 static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2455 {
2456 int pos, flags;
2457 u32 bar, start, size;
2458
2459 if (PAGE_SIZE > 0x10000)
2460 return;
2461
2462 flags = pci_resource_flags(dev, 0);
2463 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2464 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2465 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2466 PCI_BASE_ADDRESS_MEM_TYPE_32)
2467 return;
2468
2469 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2470 if (!pos)
2471 return;
2472
2473 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2474 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2475 return;
2476
2477 start = pci_resource_start(dev, 1);
2478 size = pci_resource_len(dev, 1);
2479 if (!start || size != 0x400000 || start & (size - 1))
2480 return;
2481
2482 pci_resource_flags(dev, 1) = 0;
2483 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2484 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2485 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2486
2487 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2488 }
2489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
2494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
2495
2496 #endif /* CONFIG_PCI_IOV */
2497
2498 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2499 struct pci_fixup *end)
2500 {
2501 while (f < end) {
2502 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2503 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2504 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2505 f->hook(dev);
2506 }
2507 f++;
2508 }
2509 }
2510
2511 extern struct pci_fixup __start_pci_fixups_early[];
2512 extern struct pci_fixup __end_pci_fixups_early[];
2513 extern struct pci_fixup __start_pci_fixups_header[];
2514 extern struct pci_fixup __end_pci_fixups_header[];
2515 extern struct pci_fixup __start_pci_fixups_final[];
2516 extern struct pci_fixup __end_pci_fixups_final[];
2517 extern struct pci_fixup __start_pci_fixups_enable[];
2518 extern struct pci_fixup __end_pci_fixups_enable[];
2519 extern struct pci_fixup __start_pci_fixups_resume[];
2520 extern struct pci_fixup __end_pci_fixups_resume[];
2521 extern struct pci_fixup __start_pci_fixups_resume_early[];
2522 extern struct pci_fixup __end_pci_fixups_resume_early[];
2523 extern struct pci_fixup __start_pci_fixups_suspend[];
2524 extern struct pci_fixup __end_pci_fixups_suspend[];
2525
2526
2527 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2528 {
2529 struct pci_fixup *start, *end;
2530
2531 switch(pass) {
2532 case pci_fixup_early:
2533 start = __start_pci_fixups_early;
2534 end = __end_pci_fixups_early;
2535 break;
2536
2537 case pci_fixup_header:
2538 start = __start_pci_fixups_header;
2539 end = __end_pci_fixups_header;
2540 break;
2541
2542 case pci_fixup_final:
2543 start = __start_pci_fixups_final;
2544 end = __end_pci_fixups_final;
2545 break;
2546
2547 case pci_fixup_enable:
2548 start = __start_pci_fixups_enable;
2549 end = __end_pci_fixups_enable;
2550 break;
2551
2552 case pci_fixup_resume:
2553 start = __start_pci_fixups_resume;
2554 end = __end_pci_fixups_resume;
2555 break;
2556
2557 case pci_fixup_resume_early:
2558 start = __start_pci_fixups_resume_early;
2559 end = __end_pci_fixups_resume_early;
2560 break;
2561
2562 case pci_fixup_suspend:
2563 start = __start_pci_fixups_suspend;
2564 end = __end_pci_fixups_suspend;
2565 break;
2566
2567 default:
2568 /* stupid compiler warning, you would think with an enum... */
2569 return;
2570 }
2571 pci_do_fixups(dev, start, end);
2572 }
2573 #else
2574 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2575 #endif
2576 EXPORT_SYMBOL(pci_fixup_device);
Linux kernel - Deliverables
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