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intel-iommu: IA64 support
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include "pci.h"
26
27 /* The Mellanox Tavor device gives false positive parity errors
28 * Mark this device with a broken_parity_status, to allow
29 * PCI scanning code to "skip" this now blacklisted device.
30 */
31 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
32 {
33 dev->broken_parity_status = 1; /* This device gives false positives */
34 }
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
36 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
37
38 /* Many VIA bridges seem to corrupt data for DAC. Disable it here */
39 int forbid_dac __read_mostly;
40 EXPORT_SYMBOL(forbid_dac);
41
42 static __devinit void via_no_dac(struct pci_dev *dev)
43 {
44 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
45 dev_info(&dev->dev,
46 "VIA PCI bridge detected. Disabling DAC.\n");
47 forbid_dac = 1;
48 }
49 }
50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
51
52 /* Deal with broken BIOS'es that neglect to enable passive release,
53 which can cause problems in combination with the 82441FX/PPro MTRRs */
54 static void quirk_passive_release(struct pci_dev *dev)
55 {
56 struct pci_dev *d = NULL;
57 unsigned char dlc;
58
59 /* We have to make sure a particular bit is set in the PIIX3
60 ISA bridge, so we have to go out and find it. */
61 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
62 pci_read_config_byte(d, 0x82, &dlc);
63 if (!(dlc & 1<<1)) {
64 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
65 dlc |= 1<<1;
66 pci_write_config_byte(d, 0x82, dlc);
67 }
68 }
69 }
70 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
71 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
72
73 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
74 but VIA don't answer queries. If you happen to have good contacts at VIA
75 ask them for me please -- Alan
76
77 This appears to be BIOS not version dependent. So presumably there is a
78 chipset level fix */
79 int isa_dma_bridge_buggy;
80 EXPORT_SYMBOL(isa_dma_bridge_buggy);
81
82 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
83 {
84 if (!isa_dma_bridge_buggy) {
85 isa_dma_bridge_buggy=1;
86 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
87 }
88 }
89 /*
90 * Its not totally clear which chipsets are the problematic ones
91 * We know 82C586 and 82C596 variants are affected.
92 */
93 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
100
101 int pci_pci_problems;
102 EXPORT_SYMBOL(pci_pci_problems);
103
104 /*
105 * Chipsets where PCI->PCI transfers vanish or hang
106 */
107 static void __devinit quirk_nopcipci(struct pci_dev *dev)
108 {
109 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
110 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
111 pci_pci_problems |= PCIPCI_FAIL;
112 }
113 }
114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
116
117 static void __devinit quirk_nopciamd(struct pci_dev *dev)
118 {
119 u8 rev;
120 pci_read_config_byte(dev, 0x08, &rev);
121 if (rev == 0x13) {
122 /* Erratum 24 */
123 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
124 pci_pci_problems |= PCIAGP_FAIL;
125 }
126 }
127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
128
129 /*
130 * Triton requires workarounds to be used by the drivers
131 */
132 static void __devinit quirk_triton(struct pci_dev *dev)
133 {
134 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
135 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
136 pci_pci_problems |= PCIPCI_TRITON;
137 }
138 }
139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
143
144 /*
145 * VIA Apollo KT133 needs PCI latency patch
146 * Made according to a windows driver based patch by George E. Breese
147 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
148 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
149 * the info on which Mr Breese based his work.
150 *
151 * Updated based on further information from the site and also on
152 * information provided by VIA
153 */
154 static void quirk_vialatency(struct pci_dev *dev)
155 {
156 struct pci_dev *p;
157 u8 busarb;
158 /* Ok we have a potential problem chipset here. Now see if we have
159 a buggy southbridge */
160
161 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
162 if (p!=NULL) {
163 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
164 /* Check for buggy part revisions */
165 if (p->revision < 0x40 || p->revision > 0x42)
166 goto exit;
167 } else {
168 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
169 if (p==NULL) /* No problem parts */
170 goto exit;
171 /* Check for buggy part revisions */
172 if (p->revision < 0x10 || p->revision > 0x12)
173 goto exit;
174 }
175
176 /*
177 * Ok we have the problem. Now set the PCI master grant to
178 * occur every master grant. The apparent bug is that under high
179 * PCI load (quite common in Linux of course) you can get data
180 * loss when the CPU is held off the bus for 3 bus master requests
181 * This happens to include the IDE controllers....
182 *
183 * VIA only apply this fix when an SB Live! is present but under
184 * both Linux and Windows this isnt enough, and we have seen
185 * corruption without SB Live! but with things like 3 UDMA IDE
186 * controllers. So we ignore that bit of the VIA recommendation..
187 */
188
189 pci_read_config_byte(dev, 0x76, &busarb);
190 /* Set bit 4 and bi 5 of byte 76 to 0x01
191 "Master priority rotation on every PCI master grant */
192 busarb &= ~(1<<5);
193 busarb |= (1<<4);
194 pci_write_config_byte(dev, 0x76, busarb);
195 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
196 exit:
197 pci_dev_put(p);
198 }
199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
202 /* Must restore this on a resume from RAM */
203 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
204 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
205 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
206
207 /*
208 * VIA Apollo VP3 needs ETBF on BT848/878
209 */
210 static void __devinit quirk_viaetbf(struct pci_dev *dev)
211 {
212 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
213 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
214 pci_pci_problems |= PCIPCI_VIAETBF;
215 }
216 }
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
218
219 static void __devinit quirk_vsfx(struct pci_dev *dev)
220 {
221 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
222 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
223 pci_pci_problems |= PCIPCI_VSFX;
224 }
225 }
226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
227
228 /*
229 * Ali Magik requires workarounds to be used by the drivers
230 * that DMA to AGP space. Latency must be set to 0xA and triton
231 * workaround applied too
232 * [Info kindly provided by ALi]
233 */
234 static void __init quirk_alimagik(struct pci_dev *dev)
235 {
236 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
237 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
238 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
239 }
240 }
241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
243
244 /*
245 * Natoma has some interesting boundary conditions with Zoran stuff
246 * at least
247 */
248 static void __devinit quirk_natoma(struct pci_dev *dev)
249 {
250 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
251 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
252 pci_pci_problems |= PCIPCI_NATOMA;
253 }
254 }
255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
261
262 /*
263 * This chip can cause PCI parity errors if config register 0xA0 is read
264 * while DMAs are occurring.
265 */
266 static void __devinit quirk_citrine(struct pci_dev *dev)
267 {
268 dev->cfg_size = 0xA0;
269 }
270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
271
272 /*
273 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
274 * If it's needed, re-allocate the region.
275 */
276 static void __devinit quirk_s3_64M(struct pci_dev *dev)
277 {
278 struct resource *r = &dev->resource[0];
279
280 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
281 r->start = 0;
282 r->end = 0x3ffffff;
283 }
284 }
285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
287
288 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
289 unsigned size, int nr, const char *name)
290 {
291 region &= ~(size-1);
292 if (region) {
293 struct pci_bus_region bus_region;
294 struct resource *res = dev->resource + nr;
295
296 res->name = pci_name(dev);
297 res->start = region;
298 res->end = region + size - 1;
299 res->flags = IORESOURCE_IO;
300
301 /* Convert from PCI bus to resource space. */
302 bus_region.start = res->start;
303 bus_region.end = res->end;
304 pcibios_bus_to_resource(dev, res, &bus_region);
305
306 pci_claim_resource(dev, nr);
307 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
308 }
309 }
310
311 /*
312 * ATI Northbridge setups MCE the processor if you even
313 * read somewhere between 0x3b0->0x3bb or read 0x3d3
314 */
315 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
316 {
317 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
318 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
319 request_region(0x3b0, 0x0C, "RadeonIGP");
320 request_region(0x3d3, 0x01, "RadeonIGP");
321 }
322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
323
324 /*
325 * Let's make the southbridge information explicit instead
326 * of having to worry about people probing the ACPI areas,
327 * for example.. (Yes, it happens, and if you read the wrong
328 * ACPI register it will put the machine to sleep with no
329 * way of waking it up again. Bummer).
330 *
331 * ALI M7101: Two IO regions pointed to by words at
332 * 0xE0 (64 bytes of ACPI registers)
333 * 0xE2 (32 bytes of SMB registers)
334 */
335 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
336 {
337 u16 region;
338
339 pci_read_config_word(dev, 0xE0, &region);
340 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
341 pci_read_config_word(dev, 0xE2, &region);
342 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
343 }
344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
345
346 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
347 {
348 u32 devres;
349 u32 mask, size, base;
350
351 pci_read_config_dword(dev, port, &devres);
352 if ((devres & enable) != enable)
353 return;
354 mask = (devres >> 16) & 15;
355 base = devres & 0xffff;
356 size = 16;
357 for (;;) {
358 unsigned bit = size >> 1;
359 if ((bit & mask) == bit)
360 break;
361 size = bit;
362 }
363 /*
364 * For now we only print it out. Eventually we'll want to
365 * reserve it (at least if it's in the 0x1000+ range), but
366 * let's get enough confirmation reports first.
367 */
368 base &= -size;
369 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
370 }
371
372 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
373 {
374 u32 devres;
375 u32 mask, size, base;
376
377 pci_read_config_dword(dev, port, &devres);
378 if ((devres & enable) != enable)
379 return;
380 base = devres & 0xffff0000;
381 mask = (devres & 0x3f) << 16;
382 size = 128 << 16;
383 for (;;) {
384 unsigned bit = size >> 1;
385 if ((bit & mask) == bit)
386 break;
387 size = bit;
388 }
389 /*
390 * For now we only print it out. Eventually we'll want to
391 * reserve it, but let's get enough confirmation reports first.
392 */
393 base &= -size;
394 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
395 }
396
397 /*
398 * PIIX4 ACPI: Two IO regions pointed to by longwords at
399 * 0x40 (64 bytes of ACPI registers)
400 * 0x90 (16 bytes of SMB registers)
401 * and a few strange programmable PIIX4 device resources.
402 */
403 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
404 {
405 u32 region, res_a;
406
407 pci_read_config_dword(dev, 0x40, &region);
408 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
409 pci_read_config_dword(dev, 0x90, &region);
410 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
411
412 /* Device resource A has enables for some of the other ones */
413 pci_read_config_dword(dev, 0x5c, &res_a);
414
415 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
416 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
417
418 /* Device resource D is just bitfields for static resources */
419
420 /* Device 12 enabled? */
421 if (res_a & (1 << 29)) {
422 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
423 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
424 }
425 /* Device 13 enabled? */
426 if (res_a & (1 << 30)) {
427 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
428 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
429 }
430 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
431 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
432 }
433 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
435
436 /*
437 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
438 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
439 * 0x58 (64 bytes of GPIO I/O space)
440 */
441 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
442 {
443 u32 region;
444
445 pci_read_config_dword(dev, 0x40, &region);
446 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
447
448 pci_read_config_dword(dev, 0x58, &region);
449 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
450 }
451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
461
462 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
463 {
464 u32 region;
465
466 pci_read_config_dword(dev, 0x40, &region);
467 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
468
469 pci_read_config_dword(dev, 0x48, &region);
470 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
471 }
472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
486
487 /*
488 * VIA ACPI: One IO region pointed to by longword at
489 * 0x48 or 0x20 (256 bytes of ACPI registers)
490 */
491 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
492 {
493 u32 region;
494
495 if (dev->revision & 0x10) {
496 pci_read_config_dword(dev, 0x48, &region);
497 region &= PCI_BASE_ADDRESS_IO_MASK;
498 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
499 }
500 }
501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
502
503 /*
504 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
505 * 0x48 (256 bytes of ACPI registers)
506 * 0x70 (128 bytes of hardware monitoring register)
507 * 0x90 (16 bytes of SMB registers)
508 */
509 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
510 {
511 u16 hm;
512 u32 smb;
513
514 quirk_vt82c586_acpi(dev);
515
516 pci_read_config_word(dev, 0x70, &hm);
517 hm &= PCI_BASE_ADDRESS_IO_MASK;
518 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
519
520 pci_read_config_dword(dev, 0x90, &smb);
521 smb &= PCI_BASE_ADDRESS_IO_MASK;
522 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
523 }
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
525
526 /*
527 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
528 * 0x88 (128 bytes of power management registers)
529 * 0xd0 (16 bytes of SMB registers)
530 */
531 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
532 {
533 u16 pm, smb;
534
535 pci_read_config_word(dev, 0x88, &pm);
536 pm &= PCI_BASE_ADDRESS_IO_MASK;
537 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
538
539 pci_read_config_word(dev, 0xd0, &smb);
540 smb &= PCI_BASE_ADDRESS_IO_MASK;
541 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
542 }
543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
544
545
546 #ifdef CONFIG_X86_IO_APIC
547
548 #include <asm/io_apic.h>
549
550 /*
551 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
552 * devices to the external APIC.
553 *
554 * TODO: When we have device-specific interrupt routers,
555 * this code will go away from quirks.
556 */
557 static void quirk_via_ioapic(struct pci_dev *dev)
558 {
559 u8 tmp;
560
561 if (nr_ioapics < 1)
562 tmp = 0; /* nothing routed to external APIC */
563 else
564 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
565
566 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
567 tmp == 0 ? "Disa" : "Ena");
568
569 /* Offset 0x58: External APIC IRQ output control */
570 pci_write_config_byte (dev, 0x58, tmp);
571 }
572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
574
575 /*
576 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
577 * This leads to doubled level interrupt rates.
578 * Set this bit to get rid of cycle wastage.
579 * Otherwise uncritical.
580 */
581 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
582 {
583 u8 misc_control2;
584 #define BYPASS_APIC_DEASSERT 8
585
586 pci_read_config_byte(dev, 0x5B, &misc_control2);
587 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
588 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
589 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
590 }
591 }
592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
593 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
594
595 /*
596 * The AMD io apic can hang the box when an apic irq is masked.
597 * We check all revs >= B0 (yet not in the pre production!) as the bug
598 * is currently marked NoFix
599 *
600 * We have multiple reports of hangs with this chipset that went away with
601 * noapic specified. For the moment we assume it's the erratum. We may be wrong
602 * of course. However the advice is demonstrably good even if so..
603 */
604 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
605 {
606 if (dev->revision >= 0x02) {
607 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
608 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
609 }
610 }
611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
612
613 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
614 {
615 if (dev->devfn == 0 && dev->bus->number == 0)
616 sis_apic_bug = 1;
617 }
618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
619
620 #define AMD8131_revA0 0x01
621 #define AMD8131_revB0 0x11
622 #define AMD8131_MISC 0x40
623 #define AMD8131_NIOAMODE_BIT 0
624 static void quirk_amd_8131_ioapic(struct pci_dev *dev)
625 {
626 unsigned char tmp;
627
628 if (nr_ioapics == 0)
629 return;
630
631 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
632 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
633 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
634 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
635 pci_write_config_byte( dev, AMD8131_MISC, tmp);
636 }
637 }
638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
639 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
640 #endif /* CONFIG_X86_IO_APIC */
641
642 /*
643 * Some settings of MMRBC can lead to data corruption so block changes.
644 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
645 */
646 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
647 {
648 if (dev->subordinate && dev->revision <= 0x12) {
649 dev_info(&dev->dev, "AMD8131 rev %x detected; "
650 "disabling PCI-X MMRBC\n", dev->revision);
651 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
652 }
653 }
654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
655
656 /*
657 * FIXME: it is questionable that quirk_via_acpi
658 * is needed. It shows up as an ISA bridge, and does not
659 * support the PCI_INTERRUPT_LINE register at all. Therefore
660 * it seems like setting the pci_dev's 'irq' to the
661 * value of the ACPI SCI interrupt is only done for convenience.
662 * -jgarzik
663 */
664 static void __devinit quirk_via_acpi(struct pci_dev *d)
665 {
666 /*
667 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
668 */
669 u8 irq;
670 pci_read_config_byte(d, 0x42, &irq);
671 irq &= 0xf;
672 if (irq && (irq != 2))
673 d->irq = irq;
674 }
675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
676 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
677
678
679 /*
680 * VIA bridges which have VLink
681 */
682
683 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
684
685 static void quirk_via_bridge(struct pci_dev *dev)
686 {
687 /* See what bridge we have and find the device ranges */
688 switch (dev->device) {
689 case PCI_DEVICE_ID_VIA_82C686:
690 /* The VT82C686 is special, it attaches to PCI and can have
691 any device number. All its subdevices are functions of
692 that single device. */
693 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
694 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
695 break;
696 case PCI_DEVICE_ID_VIA_8237:
697 case PCI_DEVICE_ID_VIA_8237A:
698 via_vlink_dev_lo = 15;
699 break;
700 case PCI_DEVICE_ID_VIA_8235:
701 via_vlink_dev_lo = 16;
702 break;
703 case PCI_DEVICE_ID_VIA_8231:
704 case PCI_DEVICE_ID_VIA_8233_0:
705 case PCI_DEVICE_ID_VIA_8233A:
706 case PCI_DEVICE_ID_VIA_8233C_0:
707 via_vlink_dev_lo = 17;
708 break;
709 }
710 }
711 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
713 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
716 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
717 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
719
720 /**
721 * quirk_via_vlink - VIA VLink IRQ number update
722 * @dev: PCI device
723 *
724 * If the device we are dealing with is on a PIC IRQ we need to
725 * ensure that the IRQ line register which usually is not relevant
726 * for PCI cards, is actually written so that interrupts get sent
727 * to the right place.
728 * We only do this on systems where a VIA south bridge was detected,
729 * and only for VIA devices on the motherboard (see quirk_via_bridge
730 * above).
731 */
732
733 static void quirk_via_vlink(struct pci_dev *dev)
734 {
735 u8 irq, new_irq;
736
737 /* Check if we have VLink at all */
738 if (via_vlink_dev_lo == -1)
739 return;
740
741 new_irq = dev->irq;
742
743 /* Don't quirk interrupts outside the legacy IRQ range */
744 if (!new_irq || new_irq > 15)
745 return;
746
747 /* Internal device ? */
748 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
749 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
750 return;
751
752 /* This is an internal VLink device on a PIC interrupt. The BIOS
753 ought to have set this but may not have, so we redo it */
754
755 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
756 if (new_irq != irq) {
757 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
758 irq, new_irq);
759 udelay(15); /* unknown if delay really needed */
760 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
761 }
762 }
763 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
764
765 /*
766 * VIA VT82C598 has its device ID settable and many BIOSes
767 * set it to the ID of VT82C597 for backward compatibility.
768 * We need to switch it off to be able to recognize the real
769 * type of the chip.
770 */
771 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
772 {
773 pci_write_config_byte(dev, 0xfc, 0);
774 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
775 }
776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
777
778 /*
779 * CardBus controllers have a legacy base address that enables them
780 * to respond as i82365 pcmcia controllers. We don't want them to
781 * do this even if the Linux CardBus driver is not loaded, because
782 * the Linux i82365 driver does not (and should not) handle CardBus.
783 */
784 static void quirk_cardbus_legacy(struct pci_dev *dev)
785 {
786 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
787 return;
788 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
789 }
790 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
791 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
792
793 /*
794 * Following the PCI ordering rules is optional on the AMD762. I'm not
795 * sure what the designers were smoking but let's not inhale...
796 *
797 * To be fair to AMD, it follows the spec by default, its BIOS people
798 * who turn it off!
799 */
800 static void quirk_amd_ordering(struct pci_dev *dev)
801 {
802 u32 pcic;
803 pci_read_config_dword(dev, 0x4C, &pcic);
804 if ((pcic&6)!=6) {
805 pcic |= 6;
806 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
807 pci_write_config_dword(dev, 0x4C, pcic);
808 pci_read_config_dword(dev, 0x84, &pcic);
809 pcic |= (1<<23); /* Required in this mode */
810 pci_write_config_dword(dev, 0x84, pcic);
811 }
812 }
813 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
814 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
815
816 /*
817 * DreamWorks provided workaround for Dunord I-3000 problem
818 *
819 * This card decodes and responds to addresses not apparently
820 * assigned to it. We force a larger allocation to ensure that
821 * nothing gets put too close to it.
822 */
823 static void __devinit quirk_dunord ( struct pci_dev * dev )
824 {
825 struct resource *r = &dev->resource [1];
826 r->start = 0;
827 r->end = 0xffffff;
828 }
829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
830
831 /*
832 * i82380FB mobile docking controller: its PCI-to-PCI bridge
833 * is subtractive decoding (transparent), and does indicate this
834 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
835 * instead of 0x01.
836 */
837 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
838 {
839 dev->transparent = 1;
840 }
841 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
843
844 /*
845 * Common misconfiguration of the MediaGX/Geode PCI master that will
846 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
847 * datasheets found at http://www.national.com/ds/GX for info on what
848 * these bits do. <christer@weinigel.se>
849 */
850 static void quirk_mediagx_master(struct pci_dev *dev)
851 {
852 u8 reg;
853 pci_read_config_byte(dev, 0x41, &reg);
854 if (reg & 2) {
855 reg &= ~2;
856 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
857 pci_write_config_byte(dev, 0x41, reg);
858 }
859 }
860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
861 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
862
863 /*
864 * Ensure C0 rev restreaming is off. This is normally done by
865 * the BIOS but in the odd case it is not the results are corruption
866 * hence the presence of a Linux check
867 */
868 static void quirk_disable_pxb(struct pci_dev *pdev)
869 {
870 u16 config;
871
872 if (pdev->revision != 0x04) /* Only C0 requires this */
873 return;
874 pci_read_config_word(pdev, 0x40, &config);
875 if (config & (1<<6)) {
876 config &= ~(1<<6);
877 pci_write_config_word(pdev, 0x40, config);
878 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
879 }
880 }
881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
882 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
883
884 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
885 {
886 /* set sb600/sb700/sb800 sata to ahci mode */
887 u8 tmp;
888
889 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
890 if (tmp == 0x01) {
891 pci_read_config_byte(pdev, 0x40, &tmp);
892 pci_write_config_byte(pdev, 0x40, tmp|1);
893 pci_write_config_byte(pdev, 0x9, 1);
894 pci_write_config_byte(pdev, 0xa, 6);
895 pci_write_config_byte(pdev, 0x40, tmp);
896
897 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
898 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
899 }
900 }
901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
902 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
904 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
905
906 /*
907 * Serverworks CSB5 IDE does not fully support native mode
908 */
909 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
910 {
911 u8 prog;
912 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
913 if (prog & 5) {
914 prog &= ~5;
915 pdev->class &= ~5;
916 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
917 /* PCI layer will sort out resources */
918 }
919 }
920 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
921
922 /*
923 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
924 */
925 static void __init quirk_ide_samemode(struct pci_dev *pdev)
926 {
927 u8 prog;
928
929 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
930
931 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
932 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
933 prog &= ~5;
934 pdev->class &= ~5;
935 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
936 }
937 }
938 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
939
940 /*
941 * Some ATA devices break if put into D3
942 */
943
944 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
945 {
946 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
947 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
948 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
949 }
950 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
951 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
952
953 /* This was originally an Alpha specific thing, but it really fits here.
954 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
955 */
956 static void __init quirk_eisa_bridge(struct pci_dev *dev)
957 {
958 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
959 }
960 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
961
962
963 /*
964 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
965 * is not activated. The myth is that Asus said that they do not want the
966 * users to be irritated by just another PCI Device in the Win98 device
967 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
968 * package 2.7.0 for details)
969 *
970 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
971 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
972 * becomes necessary to do this tweak in two steps -- the chosen trigger
973 * is either the Host bridge (preferred) or on-board VGA controller.
974 *
975 * Note that we used to unhide the SMBus that way on Toshiba laptops
976 * (Satellite A40 and Tecra M2) but then found that the thermal management
977 * was done by SMM code, which could cause unsynchronized concurrent
978 * accesses to the SMBus registers, with potentially bad effects. Thus you
979 * should be very careful when adding new entries: if SMM is accessing the
980 * Intel SMBus, this is a very good reason to leave it hidden.
981 *
982 * Likewise, many recent laptops use ACPI for thermal management. If the
983 * ACPI DSDT code accesses the SMBus, then Linux should not access it
984 * natively, and keeping the SMBus hidden is the right thing to do. If you
985 * are about to add an entry in the table below, please first disassemble
986 * the DSDT and double-check that there is no code accessing the SMBus.
987 */
988 static int asus_hides_smbus;
989
990 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
991 {
992 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
993 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
994 switch(dev->subsystem_device) {
995 case 0x8025: /* P4B-LX */
996 case 0x8070: /* P4B */
997 case 0x8088: /* P4B533 */
998 case 0x1626: /* L3C notebook */
999 asus_hides_smbus = 1;
1000 }
1001 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1002 switch(dev->subsystem_device) {
1003 case 0x80b1: /* P4GE-V */
1004 case 0x80b2: /* P4PE */
1005 case 0x8093: /* P4B533-V */
1006 asus_hides_smbus = 1;
1007 }
1008 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1009 switch(dev->subsystem_device) {
1010 case 0x8030: /* P4T533 */
1011 asus_hides_smbus = 1;
1012 }
1013 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1014 switch (dev->subsystem_device) {
1015 case 0x8070: /* P4G8X Deluxe */
1016 asus_hides_smbus = 1;
1017 }
1018 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1019 switch (dev->subsystem_device) {
1020 case 0x80c9: /* PU-DLS */
1021 asus_hides_smbus = 1;
1022 }
1023 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1024 switch (dev->subsystem_device) {
1025 case 0x1751: /* M2N notebook */
1026 case 0x1821: /* M5N notebook */
1027 asus_hides_smbus = 1;
1028 }
1029 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1030 switch (dev->subsystem_device) {
1031 case 0x184b: /* W1N notebook */
1032 case 0x186a: /* M6Ne notebook */
1033 asus_hides_smbus = 1;
1034 }
1035 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1036 switch (dev->subsystem_device) {
1037 case 0x80f2: /* P4P800-X */
1038 asus_hides_smbus = 1;
1039 }
1040 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1041 switch (dev->subsystem_device) {
1042 case 0x1882: /* M6V notebook */
1043 case 0x1977: /* A6VA notebook */
1044 asus_hides_smbus = 1;
1045 }
1046 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1047 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1048 switch(dev->subsystem_device) {
1049 case 0x088C: /* HP Compaq nc8000 */
1050 case 0x0890: /* HP Compaq nc6000 */
1051 asus_hides_smbus = 1;
1052 }
1053 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1054 switch (dev->subsystem_device) {
1055 case 0x12bc: /* HP D330L */
1056 case 0x12bd: /* HP D530 */
1057 asus_hides_smbus = 1;
1058 }
1059 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1060 switch (dev->subsystem_device) {
1061 case 0x12bf: /* HP xw4100 */
1062 asus_hides_smbus = 1;
1063 }
1064 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1065 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1066 switch(dev->subsystem_device) {
1067 case 0xC00C: /* Samsung P35 notebook */
1068 asus_hides_smbus = 1;
1069 }
1070 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1071 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1072 switch(dev->subsystem_device) {
1073 case 0x0058: /* Compaq Evo N620c */
1074 asus_hides_smbus = 1;
1075 }
1076 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1077 switch(dev->subsystem_device) {
1078 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1079 /* Motherboard doesn't have Host bridge
1080 * subvendor/subdevice IDs, therefore checking
1081 * its on-board VGA controller */
1082 asus_hides_smbus = 1;
1083 }
1084 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1085 switch(dev->subsystem_device) {
1086 case 0x00b8: /* Compaq Evo D510 CMT */
1087 case 0x00b9: /* Compaq Evo D510 SFF */
1088 asus_hides_smbus = 1;
1089 }
1090 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1091 switch (dev->subsystem_device) {
1092 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1093 /* Motherboard doesn't have host bridge
1094 * subvendor/subdevice IDs, therefore checking
1095 * its on-board VGA controller */
1096 asus_hides_smbus = 1;
1097 }
1098 }
1099 }
1100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1110
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1114
1115 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1116 {
1117 u16 val;
1118
1119 if (likely(!asus_hides_smbus))
1120 return;
1121
1122 pci_read_config_word(dev, 0xF2, &val);
1123 if (val & 0x8) {
1124 pci_write_config_word(dev, 0xF2, val & (~0x8));
1125 pci_read_config_word(dev, 0xF2, &val);
1126 if (val & 0x8)
1127 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1128 else
1129 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1130 }
1131 }
1132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1139 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1140 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1141 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1142 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1143 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1144 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1145 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1146
1147 /* It appears we just have one such device. If not, we have a warning */
1148 static void __iomem *asus_rcba_base;
1149 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1150 {
1151 u32 rcba;
1152
1153 if (likely(!asus_hides_smbus))
1154 return;
1155 WARN_ON(asus_rcba_base);
1156
1157 pci_read_config_dword(dev, 0xF0, &rcba);
1158 /* use bits 31:14, 16 kB aligned */
1159 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1160 if (asus_rcba_base == NULL)
1161 return;
1162 }
1163
1164 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1165 {
1166 u32 val;
1167
1168 if (likely(!asus_hides_smbus || !asus_rcba_base))
1169 return;
1170 /* read the Function Disable register, dword mode only */
1171 val = readl(asus_rcba_base + 0x3418);
1172 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1173 }
1174
1175 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1176 {
1177 if (likely(!asus_hides_smbus || !asus_rcba_base))
1178 return;
1179 iounmap(asus_rcba_base);
1180 asus_rcba_base = NULL;
1181 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1182 }
1183
1184 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1185 {
1186 asus_hides_smbus_lpc_ich6_suspend(dev);
1187 asus_hides_smbus_lpc_ich6_resume_early(dev);
1188 asus_hides_smbus_lpc_ich6_resume(dev);
1189 }
1190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1191 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1192 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1193 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1194
1195 /*
1196 * SiS 96x south bridge: BIOS typically hides SMBus device...
1197 */
1198 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1199 {
1200 u8 val = 0;
1201 pci_read_config_byte(dev, 0x77, &val);
1202 if (val & 0x10) {
1203 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1204 pci_write_config_byte(dev, 0x77, val & ~0x10);
1205 }
1206 }
1207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1211 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1212 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1213 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1214 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1215
1216 /*
1217 * ... This is further complicated by the fact that some SiS96x south
1218 * bridges pretend to be 85C503/5513 instead. In that case see if we
1219 * spotted a compatible north bridge to make sure.
1220 * (pci_find_device doesn't work yet)
1221 *
1222 * We can also enable the sis96x bit in the discovery register..
1223 */
1224 #define SIS_DETECT_REGISTER 0x40
1225
1226 static void quirk_sis_503(struct pci_dev *dev)
1227 {
1228 u8 reg;
1229 u16 devid;
1230
1231 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1232 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1233 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1234 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1235 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1236 return;
1237 }
1238
1239 /*
1240 * Ok, it now shows up as a 96x.. run the 96x quirk by
1241 * hand in case it has already been processed.
1242 * (depends on link order, which is apparently not guaranteed)
1243 */
1244 dev->device = devid;
1245 quirk_sis_96x_smbus(dev);
1246 }
1247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1248 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1249
1250
1251 /*
1252 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1253 * and MC97 modem controller are disabled when a second PCI soundcard is
1254 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1255 * -- bjd
1256 */
1257 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1258 {
1259 u8 val;
1260 int asus_hides_ac97 = 0;
1261
1262 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1263 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1264 asus_hides_ac97 = 1;
1265 }
1266
1267 if (!asus_hides_ac97)
1268 return;
1269
1270 pci_read_config_byte(dev, 0x50, &val);
1271 if (val & 0xc0) {
1272 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1273 pci_read_config_byte(dev, 0x50, &val);
1274 if (val & 0xc0)
1275 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1276 else
1277 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1278 }
1279 }
1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1281 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1282
1283 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1284
1285 /*
1286 * If we are using libata we can drive this chip properly but must
1287 * do this early on to make the additional device appear during
1288 * the PCI scanning.
1289 */
1290 static void quirk_jmicron_ata(struct pci_dev *pdev)
1291 {
1292 u32 conf1, conf5, class;
1293 u8 hdr;
1294
1295 /* Only poke fn 0 */
1296 if (PCI_FUNC(pdev->devfn))
1297 return;
1298
1299 pci_read_config_dword(pdev, 0x40, &conf1);
1300 pci_read_config_dword(pdev, 0x80, &conf5);
1301
1302 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1303 conf5 &= ~(1 << 24); /* Clear bit 24 */
1304
1305 switch (pdev->device) {
1306 case PCI_DEVICE_ID_JMICRON_JMB360:
1307 /* The controller should be in single function ahci mode */
1308 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1309 break;
1310
1311 case PCI_DEVICE_ID_JMICRON_JMB365:
1312 case PCI_DEVICE_ID_JMICRON_JMB366:
1313 /* Redirect IDE second PATA port to the right spot */
1314 conf5 |= (1 << 24);
1315 /* Fall through */
1316 case PCI_DEVICE_ID_JMICRON_JMB361:
1317 case PCI_DEVICE_ID_JMICRON_JMB363:
1318 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1319 /* Set the class codes correctly and then direct IDE 0 */
1320 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1321 break;
1322
1323 case PCI_DEVICE_ID_JMICRON_JMB368:
1324 /* The controller should be in single function IDE mode */
1325 conf1 |= 0x00C00000; /* Set 22, 23 */
1326 break;
1327 }
1328
1329 pci_write_config_dword(pdev, 0x40, conf1);
1330 pci_write_config_dword(pdev, 0x80, conf5);
1331
1332 /* Update pdev accordingly */
1333 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1334 pdev->hdr_type = hdr & 0x7f;
1335 pdev->multifunction = !!(hdr & 0x80);
1336
1337 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1338 pdev->class = class >> 8;
1339 }
1340 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1341 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1342 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1343 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1344 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1345 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1346 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1347 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1348 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1349 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1350 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1351 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1352
1353 #endif
1354
1355 #ifdef CONFIG_X86_IO_APIC
1356 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1357 {
1358 int i;
1359
1360 if ((pdev->class >> 8) != 0xff00)
1361 return;
1362
1363 /* the first BAR is the location of the IO APIC...we must
1364 * not touch this (and it's already covered by the fixmap), so
1365 * forcibly insert it into the resource tree */
1366 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1367 insert_resource(&iomem_resource, &pdev->resource[0]);
1368
1369 /* The next five BARs all seem to be rubbish, so just clean
1370 * them out */
1371 for (i=1; i < 6; i++) {
1372 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1373 }
1374
1375 }
1376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1377 #endif
1378
1379 int pcie_mch_quirk;
1380 EXPORT_SYMBOL(pcie_mch_quirk);
1381
1382 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1383 {
1384 pcie_mch_quirk = 1;
1385 }
1386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1389
1390
1391 /*
1392 * It's possible for the MSI to get corrupted if shpc and acpi
1393 * are used together on certain PXH-based systems.
1394 */
1395 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1396 {
1397 pci_msi_off(dev);
1398 dev->no_msi = 1;
1399 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1400 }
1401 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1402 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1403 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1404 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1405 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1406
1407 /*
1408 * Some Intel PCI Express chipsets have trouble with downstream
1409 * device power management.
1410 */
1411 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1412 {
1413 pci_pm_d3_delay = 120;
1414 dev->no_d1d2 = 1;
1415 }
1416
1417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1438
1439 /*
1440 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1441 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1442 * Re-allocate the region if needed...
1443 */
1444 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1445 {
1446 struct resource *r = &dev->resource[0];
1447
1448 if (r->start & 0x8) {
1449 r->start = 0;
1450 r->end = 0xf;
1451 }
1452 }
1453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1454 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1455 quirk_tc86c001_ide);
1456
1457 static void __devinit quirk_netmos(struct pci_dev *dev)
1458 {
1459 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1460 unsigned int num_serial = dev->subsystem_device & 0xf;
1461
1462 /*
1463 * These Netmos parts are multiport serial devices with optional
1464 * parallel ports. Even when parallel ports are present, they
1465 * are identified as class SERIAL, which means the serial driver
1466 * will claim them. To prevent this, mark them as class OTHER.
1467 * These combo devices should be claimed by parport_serial.
1468 *
1469 * The subdevice ID is of the form 0x00PS, where <P> is the number
1470 * of parallel ports and <S> is the number of serial ports.
1471 */
1472 switch (dev->device) {
1473 case PCI_DEVICE_ID_NETMOS_9735:
1474 case PCI_DEVICE_ID_NETMOS_9745:
1475 case PCI_DEVICE_ID_NETMOS_9835:
1476 case PCI_DEVICE_ID_NETMOS_9845:
1477 case PCI_DEVICE_ID_NETMOS_9855:
1478 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1479 num_parallel) {
1480 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1481 "%u serial); changing class SERIAL to OTHER "
1482 "(use parport_serial)\n",
1483 dev->device, num_parallel, num_serial);
1484 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1485 (dev->class & 0xff);
1486 }
1487 }
1488 }
1489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1490
1491 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1492 {
1493 u16 command, pmcsr;
1494 u8 __iomem *csr;
1495 u8 cmd_hi;
1496 int pm;
1497
1498 switch (dev->device) {
1499 /* PCI IDs taken from drivers/net/e100.c */
1500 case 0x1029:
1501 case 0x1030 ... 0x1034:
1502 case 0x1038 ... 0x103E:
1503 case 0x1050 ... 0x1057:
1504 case 0x1059:
1505 case 0x1064 ... 0x106B:
1506 case 0x1091 ... 0x1095:
1507 case 0x1209:
1508 case 0x1229:
1509 case 0x2449:
1510 case 0x2459:
1511 case 0x245D:
1512 case 0x27DC:
1513 break;
1514 default:
1515 return;
1516 }
1517
1518 /*
1519 * Some firmware hands off the e100 with interrupts enabled,
1520 * which can cause a flood of interrupts if packets are
1521 * received before the driver attaches to the device. So
1522 * disable all e100 interrupts here. The driver will
1523 * re-enable them when it's ready.
1524 */
1525 pci_read_config_word(dev, PCI_COMMAND, &command);
1526
1527 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1528 return;
1529
1530 /*
1531 * Check that the device is in the D0 power state. If it's not,
1532 * there is no point to look any further.
1533 */
1534 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1535 if (pm) {
1536 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1537 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1538 return;
1539 }
1540
1541 /* Convert from PCI bus to resource space. */
1542 csr = ioremap(pci_resource_start(dev, 0), 8);
1543 if (!csr) {
1544 dev_warn(&dev->dev, "Can't map e100 registers\n");
1545 return;
1546 }
1547
1548 cmd_hi = readb(csr + 3);
1549 if (cmd_hi == 0) {
1550 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1551 "disabling\n");
1552 writeb(1, csr + 3);
1553 }
1554
1555 iounmap(csr);
1556 }
1557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1558
1559 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1560 {
1561 /* rev 1 ncr53c810 chips don't set the class at all which means
1562 * they don't get their resources remapped. Fix that here.
1563 */
1564
1565 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1566 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1567 dev->class = PCI_CLASS_STORAGE_SCSI;
1568 }
1569 }
1570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1571
1572 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1573 {
1574 while (f < end) {
1575 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1576 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1577 #ifdef DEBUG
1578 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
1579 #endif
1580 f->hook(dev);
1581 }
1582 f++;
1583 }
1584 }
1585
1586 extern struct pci_fixup __start_pci_fixups_early[];
1587 extern struct pci_fixup __end_pci_fixups_early[];
1588 extern struct pci_fixup __start_pci_fixups_header[];
1589 extern struct pci_fixup __end_pci_fixups_header[];
1590 extern struct pci_fixup __start_pci_fixups_final[];
1591 extern struct pci_fixup __end_pci_fixups_final[];
1592 extern struct pci_fixup __start_pci_fixups_enable[];
1593 extern struct pci_fixup __end_pci_fixups_enable[];
1594 extern struct pci_fixup __start_pci_fixups_resume[];
1595 extern struct pci_fixup __end_pci_fixups_resume[];
1596 extern struct pci_fixup __start_pci_fixups_resume_early[];
1597 extern struct pci_fixup __end_pci_fixups_resume_early[];
1598 extern struct pci_fixup __start_pci_fixups_suspend[];
1599 extern struct pci_fixup __end_pci_fixups_suspend[];
1600
1601
1602 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1603 {
1604 struct pci_fixup *start, *end;
1605
1606 switch(pass) {
1607 case pci_fixup_early:
1608 start = __start_pci_fixups_early;
1609 end = __end_pci_fixups_early;
1610 break;
1611
1612 case pci_fixup_header:
1613 start = __start_pci_fixups_header;
1614 end = __end_pci_fixups_header;
1615 break;
1616
1617 case pci_fixup_final:
1618 start = __start_pci_fixups_final;
1619 end = __end_pci_fixups_final;
1620 break;
1621
1622 case pci_fixup_enable:
1623 start = __start_pci_fixups_enable;
1624 end = __end_pci_fixups_enable;
1625 break;
1626
1627 case pci_fixup_resume:
1628 start = __start_pci_fixups_resume;
1629 end = __end_pci_fixups_resume;
1630 break;
1631
1632 case pci_fixup_resume_early:
1633 start = __start_pci_fixups_resume_early;
1634 end = __end_pci_fixups_resume_early;
1635 break;
1636
1637 case pci_fixup_suspend:
1638 start = __start_pci_fixups_suspend;
1639 end = __end_pci_fixups_suspend;
1640 break;
1641
1642 default:
1643 /* stupid compiler warning, you would think with an enum... */
1644 return;
1645 }
1646 pci_do_fixups(dev, start, end);
1647 }
1648 EXPORT_SYMBOL(pci_fixup_device);
1649
1650 /* Enable 1k I/O space granularity on the Intel P64H2 */
1651 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1652 {
1653 u16 en1k;
1654 u8 io_base_lo, io_limit_lo;
1655 unsigned long base, limit;
1656 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1657
1658 pci_read_config_word(dev, 0x40, &en1k);
1659
1660 if (en1k & 0x200) {
1661 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1662
1663 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1664 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1665 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1666 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1667
1668 if (base <= limit) {
1669 res->start = base;
1670 res->end = limit + 0x3ff;
1671 }
1672 }
1673 }
1674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1675
1676 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1677 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1678 * in drivers/pci/setup-bus.c
1679 */
1680 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1681 {
1682 u16 en1k, iobl_adr, iobl_adr_1k;
1683 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1684
1685 pci_read_config_word(dev, 0x40, &en1k);
1686
1687 if (en1k & 0x200) {
1688 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1689
1690 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1691
1692 if (iobl_adr != iobl_adr_1k) {
1693 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1694 iobl_adr,iobl_adr_1k);
1695 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1696 }
1697 }
1698 }
1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1700
1701 /* Under some circumstances, AER is not linked with extended capabilities.
1702 * Force it to be linked by setting the corresponding control bit in the
1703 * config space.
1704 */
1705 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1706 {
1707 uint8_t b;
1708 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1709 if (!(b & 0x20)) {
1710 pci_write_config_byte(dev, 0xf41, b | 0x20);
1711 dev_info(&dev->dev,
1712 "Linking AER extended capability\n");
1713 }
1714 }
1715 }
1716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1717 quirk_nvidia_ck804_pcie_aer_ext_cap);
1718 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1719 quirk_nvidia_ck804_pcie_aer_ext_cap);
1720
1721 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1722 {
1723 /*
1724 * Disable PCI Bus Parking and PCI Master read caching on CX700
1725 * which causes unspecified timing errors with a VT6212L on the PCI
1726 * bus leading to USB2.0 packet loss. The defaults are that these
1727 * features are turned off but some BIOSes turn them on.
1728 */
1729
1730 uint8_t b;
1731 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1732 if (b & 0x40) {
1733 /* Turn off PCI Bus Parking */
1734 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1735
1736 dev_info(&dev->dev,
1737 "Disabling VIA CX700 PCI parking\n");
1738 }
1739 }
1740
1741 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1742 if (b != 0) {
1743 /* Turn off PCI Master read caching */
1744 pci_write_config_byte(dev, 0x72, 0x0);
1745
1746 /* Set PCI Master Bus time-out to "1x16 PCLK" */
1747 pci_write_config_byte(dev, 0x75, 0x1);
1748
1749 /* Disable "Read FIFO Timer" */
1750 pci_write_config_byte(dev, 0x77, 0x0);
1751
1752 dev_info(&dev->dev,
1753 "Disabling VIA CX700 PCI caching\n");
1754 }
1755 }
1756 }
1757 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1758
1759 /*
1760 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1761 * VPD end tag will hang the device. This problem was initially
1762 * observed when a vpd entry was created in sysfs
1763 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1764 * will dump 32k of data. Reading a full 32k will cause an access
1765 * beyond the VPD end tag causing the device to hang. Once the device
1766 * is hung, the bnx2 driver will not be able to reset the device.
1767 * We believe that it is legal to read beyond the end tag and
1768 * therefore the solution is to limit the read/write length.
1769 */
1770 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1771 {
1772 /*
1773 * Only disable the VPD capability for 5706, 5706S, 5708,
1774 * 5708S and 5709 rev. A
1775 */
1776 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
1777 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
1778 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
1779 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
1780 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1781 (dev->revision & 0xf0) == 0x0)) {
1782 if (dev->vpd)
1783 dev->vpd->len = 0x80;
1784 }
1785 }
1786
1787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1788 PCI_DEVICE_ID_NX2_5706,
1789 quirk_brcm_570x_limit_vpd);
1790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1791 PCI_DEVICE_ID_NX2_5706S,
1792 quirk_brcm_570x_limit_vpd);
1793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1794 PCI_DEVICE_ID_NX2_5708,
1795 quirk_brcm_570x_limit_vpd);
1796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1797 PCI_DEVICE_ID_NX2_5708S,
1798 quirk_brcm_570x_limit_vpd);
1799 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1800 PCI_DEVICE_ID_NX2_5709,
1801 quirk_brcm_570x_limit_vpd);
1802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1803 PCI_DEVICE_ID_NX2_5709S,
1804 quirk_brcm_570x_limit_vpd);
1805
1806 #ifdef CONFIG_PCI_MSI
1807 /* Some chipsets do not support MSI. We cannot easily rely on setting
1808 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1809 * some other busses controlled by the chipset even if Linux is not
1810 * aware of it. Instead of setting the flag on all busses in the
1811 * machine, simply disable MSI globally.
1812 */
1813 static void __init quirk_disable_all_msi(struct pci_dev *dev)
1814 {
1815 pci_no_msi();
1816 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
1817 }
1818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
1821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
1822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
1823
1824 /* Disable MSI on chipsets that are known to not support it */
1825 static void __devinit quirk_disable_msi(struct pci_dev *dev)
1826 {
1827 if (dev->subordinate) {
1828 dev_warn(&dev->dev, "MSI quirk detected; "
1829 "subordinate MSI disabled\n");
1830 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1831 }
1832 }
1833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1834
1835 /* Go through the list of Hypertransport capabilities and
1836 * return 1 if a HT MSI capability is found and enabled */
1837 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1838 {
1839 int pos, ttl = 48;
1840
1841 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1842 while (pos && ttl--) {
1843 u8 flags;
1844
1845 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1846 &flags) == 0)
1847 {
1848 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
1849 flags & HT_MSI_FLAGS_ENABLE ?
1850 "enabled" : "disabled");
1851 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1852 }
1853
1854 pos = pci_find_next_ht_capability(dev, pos,
1855 HT_CAPTYPE_MSI_MAPPING);
1856 }
1857 return 0;
1858 }
1859
1860 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1861 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1862 {
1863 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1864 dev_warn(&dev->dev, "MSI quirk detected; "
1865 "subordinate MSI disabled\n");
1866 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1867 }
1868 }
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1870 quirk_msi_ht_cap);
1871
1872
1873 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1874 * MSI are supported if the MSI capability set in any of these mappings.
1875 */
1876 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1877 {
1878 struct pci_dev *pdev;
1879
1880 if (!dev->subordinate)
1881 return;
1882
1883 /* check HT MSI cap on this chipset and the root one.
1884 * a single one having MSI is enough to be sure that MSI are supported.
1885 */
1886 pdev = pci_get_slot(dev->bus, 0);
1887 if (!pdev)
1888 return;
1889 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1890 dev_warn(&dev->dev, "MSI quirk detected; "
1891 "subordinate MSI disabled\n");
1892 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1893 }
1894 pci_dev_put(pdev);
1895 }
1896 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1897 quirk_nvidia_ck804_msi_ht_cap);
1898
1899 /* Force enable MSI mapping capability on HT bridges */
1900 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
1901 {
1902 int pos, ttl = 48;
1903
1904 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1905 while (pos && ttl--) {
1906 u8 flags;
1907
1908 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1909 &flags) == 0) {
1910 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
1911
1912 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1913 flags | HT_MSI_FLAGS_ENABLE);
1914 }
1915 pos = pci_find_next_ht_capability(dev, pos,
1916 HT_CAPTYPE_MSI_MAPPING);
1917 }
1918 }
1919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1920 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1921 ht_enable_msi_mapping);
1922
1923 static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
1924 {
1925 struct pci_dev *host_bridge;
1926 int pos, ttl = 48;
1927
1928 /*
1929 * HT MSI mapping should be disabled on devices that are below
1930 * a non-Hypertransport host bridge. Locate the host bridge...
1931 */
1932 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1933 if (host_bridge == NULL) {
1934 dev_warn(&dev->dev,
1935 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1936 return;
1937 }
1938
1939 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
1940 if (pos != 0) {
1941 /* Host bridge is to HT */
1942 ht_enable_msi_mapping(dev);
1943 return;
1944 }
1945
1946 /* Host bridge is not to HT, disable HT MSI mapping on this device */
1947 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1948 while (pos && ttl--) {
1949 u8 flags;
1950
1951 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1952 &flags) == 0) {
1953 dev_info(&dev->dev, "Disabling HT MSI mapping");
1954 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1955 flags & ~HT_MSI_FLAGS_ENABLE);
1956 }
1957 pos = pci_find_next_ht_capability(dev, pos,
1958 HT_CAPTYPE_MSI_MAPPING);
1959 }
1960 }
1961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
1962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
1963
1964 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1965 {
1966 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1967 }
1968 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1969 {
1970 struct pci_dev *p;
1971
1972 /* SB700 MSI issue will be fixed at HW level from revision A21,
1973 * we need check PCI REVISION ID of SMBus controller to get SB700
1974 * revision.
1975 */
1976 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1977 NULL);
1978 if (!p)
1979 return;
1980
1981 if ((p->revision < 0x3B) && (p->revision >= 0x30))
1982 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1983 pci_dev_put(p);
1984 }
1985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1986 PCI_DEVICE_ID_TIGON3_5780,
1987 quirk_msi_intx_disable_bug);
1988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1989 PCI_DEVICE_ID_TIGON3_5780S,
1990 quirk_msi_intx_disable_bug);
1991 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1992 PCI_DEVICE_ID_TIGON3_5714,
1993 quirk_msi_intx_disable_bug);
1994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1995 PCI_DEVICE_ID_TIGON3_5714S,
1996 quirk_msi_intx_disable_bug);
1997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1998 PCI_DEVICE_ID_TIGON3_5715,
1999 quirk_msi_intx_disable_bug);
2000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2001 PCI_DEVICE_ID_TIGON3_5715S,
2002 quirk_msi_intx_disable_bug);
2003
2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2005 quirk_msi_intx_disable_ati_bug);
2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2007 quirk_msi_intx_disable_ati_bug);
2008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2009 quirk_msi_intx_disable_ati_bug);
2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2011 quirk_msi_intx_disable_ati_bug);
2012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2013 quirk_msi_intx_disable_ati_bug);
2014
2015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2016 quirk_msi_intx_disable_bug);
2017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2018 quirk_msi_intx_disable_bug);
2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2020 quirk_msi_intx_disable_bug);
2021
2022 #endif /* CONFIG_PCI_MSI */
Linux kernel - Deliverables
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