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HID: API - fix leftovers of hidinput API in USB HID
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include "pci.h"
25
26 /* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31 {
32 dev->broken_parity_status = 1; /* This device gives false positives */
33 }
34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
37 /* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39 static void quirk_passive_release(struct pci_dev *dev)
40 {
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54 }
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
56 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
57
58 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA
60 ask them for me please -- Alan
61
62 This appears to be BIOS not version dependent. So presumably there is a
63 chipset level fix */
64 int isa_dma_bridge_buggy; /* Exported */
65
66 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
67 {
68 if (!isa_dma_bridge_buggy) {
69 isa_dma_bridge_buggy=1;
70 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
71 }
72 }
73 /*
74 * Its not totally clear which chipsets are the problematic ones
75 * We know 82C586 and 82C596 variants are affected.
76 */
77 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
84
85 int pci_pci_problems;
86
87 /*
88 * Chipsets where PCI->PCI transfers vanish or hang
89 */
90 static void __devinit quirk_nopcipci(struct pci_dev *dev)
91 {
92 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
93 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
94 pci_pci_problems |= PCIPCI_FAIL;
95 }
96 }
97
98 static void __devinit quirk_nopciamd(struct pci_dev *dev)
99 {
100 u8 rev;
101 pci_read_config_byte(dev, 0x08, &rev);
102 if (rev == 0x13) {
103 /* Erratum 24 */
104 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n");
105 pci_pci_problems |= PCIAGP_FAIL;
106 }
107 }
108
109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd );
112
113 /*
114 * Triton requires workarounds to be used by the drivers
115 */
116 static void __devinit quirk_triton(struct pci_dev *dev)
117 {
118 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
119 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
120 pci_pci_problems |= PCIPCI_TRITON;
121 }
122 }
123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
127
128 /*
129 * VIA Apollo KT133 needs PCI latency patch
130 * Made according to a windows driver based patch by George E. Breese
131 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
132 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
133 * the info on which Mr Breese based his work.
134 *
135 * Updated based on further information from the site and also on
136 * information provided by VIA
137 */
138 static void quirk_vialatency(struct pci_dev *dev)
139 {
140 struct pci_dev *p;
141 u8 rev;
142 u8 busarb;
143 /* Ok we have a potential problem chipset here. Now see if we have
144 a buggy southbridge */
145
146 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
147 if (p!=NULL) {
148 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
150 /* Check for buggy part revisions */
151 if (rev < 0x40 || rev > 0x42)
152 goto exit;
153 } else {
154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
155 if (p==NULL) /* No problem parts */
156 goto exit;
157 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
158 /* Check for buggy part revisions */
159 if (rev < 0x10 || rev > 0x12)
160 goto exit;
161 }
162
163 /*
164 * Ok we have the problem. Now set the PCI master grant to
165 * occur every master grant. The apparent bug is that under high
166 * PCI load (quite common in Linux of course) you can get data
167 * loss when the CPU is held off the bus for 3 bus master requests
168 * This happens to include the IDE controllers....
169 *
170 * VIA only apply this fix when an SB Live! is present but under
171 * both Linux and Windows this isnt enough, and we have seen
172 * corruption without SB Live! but with things like 3 UDMA IDE
173 * controllers. So we ignore that bit of the VIA recommendation..
174 */
175
176 pci_read_config_byte(dev, 0x76, &busarb);
177 /* Set bit 4 and bi 5 of byte 76 to 0x01
178 "Master priority rotation on every PCI master grant */
179 busarb &= ~(1<<5);
180 busarb |= (1<<4);
181 pci_write_config_byte(dev, 0x76, busarb);
182 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
183 exit:
184 pci_dev_put(p);
185 }
186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
189 /* Must restore this on a resume from RAM */
190 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
191 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
192 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
193
194 /*
195 * VIA Apollo VP3 needs ETBF on BT848/878
196 */
197 static void __devinit quirk_viaetbf(struct pci_dev *dev)
198 {
199 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
200 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
201 pci_pci_problems |= PCIPCI_VIAETBF;
202 }
203 }
204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
205
206 static void __devinit quirk_vsfx(struct pci_dev *dev)
207 {
208 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
209 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
210 pci_pci_problems |= PCIPCI_VSFX;
211 }
212 }
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
214
215 /*
216 * Ali Magik requires workarounds to be used by the drivers
217 * that DMA to AGP space. Latency must be set to 0xA and triton
218 * workaround applied too
219 * [Info kindly provided by ALi]
220 */
221 static void __init quirk_alimagik(struct pci_dev *dev)
222 {
223 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
224 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
225 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
226 }
227 }
228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
230
231 /*
232 * Natoma has some interesting boundary conditions with Zoran stuff
233 * at least
234 */
235 static void __devinit quirk_natoma(struct pci_dev *dev)
236 {
237 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
238 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
239 pci_pci_problems |= PCIPCI_NATOMA;
240 }
241 }
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
248
249 /*
250 * This chip can cause PCI parity errors if config register 0xA0 is read
251 * while DMAs are occurring.
252 */
253 static void __devinit quirk_citrine(struct pci_dev *dev)
254 {
255 dev->cfg_size = 0xA0;
256 }
257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
258
259 /*
260 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
261 * If it's needed, re-allocate the region.
262 */
263 static void __devinit quirk_s3_64M(struct pci_dev *dev)
264 {
265 struct resource *r = &dev->resource[0];
266
267 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
268 r->start = 0;
269 r->end = 0x3ffffff;
270 }
271 }
272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
274
275 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
276 unsigned size, int nr, const char *name)
277 {
278 region &= ~(size-1);
279 if (region) {
280 struct pci_bus_region bus_region;
281 struct resource *res = dev->resource + nr;
282
283 res->name = pci_name(dev);
284 res->start = region;
285 res->end = region + size - 1;
286 res->flags = IORESOURCE_IO;
287
288 /* Convert from PCI bus to resource space. */
289 bus_region.start = res->start;
290 bus_region.end = res->end;
291 pcibios_bus_to_resource(dev, res, &bus_region);
292
293 pci_claim_resource(dev, nr);
294 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
295 }
296 }
297
298 /*
299 * ATI Northbridge setups MCE the processor if you even
300 * read somewhere between 0x3b0->0x3bb or read 0x3d3
301 */
302 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
303 {
304 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
305 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
306 request_region(0x3b0, 0x0C, "RadeonIGP");
307 request_region(0x3d3, 0x01, "RadeonIGP");
308 }
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
310
311 /*
312 * Let's make the southbridge information explicit instead
313 * of having to worry about people probing the ACPI areas,
314 * for example.. (Yes, it happens, and if you read the wrong
315 * ACPI register it will put the machine to sleep with no
316 * way of waking it up again. Bummer).
317 *
318 * ALI M7101: Two IO regions pointed to by words at
319 * 0xE0 (64 bytes of ACPI registers)
320 * 0xE2 (32 bytes of SMB registers)
321 */
322 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
323 {
324 u16 region;
325
326 pci_read_config_word(dev, 0xE0, &region);
327 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
328 pci_read_config_word(dev, 0xE2, &region);
329 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
330 }
331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
332
333 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
334 {
335 u32 devres;
336 u32 mask, size, base;
337
338 pci_read_config_dword(dev, port, &devres);
339 if ((devres & enable) != enable)
340 return;
341 mask = (devres >> 16) & 15;
342 base = devres & 0xffff;
343 size = 16;
344 for (;;) {
345 unsigned bit = size >> 1;
346 if ((bit & mask) == bit)
347 break;
348 size = bit;
349 }
350 /*
351 * For now we only print it out. Eventually we'll want to
352 * reserve it (at least if it's in the 0x1000+ range), but
353 * let's get enough confirmation reports first.
354 */
355 base &= -size;
356 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
357 }
358
359 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
360 {
361 u32 devres;
362 u32 mask, size, base;
363
364 pci_read_config_dword(dev, port, &devres);
365 if ((devres & enable) != enable)
366 return;
367 base = devres & 0xffff0000;
368 mask = (devres & 0x3f) << 16;
369 size = 128 << 16;
370 for (;;) {
371 unsigned bit = size >> 1;
372 if ((bit & mask) == bit)
373 break;
374 size = bit;
375 }
376 /*
377 * For now we only print it out. Eventually we'll want to
378 * reserve it, but let's get enough confirmation reports first.
379 */
380 base &= -size;
381 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
382 }
383
384 /*
385 * PIIX4 ACPI: Two IO regions pointed to by longwords at
386 * 0x40 (64 bytes of ACPI registers)
387 * 0x90 (16 bytes of SMB registers)
388 * and a few strange programmable PIIX4 device resources.
389 */
390 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
391 {
392 u32 region, res_a;
393
394 pci_read_config_dword(dev, 0x40, &region);
395 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
396 pci_read_config_dword(dev, 0x90, &region);
397 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
398
399 /* Device resource A has enables for some of the other ones */
400 pci_read_config_dword(dev, 0x5c, &res_a);
401
402 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
403 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
404
405 /* Device resource D is just bitfields for static resources */
406
407 /* Device 12 enabled? */
408 if (res_a & (1 << 29)) {
409 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
410 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
411 }
412 /* Device 13 enabled? */
413 if (res_a & (1 << 30)) {
414 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
415 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
416 }
417 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
418 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
419 }
420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
422
423 /*
424 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
425 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
426 * 0x58 (64 bytes of GPIO I/O space)
427 */
428 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
429 {
430 u32 region;
431
432 pci_read_config_dword(dev, 0x40, &region);
433 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
434
435 pci_read_config_dword(dev, 0x58, &region);
436 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
437 }
438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
448
449 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
450 {
451 u32 region;
452
453 pci_read_config_dword(dev, 0x40, &region);
454 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
455
456 pci_read_config_dword(dev, 0x48, &region);
457 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
458 }
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi );
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi );
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi );
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi );
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi );
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi );
467
468 /*
469 * VIA ACPI: One IO region pointed to by longword at
470 * 0x48 or 0x20 (256 bytes of ACPI registers)
471 */
472 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
473 {
474 u8 rev;
475 u32 region;
476
477 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
478 if (rev & 0x10) {
479 pci_read_config_dword(dev, 0x48, &region);
480 region &= PCI_BASE_ADDRESS_IO_MASK;
481 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
482 }
483 }
484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
485
486 /*
487 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
488 * 0x48 (256 bytes of ACPI registers)
489 * 0x70 (128 bytes of hardware monitoring register)
490 * 0x90 (16 bytes of SMB registers)
491 */
492 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
493 {
494 u16 hm;
495 u32 smb;
496
497 quirk_vt82c586_acpi(dev);
498
499 pci_read_config_word(dev, 0x70, &hm);
500 hm &= PCI_BASE_ADDRESS_IO_MASK;
501 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
502
503 pci_read_config_dword(dev, 0x90, &smb);
504 smb &= PCI_BASE_ADDRESS_IO_MASK;
505 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
506 }
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
508
509 /*
510 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
511 * 0x88 (128 bytes of power management registers)
512 * 0xd0 (16 bytes of SMB registers)
513 */
514 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
515 {
516 u16 pm, smb;
517
518 pci_read_config_word(dev, 0x88, &pm);
519 pm &= PCI_BASE_ADDRESS_IO_MASK;
520 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
521
522 pci_read_config_word(dev, 0xd0, &smb);
523 smb &= PCI_BASE_ADDRESS_IO_MASK;
524 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
525 }
526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
527
528
529 #ifdef CONFIG_X86_IO_APIC
530
531 #include <asm/io_apic.h>
532
533 /*
534 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
535 * devices to the external APIC.
536 *
537 * TODO: When we have device-specific interrupt routers,
538 * this code will go away from quirks.
539 */
540 static void quirk_via_ioapic(struct pci_dev *dev)
541 {
542 u8 tmp;
543
544 if (nr_ioapics < 1)
545 tmp = 0; /* nothing routed to external APIC */
546 else
547 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
548
549 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
550 tmp == 0 ? "Disa" : "Ena");
551
552 /* Offset 0x58: External APIC IRQ output control */
553 pci_write_config_byte (dev, 0x58, tmp);
554 }
555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
556 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
557
558 /*
559 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
560 * This leads to doubled level interrupt rates.
561 * Set this bit to get rid of cycle wastage.
562 * Otherwise uncritical.
563 */
564 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
565 {
566 u8 misc_control2;
567 #define BYPASS_APIC_DEASSERT 8
568
569 pci_read_config_byte(dev, 0x5B, &misc_control2);
570 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
571 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
572 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
573 }
574 }
575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
576 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
577
578 /*
579 * The AMD io apic can hang the box when an apic irq is masked.
580 * We check all revs >= B0 (yet not in the pre production!) as the bug
581 * is currently marked NoFix
582 *
583 * We have multiple reports of hangs with this chipset that went away with
584 * noapic specified. For the moment we assume it's the erratum. We may be wrong
585 * of course. However the advice is demonstrably good even if so..
586 */
587 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
588 {
589 u8 rev;
590
591 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
592 if (rev >= 0x02) {
593 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
594 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
595 }
596 }
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
598
599 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
600 {
601 if (dev->devfn == 0 && dev->bus->number == 0)
602 sis_apic_bug = 1;
603 }
604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
605
606 #define AMD8131_revA0 0x01
607 #define AMD8131_revB0 0x11
608 #define AMD8131_MISC 0x40
609 #define AMD8131_NIOAMODE_BIT 0
610 static void quirk_amd_8131_ioapic(struct pci_dev *dev)
611 {
612 unsigned char revid, tmp;
613
614 if (nr_ioapics == 0)
615 return;
616
617 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
618 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
619 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
620 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
621 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
622 pci_write_config_byte( dev, AMD8131_MISC, tmp);
623 }
624 }
625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
626 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
627 #endif /* CONFIG_X86_IO_APIC */
628
629
630 /*
631 * FIXME: it is questionable that quirk_via_acpi
632 * is needed. It shows up as an ISA bridge, and does not
633 * support the PCI_INTERRUPT_LINE register at all. Therefore
634 * it seems like setting the pci_dev's 'irq' to the
635 * value of the ACPI SCI interrupt is only done for convenience.
636 * -jgarzik
637 */
638 static void __devinit quirk_via_acpi(struct pci_dev *d)
639 {
640 /*
641 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
642 */
643 u8 irq;
644 pci_read_config_byte(d, 0x42, &irq);
645 irq &= 0xf;
646 if (irq && (irq != 2))
647 d->irq = irq;
648 }
649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
651
652
653 /*
654 * VIA bridges which have VLink
655 */
656
657 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
658
659 static void quirk_via_bridge(struct pci_dev *dev)
660 {
661 /* See what bridge we have and find the device ranges */
662 switch (dev->device) {
663 case PCI_DEVICE_ID_VIA_82C686:
664 /* The VT82C686 is special, it attaches to PCI and can have
665 any device number. All its subdevices are functions of
666 that single device. */
667 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
668 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
669 break;
670 case PCI_DEVICE_ID_VIA_8237:
671 case PCI_DEVICE_ID_VIA_8237A:
672 via_vlink_dev_lo = 15;
673 break;
674 case PCI_DEVICE_ID_VIA_8235:
675 via_vlink_dev_lo = 16;
676 break;
677 case PCI_DEVICE_ID_VIA_8231:
678 case PCI_DEVICE_ID_VIA_8233_0:
679 case PCI_DEVICE_ID_VIA_8233A:
680 case PCI_DEVICE_ID_VIA_8233C_0:
681 via_vlink_dev_lo = 17;
682 break;
683 }
684 }
685 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
686 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
687 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
693
694 /**
695 * quirk_via_vlink - VIA VLink IRQ number update
696 * @dev: PCI device
697 *
698 * If the device we are dealing with is on a PIC IRQ we need to
699 * ensure that the IRQ line register which usually is not relevant
700 * for PCI cards, is actually written so that interrupts get sent
701 * to the right place.
702 * We only do this on systems where a VIA south bridge was detected,
703 * and only for VIA devices on the motherboard (see quirk_via_bridge
704 * above).
705 */
706
707 static void quirk_via_vlink(struct pci_dev *dev)
708 {
709 u8 irq, new_irq;
710
711 /* Check if we have VLink at all */
712 if (via_vlink_dev_lo == -1)
713 return;
714
715 new_irq = dev->irq;
716
717 /* Don't quirk interrupts outside the legacy IRQ range */
718 if (!new_irq || new_irq > 15)
719 return;
720
721 /* Internal device ? */
722 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
723 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
724 return;
725
726 /* This is an internal VLink device on a PIC interrupt. The BIOS
727 ought to have set this but may not have, so we redo it */
728
729 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
730 if (new_irq != irq) {
731 printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n",
732 pci_name(dev), irq, new_irq);
733 udelay(15); /* unknown if delay really needed */
734 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
735 }
736 }
737 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
738
739 /*
740 * VIA VT82C598 has its device ID settable and many BIOSes
741 * set it to the ID of VT82C597 for backward compatibility.
742 * We need to switch it off to be able to recognize the real
743 * type of the chip.
744 */
745 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
746 {
747 pci_write_config_byte(dev, 0xfc, 0);
748 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
749 }
750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
751
752 /*
753 * CardBus controllers have a legacy base address that enables them
754 * to respond as i82365 pcmcia controllers. We don't want them to
755 * do this even if the Linux CardBus driver is not loaded, because
756 * the Linux i82365 driver does not (and should not) handle CardBus.
757 */
758 static void quirk_cardbus_legacy(struct pci_dev *dev)
759 {
760 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
761 return;
762 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
763 }
764 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
765 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
766
767 /*
768 * Following the PCI ordering rules is optional on the AMD762. I'm not
769 * sure what the designers were smoking but let's not inhale...
770 *
771 * To be fair to AMD, it follows the spec by default, its BIOS people
772 * who turn it off!
773 */
774 static void quirk_amd_ordering(struct pci_dev *dev)
775 {
776 u32 pcic;
777 pci_read_config_dword(dev, 0x4C, &pcic);
778 if ((pcic&6)!=6) {
779 pcic |= 6;
780 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
781 pci_write_config_dword(dev, 0x4C, pcic);
782 pci_read_config_dword(dev, 0x84, &pcic);
783 pcic |= (1<<23); /* Required in this mode */
784 pci_write_config_dword(dev, 0x84, pcic);
785 }
786 }
787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
788 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
789
790 /*
791 * DreamWorks provided workaround for Dunord I-3000 problem
792 *
793 * This card decodes and responds to addresses not apparently
794 * assigned to it. We force a larger allocation to ensure that
795 * nothing gets put too close to it.
796 */
797 static void __devinit quirk_dunord ( struct pci_dev * dev )
798 {
799 struct resource *r = &dev->resource [1];
800 r->start = 0;
801 r->end = 0xffffff;
802 }
803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
804
805 /*
806 * i82380FB mobile docking controller: its PCI-to-PCI bridge
807 * is subtractive decoding (transparent), and does indicate this
808 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
809 * instead of 0x01.
810 */
811 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
812 {
813 dev->transparent = 1;
814 }
815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
817
818 /*
819 * Common misconfiguration of the MediaGX/Geode PCI master that will
820 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
821 * datasheets found at http://www.national.com/ds/GX for info on what
822 * these bits do. <christer@weinigel.se>
823 */
824 static void quirk_mediagx_master(struct pci_dev *dev)
825 {
826 u8 reg;
827 pci_read_config_byte(dev, 0x41, &reg);
828 if (reg & 2) {
829 reg &= ~2;
830 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
831 pci_write_config_byte(dev, 0x41, reg);
832 }
833 }
834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
835 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
836
837 /*
838 * Ensure C0 rev restreaming is off. This is normally done by
839 * the BIOS but in the odd case it is not the results are corruption
840 * hence the presence of a Linux check
841 */
842 static void quirk_disable_pxb(struct pci_dev *pdev)
843 {
844 u16 config;
845 u8 rev;
846
847 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
848 if (rev != 0x04) /* Only C0 requires this */
849 return;
850 pci_read_config_word(pdev, 0x40, &config);
851 if (config & (1<<6)) {
852 config &= ~(1<<6);
853 pci_write_config_word(pdev, 0x40, config);
854 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
855 }
856 }
857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
858 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
859
860
861 static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
862 {
863 /* set sb600 sata to ahci mode */
864 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
865 u8 tmp;
866
867 pci_read_config_byte(pdev, 0x40, &tmp);
868 pci_write_config_byte(pdev, 0x40, tmp|1);
869 pci_write_config_byte(pdev, 0x9, 1);
870 pci_write_config_byte(pdev, 0xa, 6);
871 pci_write_config_byte(pdev, 0x40, tmp);
872
873 pdev->class = 0x010601;
874 }
875 }
876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata);
877
878 /*
879 * Serverworks CSB5 IDE does not fully support native mode
880 */
881 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
882 {
883 u8 prog;
884 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
885 if (prog & 5) {
886 prog &= ~5;
887 pdev->class &= ~5;
888 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
889 /* PCI layer will sort out resources */
890 }
891 }
892 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
893
894 /*
895 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
896 */
897 static void __init quirk_ide_samemode(struct pci_dev *pdev)
898 {
899 u8 prog;
900
901 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
902
903 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
904 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
905 prog &= ~5;
906 pdev->class &= ~5;
907 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
908 }
909 }
910 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
911
912 /* This was originally an Alpha specific thing, but it really fits here.
913 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
914 */
915 static void __init quirk_eisa_bridge(struct pci_dev *dev)
916 {
917 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
918 }
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
920
921 /*
922 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
923 * when a PCI-Soundcard is added. The BIOS only gives Options
924 * "Disabled" and "AUTO". This Quirk Sets the corresponding
925 * Register-Value to enable the Soundcard.
926 *
927 * FIXME: Presently this quirk will run on anything that has an 8237
928 * which isn't correct, we need to check DMI tables or something in
929 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
930 * runs everywhere at present we suppress the printk output in most
931 * irrelevant cases.
932 */
933 static void k8t_sound_hostbridge(struct pci_dev *dev)
934 {
935 unsigned char val;
936
937 pci_read_config_byte(dev, 0x50, &val);
938 if (val == 0x88 || val == 0xc8) {
939 /* Assume it's probably a MSI-K8T-Neo2Fir */
940 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
941 pci_write_config_byte(dev, 0x50, val & (~0x40));
942
943 /* Verify the Change for Status output */
944 pci_read_config_byte(dev, 0x50, &val);
945 if (val & 0x40)
946 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
947 else
948 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
949 }
950 }
951 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
952 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
953
954 /*
955 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
956 * is not activated. The myth is that Asus said that they do not want the
957 * users to be irritated by just another PCI Device in the Win98 device
958 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
959 * package 2.7.0 for details)
960 *
961 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
962 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
963 * becomes necessary to do this tweak in two steps -- I've chosen the Host
964 * bridge as trigger.
965 */
966 static int asus_hides_smbus;
967
968 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
969 {
970 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
971 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
972 switch(dev->subsystem_device) {
973 case 0x8025: /* P4B-LX */
974 case 0x8070: /* P4B */
975 case 0x8088: /* P4B533 */
976 case 0x1626: /* L3C notebook */
977 asus_hides_smbus = 1;
978 }
979 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
980 switch(dev->subsystem_device) {
981 case 0x80b1: /* P4GE-V */
982 case 0x80b2: /* P4PE */
983 case 0x8093: /* P4B533-V */
984 asus_hides_smbus = 1;
985 }
986 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
987 switch(dev->subsystem_device) {
988 case 0x8030: /* P4T533 */
989 asus_hides_smbus = 1;
990 }
991 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
992 switch (dev->subsystem_device) {
993 case 0x8070: /* P4G8X Deluxe */
994 asus_hides_smbus = 1;
995 }
996 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
997 switch (dev->subsystem_device) {
998 case 0x80c9: /* PU-DLS */
999 asus_hides_smbus = 1;
1000 }
1001 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1002 switch (dev->subsystem_device) {
1003 case 0x1751: /* M2N notebook */
1004 case 0x1821: /* M5N notebook */
1005 asus_hides_smbus = 1;
1006 }
1007 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1008 switch (dev->subsystem_device) {
1009 case 0x184b: /* W1N notebook */
1010 case 0x186a: /* M6Ne notebook */
1011 asus_hides_smbus = 1;
1012 }
1013 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1014 switch (dev->subsystem_device) {
1015 case 0x80f2: /* P4P800-X */
1016 asus_hides_smbus = 1;
1017 }
1018 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1019 switch (dev->subsystem_device) {
1020 case 0x1882: /* M6V notebook */
1021 case 0x1977: /* A6VA notebook */
1022 asus_hides_smbus = 1;
1023 }
1024 }
1025 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1026 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1027 switch(dev->subsystem_device) {
1028 case 0x088C: /* HP Compaq nc8000 */
1029 case 0x0890: /* HP Compaq nc6000 */
1030 asus_hides_smbus = 1;
1031 }
1032 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1033 switch (dev->subsystem_device) {
1034 case 0x12bc: /* HP D330L */
1035 case 0x12bd: /* HP D530 */
1036 asus_hides_smbus = 1;
1037 }
1038 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1039 switch (dev->subsystem_device) {
1040 case 0x099c: /* HP Compaq nx6110 */
1041 asus_hides_smbus = 1;
1042 }
1043 }
1044 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1045 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1046 switch(dev->subsystem_device) {
1047 case 0x0001: /* Toshiba Satellite A40 */
1048 asus_hides_smbus = 1;
1049 }
1050 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1051 switch(dev->subsystem_device) {
1052 case 0x0001: /* Toshiba Tecra M2 */
1053 asus_hides_smbus = 1;
1054 }
1055 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1056 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1057 switch(dev->subsystem_device) {
1058 case 0xC00C: /* Samsung P35 notebook */
1059 asus_hides_smbus = 1;
1060 }
1061 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1062 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1063 switch(dev->subsystem_device) {
1064 case 0x0058: /* Compaq Evo N620c */
1065 asus_hides_smbus = 1;
1066 }
1067 }
1068 }
1069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
1077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1078
1079 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1080 {
1081 u16 val;
1082
1083 if (likely(!asus_hides_smbus))
1084 return;
1085
1086 pci_read_config_word(dev, 0xF2, &val);
1087 if (val & 0x8) {
1088 pci_write_config_word(dev, 0xF2, val & (~0x8));
1089 pci_read_config_word(dev, 0xF2, &val);
1090 if (val & 0x8)
1091 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1092 else
1093 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1094 }
1095 }
1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1099 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1102 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1103 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1104 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1105 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1106 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1107 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1108
1109 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1110 {
1111 u32 val, rcba;
1112 void __iomem *base;
1113
1114 if (likely(!asus_hides_smbus))
1115 return;
1116 pci_read_config_dword(dev, 0xF0, &rcba);
1117 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1118 if (base == NULL) return;
1119 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1120 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1121 iounmap(base);
1122 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1123 }
1124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1125 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1126
1127 /*
1128 * SiS 96x south bridge: BIOS typically hides SMBus device...
1129 */
1130 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1131 {
1132 u8 val = 0;
1133 pci_read_config_byte(dev, 0x77, &val);
1134 if (val & 0x10) {
1135 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1136 pci_write_config_byte(dev, 0x77, val & ~0x10);
1137 }
1138 }
1139
1140 /*
1141 * ... This is further complicated by the fact that some SiS96x south
1142 * bridges pretend to be 85C503/5513 instead. In that case see if we
1143 * spotted a compatible north bridge to make sure.
1144 * (pci_find_device doesn't work yet)
1145 *
1146 * We can also enable the sis96x bit in the discovery register..
1147 */
1148 static int __devinitdata sis_96x_compatible = 0;
1149
1150 #define SIS_DETECT_REGISTER 0x40
1151
1152 static void quirk_sis_503(struct pci_dev *dev)
1153 {
1154 u8 reg;
1155 u16 devid;
1156
1157 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1158 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1159 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1160 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1161 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1162 return;
1163 }
1164
1165 /* Make people aware that we changed the config.. */
1166 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1167
1168 /*
1169 * Ok, it now shows up as a 96x.. run the 96x quirk by
1170 * hand in case it has already been processed.
1171 * (depends on link order, which is apparently not guaranteed)
1172 */
1173 dev->device = devid;
1174 quirk_sis_96x_smbus(dev);
1175 }
1176
1177 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1178 {
1179 sis_96x_compatible = 1;
1180 }
1181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1187
1188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1189 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1190 /*
1191 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1192 * and MC97 modem controller are disabled when a second PCI soundcard is
1193 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1194 * -- bjd
1195 */
1196 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1197 {
1198 u8 val;
1199 int asus_hides_ac97 = 0;
1200
1201 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1202 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1203 asus_hides_ac97 = 1;
1204 }
1205
1206 if (!asus_hides_ac97)
1207 return;
1208
1209 pci_read_config_byte(dev, 0x50, &val);
1210 if (val & 0xc0) {
1211 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1212 pci_read_config_byte(dev, 0x50, &val);
1213 if (val & 0xc0)
1214 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1215 else
1216 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1217 }
1218 }
1219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1220
1221
1222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1226
1227 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1228
1229
1230 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1231 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1232 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1233 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1234
1235 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1236
1237 /*
1238 * If we are using libata we can drive this chip properly but must
1239 * do this early on to make the additional device appear during
1240 * the PCI scanning.
1241 */
1242
1243 static void quirk_jmicron_dualfn(struct pci_dev *pdev)
1244 {
1245 u32 conf;
1246 u8 hdr;
1247
1248 /* Only poke fn 0 */
1249 if (PCI_FUNC(pdev->devfn))
1250 return;
1251
1252 switch(pdev->device) {
1253 case PCI_DEVICE_ID_JMICRON_JMB365:
1254 case PCI_DEVICE_ID_JMICRON_JMB366:
1255 /* Redirect IDE second PATA port to the right spot */
1256 pci_read_config_dword(pdev, 0x80, &conf);
1257 conf |= (1 << 24);
1258 /* Fall through */
1259 pci_write_config_dword(pdev, 0x80, conf);
1260 case PCI_DEVICE_ID_JMICRON_JMB361:
1261 case PCI_DEVICE_ID_JMICRON_JMB363:
1262 pci_read_config_dword(pdev, 0x40, &conf);
1263 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1264 /* Set the class codes correctly and then direct IDE 0 */
1265 conf &= ~0x000FF200; /* Clear bit 9 and 12-19 */
1266 conf |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */
1267 pci_write_config_dword(pdev, 0x40, conf);
1268
1269 /* Reconfigure so that the PCI scanner discovers the
1270 device is now multifunction */
1271
1272 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1273 pdev->hdr_type = hdr & 0x7f;
1274 pdev->multifunction = !!(hdr & 0x80);
1275
1276 break;
1277 }
1278 }
1279
1280 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1281 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1282
1283 #endif
1284
1285 #ifdef CONFIG_X86_IO_APIC
1286 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1287 {
1288 int i;
1289
1290 if ((pdev->class >> 8) != 0xff00)
1291 return;
1292
1293 /* the first BAR is the location of the IO APIC...we must
1294 * not touch this (and it's already covered by the fixmap), so
1295 * forcibly insert it into the resource tree */
1296 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1297 insert_resource(&iomem_resource, &pdev->resource[0]);
1298
1299 /* The next five BARs all seem to be rubbish, so just clean
1300 * them out */
1301 for (i=1; i < 6; i++) {
1302 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1303 }
1304
1305 }
1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1307 #endif
1308
1309 enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1310 /* Defaults to combined */
1311 static enum ide_combined_type combined_mode;
1312
1313 static int __init combined_setup(char *str)
1314 {
1315 if (!strncmp(str, "ide", 3))
1316 combined_mode = IDE;
1317 else if (!strncmp(str, "libata", 6))
1318 combined_mode = LIBATA;
1319 else /* "combined" or anything else defaults to old behavior */
1320 combined_mode = COMBINED;
1321
1322 return 1;
1323 }
1324 __setup("combined_mode=", combined_setup);
1325
1326 #ifdef CONFIG_SATA_INTEL_COMBINED
1327 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1328 {
1329 u8 prog, comb, tmp;
1330 int ich = 0;
1331
1332 /*
1333 * Narrow down to Intel SATA PCI devices.
1334 */
1335 switch (pdev->device) {
1336 /* PCI ids taken from drivers/scsi/ata_piix.c */
1337 case 0x24d1:
1338 case 0x24df:
1339 case 0x25a3:
1340 case 0x25b0:
1341 ich = 5;
1342 break;
1343 case 0x2651:
1344 case 0x2652:
1345 case 0x2653:
1346 case 0x2680: /* ESB2 */
1347 ich = 6;
1348 break;
1349 case 0x27c0:
1350 case 0x27c4:
1351 ich = 7;
1352 break;
1353 case 0x2828: /* ICH8M */
1354 ich = 8;
1355 break;
1356 default:
1357 /* we do not handle this PCI device */
1358 return;
1359 }
1360
1361 /*
1362 * Read combined mode register.
1363 */
1364 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1365
1366 if (ich == 5) {
1367 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1368 if (tmp == 0x4) /* bits 10x */
1369 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1370 else if (tmp == 0x6) /* bits 11x */
1371 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1372 else
1373 return; /* not in combined mode */
1374 } else {
1375 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1376 tmp &= 0x3; /* interesting bits 1:0 */
1377 if (tmp & (1 << 0))
1378 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1379 else if (tmp & (1 << 1))
1380 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1381 else
1382 return; /* not in combined mode */
1383 }
1384
1385 /*
1386 * Read programming interface register.
1387 * (Tells us if it's legacy or native mode)
1388 */
1389 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1390
1391 /* if SATA port is in native mode, we're ok. */
1392 if (prog & comb)
1393 return;
1394
1395 /* Don't reserve any so the IDE driver can get them (but only if
1396 * combined_mode=ide).
1397 */
1398 if (combined_mode == IDE)
1399 return;
1400
1401 /* Grab them both for libata if combined_mode=libata. */
1402 if (combined_mode == LIBATA) {
1403 request_region(0x1f0, 8, "libata"); /* port 0 */
1404 request_region(0x170, 8, "libata"); /* port 1 */
1405 return;
1406 }
1407
1408 /* SATA port is in legacy mode. Reserve port so that
1409 * IDE driver does not attempt to use it. If request_region
1410 * fails, it will be obvious at boot time, so we don't bother
1411 * checking return values.
1412 */
1413 if (comb == (1 << 0))
1414 request_region(0x1f0, 8, "libata"); /* port 0 */
1415 else
1416 request_region(0x170, 8, "libata"); /* port 1 */
1417 }
1418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1419 #endif /* CONFIG_SATA_INTEL_COMBINED */
1420
1421
1422 int pcie_mch_quirk;
1423
1424 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1425 {
1426 pcie_mch_quirk = 1;
1427 }
1428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1431
1432
1433 /*
1434 * It's possible for the MSI to get corrupted if shpc and acpi
1435 * are used together on certain PXH-based systems.
1436 */
1437 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1438 {
1439 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1440 PCI_CAP_ID_MSI);
1441 dev->no_msi = 1;
1442
1443 printk(KERN_WARNING "PCI: PXH quirk detected, "
1444 "disabling MSI for SHPC device\n");
1445 }
1446 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1447 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1448 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1449 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1450 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1451
1452 /*
1453 * Some Intel PCI Express chipsets have trouble with downstream
1454 * device power management.
1455 */
1456 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1457 {
1458 pci_pm_d3_delay = 120;
1459 dev->no_d1d2 = 1;
1460 }
1461
1462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1470 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1471 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1472 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1473 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1474 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1475 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1483
1484 static void __devinit quirk_netmos(struct pci_dev *dev)
1485 {
1486 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1487 unsigned int num_serial = dev->subsystem_device & 0xf;
1488
1489 /*
1490 * These Netmos parts are multiport serial devices with optional
1491 * parallel ports. Even when parallel ports are present, they
1492 * are identified as class SERIAL, which means the serial driver
1493 * will claim them. To prevent this, mark them as class OTHER.
1494 * These combo devices should be claimed by parport_serial.
1495 *
1496 * The subdevice ID is of the form 0x00PS, where <P> is the number
1497 * of parallel ports and <S> is the number of serial ports.
1498 */
1499 switch (dev->device) {
1500 case PCI_DEVICE_ID_NETMOS_9735:
1501 case PCI_DEVICE_ID_NETMOS_9745:
1502 case PCI_DEVICE_ID_NETMOS_9835:
1503 case PCI_DEVICE_ID_NETMOS_9845:
1504 case PCI_DEVICE_ID_NETMOS_9855:
1505 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1506 num_parallel) {
1507 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1508 "%u serial); changing class SERIAL to OTHER "
1509 "(use parport_serial)\n",
1510 dev->device, num_parallel, num_serial);
1511 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1512 (dev->class & 0xff);
1513 }
1514 }
1515 }
1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1517
1518 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1519 {
1520 u16 command;
1521 u32 bar;
1522 u8 __iomem *csr;
1523 u8 cmd_hi;
1524
1525 switch (dev->device) {
1526 /* PCI IDs taken from drivers/net/e100.c */
1527 case 0x1029:
1528 case 0x1030 ... 0x1034:
1529 case 0x1038 ... 0x103E:
1530 case 0x1050 ... 0x1057:
1531 case 0x1059:
1532 case 0x1064 ... 0x106B:
1533 case 0x1091 ... 0x1095:
1534 case 0x1209:
1535 case 0x1229:
1536 case 0x2449:
1537 case 0x2459:
1538 case 0x245D:
1539 case 0x27DC:
1540 break;
1541 default:
1542 return;
1543 }
1544
1545 /*
1546 * Some firmware hands off the e100 with interrupts enabled,
1547 * which can cause a flood of interrupts if packets are
1548 * received before the driver attaches to the device. So
1549 * disable all e100 interrupts here. The driver will
1550 * re-enable them when it's ready.
1551 */
1552 pci_read_config_word(dev, PCI_COMMAND, &command);
1553 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1554
1555 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1556 return;
1557
1558 csr = ioremap(bar, 8);
1559 if (!csr) {
1560 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1561 pci_name(dev));
1562 return;
1563 }
1564
1565 cmd_hi = readb(csr + 3);
1566 if (cmd_hi == 0) {
1567 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1568 "enabled, disabling\n", pci_name(dev));
1569 writeb(1, csr + 3);
1570 }
1571
1572 iounmap(csr);
1573 }
1574 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1575
1576 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1577 {
1578 /* rev 1 ncr53c810 chips don't set the class at all which means
1579 * they don't get their resources remapped. Fix that here.
1580 */
1581
1582 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1583 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1584 dev->class = PCI_CLASS_STORAGE_SCSI;
1585 }
1586 }
1587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1588
1589 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1590 {
1591 while (f < end) {
1592 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1593 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1594 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1595 f->hook(dev);
1596 }
1597 f++;
1598 }
1599 }
1600
1601 extern struct pci_fixup __start_pci_fixups_early[];
1602 extern struct pci_fixup __end_pci_fixups_early[];
1603 extern struct pci_fixup __start_pci_fixups_header[];
1604 extern struct pci_fixup __end_pci_fixups_header[];
1605 extern struct pci_fixup __start_pci_fixups_final[];
1606 extern struct pci_fixup __end_pci_fixups_final[];
1607 extern struct pci_fixup __start_pci_fixups_enable[];
1608 extern struct pci_fixup __end_pci_fixups_enable[];
1609 extern struct pci_fixup __start_pci_fixups_resume[];
1610 extern struct pci_fixup __end_pci_fixups_resume[];
1611
1612
1613 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1614 {
1615 struct pci_fixup *start, *end;
1616
1617 switch(pass) {
1618 case pci_fixup_early:
1619 start = __start_pci_fixups_early;
1620 end = __end_pci_fixups_early;
1621 break;
1622
1623 case pci_fixup_header:
1624 start = __start_pci_fixups_header;
1625 end = __end_pci_fixups_header;
1626 break;
1627
1628 case pci_fixup_final:
1629 start = __start_pci_fixups_final;
1630 end = __end_pci_fixups_final;
1631 break;
1632
1633 case pci_fixup_enable:
1634 start = __start_pci_fixups_enable;
1635 end = __end_pci_fixups_enable;
1636 break;
1637
1638 case pci_fixup_resume:
1639 start = __start_pci_fixups_resume;
1640 end = __end_pci_fixups_resume;
1641 break;
1642
1643 default:
1644 /* stupid compiler warning, you would think with an enum... */
1645 return;
1646 }
1647 pci_do_fixups(dev, start, end);
1648 }
1649
1650 /* Enable 1k I/O space granularity on the Intel P64H2 */
1651 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1652 {
1653 u16 en1k;
1654 u8 io_base_lo, io_limit_lo;
1655 unsigned long base, limit;
1656 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1657
1658 pci_read_config_word(dev, 0x40, &en1k);
1659
1660 if (en1k & 0x200) {
1661 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1662
1663 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1664 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1665 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1666 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1667
1668 if (base <= limit) {
1669 res->start = base;
1670 res->end = limit + 0x3ff;
1671 }
1672 }
1673 }
1674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1675
1676 /* Under some circumstances, AER is not linked with extended capabilities.
1677 * Force it to be linked by setting the corresponding control bit in the
1678 * config space.
1679 */
1680 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1681 {
1682 uint8_t b;
1683 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1684 if (!(b & 0x20)) {
1685 pci_write_config_byte(dev, 0xf41, b | 0x20);
1686 printk(KERN_INFO
1687 "PCI: Linking AER extended capability on %s\n",
1688 pci_name(dev));
1689 }
1690 }
1691 }
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1693 quirk_nvidia_ck804_pcie_aer_ext_cap);
1694 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1695 quirk_nvidia_ck804_pcie_aer_ext_cap);
1696
1697 #ifdef CONFIG_PCI_MSI
1698 /* To disable MSI globally */
1699 int pci_msi_quirk;
1700
1701 /* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely
1702 * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1703 * some other busses controlled by the chipset even if Linux is not aware of it.
1704 * Instead of setting the flag on all busses in the machine, simply disable MSI
1705 * globally.
1706 */
1707 static void __init quirk_svw_msi(struct pci_dev *dev)
1708 {
1709 pci_msi_quirk = 1;
1710 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
1711 }
1712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi);
1713
1714 /* Disable MSI on chipsets that are known to not support it */
1715 static void __devinit quirk_disable_msi(struct pci_dev *dev)
1716 {
1717 if (dev->subordinate) {
1718 printk(KERN_WARNING "PCI: MSI quirk detected. "
1719 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1720 pci_name(dev));
1721 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1722 }
1723 }
1724 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1725
1726 /* Go through the list of Hypertransport capabilities and
1727 * return 1 if a HT MSI capability is found and enabled */
1728 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1729 {
1730 int pos, ttl = 48;
1731
1732 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1733 while (pos && ttl--) {
1734 u8 flags;
1735
1736 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1737 &flags) == 0)
1738 {
1739 printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n",
1740 flags & HT_MSI_FLAGS_ENABLE ?
1741 "enabled" : "disabled", pci_name(dev));
1742 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1743 }
1744
1745 pos = pci_find_next_ht_capability(dev, pos,
1746 HT_CAPTYPE_MSI_MAPPING);
1747 }
1748 return 0;
1749 }
1750
1751 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1752 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1753 {
1754 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1755 printk(KERN_WARNING "PCI: MSI quirk detected. "
1756 "MSI disabled on chipset %s.\n",
1757 pci_name(dev));
1758 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1759 }
1760 }
1761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1762 quirk_msi_ht_cap);
1763
1764 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1765 * MSI are supported if the MSI capability set in any of these mappings.
1766 */
1767 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1768 {
1769 struct pci_dev *pdev;
1770
1771 if (!dev->subordinate)
1772 return;
1773
1774 /* check HT MSI cap on this chipset and the root one.
1775 * a single one having MSI is enough to be sure that MSI are supported.
1776 */
1777 pdev = pci_get_slot(dev->bus, 0);
1778 if (!pdev)
1779 return;
1780 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1781 printk(KERN_WARNING "PCI: MSI quirk detected. "
1782 "MSI disabled on chipset %s.\n",
1783 pci_name(dev));
1784 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1785 }
1786 pci_dev_put(pdev);
1787 }
1788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1789 quirk_nvidia_ck804_msi_ht_cap);
1790 #endif /* CONFIG_PCI_MSI */
1791
1792 EXPORT_SYMBOL(pcie_mch_quirk);
1793 #ifdef CONFIG_HOTPLUG
1794 EXPORT_SYMBOL(pci_fixup_device);
1795 #endif
Linux kernel - Deliverables
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