2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
37 static void quirk_mmio_always_on(struct pci_dev
*dev
)
39 dev
->mmio_always_on
= 1;
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
42 PCI_CLASS_BRIDGE_HOST
, 8, quirk_mmio_always_on
);
44 /* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
48 static void quirk_mellanox_tavor(struct pci_dev
*dev
)
50 dev
->broken_parity_status
= 1; /* This device gives false positives */
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR
, quirk_mellanox_tavor
);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
, quirk_mellanox_tavor
);
55 /* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57 static void quirk_passive_release(struct pci_dev
*dev
)
59 struct pci_dev
*d
= NULL
;
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
65 pci_read_config_byte(d
, 0x82, &dlc
);
67 dev_info(&d
->dev
, "PIIX3: Enabling Passive Release\n");
69 pci_write_config_byte(d
, 0x82, dlc
);
73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
80 This appears to be BIOS not version dependent. So presumably there is a
83 static void quirk_isa_dma_hangs(struct pci_dev
*dev
)
85 if (!isa_dma_bridge_buggy
) {
86 isa_dma_bridge_buggy
= 1;
87 dev_info(&dev
->dev
, "Activating ISA DMA hang workarounds\n");
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
106 static void quirk_tigerpoint_bm_sts(struct pci_dev
*dev
)
111 pci_read_config_dword(dev
, 0x40, &pmbase
);
112 pmbase
= pmbase
& 0xff80;
116 dev_info(&dev
->dev
, FW_BUG
"TigerPoint LPC.BM_STS cleared\n");
120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_TGP_LPC
, quirk_tigerpoint_bm_sts
);
123 * Chipsets where PCI->PCI transfers vanish or hang
125 static void quirk_nopcipci(struct pci_dev
*dev
)
127 if ((pci_pci_problems
& PCIPCI_FAIL
) == 0) {
128 dev_info(&dev
->dev
, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems
|= PCIPCI_FAIL
;
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
135 static void quirk_nopciamd(struct pci_dev
*dev
)
138 pci_read_config_byte(dev
, 0x08, &rev
);
141 dev_info(&dev
->dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems
|= PCIAGP_FAIL
;
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
148 * Triton requires workarounds to be used by the drivers
150 static void quirk_triton(struct pci_dev
*dev
)
152 if ((pci_pci_problems
&PCIPCI_TRITON
) == 0) {
153 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems
|= PCIPCI_TRITON
;
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * and http://www.georgebreese.com/net/software/#PCI
167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
168 * the info on which Mr Breese based his work.
170 * Updated based on further information from the site and also on
171 * information provided by VIA
173 static void quirk_vialatency(struct pci_dev
*dev
)
177 /* Ok we have a potential problem chipset here. Now see if we have
178 a buggy southbridge */
180 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
183 /* Check for buggy part revisions */
184 if (p
->revision
< 0x40 || p
->revision
> 0x42)
187 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
188 if (p
== NULL
) /* No problem parts */
190 /* Check for buggy part revisions */
191 if (p
->revision
< 0x10 || p
->revision
> 0x12)
196 * Ok we have the problem. Now set the PCI master grant to
197 * occur every master grant. The apparent bug is that under high
198 * PCI load (quite common in Linux of course) you can get data
199 * loss when the CPU is held off the bus for 3 bus master requests
200 * This happens to include the IDE controllers....
202 * VIA only apply this fix when an SB Live! is present but under
203 * both Linux and Windows this isn't enough, and we have seen
204 * corruption without SB Live! but with things like 3 UDMA IDE
205 * controllers. So we ignore that bit of the VIA recommendation..
208 pci_read_config_byte(dev
, 0x76, &busarb
);
209 /* Set bit 4 and bi 5 of byte 76 to 0x01
210 "Master priority rotation on every PCI master grant */
213 pci_write_config_byte(dev
, 0x76, busarb
);
214 dev_info(&dev
->dev
, "Applying VIA southbridge workaround\n");
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
221 /* Must restore this on a resume from RAM */
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
227 * VIA Apollo VP3 needs ETBF on BT848/878
229 static void quirk_viaetbf(struct pci_dev
*dev
)
231 if ((pci_pci_problems
&PCIPCI_VIAETBF
) == 0) {
232 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
233 pci_pci_problems
|= PCIPCI_VIAETBF
;
236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
238 static void quirk_vsfx(struct pci_dev
*dev
)
240 if ((pci_pci_problems
&PCIPCI_VSFX
) == 0) {
241 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
242 pci_pci_problems
|= PCIPCI_VSFX
;
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
248 * Ali Magik requires workarounds to be used by the drivers
249 * that DMA to AGP space. Latency must be set to 0xA and triton
250 * workaround applied too
251 * [Info kindly provided by ALi]
253 static void quirk_alimagik(struct pci_dev
*dev
)
255 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
) == 0) {
256 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
257 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
264 * Natoma has some interesting boundary conditions with Zoran stuff
267 static void quirk_natoma(struct pci_dev
*dev
)
269 if ((pci_pci_problems
&PCIPCI_NATOMA
) == 0) {
270 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
271 pci_pci_problems
|= PCIPCI_NATOMA
;
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
282 * This chip can cause PCI parity errors if config register 0xA0 is read
283 * while DMAs are occurring.
285 static void quirk_citrine(struct pci_dev
*dev
)
287 dev
->cfg_size
= 0xA0;
289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
291 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
292 static void quirk_extend_bar_to_page(struct pci_dev
*dev
)
296 for (i
= 0; i
< PCI_STD_RESOURCE_END
; i
++) {
297 struct resource
*r
= &dev
->resource
[i
];
299 if (r
->flags
& IORESOURCE_MEM
&& resource_size(r
) < PAGE_SIZE
) {
300 r
->end
= PAGE_SIZE
- 1;
302 r
->flags
|= IORESOURCE_UNSET
;
303 dev_info(&dev
->dev
, "expanded BAR %d to page size: %pR\n",
308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, 0x034a, quirk_extend_bar_to_page
);
311 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
312 * If it's needed, re-allocate the region.
314 static void quirk_s3_64M(struct pci_dev
*dev
)
316 struct resource
*r
= &dev
->resource
[0];
318 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
319 r
->flags
|= IORESOURCE_UNSET
;
324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
328 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
329 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
330 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
331 * (which conflicts w/ BAR1's memory range).
333 static void quirk_cs5536_vsa(struct pci_dev
*dev
)
335 if (pci_resource_len(dev
, 0) != 8) {
336 struct resource
*res
= &dev
->resource
[0];
337 res
->end
= res
->start
+ 8 - 1;
338 dev_info(&dev
->dev
, "CS5536 ISA bridge bug detected (incorrect header); workaround applied\n");
341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, quirk_cs5536_vsa
);
343 static void quirk_io_region(struct pci_dev
*dev
, int port
,
344 unsigned size
, int nr
, const char *name
)
347 struct pci_bus_region bus_region
;
348 struct resource
*res
= dev
->resource
+ nr
;
350 pci_read_config_word(dev
, port
, ®ion
);
351 region
&= ~(size
- 1);
356 res
->name
= pci_name(dev
);
357 res
->flags
= IORESOURCE_IO
;
359 /* Convert from PCI bus to resource space */
360 bus_region
.start
= region
;
361 bus_region
.end
= region
+ size
- 1;
362 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
364 if (!pci_claim_resource(dev
, nr
))
365 dev_info(&dev
->dev
, "quirk: %pR claimed by %s\n", res
, name
);
369 * ATI Northbridge setups MCE the processor if you even
370 * read somewhere between 0x3b0->0x3bb or read 0x3d3
372 static void quirk_ati_exploding_mce(struct pci_dev
*dev
)
374 dev_info(&dev
->dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
375 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
376 request_region(0x3b0, 0x0C, "RadeonIGP");
377 request_region(0x3d3, 0x01, "RadeonIGP");
379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
382 * In the AMD NL platform, this device ([1022:7912]) has a class code of
383 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
385 * But the dwc3 driver is a more specific driver for this device, and we'd
386 * prefer to use it instead of xhci. To prevent xhci from claiming the
387 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
388 * defines as "USB device (not host controller)". The dwc3 driver can then
389 * claim it based on its Vendor and Device ID.
391 static void quirk_amd_nl_class(struct pci_dev
*pdev
)
394 * Use 'USB Device' (0x0c03fe) instead of PCI header provided
396 pdev
->class = 0x0c03fe;
398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_NL_USB
,
402 * Let's make the southbridge information explicit instead
403 * of having to worry about people probing the ACPI areas,
404 * for example.. (Yes, it happens, and if you read the wrong
405 * ACPI register it will put the machine to sleep with no
406 * way of waking it up again. Bummer).
408 * ALI M7101: Two IO regions pointed to by words at
409 * 0xE0 (64 bytes of ACPI registers)
410 * 0xE2 (32 bytes of SMB registers)
412 static void quirk_ali7101_acpi(struct pci_dev
*dev
)
414 quirk_io_region(dev
, 0xE0, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
415 quirk_io_region(dev
, 0xE2, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
419 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
422 u32 mask
, size
, base
;
424 pci_read_config_dword(dev
, port
, &devres
);
425 if ((devres
& enable
) != enable
)
427 mask
= (devres
>> 16) & 15;
428 base
= devres
& 0xffff;
431 unsigned bit
= size
>> 1;
432 if ((bit
& mask
) == bit
)
437 * For now we only print it out. Eventually we'll want to
438 * reserve it (at least if it's in the 0x1000+ range), but
439 * let's get enough confirmation reports first.
442 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
,
446 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
449 u32 mask
, size
, base
;
451 pci_read_config_dword(dev
, port
, &devres
);
452 if ((devres
& enable
) != enable
)
454 base
= devres
& 0xffff0000;
455 mask
= (devres
& 0x3f) << 16;
458 unsigned bit
= size
>> 1;
459 if ((bit
& mask
) == bit
)
464 * For now we only print it out. Eventually we'll want to
465 * reserve it, but let's get enough confirmation reports first.
468 dev_info(&dev
->dev
, "%s MMIO at %04x-%04x\n", name
, base
,
473 * PIIX4 ACPI: Two IO regions pointed to by longwords at
474 * 0x40 (64 bytes of ACPI registers)
475 * 0x90 (16 bytes of SMB registers)
476 * and a few strange programmable PIIX4 device resources.
478 static void quirk_piix4_acpi(struct pci_dev
*dev
)
482 quirk_io_region(dev
, 0x40, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
483 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
485 /* Device resource A has enables for some of the other ones */
486 pci_read_config_dword(dev
, 0x5c, &res_a
);
488 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
489 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
491 /* Device resource D is just bitfields for static resources */
493 /* Device 12 enabled? */
494 if (res_a
& (1 << 29)) {
495 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
496 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
498 /* Device 13 enabled? */
499 if (res_a
& (1 << 30)) {
500 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
501 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
503 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
504 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
509 #define ICH_PMBASE 0x40
510 #define ICH_ACPI_CNTL 0x44
511 #define ICH4_ACPI_EN 0x10
512 #define ICH6_ACPI_EN 0x80
513 #define ICH4_GPIOBASE 0x58
514 #define ICH4_GPIO_CNTL 0x5c
515 #define ICH4_GPIO_EN 0x10
516 #define ICH6_GPIOBASE 0x48
517 #define ICH6_GPIO_CNTL 0x4c
518 #define ICH6_GPIO_EN 0x10
521 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
522 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
523 * 0x58 (64 bytes of GPIO I/O space)
525 static void quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
530 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
531 * with low legacy (and fixed) ports. We don't know the decoding
532 * priority and can't tell whether the legacy device or the one created
533 * here is really at that address. This happens on boards with broken
537 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
538 if (enable
& ICH4_ACPI_EN
)
539 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
540 "ICH4 ACPI/GPIO/TCO");
542 pci_read_config_byte(dev
, ICH4_GPIO_CNTL
, &enable
);
543 if (enable
& ICH4_GPIO_EN
)
544 quirk_io_region(dev
, ICH4_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
558 static void ich6_lpc_acpi_gpio(struct pci_dev
*dev
)
562 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
563 if (enable
& ICH6_ACPI_EN
)
564 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
565 "ICH6 ACPI/GPIO/TCO");
567 pci_read_config_byte(dev
, ICH6_GPIO_CNTL
, &enable
);
568 if (enable
& ICH6_GPIO_EN
)
569 quirk_io_region(dev
, ICH6_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
573 static void ich6_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
, const char *name
, int dynsize
)
578 pci_read_config_dword(dev
, reg
, &val
);
586 * This is not correct. It is 16, 32 or 64 bytes depending on
587 * register D31:F0:ADh bits 5:4.
589 * But this gets us at least _part_ of it.
597 /* Just print it out for now. We should reserve it after more debugging */
598 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+size
-1);
601 static void quirk_ich6_lpc(struct pci_dev
*dev
)
603 /* Shared ACPI/GPIO decode with all ICH6+ */
604 ich6_lpc_acpi_gpio(dev
);
606 /* ICH6-specific generic IO decode */
607 ich6_lpc_generic_decode(dev
, 0x84, "LPC Generic IO decode 1", 0);
608 ich6_lpc_generic_decode(dev
, 0x88, "LPC Generic IO decode 2", 1);
610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc
);
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc
);
613 static void ich7_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
, const char *name
)
618 pci_read_config_dword(dev
, reg
, &val
);
625 * IO base in bits 15:2, mask in bits 23:18, both
629 mask
= (val
>> 16) & 0xfc;
632 /* Just print it out for now. We should reserve it after more debugging */
633 dev_info(&dev
->dev
, "%s PIO at %04x (mask %04x)\n", name
, base
, mask
);
636 /* ICH7-10 has the same common LPC generic IO decode registers */
637 static void quirk_ich7_lpc(struct pci_dev
*dev
)
639 /* We share the common ACPI/GPIO decode with ICH6 */
640 ich6_lpc_acpi_gpio(dev
);
642 /* And have 4 ICH7+ generic decodes */
643 ich7_lpc_generic_decode(dev
, 0x84, "ICH7 LPC Generic IO decode 1");
644 ich7_lpc_generic_decode(dev
, 0x88, "ICH7 LPC Generic IO decode 2");
645 ich7_lpc_generic_decode(dev
, 0x8c, "ICH7 LPC Generic IO decode 3");
646 ich7_lpc_generic_decode(dev
, 0x90, "ICH7 LPC Generic IO decode 4");
648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich7_lpc
);
649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich7_lpc
);
650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich7_lpc
);
651 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich7_lpc
);
652 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich7_lpc
);
653 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich7_lpc
);
654 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich7_lpc
);
655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich7_lpc
);
656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich7_lpc
);
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich7_lpc
);
658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich7_lpc
);
659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich7_lpc
);
660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_1
, quirk_ich7_lpc
);
663 * VIA ACPI: One IO region pointed to by longword at
664 * 0x48 or 0x20 (256 bytes of ACPI registers)
666 static void quirk_vt82c586_acpi(struct pci_dev
*dev
)
668 if (dev
->revision
& 0x10)
669 quirk_io_region(dev
, 0x48, 256, PCI_BRIDGE_RESOURCES
,
672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
675 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
676 * 0x48 (256 bytes of ACPI registers)
677 * 0x70 (128 bytes of hardware monitoring register)
678 * 0x90 (16 bytes of SMB registers)
680 static void quirk_vt82c686_acpi(struct pci_dev
*dev
)
682 quirk_vt82c586_acpi(dev
);
684 quirk_io_region(dev
, 0x70, 128, PCI_BRIDGE_RESOURCES
+1,
687 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+2, "vt82c686 SMB");
689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
692 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
693 * 0x88 (128 bytes of power management registers)
694 * 0xd0 (16 bytes of SMB registers)
696 static void quirk_vt8235_acpi(struct pci_dev
*dev
)
698 quirk_io_region(dev
, 0x88, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
699 quirk_io_region(dev
, 0xd0, 16, PCI_BRIDGE_RESOURCES
+1, "vt8235 SMB");
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
704 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
705 * Disable fast back-to-back on the secondary bus segment
707 static void quirk_xio2000a(struct pci_dev
*dev
)
709 struct pci_dev
*pdev
;
712 dev_warn(&dev
->dev
, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
713 list_for_each_entry(pdev
, &dev
->subordinate
->devices
, bus_list
) {
714 pci_read_config_word(pdev
, PCI_COMMAND
, &command
);
715 if (command
& PCI_COMMAND_FAST_BACK
)
716 pci_write_config_word(pdev
, PCI_COMMAND
, command
& ~PCI_COMMAND_FAST_BACK
);
719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_XIO2000A
,
722 #ifdef CONFIG_X86_IO_APIC
724 #include <asm/io_apic.h>
727 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
728 * devices to the external APIC.
730 * TODO: When we have device-specific interrupt routers,
731 * this code will go away from quirks.
733 static void quirk_via_ioapic(struct pci_dev
*dev
)
738 tmp
= 0; /* nothing routed to external APIC */
740 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
742 dev_info(&dev
->dev
, "%sbling VIA external APIC routing\n",
743 tmp
== 0 ? "Disa" : "Ena");
745 /* Offset 0x58: External APIC IRQ output control */
746 pci_write_config_byte(dev
, 0x58, tmp
);
748 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
752 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
753 * This leads to doubled level interrupt rates.
754 * Set this bit to get rid of cycle wastage.
755 * Otherwise uncritical.
757 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
760 #define BYPASS_APIC_DEASSERT 8
762 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
763 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
764 dev_info(&dev
->dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
765 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
772 * The AMD io apic can hang the box when an apic irq is masked.
773 * We check all revs >= B0 (yet not in the pre production!) as the bug
774 * is currently marked NoFix
776 * We have multiple reports of hangs with this chipset that went away with
777 * noapic specified. For the moment we assume it's the erratum. We may be wrong
778 * of course. However the advice is demonstrably good even if so..
780 static void quirk_amd_ioapic(struct pci_dev
*dev
)
782 if (dev
->revision
>= 0x02) {
783 dev_warn(&dev
->dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
784 dev_warn(&dev
->dev
, " : booting with the \"noapic\" option\n");
787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
789 static void quirk_ioapic_rmw(struct pci_dev
*dev
)
791 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
795 #endif /* CONFIG_X86_IO_APIC */
798 * Some settings of MMRBC can lead to data corruption so block changes.
799 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
801 static void quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
803 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
804 dev_info(&dev
->dev
, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
806 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
809 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
812 * FIXME: it is questionable that quirk_via_acpi
813 * is needed. It shows up as an ISA bridge, and does not
814 * support the PCI_INTERRUPT_LINE register at all. Therefore
815 * it seems like setting the pci_dev's 'irq' to the
816 * value of the ACPI SCI interrupt is only done for convenience.
819 static void quirk_via_acpi(struct pci_dev
*d
)
822 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
825 pci_read_config_byte(d
, 0x42, &irq
);
827 if (irq
&& (irq
!= 2))
830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
835 * VIA bridges which have VLink
838 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
840 static void quirk_via_bridge(struct pci_dev
*dev
)
842 /* See what bridge we have and find the device ranges */
843 switch (dev
->device
) {
844 case PCI_DEVICE_ID_VIA_82C686
:
845 /* The VT82C686 is special, it attaches to PCI and can have
846 any device number. All its subdevices are functions of
847 that single device. */
848 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
849 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
851 case PCI_DEVICE_ID_VIA_8237
:
852 case PCI_DEVICE_ID_VIA_8237A
:
853 via_vlink_dev_lo
= 15;
855 case PCI_DEVICE_ID_VIA_8235
:
856 via_vlink_dev_lo
= 16;
858 case PCI_DEVICE_ID_VIA_8231
:
859 case PCI_DEVICE_ID_VIA_8233_0
:
860 case PCI_DEVICE_ID_VIA_8233A
:
861 case PCI_DEVICE_ID_VIA_8233C_0
:
862 via_vlink_dev_lo
= 17;
866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
876 * quirk_via_vlink - VIA VLink IRQ number update
879 * If the device we are dealing with is on a PIC IRQ we need to
880 * ensure that the IRQ line register which usually is not relevant
881 * for PCI cards, is actually written so that interrupts get sent
882 * to the right place.
883 * We only do this on systems where a VIA south bridge was detected,
884 * and only for VIA devices on the motherboard (see quirk_via_bridge
888 static void quirk_via_vlink(struct pci_dev
*dev
)
892 /* Check if we have VLink at all */
893 if (via_vlink_dev_lo
== -1)
898 /* Don't quirk interrupts outside the legacy IRQ range */
899 if (!new_irq
|| new_irq
> 15)
902 /* Internal device ? */
903 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
904 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
907 /* This is an internal VLink device on a PIC interrupt. The BIOS
908 ought to have set this but may not have, so we redo it */
910 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
911 if (new_irq
!= irq
) {
912 dev_info(&dev
->dev
, "VIA VLink IRQ fixup, from %d to %d\n",
914 udelay(15); /* unknown if delay really needed */
915 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
918 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
921 * VIA VT82C598 has its device ID settable and many BIOSes
922 * set it to the ID of VT82C597 for backward compatibility.
923 * We need to switch it off to be able to recognize the real
926 static void quirk_vt82c598_id(struct pci_dev
*dev
)
928 pci_write_config_byte(dev
, 0xfc, 0);
929 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
931 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
934 * CardBus controllers have a legacy base address that enables them
935 * to respond as i82365 pcmcia controllers. We don't want them to
936 * do this even if the Linux CardBus driver is not loaded, because
937 * the Linux i82365 driver does not (and should not) handle CardBus.
939 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
941 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
943 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
944 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
945 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
946 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
949 * Following the PCI ordering rules is optional on the AMD762. I'm not
950 * sure what the designers were smoking but let's not inhale...
952 * To be fair to AMD, it follows the spec by default, its BIOS people
955 static void quirk_amd_ordering(struct pci_dev
*dev
)
958 pci_read_config_dword(dev
, 0x4C, &pcic
);
959 if ((pcic
& 6) != 6) {
961 dev_warn(&dev
->dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
962 pci_write_config_dword(dev
, 0x4C, pcic
);
963 pci_read_config_dword(dev
, 0x84, &pcic
);
964 pcic
|= (1 << 23); /* Required in this mode */
965 pci_write_config_dword(dev
, 0x84, pcic
);
968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
969 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
972 * DreamWorks provided workaround for Dunord I-3000 problem
974 * This card decodes and responds to addresses not apparently
975 * assigned to it. We force a larger allocation to ensure that
976 * nothing gets put too close to it.
978 static void quirk_dunord(struct pci_dev
*dev
)
980 struct resource
*r
= &dev
->resource
[1];
982 r
->flags
|= IORESOURCE_UNSET
;
986 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
989 * i82380FB mobile docking controller: its PCI-to-PCI bridge
990 * is subtractive decoding (transparent), and does indicate this
991 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
994 static void quirk_transparent_bridge(struct pci_dev
*dev
)
996 dev
->transparent
= 1;
998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
1002 * Common misconfiguration of the MediaGX/Geode PCI master that will
1003 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1004 * datasheets found at http://www.national.com/analog for info on what
1005 * these bits do. <christer@weinigel.se>
1007 static void quirk_mediagx_master(struct pci_dev
*dev
)
1011 pci_read_config_byte(dev
, 0x41, ®
);
1014 dev_info(&dev
->dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1016 pci_write_config_byte(dev
, 0x41, reg
);
1019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1020 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1023 * Ensure C0 rev restreaming is off. This is normally done by
1024 * the BIOS but in the odd case it is not the results are corruption
1025 * hence the presence of a Linux check
1027 static void quirk_disable_pxb(struct pci_dev
*pdev
)
1031 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
1033 pci_read_config_word(pdev
, 0x40, &config
);
1034 if (config
& (1<<6)) {
1036 pci_write_config_word(pdev
, 0x40, config
);
1037 dev_info(&pdev
->dev
, "C0 revision 450NX. Disabling PCI restreaming\n");
1040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1041 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1043 static void quirk_amd_ide_mode(struct pci_dev
*pdev
)
1045 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1048 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
1050 pci_read_config_byte(pdev
, 0x40, &tmp
);
1051 pci_write_config_byte(pdev
, 0x40, tmp
|1);
1052 pci_write_config_byte(pdev
, 0x9, 1);
1053 pci_write_config_byte(pdev
, 0xa, 6);
1054 pci_write_config_byte(pdev
, 0x40, tmp
);
1056 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
1057 dev_info(&pdev
->dev
, "set SATA to AHCI mode\n");
1060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1061 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1063 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1065 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1067 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1070 * Serverworks CSB5 IDE does not fully support native mode
1072 static void quirk_svwks_csb5ide(struct pci_dev
*pdev
)
1075 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1079 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1080 /* PCI layer will sort out resources */
1083 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
1086 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1088 static void quirk_ide_samemode(struct pci_dev
*pdev
)
1092 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1094 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
1095 dev_info(&pdev
->dev
, "IDE mode mismatch; forcing legacy mode\n");
1098 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1101 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
1104 * Some ATA devices break if put into D3
1107 static void quirk_no_ata_d3(struct pci_dev
*pdev
)
1109 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
1111 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1112 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
,
1113 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1114 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
1115 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1116 /* ALi loses some register settings that we cannot then restore */
1117 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
,
1118 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1119 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1120 occur when mode detecting */
1121 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
,
1122 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1124 /* This was originally an Alpha specific thing, but it really fits here.
1125 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1127 static void quirk_eisa_bridge(struct pci_dev
*dev
)
1129 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
1131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
1135 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1136 * is not activated. The myth is that Asus said that they do not want the
1137 * users to be irritated by just another PCI Device in the Win98 device
1138 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1139 * package 2.7.0 for details)
1141 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1142 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1143 * becomes necessary to do this tweak in two steps -- the chosen trigger
1144 * is either the Host bridge (preferred) or on-board VGA controller.
1146 * Note that we used to unhide the SMBus that way on Toshiba laptops
1147 * (Satellite A40 and Tecra M2) but then found that the thermal management
1148 * was done by SMM code, which could cause unsynchronized concurrent
1149 * accesses to the SMBus registers, with potentially bad effects. Thus you
1150 * should be very careful when adding new entries: if SMM is accessing the
1151 * Intel SMBus, this is a very good reason to leave it hidden.
1153 * Likewise, many recent laptops use ACPI for thermal management. If the
1154 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1155 * natively, and keeping the SMBus hidden is the right thing to do. If you
1156 * are about to add an entry in the table below, please first disassemble
1157 * the DSDT and double-check that there is no code accessing the SMBus.
1159 static int asus_hides_smbus
;
1161 static void asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
1163 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1164 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
1165 switch (dev
->subsystem_device
) {
1166 case 0x8025: /* P4B-LX */
1167 case 0x8070: /* P4B */
1168 case 0x8088: /* P4B533 */
1169 case 0x1626: /* L3C notebook */
1170 asus_hides_smbus
= 1;
1172 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
1173 switch (dev
->subsystem_device
) {
1174 case 0x80b1: /* P4GE-V */
1175 case 0x80b2: /* P4PE */
1176 case 0x8093: /* P4B533-V */
1177 asus_hides_smbus
= 1;
1179 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
1180 switch (dev
->subsystem_device
) {
1181 case 0x8030: /* P4T533 */
1182 asus_hides_smbus
= 1;
1184 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1185 switch (dev
->subsystem_device
) {
1186 case 0x8070: /* P4G8X Deluxe */
1187 asus_hides_smbus
= 1;
1189 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1190 switch (dev
->subsystem_device
) {
1191 case 0x80c9: /* PU-DLS */
1192 asus_hides_smbus
= 1;
1194 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1195 switch (dev
->subsystem_device
) {
1196 case 0x1751: /* M2N notebook */
1197 case 0x1821: /* M5N notebook */
1198 case 0x1897: /* A6L notebook */
1199 asus_hides_smbus
= 1;
1201 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1202 switch (dev
->subsystem_device
) {
1203 case 0x184b: /* W1N notebook */
1204 case 0x186a: /* M6Ne notebook */
1205 asus_hides_smbus
= 1;
1207 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1208 switch (dev
->subsystem_device
) {
1209 case 0x80f2: /* P4P800-X */
1210 asus_hides_smbus
= 1;
1212 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1213 switch (dev
->subsystem_device
) {
1214 case 0x1882: /* M6V notebook */
1215 case 0x1977: /* A6VA notebook */
1216 asus_hides_smbus
= 1;
1218 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1219 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1220 switch (dev
->subsystem_device
) {
1221 case 0x088C: /* HP Compaq nc8000 */
1222 case 0x0890: /* HP Compaq nc6000 */
1223 asus_hides_smbus
= 1;
1225 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1226 switch (dev
->subsystem_device
) {
1227 case 0x12bc: /* HP D330L */
1228 case 0x12bd: /* HP D530 */
1229 case 0x006a: /* HP Compaq nx9500 */
1230 asus_hides_smbus
= 1;
1232 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1233 switch (dev
->subsystem_device
) {
1234 case 0x12bf: /* HP xw4100 */
1235 asus_hides_smbus
= 1;
1237 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1238 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1239 switch (dev
->subsystem_device
) {
1240 case 0xC00C: /* Samsung P35 notebook */
1241 asus_hides_smbus
= 1;
1243 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1244 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1245 switch (dev
->subsystem_device
) {
1246 case 0x0058: /* Compaq Evo N620c */
1247 asus_hides_smbus
= 1;
1249 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1250 switch (dev
->subsystem_device
) {
1251 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1252 /* Motherboard doesn't have Host bridge
1253 * subvendor/subdevice IDs, therefore checking
1254 * its on-board VGA controller */
1255 asus_hides_smbus
= 1;
1257 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82801DB_2
)
1258 switch (dev
->subsystem_device
) {
1259 case 0x00b8: /* Compaq Evo D510 CMT */
1260 case 0x00b9: /* Compaq Evo D510 SFF */
1261 case 0x00ba: /* Compaq Evo D510 USDT */
1262 /* Motherboard doesn't have Host bridge
1263 * subvendor/subdevice IDs and on-board VGA
1264 * controller is disabled if an AGP card is
1265 * inserted, therefore checking USB UHCI
1267 asus_hides_smbus
= 1;
1269 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1270 switch (dev
->subsystem_device
) {
1271 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1272 /* Motherboard doesn't have host bridge
1273 * subvendor/subdevice IDs, therefore checking
1274 * its on-board VGA controller */
1275 asus_hides_smbus
= 1;
1279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_2
, asus_hides_smbus_hostbridge
);
1292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1294 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1298 if (likely(!asus_hides_smbus
))
1301 pci_read_config_word(dev
, 0xF2, &val
);
1303 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1304 pci_read_config_word(dev
, 0xF2, &val
);
1306 dev_info(&dev
->dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1309 dev_info(&dev
->dev
, "Enabled i801 SMBus device\n");
1312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1319 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1320 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1321 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1322 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1323 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1324 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1325 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1327 /* It appears we just have one such device. If not, we have a warning */
1328 static void __iomem
*asus_rcba_base
;
1329 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1333 if (likely(!asus_hides_smbus
))
1335 WARN_ON(asus_rcba_base
);
1337 pci_read_config_dword(dev
, 0xF0, &rcba
);
1338 /* use bits 31:14, 16 kB aligned */
1339 asus_rcba_base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000);
1340 if (asus_rcba_base
== NULL
)
1344 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1348 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1350 /* read the Function Disable register, dword mode only */
1351 val
= readl(asus_rcba_base
+ 0x3418);
1352 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418); /* enable the SMBus device */
1355 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1357 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1359 iounmap(asus_rcba_base
);
1360 asus_rcba_base
= NULL
;
1361 dev_info(&dev
->dev
, "Enabled ICH6/i801 SMBus device\n");
1364 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1366 asus_hides_smbus_lpc_ich6_suspend(dev
);
1367 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1368 asus_hides_smbus_lpc_ich6_resume(dev
);
1370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1371 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1372 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1376 * SiS 96x south bridge: BIOS typically hides SMBus device...
1378 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1381 pci_read_config_byte(dev
, 0x77, &val
);
1383 dev_info(&dev
->dev
, "Enabling SiS 96x SMBus\n");
1384 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1389 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1390 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1391 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1392 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1393 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1394 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1397 * ... This is further complicated by the fact that some SiS96x south
1398 * bridges pretend to be 85C503/5513 instead. In that case see if we
1399 * spotted a compatible north bridge to make sure.
1400 * (pci_find_device doesn't work yet)
1402 * We can also enable the sis96x bit in the discovery register..
1404 #define SIS_DETECT_REGISTER 0x40
1406 static void quirk_sis_503(struct pci_dev
*dev
)
1411 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1412 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1413 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1414 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1415 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1420 * Ok, it now shows up as a 96x.. run the 96x quirk by
1421 * hand in case it has already been processed.
1422 * (depends on link order, which is apparently not guaranteed)
1424 dev
->device
= devid
;
1425 quirk_sis_96x_smbus(dev
);
1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1432 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1433 * and MC97 modem controller are disabled when a second PCI soundcard is
1434 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1437 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1440 int asus_hides_ac97
= 0;
1442 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1443 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1444 asus_hides_ac97
= 1;
1447 if (!asus_hides_ac97
)
1450 pci_read_config_byte(dev
, 0x50, &val
);
1452 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1453 pci_read_config_byte(dev
, 0x50, &val
);
1455 dev_info(&dev
->dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1458 dev_info(&dev
->dev
, "Enabled onboard AC97/MC97 devices\n");
1461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1462 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1464 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1467 * If we are using libata we can drive this chip properly but must
1468 * do this early on to make the additional device appear during
1471 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1473 u32 conf1
, conf5
, class;
1476 /* Only poke fn 0 */
1477 if (PCI_FUNC(pdev
->devfn
))
1480 pci_read_config_dword(pdev
, 0x40, &conf1
);
1481 pci_read_config_dword(pdev
, 0x80, &conf5
);
1483 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1484 conf5
&= ~(1 << 24); /* Clear bit 24 */
1486 switch (pdev
->device
) {
1487 case PCI_DEVICE_ID_JMICRON_JMB360
: /* SATA single port */
1488 case PCI_DEVICE_ID_JMICRON_JMB362
: /* SATA dual ports */
1489 case PCI_DEVICE_ID_JMICRON_JMB364
: /* SATA dual ports */
1490 /* The controller should be in single function ahci mode */
1491 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1494 case PCI_DEVICE_ID_JMICRON_JMB365
:
1495 case PCI_DEVICE_ID_JMICRON_JMB366
:
1496 /* Redirect IDE second PATA port to the right spot */
1499 case PCI_DEVICE_ID_JMICRON_JMB361
:
1500 case PCI_DEVICE_ID_JMICRON_JMB363
:
1501 case PCI_DEVICE_ID_JMICRON_JMB369
:
1502 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1503 /* Set the class codes correctly and then direct IDE 0 */
1504 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1507 case PCI_DEVICE_ID_JMICRON_JMB368
:
1508 /* The controller should be in single function IDE mode */
1509 conf1
|= 0x00C00000; /* Set 22, 23 */
1513 pci_write_config_dword(pdev
, 0x40, conf1
);
1514 pci_write_config_dword(pdev
, 0x80, conf5
);
1516 /* Update pdev accordingly */
1517 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1518 pdev
->hdr_type
= hdr
& 0x7f;
1519 pdev
->multifunction
= !!(hdr
& 0x80);
1521 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1522 pdev
->class = class >> 8;
1524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1525 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1526 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1527 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1528 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1529 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1530 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1531 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1532 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1534 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1535 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1536 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1537 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1538 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1539 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1540 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1541 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1545 #ifdef CONFIG_X86_IO_APIC
1546 static void quirk_alder_ioapic(struct pci_dev
*pdev
)
1550 if ((pdev
->class >> 8) != 0xff00)
1553 /* the first BAR is the location of the IO APIC...we must
1554 * not touch this (and it's already covered by the fixmap), so
1555 * forcibly insert it into the resource tree */
1556 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1557 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1559 /* The next five BARs all seem to be rubbish, so just clean
1561 for (i
= 1; i
< 6; i
++)
1562 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1567 static void quirk_pcie_mch(struct pci_dev
*pdev
)
1572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1578 * It's possible for the MSI to get corrupted if shpc and acpi
1579 * are used together on certain PXH-based systems.
1581 static void quirk_pcie_pxh(struct pci_dev
*dev
)
1585 dev_warn(&dev
->dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1587 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1588 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1589 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1590 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1591 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1594 * Some Intel PCI Express chipsets have trouble with downstream
1595 * device power management.
1597 static void quirk_intel_pcie_pm(struct pci_dev
*dev
)
1599 pci_pm_d3_delay
= 120;
1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1625 #ifdef CONFIG_X86_IO_APIC
1627 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1628 * remap the original interrupt in the linux kernel to the boot interrupt, so
1629 * that a PCI device's interrupt handler is installed on the boot interrupt
1632 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev
*dev
)
1634 if (noioapicquirk
|| noioapicreroute
)
1637 dev
->irq_reroute_variant
= INTEL_IRQ_REROUTE_VARIANT
;
1638 dev_info(&dev
->dev
, "rerouting interrupts for [%04x:%04x]\n",
1639 dev
->vendor
, dev
->device
);
1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1649 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1650 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1651 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1652 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1653 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1654 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1655 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1656 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1659 * On some chipsets we can disable the generation of legacy INTx boot
1664 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1665 * 300641-004US, section 5.7.3.
1667 #define INTEL_6300_IOAPIC_ABAR 0x40
1668 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1670 static void quirk_disable_intel_boot_interrupt(struct pci_dev
*dev
)
1672 u16 pci_config_word
;
1677 pci_read_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, &pci_config_word
);
1678 pci_config_word
|= INTEL_6300_DISABLE_BOOT_IRQ
;
1679 pci_write_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, pci_config_word
);
1681 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1682 dev
->vendor
, dev
->device
);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1685 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1688 * disable boot interrupts on HT-1000
1690 #define BC_HT1000_FEATURE_REG 0x64
1691 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1692 #define BC_HT1000_MAP_IDX 0xC00
1693 #define BC_HT1000_MAP_DATA 0xC01
1695 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev
*dev
)
1697 u32 pci_config_dword
;
1703 pci_read_config_dword(dev
, BC_HT1000_FEATURE_REG
, &pci_config_dword
);
1704 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
|
1705 BC_HT1000_PIC_REGS_ENABLE
);
1707 for (irq
= 0x10; irq
< 0x10 + 32; irq
++) {
1708 outb(irq
, BC_HT1000_MAP_IDX
);
1709 outb(0x00, BC_HT1000_MAP_DATA
);
1712 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
);
1714 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1715 dev
->vendor
, dev
->device
);
1717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1718 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1721 * disable boot interrupts on AMD and ATI chipsets
1724 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1725 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1726 * (due to an erratum).
1728 #define AMD_813X_MISC 0x40
1729 #define AMD_813X_NOIOAMODE (1<<0)
1730 #define AMD_813X_REV_B1 0x12
1731 #define AMD_813X_REV_B2 0x13
1733 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev
*dev
)
1735 u32 pci_config_dword
;
1739 if ((dev
->revision
== AMD_813X_REV_B1
) ||
1740 (dev
->revision
== AMD_813X_REV_B2
))
1743 pci_read_config_dword(dev
, AMD_813X_MISC
, &pci_config_dword
);
1744 pci_config_dword
&= ~AMD_813X_NOIOAMODE
;
1745 pci_write_config_dword(dev
, AMD_813X_MISC
, pci_config_dword
);
1747 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1748 dev
->vendor
, dev
->device
);
1750 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1751 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1753 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1755 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1757 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev
*dev
)
1759 u16 pci_config_word
;
1764 pci_read_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, &pci_config_word
);
1765 if (!pci_config_word
) {
1766 dev_info(&dev
->dev
, "boot interrupts on device [%04x:%04x] already disabled\n",
1767 dev
->vendor
, dev
->device
);
1770 pci_write_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, 0);
1771 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1772 dev
->vendor
, dev
->device
);
1774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
1775 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
1776 #endif /* CONFIG_X86_IO_APIC */
1779 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1780 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1781 * Re-allocate the region if needed...
1783 static void quirk_tc86c001_ide(struct pci_dev
*dev
)
1785 struct resource
*r
= &dev
->resource
[0];
1787 if (r
->start
& 0x8) {
1788 r
->flags
|= IORESOURCE_UNSET
;
1793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
1794 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
1795 quirk_tc86c001_ide
);
1798 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1799 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1800 * being read correctly if bit 7 of the base address is set.
1801 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1802 * Re-allocate the regions to a 256-byte boundary if necessary.
1804 static void quirk_plx_pci9050(struct pci_dev
*dev
)
1808 /* Fixed in revision 2 (PCI 9052). */
1809 if (dev
->revision
>= 2)
1811 for (bar
= 0; bar
<= 1; bar
++)
1812 if (pci_resource_len(dev
, bar
) == 0x80 &&
1813 (pci_resource_start(dev
, bar
) & 0x80)) {
1814 struct resource
*r
= &dev
->resource
[bar
];
1815 dev_info(&dev
->dev
, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1817 r
->flags
|= IORESOURCE_UNSET
;
1822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1825 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1826 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1827 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1828 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1830 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1833 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050
);
1834 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050
);
1836 static void quirk_netmos(struct pci_dev
*dev
)
1838 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1839 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1842 * These Netmos parts are multiport serial devices with optional
1843 * parallel ports. Even when parallel ports are present, they
1844 * are identified as class SERIAL, which means the serial driver
1845 * will claim them. To prevent this, mark them as class OTHER.
1846 * These combo devices should be claimed by parport_serial.
1848 * The subdevice ID is of the form 0x00PS, where <P> is the number
1849 * of parallel ports and <S> is the number of serial ports.
1851 switch (dev
->device
) {
1852 case PCI_DEVICE_ID_NETMOS_9835
:
1853 /* Well, this rule doesn't hold for the following 9835 device */
1854 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
1855 dev
->subsystem_device
== 0x0299)
1857 case PCI_DEVICE_ID_NETMOS_9735
:
1858 case PCI_DEVICE_ID_NETMOS_9745
:
1859 case PCI_DEVICE_ID_NETMOS_9845
:
1860 case PCI_DEVICE_ID_NETMOS_9855
:
1862 dev_info(&dev
->dev
, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1863 dev
->device
, num_parallel
, num_serial
);
1864 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1865 (dev
->class & 0xff);
1869 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
,
1870 PCI_CLASS_COMMUNICATION_SERIAL
, 8, quirk_netmos
);
1872 static void quirk_e100_interrupt(struct pci_dev
*dev
)
1878 switch (dev
->device
) {
1879 /* PCI IDs taken from drivers/net/e100.c */
1881 case 0x1030 ... 0x1034:
1882 case 0x1038 ... 0x103E:
1883 case 0x1050 ... 0x1057:
1885 case 0x1064 ... 0x106B:
1886 case 0x1091 ... 0x1095:
1899 * Some firmware hands off the e100 with interrupts enabled,
1900 * which can cause a flood of interrupts if packets are
1901 * received before the driver attaches to the device. So
1902 * disable all e100 interrupts here. The driver will
1903 * re-enable them when it's ready.
1905 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1907 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
1911 * Check that the device is in the D0 power state. If it's not,
1912 * there is no point to look any further.
1915 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1916 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
1920 /* Convert from PCI bus to resource space. */
1921 csr
= ioremap(pci_resource_start(dev
, 0), 8);
1923 dev_warn(&dev
->dev
, "Can't map e100 registers\n");
1927 cmd_hi
= readb(csr
+ 3);
1929 dev_warn(&dev
->dev
, "Firmware left e100 interrupts enabled; disabling\n");
1935 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
1936 PCI_CLASS_NETWORK_ETHERNET
, 8, quirk_e100_interrupt
);
1939 * The 82575 and 82598 may experience data corruption issues when transitioning
1940 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1942 static void quirk_disable_aspm_l0s(struct pci_dev
*dev
)
1944 dev_info(&dev
->dev
, "Disabling L0s\n");
1945 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
);
1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a7, quirk_disable_aspm_l0s
);
1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a9, quirk_disable_aspm_l0s
);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10b6, quirk_disable_aspm_l0s
);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c6, quirk_disable_aspm_l0s
);
1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c7, quirk_disable_aspm_l0s
);
1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c8, quirk_disable_aspm_l0s
);
1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10d6, quirk_disable_aspm_l0s
);
1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10db, quirk_disable_aspm_l0s
);
1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10dd, quirk_disable_aspm_l0s
);
1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10e1, quirk_disable_aspm_l0s
);
1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10ec, quirk_disable_aspm_l0s
);
1958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f1, quirk_disable_aspm_l0s
);
1959 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f4, quirk_disable_aspm_l0s
);
1960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1508, quirk_disable_aspm_l0s
);
1962 static void fixup_rev1_53c810(struct pci_dev
*dev
)
1964 /* rev 1 ncr53c810 chips don't set the class at all which means
1965 * they don't get their resources remapped. Fix that here.
1968 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1969 dev_info(&dev
->dev
, "NCR 53c810 rev 1 detected; setting PCI class\n");
1970 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1973 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1975 /* Enable 1k I/O space granularity on the Intel P64H2 */
1976 static void quirk_p64h2_1k_io(struct pci_dev
*dev
)
1980 pci_read_config_word(dev
, 0x40, &en1k
);
1983 dev_info(&dev
->dev
, "Enable I/O Space to 1KB granularity\n");
1984 dev
->io_window_1k
= 1;
1987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
1989 /* Under some circumstances, AER is not linked with extended capabilities.
1990 * Force it to be linked by setting the corresponding control bit in the
1993 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
1996 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
1998 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
1999 dev_info(&dev
->dev
, "Linking AER extended capability\n");
2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2004 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2005 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2006 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2008 static void quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
2011 * Disable PCI Bus Parking and PCI Master read caching on CX700
2012 * which causes unspecified timing errors with a VT6212L on the PCI
2013 * bus leading to USB2.0 packet loss.
2015 * This quirk is only enabled if a second (on the external PCI bus)
2016 * VT6212L is found -- the CX700 core itself also contains a USB
2017 * host controller with the same PCI ID as the VT6212L.
2020 /* Count VT6212L instances */
2021 struct pci_dev
*p
= pci_get_device(PCI_VENDOR_ID_VIA
,
2022 PCI_DEVICE_ID_VIA_8235_USB_2
, NULL
);
2025 /* p should contain the first (internal) VT6212L -- see if we have
2026 an external one by searching again */
2027 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235_USB_2
, p
);
2032 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
2034 /* Turn off PCI Bus Parking */
2035 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
2037 dev_info(&dev
->dev
, "Disabling VIA CX700 PCI parking\n");
2041 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
2043 /* Turn off PCI Master read caching */
2044 pci_write_config_byte(dev
, 0x72, 0x0);
2046 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2047 pci_write_config_byte(dev
, 0x75, 0x1);
2049 /* Disable "Read FIFO Timer" */
2050 pci_write_config_byte(dev
, 0x77, 0x0);
2052 dev_info(&dev
->dev
, "Disabling VIA CX700 PCI caching\n");
2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
2059 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2060 * VPD end tag will hang the device. This problem was initially
2061 * observed when a vpd entry was created in sysfs
2062 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2063 * will dump 32k of data. Reading a full 32k will cause an access
2064 * beyond the VPD end tag causing the device to hang. Once the device
2065 * is hung, the bnx2 driver will not be able to reset the device.
2066 * We believe that it is legal to read beyond the end tag and
2067 * therefore the solution is to limit the read/write length.
2069 static void quirk_brcm_570x_limit_vpd(struct pci_dev
*dev
)
2072 * Only disable the VPD capability for 5706, 5706S, 5708,
2073 * 5708S and 5709 rev. A
2075 if ((dev
->device
== PCI_DEVICE_ID_NX2_5706
) ||
2076 (dev
->device
== PCI_DEVICE_ID_NX2_5706S
) ||
2077 (dev
->device
== PCI_DEVICE_ID_NX2_5708
) ||
2078 (dev
->device
== PCI_DEVICE_ID_NX2_5708S
) ||
2079 ((dev
->device
== PCI_DEVICE_ID_NX2_5709
) &&
2080 (dev
->revision
& 0xf0) == 0x0)) {
2082 dev
->vpd
->len
= 0x80;
2086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2087 PCI_DEVICE_ID_NX2_5706
,
2088 quirk_brcm_570x_limit_vpd
);
2089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2090 PCI_DEVICE_ID_NX2_5706S
,
2091 quirk_brcm_570x_limit_vpd
);
2092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2093 PCI_DEVICE_ID_NX2_5708
,
2094 quirk_brcm_570x_limit_vpd
);
2095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2096 PCI_DEVICE_ID_NX2_5708S
,
2097 quirk_brcm_570x_limit_vpd
);
2098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2099 PCI_DEVICE_ID_NX2_5709
,
2100 quirk_brcm_570x_limit_vpd
);
2101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2102 PCI_DEVICE_ID_NX2_5709S
,
2103 quirk_brcm_570x_limit_vpd
);
2105 static void quirk_brcm_5719_limit_mrrs(struct pci_dev
*dev
)
2109 pci_read_config_dword(dev
, 0xf4, &rev
);
2111 /* Only CAP the MRRS if the device is a 5719 A0 */
2112 if (rev
== 0x05719000) {
2113 int readrq
= pcie_get_readrq(dev
);
2115 pcie_set_readrq(dev
, 2048);
2119 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM
,
2120 PCI_DEVICE_ID_TIGON3_5719
,
2121 quirk_brcm_5719_limit_mrrs
);
2123 /* Originally in EDAC sources for i82875P:
2124 * Intel tells BIOS developers to hide device 6 which
2125 * configures the overflow device access containing
2126 * the DRBs - this is where we expose device 6.
2127 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2129 static void quirk_unhide_mch_dev6(struct pci_dev
*dev
)
2133 if (pci_read_config_byte(dev
, 0xF4, ®
) == 0 && !(reg
& 0x02)) {
2134 dev_info(&dev
->dev
, "Enabling MCH 'Overflow' Device\n");
2135 pci_write_config_byte(dev
, 0xF4, reg
| 0x02);
2139 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
,
2140 quirk_unhide_mch_dev6
);
2141 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
,
2142 quirk_unhide_mch_dev6
);
2144 #ifdef CONFIG_TILEPRO
2146 * The Tilera TILEmpower tilepro platform needs to set the link speed
2147 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2148 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2149 * capability register of the PEX8624 PCIe switch. The switch
2150 * supports link speed auto negotiation, but falsely sets
2151 * the link speed to 5GT/s.
2153 static void quirk_tile_plx_gen1(struct pci_dev
*dev
)
2155 if (tile_plx_gen1
) {
2156 pci_write_config_dword(dev
, 0x98, 0x1);
2160 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX
, 0x8624, quirk_tile_plx_gen1
);
2161 #endif /* CONFIG_TILEPRO */
2163 #ifdef CONFIG_PCI_MSI
2164 /* Some chipsets do not support MSI. We cannot easily rely on setting
2165 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2166 * some other buses controlled by the chipset even if Linux is not
2167 * aware of it. Instead of setting the flag on all buses in the
2168 * machine, simply disable MSI globally.
2170 static void quirk_disable_all_msi(struct pci_dev
*dev
)
2173 dev_warn(&dev
->dev
, "MSI quirk detected; MSI disabled\n");
2175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
2176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
2177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
2178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
2179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
2180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3364
, quirk_disable_all_msi
);
2181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8380_0
, quirk_disable_all_msi
);
2183 /* Disable MSI on chipsets that are known to not support it */
2184 static void quirk_disable_msi(struct pci_dev
*dev
)
2186 if (dev
->subordinate
) {
2187 dev_warn(&dev
->dev
, "MSI quirk detected; subordinate MSI disabled\n");
2188 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
2192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0xa238, quirk_disable_msi
);
2193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x5a3f, quirk_disable_msi
);
2196 * The APC bridge device in AMD 780 family northbridges has some random
2197 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2198 * we use the possible vendor/device IDs of the host bridge for the
2199 * declared quirk, and search for the APC bridge by slot number.
2201 static void quirk_amd_780_apc_msi(struct pci_dev
*host_bridge
)
2203 struct pci_dev
*apc_bridge
;
2205 apc_bridge
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(1, 0));
2207 if (apc_bridge
->device
== 0x9602)
2208 quirk_disable_msi(apc_bridge
);
2209 pci_dev_put(apc_bridge
);
2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9600, quirk_amd_780_apc_msi
);
2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9601, quirk_amd_780_apc_msi
);
2215 /* Go through the list of Hypertransport capabilities and
2216 * return 1 if a HT MSI capability is found and enabled */
2217 static int msi_ht_cap_enabled(struct pci_dev
*dev
)
2221 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2222 while (pos
&& ttl
--) {
2225 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2227 dev_info(&dev
->dev
, "Found %s HT MSI Mapping\n",
2228 flags
& HT_MSI_FLAGS_ENABLE
?
2229 "enabled" : "disabled");
2230 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
2233 pos
= pci_find_next_ht_capability(dev
, pos
,
2234 HT_CAPTYPE_MSI_MAPPING
);
2239 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2240 static void quirk_msi_ht_cap(struct pci_dev
*dev
)
2242 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
2243 dev_warn(&dev
->dev
, "MSI quirk detected; subordinate MSI disabled\n");
2244 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
2250 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2251 * MSI are supported if the MSI capability set in any of these mappings.
2253 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
2255 struct pci_dev
*pdev
;
2257 if (!dev
->subordinate
)
2260 /* check HT MSI cap on this chipset and the root one.
2261 * a single one having MSI is enough to be sure that MSI are supported.
2263 pdev
= pci_get_slot(dev
->bus
, 0);
2266 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
2267 dev_warn(&dev
->dev
, "MSI quirk detected; subordinate MSI disabled\n");
2268 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2273 quirk_nvidia_ck804_msi_ht_cap
);
2275 /* Force enable MSI mapping capability on HT bridges */
2276 static void ht_enable_msi_mapping(struct pci_dev
*dev
)
2280 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2281 while (pos
&& ttl
--) {
2284 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2286 dev_info(&dev
->dev
, "Enabling HT MSI Mapping\n");
2288 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2289 flags
| HT_MSI_FLAGS_ENABLE
);
2291 pos
= pci_find_next_ht_capability(dev
, pos
,
2292 HT_CAPTYPE_MSI_MAPPING
);
2295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
2296 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
2297 ht_enable_msi_mapping
);
2299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
,
2300 ht_enable_msi_mapping
);
2302 /* The P5N32-SLI motherboards from Asus have a problem with msi
2303 * for the MCP55 NIC. It is not yet determined whether the msi problem
2304 * also affects other devices. As for now, turn off msi for this device.
2306 static void nvenet_msi_disable(struct pci_dev
*dev
)
2308 const char *board_name
= dmi_get_system_info(DMI_BOARD_NAME
);
2311 (strstr(board_name
, "P5N32-SLI PREMIUM") ||
2312 strstr(board_name
, "P5N32-E SLI"))) {
2313 dev_info(&dev
->dev
, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2317 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2318 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
2319 nvenet_msi_disable
);
2322 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2323 * config register. This register controls the routing of legacy
2324 * interrupts from devices that route through the MCP55. If this register
2325 * is misprogrammed, interrupts are only sent to the BSP, unlike
2326 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2327 * having this register set properly prevents kdump from booting up
2328 * properly, so let's make sure that we have it set correctly.
2329 * Note that this is an undocumented register.
2331 static void nvbridge_check_legacy_irq_routing(struct pci_dev
*dev
)
2335 if (!pci_find_capability(dev
, PCI_CAP_ID_HT
))
2338 pci_read_config_dword(dev
, 0x74, &cfg
);
2340 if (cfg
& ((1 << 2) | (1 << 15))) {
2341 printk(KERN_INFO
"Rewriting irq routing register on MCP55\n");
2342 cfg
&= ~((1 << 2) | (1 << 15));
2343 pci_write_config_dword(dev
, 0x74, cfg
);
2347 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2348 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0
,
2349 nvbridge_check_legacy_irq_routing
);
2351 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2352 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4
,
2353 nvbridge_check_legacy_irq_routing
);
2355 static int ht_check_msi_mapping(struct pci_dev
*dev
)
2360 /* check if there is HT MSI cap or enabled on this device */
2361 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2362 while (pos
&& ttl
--) {
2367 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2369 if (flags
& HT_MSI_FLAGS_ENABLE
) {
2376 pos
= pci_find_next_ht_capability(dev
, pos
,
2377 HT_CAPTYPE_MSI_MAPPING
);
2383 static int host_bridge_with_leaf(struct pci_dev
*host_bridge
)
2385 struct pci_dev
*dev
;
2390 dev_no
= host_bridge
->devfn
>> 3;
2391 for (i
= dev_no
+ 1; i
< 0x20; i
++) {
2392 dev
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(i
, 0));
2396 /* found next host bridge ?*/
2397 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2403 if (ht_check_msi_mapping(dev
)) {
2414 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2415 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2417 static int is_end_of_ht_chain(struct pci_dev
*dev
)
2423 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2428 pci_read_config_word(dev
, pos
+ PCI_CAP_FLAGS
, &flags
);
2430 ctrl_off
= ((flags
>> 10) & 1) ?
2431 PCI_HT_CAP_SLAVE_CTRL0
: PCI_HT_CAP_SLAVE_CTRL1
;
2432 pci_read_config_word(dev
, pos
+ ctrl_off
, &ctrl
);
2434 if (ctrl
& (1 << 6))
2441 static void nv_ht_enable_msi_mapping(struct pci_dev
*dev
)
2443 struct pci_dev
*host_bridge
;
2448 dev_no
= dev
->devfn
>> 3;
2449 for (i
= dev_no
; i
>= 0; i
--) {
2450 host_bridge
= pci_get_slot(dev
->bus
, PCI_DEVFN(i
, 0));
2454 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2459 pci_dev_put(host_bridge
);
2465 /* don't enable end_device/host_bridge with leaf directly here */
2466 if (host_bridge
== dev
&& is_end_of_ht_chain(host_bridge
) &&
2467 host_bridge_with_leaf(host_bridge
))
2470 /* root did that ! */
2471 if (msi_ht_cap_enabled(host_bridge
))
2474 ht_enable_msi_mapping(dev
);
2477 pci_dev_put(host_bridge
);
2480 static void ht_disable_msi_mapping(struct pci_dev
*dev
)
2484 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2485 while (pos
&& ttl
--) {
2488 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2490 dev_info(&dev
->dev
, "Disabling HT MSI Mapping\n");
2492 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2493 flags
& ~HT_MSI_FLAGS_ENABLE
);
2495 pos
= pci_find_next_ht_capability(dev
, pos
,
2496 HT_CAPTYPE_MSI_MAPPING
);
2500 static void __nv_msi_ht_cap_quirk(struct pci_dev
*dev
, int all
)
2502 struct pci_dev
*host_bridge
;
2506 if (!pci_msi_enabled())
2509 /* check if there is HT MSI cap or enabled on this device */
2510 found
= ht_check_msi_mapping(dev
);
2517 * HT MSI mapping should be disabled on devices that are below
2518 * a non-Hypertransport host bridge. Locate the host bridge...
2520 host_bridge
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2521 if (host_bridge
== NULL
) {
2522 dev_warn(&dev
->dev
, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2526 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2528 /* Host bridge is to HT */
2530 /* it is not enabled, try to enable it */
2532 ht_enable_msi_mapping(dev
);
2534 nv_ht_enable_msi_mapping(dev
);
2539 /* HT MSI is not enabled */
2543 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2544 ht_disable_msi_mapping(dev
);
2547 pci_dev_put(host_bridge
);
2550 static void nv_msi_ht_cap_quirk_all(struct pci_dev
*dev
)
2552 return __nv_msi_ht_cap_quirk(dev
, 1);
2555 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev
*dev
)
2557 return __nv_msi_ht_cap_quirk(dev
, 0);
2560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2561 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2564 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2566 static void quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
2568 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2570 static void quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
2574 /* SB700 MSI issue will be fixed at HW level from revision A21,
2575 * we need check PCI REVISION ID of SMBus controller to get SB700
2578 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2583 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
2584 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2587 static void quirk_msi_intx_disable_qca_bug(struct pci_dev
*dev
)
2589 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2590 if (dev
->revision
< 0x18) {
2591 dev_info(&dev
->dev
, "set MSI_INTX_DISABLE_BUG flag\n");
2592 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2596 PCI_DEVICE_ID_TIGON3_5780
,
2597 quirk_msi_intx_disable_bug
);
2598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2599 PCI_DEVICE_ID_TIGON3_5780S
,
2600 quirk_msi_intx_disable_bug
);
2601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2602 PCI_DEVICE_ID_TIGON3_5714
,
2603 quirk_msi_intx_disable_bug
);
2604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2605 PCI_DEVICE_ID_TIGON3_5714S
,
2606 quirk_msi_intx_disable_bug
);
2607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2608 PCI_DEVICE_ID_TIGON3_5715
,
2609 quirk_msi_intx_disable_bug
);
2610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2611 PCI_DEVICE_ID_TIGON3_5715S
,
2612 quirk_msi_intx_disable_bug
);
2614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
2615 quirk_msi_intx_disable_ati_bug
);
2616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
2617 quirk_msi_intx_disable_ati_bug
);
2618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
2619 quirk_msi_intx_disable_ati_bug
);
2620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
2621 quirk_msi_intx_disable_ati_bug
);
2622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
2623 quirk_msi_intx_disable_ati_bug
);
2625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
2626 quirk_msi_intx_disable_bug
);
2627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
2628 quirk_msi_intx_disable_bug
);
2629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
2630 quirk_msi_intx_disable_bug
);
2632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1062,
2633 quirk_msi_intx_disable_bug
);
2634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1063,
2635 quirk_msi_intx_disable_bug
);
2636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2060,
2637 quirk_msi_intx_disable_bug
);
2638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2062,
2639 quirk_msi_intx_disable_bug
);
2640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1073,
2641 quirk_msi_intx_disable_bug
);
2642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1083,
2643 quirk_msi_intx_disable_bug
);
2644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1090,
2645 quirk_msi_intx_disable_qca_bug
);
2646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1091,
2647 quirk_msi_intx_disable_qca_bug
);
2648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a0,
2649 quirk_msi_intx_disable_qca_bug
);
2650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a1,
2651 quirk_msi_intx_disable_qca_bug
);
2652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0xe091,
2653 quirk_msi_intx_disable_qca_bug
);
2654 #endif /* CONFIG_PCI_MSI */
2656 /* Allow manual resource allocation for PCI hotplug bridges
2657 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2658 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2659 * kernel fails to allocate resources when hotplug device is
2660 * inserted and PCI bus is rescanned.
2662 static void quirk_hotplug_bridge(struct pci_dev
*dev
)
2664 dev
->is_hotplug_bridge
= 1;
2667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT
, 0x0020, quirk_hotplug_bridge
);
2670 * This is a quirk for the Ricoh MMC controller found as a part of
2671 * some mulifunction chips.
2673 * This is very similar and based on the ricoh_mmc driver written by
2674 * Philip Langdale. Thank you for these magic sequences.
2676 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2677 * and one or both of cardbus or firewire.
2679 * It happens that they implement SD and MMC
2680 * support as separate controllers (and PCI functions). The linux SDHCI
2681 * driver supports MMC cards but the chip detects MMC cards in hardware
2682 * and directs them to the MMC controller - so the SDHCI driver never sees
2685 * To get around this, we must disable the useless MMC controller.
2686 * At that point, the SDHCI controller will start seeing them
2687 * It seems to be the case that the relevant PCI registers to deactivate the
2688 * MMC controller live on PCI function 0, which might be the cardbus controller
2689 * or the firewire controller, depending on the particular chip in question
2691 * This has to be done early, because as soon as we disable the MMC controller
2692 * other pci functions shift up one level, e.g. function #2 becomes function
2693 * #1, and this will confuse the pci core.
2696 #ifdef CONFIG_MMC_RICOH_MMC
2697 static void ricoh_mmc_fixup_rl5c476(struct pci_dev
*dev
)
2699 /* disable via cardbus interface */
2704 /* disable must be done via function #0 */
2705 if (PCI_FUNC(dev
->devfn
))
2708 pci_read_config_byte(dev
, 0xB7, &disable
);
2712 pci_read_config_byte(dev
, 0x8E, &write_enable
);
2713 pci_write_config_byte(dev
, 0x8E, 0xAA);
2714 pci_read_config_byte(dev
, 0x8D, &write_target
);
2715 pci_write_config_byte(dev
, 0x8D, 0xB7);
2716 pci_write_config_byte(dev
, 0xB7, disable
| 0x02);
2717 pci_write_config_byte(dev
, 0x8E, write_enable
);
2718 pci_write_config_byte(dev
, 0x8D, write_target
);
2720 dev_notice(&dev
->dev
, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2721 dev_notice(&dev
->dev
, "MMC cards are now supported by standard SDHCI controller\n");
2723 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
2724 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
2726 static void ricoh_mmc_fixup_r5c832(struct pci_dev
*dev
)
2728 /* disable via firewire interface */
2732 /* disable must be done via function #0 */
2733 if (PCI_FUNC(dev
->devfn
))
2736 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2737 * certain types of SD/MMC cards. Lowering the SD base
2738 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2740 * 0x150 - SD2.0 mode enable for changing base clock
2741 * frequency to 50Mhz
2742 * 0xe1 - Base clock frequency
2743 * 0x32 - 50Mhz new clock frequency
2744 * 0xf9 - Key register for 0x150
2745 * 0xfc - key register for 0xe1
2747 if (dev
->device
== PCI_DEVICE_ID_RICOH_R5CE822
||
2748 dev
->device
== PCI_DEVICE_ID_RICOH_R5CE823
) {
2749 pci_write_config_byte(dev
, 0xf9, 0xfc);
2750 pci_write_config_byte(dev
, 0x150, 0x10);
2751 pci_write_config_byte(dev
, 0xf9, 0x00);
2752 pci_write_config_byte(dev
, 0xfc, 0x01);
2753 pci_write_config_byte(dev
, 0xe1, 0x32);
2754 pci_write_config_byte(dev
, 0xfc, 0x00);
2756 dev_notice(&dev
->dev
, "MMC controller base frequency changed to 50Mhz.\n");
2759 pci_read_config_byte(dev
, 0xCB, &disable
);
2764 pci_read_config_byte(dev
, 0xCA, &write_enable
);
2765 pci_write_config_byte(dev
, 0xCA, 0x57);
2766 pci_write_config_byte(dev
, 0xCB, disable
| 0x02);
2767 pci_write_config_byte(dev
, 0xCA, write_enable
);
2769 dev_notice(&dev
->dev
, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2770 dev_notice(&dev
->dev
, "MMC cards are now supported by standard SDHCI controller\n");
2773 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
2774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
2775 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
2776 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
2777 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
2778 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
2779 #endif /*CONFIG_MMC_RICOH_MMC*/
2781 #ifdef CONFIG_DMAR_TABLE
2782 #define VTUNCERRMSK_REG 0x1ac
2783 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2785 * This is a quirk for masking vt-d spec defined errors to platform error
2786 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2787 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2788 * on the RAS config settings of the platform) when a vt-d fault happens.
2789 * The resulting SMI caused the system to hang.
2791 * VT-d spec related errors are already handled by the VT-d OS code, so no
2792 * need to report the same error through other channels.
2794 static void vtd_mask_spec_errors(struct pci_dev
*dev
)
2798 pci_read_config_dword(dev
, VTUNCERRMSK_REG
, &word
);
2799 pci_write_config_dword(dev
, VTUNCERRMSK_REG
, word
| VTD_MSK_SPEC_ERRORS
);
2801 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x342e, vtd_mask_spec_errors
);
2802 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x3c28, vtd_mask_spec_errors
);
2805 static void fixup_ti816x_class(struct pci_dev
*dev
)
2807 /* TI 816x devices do not have class code set when in PCIe boot mode */
2808 dev_info(&dev
->dev
, "Setting PCI class for 816x PCIe device\n");
2809 dev
->class = PCI_CLASS_MULTIMEDIA_VIDEO
;
2811 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI
, 0xb800,
2812 PCI_CLASS_NOT_DEFINED
, 0, fixup_ti816x_class
);
2814 /* Some PCIe devices do not work reliably with the claimed maximum
2815 * payload size supported.
2817 static void fixup_mpss_256(struct pci_dev
*dev
)
2819 dev
->pcie_mpss
= 1; /* 256 bytes */
2821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
2822 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0
, fixup_mpss_256
);
2823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
2824 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1
, fixup_mpss_256
);
2825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
2826 PCI_DEVICE_ID_SOLARFLARE_SFC4000B
, fixup_mpss_256
);
2828 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2829 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2830 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2831 * until all of the devices are discovered and buses walked, read completion
2832 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2833 * it is possible to hotplug a device with MPS of 256B.
2835 static void quirk_intel_mc_errata(struct pci_dev
*dev
)
2840 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
)
2843 /* Intel errata specifies bits to change but does not say what they are.
2844 * Keeping them magical until such time as the registers and values can
2847 err
= pci_read_config_word(dev
, 0x48, &rcc
);
2849 dev_err(&dev
->dev
, "Error attempting to read the read completion coalescing register\n");
2853 if (!(rcc
& (1 << 10)))
2858 err
= pci_write_config_word(dev
, 0x48, rcc
);
2860 dev_err(&dev
->dev
, "Error attempting to write the read completion coalescing register\n");
2864 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2866 /* Intel 5000 series memory controllers and ports 2-7 */
2867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25c0, quirk_intel_mc_errata
);
2868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d0, quirk_intel_mc_errata
);
2869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d4, quirk_intel_mc_errata
);
2870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d8, quirk_intel_mc_errata
);
2871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_mc_errata
);
2872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_mc_errata
);
2873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_mc_errata
);
2874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_mc_errata
);
2875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_mc_errata
);
2876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_mc_errata
);
2877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_mc_errata
);
2878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_mc_errata
);
2879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_mc_errata
);
2880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_mc_errata
);
2881 /* Intel 5100 series memory controllers and ports 2-7 */
2882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65c0, quirk_intel_mc_errata
);
2883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e2, quirk_intel_mc_errata
);
2884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e3, quirk_intel_mc_errata
);
2885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e4, quirk_intel_mc_errata
);
2886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e5, quirk_intel_mc_errata
);
2887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e6, quirk_intel_mc_errata
);
2888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e7, quirk_intel_mc_errata
);
2889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f7, quirk_intel_mc_errata
);
2890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f8, quirk_intel_mc_errata
);
2891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f9, quirk_intel_mc_errata
);
2892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65fa, quirk_intel_mc_errata
);
2896 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2897 * work around this, query the size it should be configured to by the device and
2898 * modify the resource end to correspond to this new size.
2900 static void quirk_intel_ntb(struct pci_dev
*dev
)
2905 rc
= pci_read_config_byte(dev
, 0x00D0, &val
);
2909 dev
->resource
[2].end
= dev
->resource
[2].start
+ ((u64
) 1 << val
) - 1;
2911 rc
= pci_read_config_byte(dev
, 0x00D1, &val
);
2915 dev
->resource
[4].end
= dev
->resource
[4].start
+ ((u64
) 1 << val
) - 1;
2917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e08, quirk_intel_ntb
);
2918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e0d, quirk_intel_ntb
);
2920 static ktime_t
fixup_debug_start(struct pci_dev
*dev
,
2921 void (*fn
)(struct pci_dev
*dev
))
2923 ktime_t calltime
= ktime_set(0, 0);
2925 dev_dbg(&dev
->dev
, "calling %pF\n", fn
);
2926 if (initcall_debug
) {
2927 pr_debug("calling %pF @ %i for %s\n",
2928 fn
, task_pid_nr(current
), dev_name(&dev
->dev
));
2929 calltime
= ktime_get();
2935 static void fixup_debug_report(struct pci_dev
*dev
, ktime_t calltime
,
2936 void (*fn
)(struct pci_dev
*dev
))
2938 ktime_t delta
, rettime
;
2939 unsigned long long duration
;
2941 if (initcall_debug
) {
2942 rettime
= ktime_get();
2943 delta
= ktime_sub(rettime
, calltime
);
2944 duration
= (unsigned long long) ktime_to_ns(delta
) >> 10;
2945 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2946 fn
, duration
, dev_name(&dev
->dev
));
2951 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2952 * even though no one is handling them (f.e. i915 driver is never loaded).
2953 * Additionally the interrupt destination is not set up properly
2954 * and the interrupt ends up -somewhere-.
2956 * These spurious interrupts are "sticky" and the kernel disables
2957 * the (shared) interrupt line after 100.000+ generated interrupts.
2959 * Fix it by disabling the still enabled interrupts.
2960 * This resolves crashes often seen on monitor unplug.
2962 #define I915_DEIER_REG 0x4400c
2963 static void disable_igfx_irq(struct pci_dev
*dev
)
2965 void __iomem
*regs
= pci_iomap(dev
, 0, 0);
2967 dev_warn(&dev
->dev
, "igfx quirk: Can't iomap PCI device\n");
2971 /* Check if any interrupt line is still enabled */
2972 if (readl(regs
+ I915_DEIER_REG
) != 0) {
2973 dev_warn(&dev
->dev
, "BIOS left Intel GPU interrupts enabled; disabling\n");
2975 writel(0, regs
+ I915_DEIER_REG
);
2978 pci_iounmap(dev
, regs
);
2980 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0102, disable_igfx_irq
);
2981 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x010a, disable_igfx_irq
);
2982 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0152, disable_igfx_irq
);
2985 * PCI devices which are on Intel chips can skip the 10ms delay
2986 * before entering D3 mode.
2988 static void quirk_remove_d3_delay(struct pci_dev
*dev
)
2992 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c00, quirk_remove_d3_delay
);
2993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0412, quirk_remove_d3_delay
);
2994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c0c, quirk_remove_d3_delay
);
2995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c31, quirk_remove_d3_delay
);
2996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3a, quirk_remove_d3_delay
);
2997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3d, quirk_remove_d3_delay
);
2998 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c2d, quirk_remove_d3_delay
);
2999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c20, quirk_remove_d3_delay
);
3000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c18, quirk_remove_d3_delay
);
3001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c1c, quirk_remove_d3_delay
);
3002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c26, quirk_remove_d3_delay
);
3003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c4e, quirk_remove_d3_delay
);
3004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c02, quirk_remove_d3_delay
);
3005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c22, quirk_remove_d3_delay
);
3008 * Some devices may pass our check in pci_intx_mask_supported if
3009 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3010 * support this feature.
3012 static void quirk_broken_intx_masking(struct pci_dev
*dev
)
3014 dev
->broken_intx_masking
= 1;
3016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO
, 0x0030,
3017 quirk_broken_intx_masking
);
3018 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3019 quirk_broken_intx_masking
);
3021 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3022 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3024 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK
, 0x8169,
3027 quirk_broken_intx_masking
);
3028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX
, PCI_ANY_ID
,
3029 quirk_broken_intx_masking
);
3031 static void quirk_no_bus_reset(struct pci_dev
*dev
)
3033 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_BUS_RESET
;
3037 * Atheros AR93xx chips do not behave after a bus reset. The device will
3038 * throw a Link Down error on AER-capable systems and regardless of AER,
3039 * config space of the device is never accessible again and typically
3040 * causes the system to hang or reset when access is attempted.
3041 * http://www.spinics.net/lists/linux-pci/msg34797.html
3043 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0030, quirk_no_bus_reset
);
3047 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3049 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3050 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3051 * be present after resume if a device was plugged in before suspend.
3053 * The thunderbolt controller consists of a pcie switch with downstream
3054 * bridges leading to the NHI and to the tunnel pci bridges.
3056 * This quirk cuts power to the whole chip. Therefore we have to apply it
3057 * during suspend_noirq of the upstream bridge.
3059 * Power is automagically restored before resume. No action is needed.
3061 static void quirk_apple_poweroff_thunderbolt(struct pci_dev
*dev
)
3063 acpi_handle bridge
, SXIO
, SXFP
, SXLV
;
3065 if (!dmi_match(DMI_BOARD_VENDOR
, "Apple Inc."))
3067 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
)
3069 bridge
= ACPI_HANDLE(&dev
->dev
);
3073 * SXIO and SXLV are present only on machines requiring this quirk.
3074 * TB bridges in external devices might have the same device id as those
3075 * on the host, but they will not have the associated ACPI methods. This
3076 * implicitly checks that we are at the right bridge.
3078 if (ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXIO", &SXIO
))
3079 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXFP", &SXFP
))
3080 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXLV", &SXLV
)))
3082 dev_info(&dev
->dev
, "quirk: cutting power to thunderbolt controller...\n");
3084 /* magic sequence */
3085 acpi_execute_simple_method(SXIO
, NULL
, 1);
3086 acpi_execute_simple_method(SXFP
, NULL
, 0);
3088 acpi_execute_simple_method(SXLV
, NULL
, 0);
3089 acpi_execute_simple_method(SXIO
, NULL
, 0);
3090 acpi_execute_simple_method(SXLV
, NULL
, 0);
3092 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL
, 0x1547,
3093 quirk_apple_poweroff_thunderbolt
);
3096 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3098 * During suspend the thunderbolt controller is reset and all pci
3099 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3100 * during resume. We have to manually wait for the NHI since there is
3101 * no parent child relationship between the NHI and the tunneled
3104 static void quirk_apple_wait_for_thunderbolt(struct pci_dev
*dev
)
3106 struct pci_dev
*sibling
= NULL
;
3107 struct pci_dev
*nhi
= NULL
;
3109 if (!dmi_match(DMI_BOARD_VENDOR
, "Apple Inc."))
3111 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_DOWNSTREAM
)
3114 * Find the NHI and confirm that we are a bridge on the tb host
3115 * controller and not on a tb endpoint.
3117 sibling
= pci_get_slot(dev
->bus
, 0x0);
3119 goto out
; /* we are the downstream bridge to the NHI */
3120 if (!sibling
|| !sibling
->subordinate
)
3122 nhi
= pci_get_slot(sibling
->subordinate
, 0x0);
3125 if (nhi
->vendor
!= PCI_VENDOR_ID_INTEL
3126 || (nhi
->device
!= 0x1547 && nhi
->device
!= 0x156c)
3127 || nhi
->subsystem_vendor
!= 0x2222
3128 || nhi
->subsystem_device
!= 0x1111)
3130 dev_info(&dev
->dev
, "quirk: wating for thunderbolt to reestablish pci tunnels...\n");
3131 device_pm_wait_for_dev(&dev
->dev
, &nhi
->dev
);
3134 pci_dev_put(sibling
);
3136 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, 0x1547,
3137 quirk_apple_wait_for_thunderbolt
);
3138 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, 0x156d,
3139 quirk_apple_wait_for_thunderbolt
);
3142 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
,
3143 struct pci_fixup
*end
)
3147 for (; f
< end
; f
++)
3148 if ((f
->class == (u32
) (dev
->class >> f
->class_shift
) ||
3149 f
->class == (u32
) PCI_ANY_ID
) &&
3150 (f
->vendor
== dev
->vendor
||
3151 f
->vendor
== (u16
) PCI_ANY_ID
) &&
3152 (f
->device
== dev
->device
||
3153 f
->device
== (u16
) PCI_ANY_ID
)) {
3154 calltime
= fixup_debug_start(dev
, f
->hook
);
3156 fixup_debug_report(dev
, calltime
, f
->hook
);
3160 extern struct pci_fixup __start_pci_fixups_early
[];
3161 extern struct pci_fixup __end_pci_fixups_early
[];
3162 extern struct pci_fixup __start_pci_fixups_header
[];
3163 extern struct pci_fixup __end_pci_fixups_header
[];
3164 extern struct pci_fixup __start_pci_fixups_final
[];
3165 extern struct pci_fixup __end_pci_fixups_final
[];
3166 extern struct pci_fixup __start_pci_fixups_enable
[];
3167 extern struct pci_fixup __end_pci_fixups_enable
[];
3168 extern struct pci_fixup __start_pci_fixups_resume
[];
3169 extern struct pci_fixup __end_pci_fixups_resume
[];
3170 extern struct pci_fixup __start_pci_fixups_resume_early
[];
3171 extern struct pci_fixup __end_pci_fixups_resume_early
[];
3172 extern struct pci_fixup __start_pci_fixups_suspend
[];
3173 extern struct pci_fixup __end_pci_fixups_suspend
[];
3174 extern struct pci_fixup __start_pci_fixups_suspend_late
[];
3175 extern struct pci_fixup __end_pci_fixups_suspend_late
[];
3177 static bool pci_apply_fixup_final_quirks
;
3179 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
3181 struct pci_fixup
*start
, *end
;
3184 case pci_fixup_early
:
3185 start
= __start_pci_fixups_early
;
3186 end
= __end_pci_fixups_early
;
3189 case pci_fixup_header
:
3190 start
= __start_pci_fixups_header
;
3191 end
= __end_pci_fixups_header
;
3194 case pci_fixup_final
:
3195 if (!pci_apply_fixup_final_quirks
)
3197 start
= __start_pci_fixups_final
;
3198 end
= __end_pci_fixups_final
;
3201 case pci_fixup_enable
:
3202 start
= __start_pci_fixups_enable
;
3203 end
= __end_pci_fixups_enable
;
3206 case pci_fixup_resume
:
3207 start
= __start_pci_fixups_resume
;
3208 end
= __end_pci_fixups_resume
;
3211 case pci_fixup_resume_early
:
3212 start
= __start_pci_fixups_resume_early
;
3213 end
= __end_pci_fixups_resume_early
;
3216 case pci_fixup_suspend
:
3217 start
= __start_pci_fixups_suspend
;
3218 end
= __end_pci_fixups_suspend
;
3221 case pci_fixup_suspend_late
:
3222 start
= __start_pci_fixups_suspend_late
;
3223 end
= __end_pci_fixups_suspend_late
;
3227 /* stupid compiler warning, you would think with an enum... */
3230 pci_do_fixups(dev
, start
, end
);
3232 EXPORT_SYMBOL(pci_fixup_device
);
3235 static int __init
pci_apply_final_quirks(void)
3237 struct pci_dev
*dev
= NULL
;
3241 if (pci_cache_line_size
)
3242 printk(KERN_DEBUG
"PCI: CLS %u bytes\n",
3243 pci_cache_line_size
<< 2);
3245 pci_apply_fixup_final_quirks
= true;
3246 for_each_pci_dev(dev
) {
3247 pci_fixup_device(pci_fixup_final
, dev
);
3249 * If arch hasn't set it explicitly yet, use the CLS
3250 * value shared by all PCI devices. If there's a
3251 * mismatch, fall back to the default value.
3253 if (!pci_cache_line_size
) {
3254 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &tmp
);
3257 if (!tmp
|| cls
== tmp
)
3260 printk(KERN_DEBUG
"PCI: CLS mismatch (%u != %u), using %u bytes\n",
3262 pci_dfl_cache_line_size
<< 2);
3263 pci_cache_line_size
= pci_dfl_cache_line_size
;
3267 if (!pci_cache_line_size
) {
3268 printk(KERN_DEBUG
"PCI: CLS %u bytes, default %u\n",
3269 cls
<< 2, pci_dfl_cache_line_size
<< 2);
3270 pci_cache_line_size
= cls
? cls
: pci_dfl_cache_line_size
;
3276 fs_initcall_sync(pci_apply_final_quirks
);
3279 * Followings are device-specific reset methods which can be used to
3280 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3283 static int reset_intel_generic_dev(struct pci_dev
*dev
, int probe
)
3287 /* only implement PCI_CLASS_SERIAL_USB at present */
3288 if (dev
->class == PCI_CLASS_SERIAL_USB
) {
3289 pos
= pci_find_capability(dev
, PCI_CAP_ID_VNDR
);
3296 pci_write_config_byte(dev
, pos
+ 0x4, 1);
3305 static int reset_intel_82599_sfp_virtfn(struct pci_dev
*dev
, int probe
)
3308 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3310 * The 82599 supports FLR on VFs, but FLR support is reported only
3311 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3312 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3318 if (!pci_wait_for_pending_transaction(dev
))
3319 dev_err(&dev
->dev
, "transaction is not cleared; proceeding with reset anyway\n");
3321 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3328 #include "../gpu/drm/i915/i915_reg.h"
3329 #define MSG_CTL 0x45010
3330 #define NSDE_PWR_STATE 0xd0100
3331 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3333 static int reset_ivb_igd(struct pci_dev
*dev
, int probe
)
3335 void __iomem
*mmio_base
;
3336 unsigned long timeout
;
3342 mmio_base
= pci_iomap(dev
, 0, 0);
3346 iowrite32(0x00000002, mmio_base
+ MSG_CTL
);
3349 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3350 * driver loaded sets the right bits. However, this's a reset and
3351 * the bits have been set by i915 previously, so we clobber
3352 * SOUTH_CHICKEN2 register directly here.
3354 iowrite32(0x00000005, mmio_base
+ SOUTH_CHICKEN2
);
3356 val
= ioread32(mmio_base
+ PCH_PP_CONTROL
) & 0xfffffffe;
3357 iowrite32(val
, mmio_base
+ PCH_PP_CONTROL
);
3359 timeout
= jiffies
+ msecs_to_jiffies(IGD_OPERATION_TIMEOUT
);
3361 val
= ioread32(mmio_base
+ PCH_PP_STATUS
);
3362 if ((val
& 0xb0000000) == 0)
3363 goto reset_complete
;
3365 } while (time_before(jiffies
, timeout
));
3366 dev_warn(&dev
->dev
, "timeout during reset\n");
3369 iowrite32(0x00000002, mmio_base
+ NSDE_PWR_STATE
);
3371 pci_iounmap(dev
, mmio_base
);
3376 * Device-specific reset method for Chelsio T4-based adapters.
3378 static int reset_chelsio_generic_dev(struct pci_dev
*dev
, int probe
)
3384 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3385 * that we have no device-specific reset method.
3387 if ((dev
->device
& 0xf000) != 0x4000)
3391 * If this is the "probe" phase, return 0 indicating that we can
3392 * reset this device.
3398 * T4 can wedge if there are DMAs in flight within the chip and Bus
3399 * Master has been disabled. We need to have it on till the Function
3400 * Level Reset completes. (BUS_MASTER is disabled in
3401 * pci_reset_function()).
3403 pci_read_config_word(dev
, PCI_COMMAND
, &old_command
);
3404 pci_write_config_word(dev
, PCI_COMMAND
,
3405 old_command
| PCI_COMMAND_MASTER
);
3408 * Perform the actual device function reset, saving and restoring
3409 * configuration information around the reset.
3411 pci_save_state(dev
);
3414 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3415 * are disabled when an MSI-X interrupt message needs to be delivered.
3416 * So we briefly re-enable MSI-X interrupts for the duration of the
3417 * FLR. The pci_restore_state() below will restore the original
3420 pci_read_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
, &msix_flags
);
3421 if ((msix_flags
& PCI_MSIX_FLAGS_ENABLE
) == 0)
3422 pci_write_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
,
3424 PCI_MSIX_FLAGS_ENABLE
|
3425 PCI_MSIX_FLAGS_MASKALL
);
3428 * Start of pcie_flr() code sequence. This reset code is a copy of
3429 * the guts of pcie_flr() because that's not an exported function.
3432 if (!pci_wait_for_pending_transaction(dev
))
3433 dev_err(&dev
->dev
, "transaction is not cleared; proceeding with reset anyway\n");
3435 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3439 * End of pcie_flr() code sequence.
3443 * Restore the configuration information (BAR values, etc.) including
3444 * the original PCI Configuration Space Command word, and return
3447 pci_restore_state(dev
);
3448 pci_write_config_word(dev
, PCI_COMMAND
, old_command
);
3452 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3453 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3454 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3456 static const struct pci_dev_reset_methods pci_dev_reset_methods
[] = {
3457 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82599_SFP_VF
,
3458 reset_intel_82599_sfp_virtfn
},
3459 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M_VGA
,
3461 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M2_VGA
,
3463 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
3464 reset_intel_generic_dev
},
3465 { PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
3466 reset_chelsio_generic_dev
},
3471 * These device-specific reset methods are here rather than in a driver
3472 * because when a host assigns a device to a guest VM, the host may need
3473 * to reset the device but probably doesn't have a driver for it.
3475 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
)
3477 const struct pci_dev_reset_methods
*i
;
3479 for (i
= pci_dev_reset_methods
; i
->reset
; i
++) {
3480 if ((i
->vendor
== dev
->vendor
||
3481 i
->vendor
== (u16
)PCI_ANY_ID
) &&
3482 (i
->device
== dev
->device
||
3483 i
->device
== (u16
)PCI_ANY_ID
))
3484 return i
->reset(dev
, probe
);
3490 static void quirk_dma_func0_alias(struct pci_dev
*dev
)
3492 if (PCI_FUNC(dev
->devfn
) != 0) {
3493 dev
->dma_alias_devfn
= PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0);
3494 dev
->dev_flags
|= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
;
3499 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3501 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe832, quirk_dma_func0_alias
);
3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe476, quirk_dma_func0_alias
);
3506 static void quirk_dma_func1_alias(struct pci_dev
*dev
)
3508 if (PCI_FUNC(dev
->devfn
) != 1) {
3509 dev
->dma_alias_devfn
= PCI_DEVFN(PCI_SLOT(dev
->devfn
), 1);
3510 dev
->dev_flags
|= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
;
3515 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3516 * SKUs function 1 is present and is a legacy IDE controller, in other
3517 * SKUs this function is not present, making this a ghost requester.
3518 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9123,
3521 quirk_dma_func1_alias
);
3522 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9130,
3524 quirk_dma_func1_alias
);
3525 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9172,
3527 quirk_dma_func1_alias
);
3528 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x917a,
3530 quirk_dma_func1_alias
);
3531 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x91a0,
3533 quirk_dma_func1_alias
);
3534 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9230,
3536 quirk_dma_func1_alias
);
3537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0642,
3538 quirk_dma_func1_alias
);
3539 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON
,
3541 PCI_DEVICE_ID_JMICRON_JMB388_ESD
,
3542 quirk_dma_func1_alias
);
3545 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3546 * using the wrong DMA alias for the device. Some of these devices can be
3547 * used as either forward or reverse bridges, so we need to test whether the
3548 * device is operating in the correct mode. We could probably apply this
3549 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3550 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3551 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3553 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev
*pdev
)
3555 if (!pci_is_root_bus(pdev
->bus
) &&
3556 pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
3557 !pci_is_pcie(pdev
) && pci_is_pcie(pdev
->bus
->self
) &&
3558 pci_pcie_type(pdev
->bus
->self
) != PCI_EXP_TYPE_PCI_BRIDGE
)
3559 pdev
->dev_flags
|= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
;
3561 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA
, 0x1080,
3563 quirk_use_pcie_bridge_dma_alias
);
3564 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3565 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias
);
3566 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3567 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias
);
3568 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3569 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias
);
3572 * AMD has indicated that the devices below do not support peer-to-peer
3573 * in any system where they are found in the southbridge with an AMD
3574 * IOMMU in the system. Multifunction devices that do not support
3575 * peer-to-peer between functions can claim to support a subset of ACS.
3576 * Such devices effectively enable request redirect (RR) and completion
3577 * redirect (CR) since all transactions are redirected to the upstream
3580 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3581 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3582 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3584 * 1002:4385 SBx00 SMBus Controller
3585 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3586 * 1002:4383 SBx00 Azalia (Intel HDA)
3587 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3588 * 1002:4384 SBx00 PCI to PCI Bridge
3589 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3591 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3593 * 1022:780f [AMD] FCH PCI Bridge
3594 * 1022:7809 [AMD] FCH USB OHCI Controller
3596 static int pci_quirk_amd_sb_acs(struct pci_dev
*dev
, u16 acs_flags
)
3599 struct acpi_table_header
*header
= NULL
;
3602 /* Targeting multifunction devices on the SB (appears on root bus) */
3603 if (!dev
->multifunction
|| !pci_is_root_bus(dev
->bus
))
3606 /* The IVRS table describes the AMD IOMMU */
3607 status
= acpi_get_table("IVRS", 0, &header
);
3608 if (ACPI_FAILURE(status
))
3611 /* Filter out flags not applicable to multifunction */
3612 acs_flags
&= (PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
| PCI_ACS_DT
);
3614 return acs_flags
& ~(PCI_ACS_RR
| PCI_ACS_CR
) ? 0 : 1;
3621 * Many Intel PCH root ports do provide ACS-like features to disable peer
3622 * transactions and validate bus numbers in requests, but do not provide an
3623 * actual PCIe ACS capability. This is the list of device IDs known to fall
3624 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3626 static const u16 pci_quirk_intel_pch_acs_ids
[] = {
3628 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3629 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3630 /* Cougarpoint PCH */
3631 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3632 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3633 /* Pantherpoint PCH */
3634 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3635 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3636 /* Lynxpoint-H PCH */
3637 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3638 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3639 /* Lynxpoint-LP PCH */
3640 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3641 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3643 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3644 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3645 /* Patsburg (X79) PCH */
3646 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
3649 static bool pci_quirk_intel_pch_acs_match(struct pci_dev
*dev
)
3653 /* Filter out a few obvious non-matches first */
3654 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
3657 for (i
= 0; i
< ARRAY_SIZE(pci_quirk_intel_pch_acs_ids
); i
++)
3658 if (pci_quirk_intel_pch_acs_ids
[i
] == dev
->device
)
3664 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3666 static int pci_quirk_intel_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
3668 u16 flags
= dev
->dev_flags
& PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
?
3669 INTEL_PCH_ACS_FLAGS
: 0;
3671 if (!pci_quirk_intel_pch_acs_match(dev
))
3674 return acs_flags
& ~flags
? 0 : 1;
3677 static int pci_quirk_mf_endpoint_acs(struct pci_dev
*dev
, u16 acs_flags
)
3680 * SV, TB, and UF are not relevant to multifunction endpoints.
3682 * Multifunction devices are only required to implement RR, CR, and DT
3683 * in their ACS capability if they support peer-to-peer transactions.
3684 * Devices matching this quirk have been verified by the vendor to not
3685 * perform peer-to-peer with other functions, allowing us to mask out
3686 * these bits as if they were unimplemented in the ACS capability.
3688 acs_flags
&= ~(PCI_ACS_SV
| PCI_ACS_TB
| PCI_ACS_RR
|
3689 PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_DT
);
3691 return acs_flags
? 0 : 1;
3694 static const struct pci_dev_acs_enabled
{
3697 int (*acs_enabled
)(struct pci_dev
*dev
, u16 acs_flags
);
3698 } pci_dev_acs_enabled
[] = {
3699 { PCI_VENDOR_ID_ATI
, 0x4385, pci_quirk_amd_sb_acs
},
3700 { PCI_VENDOR_ID_ATI
, 0x439c, pci_quirk_amd_sb_acs
},
3701 { PCI_VENDOR_ID_ATI
, 0x4383, pci_quirk_amd_sb_acs
},
3702 { PCI_VENDOR_ID_ATI
, 0x439d, pci_quirk_amd_sb_acs
},
3703 { PCI_VENDOR_ID_ATI
, 0x4384, pci_quirk_amd_sb_acs
},
3704 { PCI_VENDOR_ID_ATI
, 0x4399, pci_quirk_amd_sb_acs
},
3705 { PCI_VENDOR_ID_AMD
, 0x780f, pci_quirk_amd_sb_acs
},
3706 { PCI_VENDOR_ID_AMD
, 0x7809, pci_quirk_amd_sb_acs
},
3707 { PCI_VENDOR_ID_SOLARFLARE
, 0x0903, pci_quirk_mf_endpoint_acs
},
3708 { PCI_VENDOR_ID_SOLARFLARE
, 0x0923, pci_quirk_mf_endpoint_acs
},
3709 { PCI_VENDOR_ID_INTEL
, 0x10C6, pci_quirk_mf_endpoint_acs
},
3710 { PCI_VENDOR_ID_INTEL
, 0x10DB, pci_quirk_mf_endpoint_acs
},
3711 { PCI_VENDOR_ID_INTEL
, 0x10DD, pci_quirk_mf_endpoint_acs
},
3712 { PCI_VENDOR_ID_INTEL
, 0x10E1, pci_quirk_mf_endpoint_acs
},
3713 { PCI_VENDOR_ID_INTEL
, 0x10F1, pci_quirk_mf_endpoint_acs
},
3714 { PCI_VENDOR_ID_INTEL
, 0x10F7, pci_quirk_mf_endpoint_acs
},
3715 { PCI_VENDOR_ID_INTEL
, 0x10F8, pci_quirk_mf_endpoint_acs
},
3716 { PCI_VENDOR_ID_INTEL
, 0x10F9, pci_quirk_mf_endpoint_acs
},
3717 { PCI_VENDOR_ID_INTEL
, 0x10FA, pci_quirk_mf_endpoint_acs
},
3718 { PCI_VENDOR_ID_INTEL
, 0x10FB, pci_quirk_mf_endpoint_acs
},
3719 { PCI_VENDOR_ID_INTEL
, 0x10FC, pci_quirk_mf_endpoint_acs
},
3720 { PCI_VENDOR_ID_INTEL
, 0x1507, pci_quirk_mf_endpoint_acs
},
3721 { PCI_VENDOR_ID_INTEL
, 0x1514, pci_quirk_mf_endpoint_acs
},
3722 { PCI_VENDOR_ID_INTEL
, 0x151C, pci_quirk_mf_endpoint_acs
},
3723 { PCI_VENDOR_ID_INTEL
, 0x1529, pci_quirk_mf_endpoint_acs
},
3724 { PCI_VENDOR_ID_INTEL
, 0x152A, pci_quirk_mf_endpoint_acs
},
3725 { PCI_VENDOR_ID_INTEL
, 0x154D, pci_quirk_mf_endpoint_acs
},
3726 { PCI_VENDOR_ID_INTEL
, 0x154F, pci_quirk_mf_endpoint_acs
},
3727 { PCI_VENDOR_ID_INTEL
, 0x1551, pci_quirk_mf_endpoint_acs
},
3728 { PCI_VENDOR_ID_INTEL
, 0x1558, pci_quirk_mf_endpoint_acs
},
3729 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_pch_acs
},
3733 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
)
3735 const struct pci_dev_acs_enabled
*i
;
3739 * Allow devices that do not expose standard PCIe ACS capabilities
3740 * or control to indicate their support here. Multi-function express
3741 * devices which do not allow internal peer-to-peer between functions,
3742 * but do not implement PCIe ACS may wish to return true here.
3744 for (i
= pci_dev_acs_enabled
; i
->acs_enabled
; i
++) {
3745 if ((i
->vendor
== dev
->vendor
||
3746 i
->vendor
== (u16
)PCI_ANY_ID
) &&
3747 (i
->device
== dev
->device
||
3748 i
->device
== (u16
)PCI_ANY_ID
)) {
3749 ret
= i
->acs_enabled(dev
, acs_flags
);
3758 /* Config space offset of Root Complex Base Address register */
3759 #define INTEL_LPC_RCBA_REG 0xf0
3760 /* 31:14 RCBA address */
3761 #define INTEL_LPC_RCBA_MASK 0xffffc000
3763 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
3765 /* Backbone Scratch Pad Register */
3766 #define INTEL_BSPR_REG 0x1104
3767 /* Backbone Peer Non-Posted Disable */
3768 #define INTEL_BSPR_REG_BPNPD (1 << 8)
3769 /* Backbone Peer Posted Disable */
3770 #define INTEL_BSPR_REG_BPPD (1 << 9)
3772 /* Upstream Peer Decode Configuration Register */
3773 #define INTEL_UPDCR_REG 0x1114
3774 /* 5:0 Peer Decode Enable bits */
3775 #define INTEL_UPDCR_REG_MASK 0x3f
3777 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev
*dev
)
3779 u32 rcba
, bspr
, updcr
;
3780 void __iomem
*rcba_mem
;
3783 * Read the RCBA register from the LPC (D31:F0). PCH root ports
3784 * are D28:F* and therefore get probed before LPC, thus we can't
3785 * use pci_get_slot/pci_read_config_dword here.
3787 pci_bus_read_config_dword(dev
->bus
, PCI_DEVFN(31, 0),
3788 INTEL_LPC_RCBA_REG
, &rcba
);
3789 if (!(rcba
& INTEL_LPC_RCBA_ENABLE
))
3792 rcba_mem
= ioremap_nocache(rcba
& INTEL_LPC_RCBA_MASK
,
3793 PAGE_ALIGN(INTEL_UPDCR_REG
));
3798 * The BSPR can disallow peer cycles, but it's set by soft strap and
3799 * therefore read-only. If both posted and non-posted peer cycles are
3800 * disallowed, we're ok. If either are allowed, then we need to use
3801 * the UPDCR to disable peer decodes for each port. This provides the
3802 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
3804 bspr
= readl(rcba_mem
+ INTEL_BSPR_REG
);
3805 bspr
&= INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
;
3806 if (bspr
!= (INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
)) {
3807 updcr
= readl(rcba_mem
+ INTEL_UPDCR_REG
);
3808 if (updcr
& INTEL_UPDCR_REG_MASK
) {
3809 dev_info(&dev
->dev
, "Disabling UPDCR peer decodes\n");
3810 updcr
&= ~INTEL_UPDCR_REG_MASK
;
3811 writel(updcr
, rcba_mem
+ INTEL_UPDCR_REG
);
3819 /* Miscellaneous Port Configuration register */
3820 #define INTEL_MPC_REG 0xd8
3821 /* MPC: Invalid Receive Bus Number Check Enable */
3822 #define INTEL_MPC_REG_IRBNCE (1 << 26)
3824 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev
*dev
)
3829 * When enabled, the IRBNCE bit of the MPC register enables the
3830 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
3831 * ensures that requester IDs fall within the bus number range
3832 * of the bridge. Enable if not already.
3834 pci_read_config_dword(dev
, INTEL_MPC_REG
, &mpc
);
3835 if (!(mpc
& INTEL_MPC_REG_IRBNCE
)) {
3836 dev_info(&dev
->dev
, "Enabling MPC IRBNCE\n");
3837 mpc
|= INTEL_MPC_REG_IRBNCE
;
3838 pci_write_config_word(dev
, INTEL_MPC_REG
, mpc
);
3842 static int pci_quirk_enable_intel_pch_acs(struct pci_dev
*dev
)
3844 if (!pci_quirk_intel_pch_acs_match(dev
))
3847 if (pci_quirk_enable_intel_lpc_acs(dev
)) {
3848 dev_warn(&dev
->dev
, "Failed to enable Intel PCH ACS quirk\n");
3852 pci_quirk_enable_intel_rp_mpc_acs(dev
);
3854 dev
->dev_flags
|= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
;
3856 dev_info(&dev
->dev
, "Intel PCH root port ACS workaround enabled\n");
3861 static const struct pci_dev_enable_acs
{
3864 int (*enable_acs
)(struct pci_dev
*dev
);
3865 } pci_dev_enable_acs
[] = {
3866 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_enable_intel_pch_acs
},
3870 void pci_dev_specific_enable_acs(struct pci_dev
*dev
)
3872 const struct pci_dev_enable_acs
*i
;
3875 for (i
= pci_dev_enable_acs
; i
->enable_acs
; i
++) {
3876 if ((i
->vendor
== dev
->vendor
||
3877 i
->vendor
== (u16
)PCI_ANY_ID
) &&
3878 (i
->device
== dev
->device
||
3879 i
->device
== (u16
)PCI_ANY_ID
)) {
3880 ret
= i
->enable_acs(dev
);