2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
30 static void pbus_assign_resources_sorted(const struct pci_bus
*bus
)
34 struct resource_list head
, *list
, *tmp
;
38 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
39 u16
class = dev
->class >> 8;
41 /* Don't touch classless devices or host bridges or ioapics. */
42 if (class == PCI_CLASS_NOT_DEFINED
||
43 class == PCI_CLASS_BRIDGE_HOST
)
46 /* Don't touch ioapic devices already enabled by firmware */
47 if (class == PCI_CLASS_SYSTEM_PIC
) {
49 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
50 if (command
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
))
54 pdev_sort_resources(dev
, &head
);
57 for (list
= head
.next
; list
;) {
59 idx
= res
- &list
->dev
->resource
[0];
60 if (pci_assign_resource(list
->dev
, idx
)) {
61 /* FIXME: get rid of this */
72 void pci_setup_cardbus(struct pci_bus
*bus
)
74 struct pci_dev
*bridge
= bus
->self
;
75 struct pci_bus_region region
;
77 dev_info(&bridge
->dev
, "CardBus bridge, secondary bus %04x:%02x\n",
78 pci_domain_nr(bus
), bus
->number
);
80 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[0]);
81 if (bus
->resource
[0]->flags
& IORESOURCE_IO
) {
83 * The IO resource is allocated a range twice as large as it
84 * would normally need. This allows us to set both IO regs.
86 dev_info(&bridge
->dev
, " IO window: %#08lx-%#08lx\n",
87 (unsigned long)region
.start
,
88 (unsigned long)region
.end
);
89 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_0
,
91 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_0
,
95 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[1]);
96 if (bus
->resource
[1]->flags
& IORESOURCE_IO
) {
97 dev_info(&bridge
->dev
, " IO window: %#08lx-%#08lx\n",
98 (unsigned long)region
.start
,
99 (unsigned long)region
.end
);
100 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_1
,
102 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_1
,
106 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[2]);
107 if (bus
->resource
[2]->flags
& IORESOURCE_MEM
) {
108 dev_info(&bridge
->dev
, " PREFETCH window: %#08lx-%#08lx\n",
109 (unsigned long)region
.start
,
110 (unsigned long)region
.end
);
111 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_0
,
113 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_0
,
117 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[3]);
118 if (bus
->resource
[3]->flags
& IORESOURCE_MEM
) {
119 dev_info(&bridge
->dev
, " MEM window: %#08lx-%#08lx\n",
120 (unsigned long)region
.start
,
121 (unsigned long)region
.end
);
122 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_1
,
124 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_1
,
128 EXPORT_SYMBOL(pci_setup_cardbus
);
130 /* Initialize bridges with base/limit values we have collected.
131 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
132 requires that if there is no I/O ports or memory behind the
133 bridge, corresponding range must be turned off by writing base
134 value greater than limit to the bridge's base/limit registers.
136 Note: care must be taken when updating I/O base/limit registers
137 of bridges which support 32-bit I/O. This update requires two
138 config space writes, so it's quite possible that an I/O window of
139 the bridge will have some undesirable address (e.g. 0) after the
140 first write. Ditto 64-bit prefetchable MMIO. */
141 static void pci_setup_bridge(struct pci_bus
*bus
)
143 struct pci_dev
*bridge
= bus
->self
;
144 struct pci_bus_region region
;
145 u32 l
, bu
, lu
, io_upper16
;
148 if (pci_is_enabled(bridge
))
151 dev_info(&bridge
->dev
, "PCI bridge, secondary bus %04x:%02x\n",
152 pci_domain_nr(bus
), bus
->number
);
154 /* Set up the top and bottom of the PCI I/O segment for this bus. */
155 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[0]);
156 if (bus
->resource
[0]->flags
& IORESOURCE_IO
) {
157 pci_read_config_dword(bridge
, PCI_IO_BASE
, &l
);
159 l
|= (region
.start
>> 8) & 0x00f0;
160 l
|= region
.end
& 0xf000;
161 /* Set up upper 16 bits of I/O base/limit. */
162 io_upper16
= (region
.end
& 0xffff0000) | (region
.start
>> 16);
163 dev_info(&bridge
->dev
, " IO window: %#04lx-%#04lx\n",
164 (unsigned long)region
.start
,
165 (unsigned long)region
.end
);
168 /* Clear upper 16 bits of I/O base/limit. */
171 dev_info(&bridge
->dev
, " IO window: disabled\n");
173 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
174 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, 0x0000ffff);
175 /* Update lower 16 bits of I/O base/limit. */
176 pci_write_config_dword(bridge
, PCI_IO_BASE
, l
);
177 /* Update upper 16 bits of I/O base/limit. */
178 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, io_upper16
);
180 /* Set up the top and bottom of the PCI Memory segment
182 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[1]);
183 if (bus
->resource
[1]->flags
& IORESOURCE_MEM
) {
184 l
= (region
.start
>> 16) & 0xfff0;
185 l
|= region
.end
& 0xfff00000;
186 dev_info(&bridge
->dev
, " MEM window: %#08lx-%#08lx\n",
187 (unsigned long)region
.start
,
188 (unsigned long)region
.end
);
192 dev_info(&bridge
->dev
, " MEM window: disabled\n");
194 pci_write_config_dword(bridge
, PCI_MEMORY_BASE
, l
);
196 /* Clear out the upper 32 bits of PREF limit.
197 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
198 disables PREF range, which is ok. */
199 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, 0);
201 /* Set up PREF base/limit. */
204 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[2]);
205 if (bus
->resource
[2]->flags
& IORESOURCE_PREFETCH
) {
207 l
= (region
.start
>> 16) & 0xfff0;
208 l
|= region
.end
& 0xfff00000;
209 if (bus
->resource
[2]->flags
& IORESOURCE_MEM_64
) {
211 bu
= upper_32_bits(region
.start
);
212 lu
= upper_32_bits(region
.end
);
215 dev_info(&bridge
->dev
, " PREFETCH window: %#0*llx-%#0*llx\n",
216 width
, (unsigned long long)region
.start
,
217 width
, (unsigned long long)region
.end
);
221 dev_info(&bridge
->dev
, " PREFETCH window: disabled\n");
223 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, l
);
226 /* Set the upper 32 bits of PREF base & limit. */
227 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, bu
);
228 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, lu
);
231 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
, bus
->bridge_ctl
);
234 /* Check whether the bridge supports optional I/O and
235 prefetchable memory ranges. If not, the respective
236 base/limit registers must be read-only and read as 0. */
237 static void pci_bridge_check_ranges(struct pci_bus
*bus
)
241 struct pci_dev
*bridge
= bus
->self
;
242 struct resource
*b_res
;
244 b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
245 b_res
[1].flags
|= IORESOURCE_MEM
;
247 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
249 pci_write_config_word(bridge
, PCI_IO_BASE
, 0xf0f0);
250 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
251 pci_write_config_word(bridge
, PCI_IO_BASE
, 0x0);
254 b_res
[0].flags
|= IORESOURCE_IO
;
255 /* DECchip 21050 pass 2 errata: the bridge may miss an address
256 disconnect boundary by one PCI data phase.
257 Workaround: do not use prefetching on this device. */
258 if (bridge
->vendor
== PCI_VENDOR_ID_DEC
&& bridge
->device
== 0x0001)
260 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
262 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
,
264 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
265 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, 0x0);
268 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
269 if ((pmem
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
)
270 b_res
[2].flags
|= IORESOURCE_MEM_64
;
273 /* double check if bridge does support 64 bit pref */
274 if (b_res
[2].flags
& IORESOURCE_MEM_64
) {
275 u32 mem_base_hi
, tmp
;
276 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
278 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
280 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &tmp
);
282 b_res
[2].flags
&= ~IORESOURCE_MEM_64
;
283 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
288 /* Helper function for sizing routines: find first available
289 bus resource of a given type. Note: we intentionally skip
290 the bus resources which have already been assigned (that is,
291 have non-NULL parent resource). */
292 static struct resource
*find_free_bus_resource(struct pci_bus
*bus
, unsigned long type
)
296 unsigned long type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
|
299 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
300 r
= bus
->resource
[i
];
301 if (r
== &ioport_resource
|| r
== &iomem_resource
)
303 if (r
&& (r
->flags
& type_mask
) == type
&& !r
->parent
)
309 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
310 since these windows have 4K granularity and the IO ranges
311 of non-bridge PCI devices are limited to 256 bytes.
312 We must be careful with the ISA aliasing though. */
313 static void pbus_size_io(struct pci_bus
*bus
)
316 struct resource
*b_res
= find_free_bus_resource(bus
, IORESOURCE_IO
);
317 unsigned long size
= 0, size1
= 0;
322 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
325 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
326 struct resource
*r
= &dev
->resource
[i
];
327 unsigned long r_size
;
329 if (r
->parent
|| !(r
->flags
& IORESOURCE_IO
))
331 r_size
= resource_size(r
);
334 /* Might be re-aligned for ISA */
340 /* To be fixed in 2.5: we should have sort of HAVE_ISA
341 flag in the struct pci_bus. */
342 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
343 size
= (size
& 0xff) + ((size
& ~0xffUL
) << 2);
345 size
= ALIGN(size
+ size1
, 4096);
350 /* Alignment of the IO window is always 4K */
352 b_res
->end
= b_res
->start
+ size
- 1;
353 b_res
->flags
|= IORESOURCE_STARTALIGN
;
356 /* Calculate the size of the bus and minimal alignment which
357 guarantees that all child resources fit in this size. */
358 static int pbus_size_mem(struct pci_bus
*bus
, unsigned long mask
, unsigned long type
)
361 resource_size_t min_align
, align
, size
;
362 resource_size_t aligns
[12]; /* Alignments from 1Mb to 2Gb */
363 int order
, max_order
;
364 struct resource
*b_res
= find_free_bus_resource(bus
, type
);
365 unsigned int mem64_mask
= 0;
370 memset(aligns
, 0, sizeof(aligns
));
374 mem64_mask
= b_res
->flags
& IORESOURCE_MEM_64
;
375 b_res
->flags
&= ~IORESOURCE_MEM_64
;
377 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
380 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
381 struct resource
*r
= &dev
->resource
[i
];
382 resource_size_t r_size
;
384 if (r
->parent
|| (r
->flags
& mask
) != type
)
386 r_size
= resource_size(r
);
387 /* For bridges size != alignment */
388 align
= resource_alignment(r
);
389 order
= __ffs(align
) - 20;
391 dev_warn(&dev
->dev
, "BAR %d bad alignment %llx: "
392 "%pR\n", i
, (unsigned long long)align
, r
);
399 /* Exclude ranges with size > align from
400 calculation of the alignment. */
402 aligns
[order
] += align
;
403 if (order
> max_order
)
405 mem64_mask
&= r
->flags
& IORESOURCE_MEM_64
;
411 for (order
= 0; order
<= max_order
; order
++) {
412 resource_size_t align1
= 1;
414 align1
<<= (order
+ 20);
418 else if (ALIGN(align
+ min_align
, min_align
) < align1
)
419 min_align
= align1
>> 1;
420 align
+= aligns
[order
];
422 size
= ALIGN(size
, min_align
);
427 b_res
->start
= min_align
;
428 b_res
->end
= size
+ min_align
- 1;
429 b_res
->flags
|= IORESOURCE_STARTALIGN
;
430 b_res
->flags
|= mem64_mask
;
434 static void pci_bus_size_cardbus(struct pci_bus
*bus
)
436 struct pci_dev
*bridge
= bus
->self
;
437 struct resource
*b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
441 * Reserve some resources for CardBus. We reserve
442 * a fixed amount of bus space for CardBus bridges.
445 b_res
[0].end
= pci_cardbus_io_size
- 1;
446 b_res
[0].flags
|= IORESOURCE_IO
| IORESOURCE_SIZEALIGN
;
449 b_res
[1].end
= pci_cardbus_io_size
- 1;
450 b_res
[1].flags
|= IORESOURCE_IO
| IORESOURCE_SIZEALIGN
;
453 * Check whether prefetchable memory is supported
456 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
457 if (!(ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
)) {
458 ctrl
|= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
;
459 pci_write_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, ctrl
);
460 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
464 * If we have prefetchable memory support, allocate
465 * two regions. Otherwise, allocate one region of
468 if (ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
) {
470 b_res
[2].end
= pci_cardbus_mem_size
- 1;
471 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
| IORESOURCE_SIZEALIGN
;
474 b_res
[3].end
= pci_cardbus_mem_size
- 1;
475 b_res
[3].flags
|= IORESOURCE_MEM
| IORESOURCE_SIZEALIGN
;
478 b_res
[3].end
= pci_cardbus_mem_size
* 2 - 1;
479 b_res
[3].flags
|= IORESOURCE_MEM
| IORESOURCE_SIZEALIGN
;
483 void __ref
pci_bus_size_bridges(struct pci_bus
*bus
)
486 unsigned long mask
, prefmask
;
488 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
489 struct pci_bus
*b
= dev
->subordinate
;
493 switch (dev
->class >> 8) {
494 case PCI_CLASS_BRIDGE_CARDBUS
:
495 pci_bus_size_cardbus(b
);
498 case PCI_CLASS_BRIDGE_PCI
:
500 pci_bus_size_bridges(b
);
509 switch (bus
->self
->class >> 8) {
510 case PCI_CLASS_BRIDGE_CARDBUS
:
511 /* don't size cardbuses yet. */
514 case PCI_CLASS_BRIDGE_PCI
:
515 pci_bridge_check_ranges(bus
);
518 /* If the bridge supports prefetchable range, size it
519 separately. If it doesn't, or its prefetchable window
520 has already been allocated by arch code, try
521 non-prefetchable range for both types of PCI memory
523 mask
= IORESOURCE_MEM
;
524 prefmask
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
525 if (pbus_size_mem(bus
, prefmask
, prefmask
))
526 mask
= prefmask
; /* Success, size non-prefetch only. */
527 pbus_size_mem(bus
, mask
, IORESOURCE_MEM
);
531 EXPORT_SYMBOL(pci_bus_size_bridges
);
533 void __ref
pci_bus_assign_resources(const struct pci_bus
*bus
)
538 pbus_assign_resources_sorted(bus
);
540 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
541 b
= dev
->subordinate
;
545 pci_bus_assign_resources(b
);
547 switch (dev
->class >> 8) {
548 case PCI_CLASS_BRIDGE_PCI
:
552 case PCI_CLASS_BRIDGE_CARDBUS
:
553 pci_setup_cardbus(b
);
557 dev_info(&dev
->dev
, "not setting up bridge for bus "
558 "%04x:%02x\n", pci_domain_nr(b
), b
->number
);
563 EXPORT_SYMBOL(pci_bus_assign_resources
);
565 static void pci_bus_dump_res(struct pci_bus
*bus
)
569 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
570 struct resource
*res
= bus
->resource
[i
];
571 if (!res
|| !res
->end
)
574 dev_printk(KERN_DEBUG
, &bus
->dev
, "resource %d %s %pR\n", i
,
575 (res
->flags
& IORESOURCE_IO
) ? "io: " :
576 ((res
->flags
& IORESOURCE_PREFETCH
)? "pref mem":"mem:"),
581 static void pci_bus_dump_resources(struct pci_bus
*bus
)
587 pci_bus_dump_res(bus
);
589 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
590 b
= dev
->subordinate
;
594 pci_bus_dump_resources(b
);
599 pci_assign_unassigned_resources(void)
603 /* Depth first, calculate sizes and alignments of all
604 subordinate buses. */
605 list_for_each_entry(bus
, &pci_root_buses
, node
) {
606 pci_bus_size_bridges(bus
);
608 /* Depth last, allocate resources and update the hardware. */
609 list_for_each_entry(bus
, &pci_root_buses
, node
) {
610 pci_bus_assign_resources(bus
);
611 pci_enable_bridges(bus
);
614 /* dump the resource on buses */
615 list_for_each_entry(bus
, &pci_root_buses
, node
) {
616 pci_bus_dump_resources(bus
);