2 * drivers/pci/setup-res.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
29 void pci_update_resource(struct pci_dev
*dev
, int resno
)
31 struct pci_bus_region region
;
36 enum pci_bar_type type
;
37 struct resource
*res
= dev
->resource
+ resno
;
40 * Ignore resources for unimplemented BARs and unused resource slots
46 if (res
->flags
& IORESOURCE_UNSET
)
50 * Ignore non-moveable resources. This might be legacy resources for
51 * which no functional BAR register exists or another important
52 * system resource we shouldn't move around.
54 if (res
->flags
& IORESOURCE_PCI_FIXED
)
57 pcibios_resource_to_bus(dev
->bus
, ®ion
, res
);
59 new = region
.start
| (res
->flags
& PCI_REGION_FLAG_MASK
);
60 if (res
->flags
& IORESOURCE_IO
)
61 mask
= (u32
)PCI_BASE_ADDRESS_IO_MASK
;
63 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
65 reg
= pci_resource_bar(dev
, resno
, &type
);
68 if (type
!= pci_bar_unknown
) {
69 if (!(res
->flags
& IORESOURCE_ROM_ENABLE
))
71 new |= PCI_ROM_ADDRESS_ENABLE
;
75 * We can't update a 64-bit BAR atomically, so when possible,
76 * disable decoding so that a half-updated BAR won't conflict
77 * with another device.
79 disable
= (res
->flags
& IORESOURCE_MEM_64
) && !dev
->mmio_always_on
;
81 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
82 pci_write_config_word(dev
, PCI_COMMAND
,
83 cmd
& ~PCI_COMMAND_MEMORY
);
86 pci_write_config_dword(dev
, reg
, new);
87 pci_read_config_dword(dev
, reg
, &check
);
89 if ((new ^ check
) & mask
) {
90 dev_err(&dev
->dev
, "BAR %d: error updating (%#08x != %#08x)\n",
94 if (res
->flags
& IORESOURCE_MEM_64
) {
95 new = region
.start
>> 16 >> 16;
96 pci_write_config_dword(dev
, reg
+ 4, new);
97 pci_read_config_dword(dev
, reg
+ 4, &check
);
99 dev_err(&dev
->dev
, "BAR %d: error updating (high %#08x != %#08x)\n",
105 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
108 int pci_claim_resource(struct pci_dev
*dev
, int resource
)
110 struct resource
*res
= &dev
->resource
[resource
];
111 struct resource
*root
, *conflict
;
113 if (res
->flags
& IORESOURCE_UNSET
) {
114 dev_info(&dev
->dev
, "can't claim BAR %d %pR: no address assigned\n",
119 root
= pci_find_parent_resource(dev
, res
);
121 dev_info(&dev
->dev
, "can't claim BAR %d %pR: no compatible bridge window\n",
123 res
->flags
|= IORESOURCE_UNSET
;
127 conflict
= request_resource_conflict(root
, res
);
129 dev_info(&dev
->dev
, "can't claim BAR %d %pR: address conflict with %s %pR\n",
130 resource
, res
, conflict
->name
, conflict
);
131 res
->flags
|= IORESOURCE_UNSET
;
137 EXPORT_SYMBOL(pci_claim_resource
);
139 void pci_disable_bridge_window(struct pci_dev
*dev
)
141 dev_info(&dev
->dev
, "disabling bridge mem windows\n");
143 /* MMIO Base/Limit */
144 pci_write_config_dword(dev
, PCI_MEMORY_BASE
, 0x0000fff0);
146 /* Prefetchable MMIO Base/Limit */
147 pci_write_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, 0);
148 pci_write_config_dword(dev
, PCI_PREF_MEMORY_BASE
, 0x0000fff0);
149 pci_write_config_dword(dev
, PCI_PREF_BASE_UPPER32
, 0xffffffff);
153 * Generic function that returns a value indicating that the device's
154 * original BIOS BAR address was not saved and so is not available for
157 * Can be over-ridden by architecture specific code that implements
158 * reinstatement functionality rather than leaving it disabled when
159 * normal allocation attempts fail.
161 resource_size_t __weak
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
)
166 static int pci_revert_fw_address(struct resource
*res
, struct pci_dev
*dev
,
167 int resno
, resource_size_t size
)
169 struct resource
*root
, *conflict
;
170 resource_size_t fw_addr
, start
, end
;
172 fw_addr
= pcibios_retrieve_fw_addr(dev
, resno
);
178 res
->start
= fw_addr
;
179 res
->end
= res
->start
+ size
- 1;
181 root
= pci_find_parent_resource(dev
, res
);
183 if (res
->flags
& IORESOURCE_IO
)
184 root
= &ioport_resource
;
186 root
= &iomem_resource
;
189 dev_info(&dev
->dev
, "BAR %d: trying firmware assignment %pR\n",
191 conflict
= request_resource_conflict(root
, res
);
193 dev_info(&dev
->dev
, "BAR %d: %pR conflicts with %s %pR\n",
194 resno
, res
, conflict
->name
, conflict
);
202 static int __pci_assign_resource(struct pci_bus
*bus
, struct pci_dev
*dev
,
203 int resno
, resource_size_t size
, resource_size_t align
)
205 struct resource
*res
= dev
->resource
+ resno
;
209 min
= (res
->flags
& IORESOURCE_IO
) ? PCIBIOS_MIN_IO
: PCIBIOS_MIN_MEM
;
212 * First, try exact prefetching match. Even if a 64-bit
213 * prefetchable bridge window is below 4GB, we can't put a 32-bit
214 * prefetchable resource in it because pbus_size_mem() assumes a
215 * 64-bit window will contain no 32-bit resources. If we assign
216 * things differently than they were sized, not everything will fit.
218 ret
= pci_bus_alloc_resource(bus
, res
, size
, align
, min
,
219 IORESOURCE_PREFETCH
| IORESOURCE_MEM_64
,
220 pcibios_align_resource
, dev
);
225 * If the prefetchable window is only 32 bits wide, we can put
226 * 64-bit prefetchable resources in it.
228 if ((res
->flags
& (IORESOURCE_PREFETCH
| IORESOURCE_MEM_64
)) ==
229 (IORESOURCE_PREFETCH
| IORESOURCE_MEM_64
)) {
230 ret
= pci_bus_alloc_resource(bus
, res
, size
, align
, min
,
232 pcibios_align_resource
, dev
);
238 * If we didn't find a better match, we can put any memory resource
239 * in a non-prefetchable window. If this resource is 32 bits and
240 * non-prefetchable, the first call already tried the only possibility
241 * so we don't need to try again.
243 if (res
->flags
& (IORESOURCE_PREFETCH
| IORESOURCE_MEM_64
))
244 ret
= pci_bus_alloc_resource(bus
, res
, size
, align
, min
, 0,
245 pcibios_align_resource
, dev
);
250 static int _pci_assign_resource(struct pci_dev
*dev
, int resno
,
251 resource_size_t size
, resource_size_t min_align
)
257 while ((ret
= __pci_assign_resource(bus
, dev
, resno
, size
, min_align
))) {
258 if (!bus
->parent
|| !bus
->self
->transparent
)
266 int pci_assign_resource(struct pci_dev
*dev
, int resno
)
268 struct resource
*res
= dev
->resource
+ resno
;
269 resource_size_t align
, size
;
272 res
->flags
|= IORESOURCE_UNSET
;
273 align
= pci_resource_alignment(dev
, res
);
275 dev_info(&dev
->dev
, "BAR %d: can't assign %pR (bogus alignment)\n",
280 size
= resource_size(res
);
281 ret
= _pci_assign_resource(dev
, resno
, size
, align
);
284 * If we failed to assign anything, let's try the address
285 * where firmware left it. That at least has a chance of
286 * working, which is better than just leaving it disabled.
289 dev_info(&dev
->dev
, "BAR %d: no space for %pR\n", resno
, res
);
290 ret
= pci_revert_fw_address(res
, dev
, resno
, size
);
294 dev_info(&dev
->dev
, "BAR %d: failed to assign %pR\n", resno
,
299 res
->flags
&= ~IORESOURCE_UNSET
;
300 res
->flags
&= ~IORESOURCE_STARTALIGN
;
301 dev_info(&dev
->dev
, "BAR %d: assigned %pR\n", resno
, res
);
302 if (resno
< PCI_BRIDGE_RESOURCES
)
303 pci_update_resource(dev
, resno
);
307 EXPORT_SYMBOL(pci_assign_resource
);
309 int pci_reassign_resource(struct pci_dev
*dev
, int resno
, resource_size_t addsize
,
310 resource_size_t min_align
)
312 struct resource
*res
= dev
->resource
+ resno
;
314 resource_size_t new_size
;
318 res
->flags
|= IORESOURCE_UNSET
;
320 dev_info(&dev
->dev
, "BAR %d: can't reassign an unassigned resource %pR\n",
325 /* already aligned with min_align */
326 new_size
= resource_size(res
) + addsize
;
327 ret
= _pci_assign_resource(dev
, resno
, new_size
, min_align
);
330 dev_info(&dev
->dev
, "BAR %d: %pR (failed to expand by %#llx)\n",
331 resno
, res
, (unsigned long long) addsize
);
335 res
->flags
&= ~IORESOURCE_UNSET
;
336 res
->flags
&= ~IORESOURCE_STARTALIGN
;
337 dev_info(&dev
->dev
, "BAR %d: reassigned %pR (expanded by %#llx)\n",
338 resno
, res
, (unsigned long long) addsize
);
339 if (resno
< PCI_BRIDGE_RESOURCES
)
340 pci_update_resource(dev
, resno
);
345 int pci_enable_resources(struct pci_dev
*dev
, int mask
)
351 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
354 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
355 if (!(mask
& (1 << i
)))
358 r
= &dev
->resource
[i
];
360 if (!(r
->flags
& (IORESOURCE_IO
| IORESOURCE_MEM
)))
362 if ((i
== PCI_ROM_RESOURCE
) &&
363 (!(r
->flags
& IORESOURCE_ROM_ENABLE
)))
366 if (r
->flags
& IORESOURCE_UNSET
) {
367 dev_err(&dev
->dev
, "can't enable device: BAR %d %pR not assigned\n",
373 dev_err(&dev
->dev
, "can't enable device: BAR %d %pR not claimed\n",
378 if (r
->flags
& IORESOURCE_IO
)
379 cmd
|= PCI_COMMAND_IO
;
380 if (r
->flags
& IORESOURCE_MEM
)
381 cmd
|= PCI_COMMAND_MEMORY
;
384 if (cmd
!= old_cmd
) {
385 dev_info(&dev
->dev
, "enabling device (%04x -> %04x)\n",
387 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);