drivers/phy/phy-rockchip-usb.c

   1 /*
   2  * Rockchip usb PHY driver
   3  *
   4  * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/phy/phy.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/regmap.h>
  31 #include <linux/mfd/syscon.h>
  32
  33 /*
  34  * The higher 16-bit of this register is used for write protection
  35  * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
  36  */
  37 #define SIDDQ_WRITE_ENA BIT(29)
  38 #define SIDDQ_ON                BIT(13)
  39 #define SIDDQ_OFF               (0 << 13)
  40
  41 struct rockchip_usb_phys {
  42         int reg;
  43         const char *pll_name;
  44 };
  45
  46 struct rockchip_usb_phy_pdata {
  47         struct rockchip_usb_phys *phys;
  48 };
  49
  50 struct rockchip_usb_phy_base {
  51         struct device *dev;
  52         struct regmap *reg_base;
  53         const struct rockchip_usb_phy_pdata *pdata;
  54 };
  55
  56 struct rockchip_usb_phy {
  57         struct rockchip_usb_phy_base *base;
  58         struct device_node *np;
  59         unsigned int    reg_offset;
  60         struct clk      *clk;
  61         struct clk      *clk480m;
  62         struct clk_hw   clk480m_hw;
  63         struct phy      *phy;
  64 };
  65
  66 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
  67                                            bool siddq)
  68 {
  69         return regmap_write(phy->base->reg_base, phy->reg_offset,
  70                             SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
  71 }
  72
  73 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
  74                                                 unsigned long parent_rate)
  75 {
  76         return 480000000;
  77 }
  78
  79 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
  80 {
  81         struct rockchip_usb_phy *phy = container_of(hw,
  82                                                     struct rockchip_usb_phy,
  83                                                     clk480m_hw);
  84
  85         /* Power down usb phy analog blocks by set siddq 1 */
  86         rockchip_usb_phy_power(phy, 1);
  87 }
  88
  89 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
  90 {
  91         struct rockchip_usb_phy *phy = container_of(hw,
  92                                                     struct rockchip_usb_phy,
  93                                                     clk480m_hw);
  94
  95         /* Power up usb phy analog blocks by set siddq 0 */
  96         return rockchip_usb_phy_power(phy, 0);
  97 }
  98
  99 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
 100 {
 101         struct rockchip_usb_phy *phy = container_of(hw,
 102                                                     struct rockchip_usb_phy,
 103                                                     clk480m_hw);
 104         int ret;
 105         u32 val;
 106
 107         ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
 108         if (ret < 0)
 109                 return ret;
 110
 111         return (val & SIDDQ_ON) ? 0 : 1;
 112 }
 113
 114 static const struct clk_ops rockchip_usb_phy480m_ops = {
 115         .enable = rockchip_usb_phy480m_enable,
 116         .disable = rockchip_usb_phy480m_disable,
 117         .is_enabled = rockchip_usb_phy480m_is_enabled,
 118         .recalc_rate = rockchip_usb_phy480m_recalc_rate,
 119 };
 120
 121 static int rockchip_usb_phy_power_off(struct phy *_phy)
 122 {
 123         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 124
 125         clk_disable_unprepare(phy->clk480m);
 126
 127         return 0;
 128 }
 129
 130 static int rockchip_usb_phy_power_on(struct phy *_phy)
 131 {
 132         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 133
 134         return clk_prepare_enable(phy->clk480m);
 135 }
 136
 137 static const struct phy_ops ops = {
 138         .power_on       = rockchip_usb_phy_power_on,
 139         .power_off      = rockchip_usb_phy_power_off,
 140         .owner          = THIS_MODULE,
 141 };
 142
 143 static void rockchip_usb_phy_action(void *data)
 144 {
 145         struct rockchip_usb_phy *rk_phy = data;
 146
 147         of_clk_del_provider(rk_phy->np);
 148         clk_unregister(rk_phy->clk480m);
 149
 150         if (rk_phy->clk)
 151                 clk_put(rk_phy->clk);
 152 }
 153
 154 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 155                                  struct device_node *child)
 156 {
 157         struct rockchip_usb_phy *rk_phy;
 158         unsigned int reg_offset;
 159         const char *clk_name;
 160         struct clk_init_data init;
 161         int err, i;
 162
 163         rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
 164         if (!rk_phy)
 165                 return -ENOMEM;
 166
 167         rk_phy->base = base;
 168         rk_phy->np = child;
 169
 170         if (of_property_read_u32(child, "reg", &reg_offset)) {
 171                 dev_err(base->dev, "missing reg property in node %s\n",
 172                         child->name);
 173                 return -EINVAL;
 174         }
 175
 176         rk_phy->reg_offset = reg_offset;
 177
 178         rk_phy->clk = of_clk_get_by_name(child, "phyclk");
 179         if (IS_ERR(rk_phy->clk))
 180                 rk_phy->clk = NULL;
 181
 182         i = 0;
 183         init.name = NULL;
 184         while (base->pdata->phys[i].reg) {
 185                 if (base->pdata->phys[i].reg == reg_offset) {
 186                         init.name = base->pdata->phys[i].pll_name;
 187                         break;
 188                 }
 189                 i++;
 190         }
 191
 192         if (!init.name) {
 193                 dev_err(base->dev, "phy data not found\n");
 194                 return -EINVAL;
 195         }
 196
 197         if (rk_phy->clk) {
 198                 clk_name = __clk_get_name(rk_phy->clk);
 199                 init.flags = 0;
 200                 init.parent_names = &clk_name;
 201                 init.num_parents = 1;
 202         } else {
 203                 init.flags = CLK_IS_ROOT;
 204                 init.parent_names = NULL;
 205                 init.num_parents = 0;
 206         }
 207
 208         init.ops = &rockchip_usb_phy480m_ops;
 209         rk_phy->clk480m_hw.init = &init;
 210
 211         rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
 212         if (IS_ERR(rk_phy->clk480m)) {
 213                 err = PTR_ERR(rk_phy->clk480m);
 214                 goto err_clk;
 215         }
 216
 217         err = of_clk_add_provider(child, of_clk_src_simple_get,
 218                                   rk_phy->clk480m);
 219         if (err < 0)
 220                 goto err_clk_prov;
 221
 222         err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
 223         if (err)
 224                 goto err_devm_action;
 225
 226         rk_phy->phy = devm_phy_create(base->dev, child, &ops);
 227         if (IS_ERR(rk_phy->phy)) {
 228                 dev_err(base->dev, "failed to create PHY\n");
 229                 return PTR_ERR(rk_phy->phy);
 230         }
 231         phy_set_drvdata(rk_phy->phy, rk_phy);
 232
 233         /* only power up usb phy when it use, so disable it when init*/
 234         return rockchip_usb_phy_power(rk_phy, 1);
 235
 236 err_devm_action:
 237         of_clk_del_provider(child);
 238 err_clk_prov:
 239         clk_unregister(rk_phy->clk480m);
 240 err_clk:
 241         if (rk_phy->clk)
 242                 clk_put(rk_phy->clk);
 243         return err;
 244 }
 245
 246 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
 247         .phys = (struct rockchip_usb_phys[]){
 248                 { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
 249                 { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
 250                 { /* sentinel */ }
 251         },
 252 };
 253
 254 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
 255         .phys = (struct rockchip_usb_phys[]){
 256                 { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
 257                 { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
 258                 { /* sentinel */ }
 259         },
 260 };
 261
 262 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
 263         .phys = (struct rockchip_usb_phys[]){
 264                 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
 265                 { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
 266                 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
 267                 { /* sentinel */ }
 268         },
 269 };
 270
 271 static int rockchip_usb_phy_probe(struct platform_device *pdev)
 272 {
 273         struct device *dev = &pdev->dev;
 274         struct rockchip_usb_phy_base *phy_base;
 275         struct phy_provider *phy_provider;
 276         const struct of_device_id *match;
 277         struct device_node *child;
 278         int err;
 279
 280         phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
 281         if (!phy_base)
 282                 return -ENOMEM;
 283
 284         match = of_match_device(dev->driver->of_match_table, dev);
 285         if (!match || !match->data) {
 286                 dev_err(dev, "missing phy data\n");
 287                 return -EINVAL;
 288         }
 289
 290         phy_base->pdata = match->data;
 291
 292         phy_base->dev = dev;
 293         phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node,
 294                                                              "rockchip,grf");
 295         if (IS_ERR(phy_base->reg_base)) {
 296                 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
 297                 return PTR_ERR(phy_base->reg_base);
 298         }
 299
 300         for_each_available_child_of_node(dev->of_node, child) {
 301                 err = rockchip_usb_phy_init(phy_base, child);
 302                 if (err) {
 303                         of_node_put(child);
 304                         return err;
 305                 }
 306         }
 307
 308         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 309         return PTR_ERR_OR_ZERO(phy_provider);
 310 }
 311
 312 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
 313         { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
 314         { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
 315         { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
 316         {}
 317 };
 318
 319 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
 320
 321 static struct platform_driver rockchip_usb_driver = {
 322         .probe          = rockchip_usb_phy_probe,
 323         .driver         = {
 324                 .name   = "rockchip-usb-phy",
 325                 .of_match_table = rockchip_usb_phy_dt_ids,
 326         },
 327 };
 328
 329 module_platform_driver(rockchip_usb_driver);
 330
 331 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
 332 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
 333 MODULE_LICENSE("GPL v2");