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include/linux/mlx5/device.h: kill BUILD_BUG_ON()s
[deliverable/linux.git] / drivers / pinctrl / pinctrl-amd.c
1 /*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
37
38 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
39 {
40 unsigned long flags;
41 u32 pin_reg;
42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
43
44 spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
47 writel(pin_reg, gpio_dev->base + offset * 4);
48 spin_unlock_irqrestore(&gpio_dev->lock, flags);
49
50 return 0;
51 }
52
53 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
54 int value)
55 {
56 u32 pin_reg;
57 unsigned long flags;
58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
59
60 spin_lock_irqsave(&gpio_dev->lock, flags);
61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
63 if (value)
64 pin_reg |= BIT(OUTPUT_VALUE_OFF);
65 else
66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
68 spin_unlock_irqrestore(&gpio_dev->lock, flags);
69
70 return 0;
71 }
72
73 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
74 {
75 u32 pin_reg;
76 unsigned long flags;
77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
78
79 spin_lock_irqsave(&gpio_dev->lock, flags);
80 pin_reg = readl(gpio_dev->base + offset * 4);
81 spin_unlock_irqrestore(&gpio_dev->lock, flags);
82
83 return !!(pin_reg & BIT(PIN_STS_OFF));
84 }
85
86 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
87 {
88 u32 pin_reg;
89 unsigned long flags;
90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
91
92 spin_lock_irqsave(&gpio_dev->lock, flags);
93 pin_reg = readl(gpio_dev->base + offset * 4);
94 if (value)
95 pin_reg |= BIT(OUTPUT_VALUE_OFF);
96 else
97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
98 writel(pin_reg, gpio_dev->base + offset * 4);
99 spin_unlock_irqrestore(&gpio_dev->lock, flags);
100 }
101
102 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
103 unsigned debounce)
104 {
105 u32 time;
106 u32 pin_reg;
107 int ret = 0;
108 unsigned long flags;
109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
110
111 spin_lock_irqsave(&gpio_dev->lock, flags);
112 pin_reg = readl(gpio_dev->base + offset * 4);
113
114 if (debounce) {
115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
116 pin_reg &= ~DB_TMR_OUT_MASK;
117 /*
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
120 Time
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
125 */
126
127 if (debounce < 61) {
128 pin_reg |= 1;
129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
131 } else if (debounce < 976) {
132 time = debounce / 61;
133 pin_reg |= time & DB_TMR_OUT_MASK;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 3900) {
137 time = debounce / 244;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 250000) {
142 time = debounce / 15600;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg |= BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 1000000) {
147 time = debounce / 62500;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
151 } else {
152 pin_reg &= ~DB_CNTRl_MASK;
153 ret = -EINVAL;
154 }
155 } else {
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg &= ~DB_TMR_OUT_MASK;
159 pin_reg &= ~DB_CNTRl_MASK;
160 }
161 writel(pin_reg, gpio_dev->base + offset * 4);
162 spin_unlock_irqrestore(&gpio_dev->lock, flags);
163
164 return ret;
165 }
166
167 #ifdef CONFIG_DEBUG_FS
168 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
169 {
170 u32 pin_reg;
171 unsigned long flags;
172 unsigned int bank, i, pin_num;
173 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
174
175 char *level_trig;
176 char *active_level;
177 char *interrupt_enable;
178 char *interrupt_mask;
179 char *wake_cntrl0;
180 char *wake_cntrl1;
181 char *wake_cntrl2;
182 char *pin_sts;
183 char *pull_up_sel;
184 char *pull_up_enable;
185 char *pull_down_enable;
186 char *output_value;
187 char *output_enable;
188
189 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
190 seq_printf(s, "GPIO bank%d\t", bank);
191
192 switch (bank) {
193 case 0:
194 i = 0;
195 pin_num = AMD_GPIO_PINS_BANK0;
196 break;
197 case 1:
198 i = 64;
199 pin_num = AMD_GPIO_PINS_BANK1 + i;
200 break;
201 case 2:
202 i = 128;
203 pin_num = AMD_GPIO_PINS_BANK2 + i;
204 break;
205 }
206
207 for (; i < pin_num; i++) {
208 seq_printf(s, "pin%d\t", i);
209 spin_lock_irqsave(&gpio_dev->lock, flags);
210 pin_reg = readl(gpio_dev->base + i * 4);
211 spin_unlock_irqrestore(&gpio_dev->lock, flags);
212
213 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
214 interrupt_enable = "interrupt is enabled|";
215
216 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
217 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
218 active_level = "Active low|";
219 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
220 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
221 active_level = "Active high|";
222 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
223 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
224 active_level = "Active on both|";
225 else
226 active_level = "Unknow Active level|";
227
228 if (pin_reg & BIT(LEVEL_TRIG_OFF))
229 level_trig = "Level trigger|";
230 else
231 level_trig = "Edge trigger|";
232
233 } else {
234 interrupt_enable =
235 "interrupt is disabled|";
236 active_level = " ";
237 level_trig = " ";
238 }
239
240 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
241 interrupt_mask =
242 "interrupt is unmasked|";
243 else
244 interrupt_mask =
245 "interrupt is masked|";
246
247 if (pin_reg & BIT(WAKE_CNTRL_OFF))
248 wake_cntrl0 = "enable wakeup in S0i3 state|";
249 else
250 wake_cntrl0 = "disable wakeup in S0i3 state|";
251
252 if (pin_reg & BIT(WAKE_CNTRL_OFF))
253 wake_cntrl1 = "enable wakeup in S3 state|";
254 else
255 wake_cntrl1 = "disable wakeup in S3 state|";
256
257 if (pin_reg & BIT(WAKE_CNTRL_OFF))
258 wake_cntrl2 = "enable wakeup in S4/S5 state|";
259 else
260 wake_cntrl2 = "disable wakeup in S4/S5 state|";
261
262 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
263 pull_up_enable = "pull-up is enabled|";
264 if (pin_reg & BIT(PULL_UP_SEL_OFF))
265 pull_up_sel = "8k pull-up|";
266 else
267 pull_up_sel = "4k pull-up|";
268 } else {
269 pull_up_enable = "pull-up is disabled|";
270 pull_up_sel = " ";
271 }
272
273 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
274 pull_down_enable = "pull-down is enabled|";
275 else
276 pull_down_enable = "Pull-down is disabled|";
277
278 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
279 pin_sts = " ";
280 output_enable = "output is enabled|";
281 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
282 output_value = "output is high|";
283 else
284 output_value = "output is low|";
285 } else {
286 output_enable = "output is disabled|";
287 output_value = " ";
288
289 if (pin_reg & BIT(PIN_STS_OFF))
290 pin_sts = "input is high|";
291 else
292 pin_sts = "input is low|";
293 }
294
295 seq_printf(s, "%s %s %s %s %s %s\n"
296 " %s %s %s %s %s %s %s 0x%x\n",
297 level_trig, active_level, interrupt_enable,
298 interrupt_mask, wake_cntrl0, wake_cntrl1,
299 wake_cntrl2, pin_sts, pull_up_sel,
300 pull_up_enable, pull_down_enable,
301 output_value, output_enable, pin_reg);
302 }
303 }
304 }
305 #else
306 #define amd_gpio_dbg_show NULL
307 #endif
308
309 static void amd_gpio_irq_enable(struct irq_data *d)
310 {
311 u32 pin_reg;
312 unsigned long flags;
313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
314 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
315
316 spin_lock_irqsave(&gpio_dev->lock, flags);
317 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
318 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
319 pin_reg |= BIT(INTERRUPT_MASK_OFF);
320 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
321 spin_unlock_irqrestore(&gpio_dev->lock, flags);
322 }
323
324 static void amd_gpio_irq_disable(struct irq_data *d)
325 {
326 u32 pin_reg;
327 unsigned long flags;
328 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
329 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
330
331 spin_lock_irqsave(&gpio_dev->lock, flags);
332 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
333 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
334 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
335 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
336 spin_unlock_irqrestore(&gpio_dev->lock, flags);
337 }
338
339 static void amd_gpio_irq_mask(struct irq_data *d)
340 {
341 u32 pin_reg;
342 unsigned long flags;
343 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
344 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
345
346 spin_lock_irqsave(&gpio_dev->lock, flags);
347 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
348 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
349 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
350 spin_unlock_irqrestore(&gpio_dev->lock, flags);
351 }
352
353 static void amd_gpio_irq_unmask(struct irq_data *d)
354 {
355 u32 pin_reg;
356 unsigned long flags;
357 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
358 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
359
360 spin_lock_irqsave(&gpio_dev->lock, flags);
361 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
362 pin_reg |= BIT(INTERRUPT_MASK_OFF);
363 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
364 spin_unlock_irqrestore(&gpio_dev->lock, flags);
365 }
366
367 static void amd_gpio_irq_eoi(struct irq_data *d)
368 {
369 u32 reg;
370 unsigned long flags;
371 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
372 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
373
374 spin_lock_irqsave(&gpio_dev->lock, flags);
375 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
376 reg |= EOI_MASK;
377 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
378 spin_unlock_irqrestore(&gpio_dev->lock, flags);
379 }
380
381 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
382 {
383 int ret = 0;
384 u32 pin_reg;
385 unsigned long flags;
386 u32 level_trig;
387 u32 active_level;
388 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
389 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
390
391 spin_lock_irqsave(&gpio_dev->lock, flags);
392 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
393
394 /*
395 * When level_trig is set EDGE and active_level is set HIGH in BIOS
396 * default settings, ignore incoming settings from client and use
397 * BIOS settings to configure GPIO register.
398 */
399 level_trig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF);
400 active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
401
402 if((!level_trig) &&
403 ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) {
404 type = IRQ_TYPE_EDGE_FALLING;
405 }
406
407 switch (type & IRQ_TYPE_SENSE_MASK) {
408 case IRQ_TYPE_EDGE_RISING:
409 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
410 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
411 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
412 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
413 irq_set_handler_locked(d, handle_edge_irq);
414 break;
415
416 case IRQ_TYPE_EDGE_FALLING:
417 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
418 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
419 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
420 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
421 irq_set_handler_locked(d, handle_edge_irq);
422 break;
423
424 case IRQ_TYPE_EDGE_BOTH:
425 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
426 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
427 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
428 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
429 irq_set_handler_locked(d, handle_edge_irq);
430 break;
431
432 case IRQ_TYPE_LEVEL_HIGH:
433 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
434 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
435 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
436 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
437 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
438 irq_set_handler_locked(d, handle_level_irq);
439 break;
440
441 case IRQ_TYPE_LEVEL_LOW:
442 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
443 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
444 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
445 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
446 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
447 irq_set_handler_locked(d, handle_level_irq);
448 break;
449
450 case IRQ_TYPE_NONE:
451 break;
452
453 default:
454 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
455 ret = -EINVAL;
456 }
457
458 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
459 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
460 spin_unlock_irqrestore(&gpio_dev->lock, flags);
461
462 return ret;
463 }
464
465 static void amd_irq_ack(struct irq_data *d)
466 {
467 /*
468 * based on HW design,there is no need to ack HW
469 * before handle current irq. But this routine is
470 * necessary for handle_edge_irq
471 */
472 }
473
474 static struct irq_chip amd_gpio_irqchip = {
475 .name = "amd_gpio",
476 .irq_ack = amd_irq_ack,
477 .irq_enable = amd_gpio_irq_enable,
478 .irq_disable = amd_gpio_irq_disable,
479 .irq_mask = amd_gpio_irq_mask,
480 .irq_unmask = amd_gpio_irq_unmask,
481 .irq_eoi = amd_gpio_irq_eoi,
482 .irq_set_type = amd_gpio_irq_set_type,
483 };
484
485 static void amd_gpio_irq_handler(struct irq_desc *desc)
486 {
487 u32 i;
488 u32 off;
489 u32 reg;
490 u32 pin_reg;
491 u64 reg64;
492 int handled = 0;
493 unsigned int irq;
494 unsigned long flags;
495 struct irq_chip *chip = irq_desc_get_chip(desc);
496 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
497 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
498
499 chained_irq_enter(chip, desc);
500 /*enable GPIO interrupt again*/
501 spin_lock_irqsave(&gpio_dev->lock, flags);
502 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
503 reg64 = reg;
504 reg64 = reg64 << 32;
505
506 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
507 reg64 |= reg;
508 spin_unlock_irqrestore(&gpio_dev->lock, flags);
509
510 /*
511 * first 46 bits indicates interrupt status.
512 * one bit represents four interrupt sources.
513 */
514 for (off = 0; off < 46 ; off++) {
515 if (reg64 & BIT(off)) {
516 for (i = 0; i < 4; i++) {
517 pin_reg = readl(gpio_dev->base +
518 (off * 4 + i) * 4);
519 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
520 (pin_reg & BIT(WAKE_STS_OFF))) {
521 irq = irq_find_mapping(gc->irqdomain,
522 off * 4 + i);
523 generic_handle_irq(irq);
524 writel(pin_reg,
525 gpio_dev->base
526 + (off * 4 + i) * 4);
527 handled++;
528 }
529 }
530 }
531 }
532
533 if (handled == 0)
534 handle_bad_irq(desc);
535
536 spin_lock_irqsave(&gpio_dev->lock, flags);
537 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
538 reg |= EOI_MASK;
539 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
540 spin_unlock_irqrestore(&gpio_dev->lock, flags);
541
542 chained_irq_exit(chip, desc);
543 }
544
545 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
546 {
547 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
548
549 return gpio_dev->ngroups;
550 }
551
552 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
553 unsigned group)
554 {
555 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
556
557 return gpio_dev->groups[group].name;
558 }
559
560 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
561 unsigned group,
562 const unsigned **pins,
563 unsigned *num_pins)
564 {
565 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
566
567 *pins = gpio_dev->groups[group].pins;
568 *num_pins = gpio_dev->groups[group].npins;
569 return 0;
570 }
571
572 static const struct pinctrl_ops amd_pinctrl_ops = {
573 .get_groups_count = amd_get_groups_count,
574 .get_group_name = amd_get_group_name,
575 .get_group_pins = amd_get_group_pins,
576 #ifdef CONFIG_OF
577 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
578 .dt_free_map = pinctrl_utils_free_map,
579 #endif
580 };
581
582 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
583 unsigned int pin,
584 unsigned long *config)
585 {
586 u32 pin_reg;
587 unsigned arg;
588 unsigned long flags;
589 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
590 enum pin_config_param param = pinconf_to_config_param(*config);
591
592 spin_lock_irqsave(&gpio_dev->lock, flags);
593 pin_reg = readl(gpio_dev->base + pin*4);
594 spin_unlock_irqrestore(&gpio_dev->lock, flags);
595 switch (param) {
596 case PIN_CONFIG_INPUT_DEBOUNCE:
597 arg = pin_reg & DB_TMR_OUT_MASK;
598 break;
599
600 case PIN_CONFIG_BIAS_PULL_DOWN:
601 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
602 break;
603
604 case PIN_CONFIG_BIAS_PULL_UP:
605 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
606 break;
607
608 case PIN_CONFIG_DRIVE_STRENGTH:
609 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
610 break;
611
612 default:
613 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
614 param);
615 return -ENOTSUPP;
616 }
617
618 *config = pinconf_to_config_packed(param, arg);
619
620 return 0;
621 }
622
623 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
624 unsigned long *configs, unsigned num_configs)
625 {
626 int i;
627 u32 arg;
628 int ret = 0;
629 u32 pin_reg;
630 unsigned long flags;
631 enum pin_config_param param;
632 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
633
634 spin_lock_irqsave(&gpio_dev->lock, flags);
635 for (i = 0; i < num_configs; i++) {
636 param = pinconf_to_config_param(configs[i]);
637 arg = pinconf_to_config_argument(configs[i]);
638 pin_reg = readl(gpio_dev->base + pin*4);
639
640 switch (param) {
641 case PIN_CONFIG_INPUT_DEBOUNCE:
642 pin_reg &= ~DB_TMR_OUT_MASK;
643 pin_reg |= arg & DB_TMR_OUT_MASK;
644 break;
645
646 case PIN_CONFIG_BIAS_PULL_DOWN:
647 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
648 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
649 break;
650
651 case PIN_CONFIG_BIAS_PULL_UP:
652 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
653 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
654 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
655 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
656 break;
657
658 case PIN_CONFIG_DRIVE_STRENGTH:
659 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
660 << DRV_STRENGTH_SEL_OFF);
661 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
662 << DRV_STRENGTH_SEL_OFF;
663 break;
664
665 default:
666 dev_err(&gpio_dev->pdev->dev,
667 "Invalid config param %04x\n", param);
668 ret = -ENOTSUPP;
669 }
670
671 writel(pin_reg, gpio_dev->base + pin*4);
672 }
673 spin_unlock_irqrestore(&gpio_dev->lock, flags);
674
675 return ret;
676 }
677
678 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
679 unsigned int group,
680 unsigned long *config)
681 {
682 const unsigned *pins;
683 unsigned npins;
684 int ret;
685
686 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
687 if (ret)
688 return ret;
689
690 if (amd_pinconf_get(pctldev, pins[0], config))
691 return -ENOTSUPP;
692
693 return 0;
694 }
695
696 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
697 unsigned group, unsigned long *configs,
698 unsigned num_configs)
699 {
700 const unsigned *pins;
701 unsigned npins;
702 int i, ret;
703
704 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
705 if (ret)
706 return ret;
707 for (i = 0; i < npins; i++) {
708 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
709 return -ENOTSUPP;
710 }
711 return 0;
712 }
713
714 static const struct pinconf_ops amd_pinconf_ops = {
715 .pin_config_get = amd_pinconf_get,
716 .pin_config_set = amd_pinconf_set,
717 .pin_config_group_get = amd_pinconf_group_get,
718 .pin_config_group_set = amd_pinconf_group_set,
719 };
720
721 static struct pinctrl_desc amd_pinctrl_desc = {
722 .pins = kerncz_pins,
723 .npins = ARRAY_SIZE(kerncz_pins),
724 .pctlops = &amd_pinctrl_ops,
725 .confops = &amd_pinconf_ops,
726 .owner = THIS_MODULE,
727 };
728
729 static int amd_gpio_probe(struct platform_device *pdev)
730 {
731 int ret = 0;
732 int irq_base;
733 struct resource *res;
734 struct amd_gpio *gpio_dev;
735
736 gpio_dev = devm_kzalloc(&pdev->dev,
737 sizeof(struct amd_gpio), GFP_KERNEL);
738 if (!gpio_dev)
739 return -ENOMEM;
740
741 spin_lock_init(&gpio_dev->lock);
742
743 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
744 if (!res) {
745 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
746 return -EINVAL;
747 }
748
749 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
750 resource_size(res));
751 if (!gpio_dev->base)
752 return -ENOMEM;
753
754 irq_base = platform_get_irq(pdev, 0);
755 if (irq_base < 0) {
756 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
757 return -EINVAL;
758 }
759
760 gpio_dev->pdev = pdev;
761 gpio_dev->gc.direction_input = amd_gpio_direction_input;
762 gpio_dev->gc.direction_output = amd_gpio_direction_output;
763 gpio_dev->gc.get = amd_gpio_get_value;
764 gpio_dev->gc.set = amd_gpio_set_value;
765 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
766 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
767
768 gpio_dev->gc.base = 0;
769 gpio_dev->gc.label = pdev->name;
770 gpio_dev->gc.owner = THIS_MODULE;
771 gpio_dev->gc.parent = &pdev->dev;
772 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
773 #if defined(CONFIG_OF_GPIO)
774 gpio_dev->gc.of_node = pdev->dev.of_node;
775 #endif
776
777 gpio_dev->groups = kerncz_groups;
778 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
779
780 amd_pinctrl_desc.name = dev_name(&pdev->dev);
781 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
782 gpio_dev);
783 if (IS_ERR(gpio_dev->pctrl)) {
784 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
785 return PTR_ERR(gpio_dev->pctrl);
786 }
787
788 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
789 if (ret)
790 return ret;
791
792 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
793 0, 0, TOTAL_NUMBER_OF_PINS);
794 if (ret) {
795 dev_err(&pdev->dev, "Failed to add pin range\n");
796 goto out2;
797 }
798
799 ret = gpiochip_irqchip_add(&gpio_dev->gc,
800 &amd_gpio_irqchip,
801 0,
802 handle_simple_irq,
803 IRQ_TYPE_NONE);
804 if (ret) {
805 dev_err(&pdev->dev, "could not add irqchip\n");
806 ret = -ENODEV;
807 goto out2;
808 }
809
810 gpiochip_set_chained_irqchip(&gpio_dev->gc,
811 &amd_gpio_irqchip,
812 irq_base,
813 amd_gpio_irq_handler);
814
815 platform_set_drvdata(pdev, gpio_dev);
816
817 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
818 return ret;
819
820 out2:
821 gpiochip_remove(&gpio_dev->gc);
822
823 return ret;
824 }
825
826 static int amd_gpio_remove(struct platform_device *pdev)
827 {
828 struct amd_gpio *gpio_dev;
829
830 gpio_dev = platform_get_drvdata(pdev);
831
832 gpiochip_remove(&gpio_dev->gc);
833
834 return 0;
835 }
836
837 static const struct acpi_device_id amd_gpio_acpi_match[] = {
838 { "AMD0030", 0 },
839 { "AMDI0030", 0},
840 { },
841 };
842 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
843
844 static struct platform_driver amd_gpio_driver = {
845 .driver = {
846 .name = "amd_gpio",
847 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
848 },
849 .probe = amd_gpio_probe,
850 .remove = amd_gpio_remove,
851 };
852
853 module_platform_driver(amd_gpio_driver);
854
855 MODULE_LICENSE("GPL v2");
856 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
857 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux kernel - Deliverables
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