2 * at91 pinctrl driver based on at91 pinmux core
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
20 #include <linux/gpio.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 /* Since we request GPIOs from ourself */
26 #include <linux/pinctrl/consumer.h>
28 #include <mach/hardware.h>
29 #include <mach/at91_pio.h>
33 #define MAX_GPIO_BANKS 5
34 #define MAX_NB_GPIO_PER_BANK 32
36 struct at91_pinctrl_mux_ops
;
38 struct at91_gpio_chip
{
39 struct gpio_chip chip
;
40 struct pinctrl_gpio_range range
;
41 struct at91_gpio_chip
*next
; /* Bank sharing same clock */
42 int pioc_hwirq
; /* PIO bank interrupt identifier on AIC */
43 int pioc_virq
; /* PIO bank Linux virtual interrupt */
44 int pioc_idx
; /* PIO bank index */
45 void __iomem
*regbase
; /* PIO bank virtual address */
46 struct clk
*clock
; /* associated clock */
47 struct at91_pinctrl_mux_ops
*ops
; /* ops */
50 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
52 static struct at91_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
54 static int gpio_banks
;
56 #define PULL_UP (1 << 0)
57 #define MULTI_DRIVE (1 << 1)
58 #define DEGLITCH (1 << 2)
59 #define PULL_DOWN (1 << 3)
60 #define DIS_SCHMIT (1 << 4)
61 #define DRIVE_STRENGTH_SHIFT 5
62 #define DRIVE_STRENGTH_MASK 0x3
63 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
64 #define DEBOUNCE (1 << 16)
65 #define DEBOUNCE_VAL_SHIFT 17
66 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
69 * These defines will translated the dt binding settings to our internal
70 * settings. They are not necessarily the same value as the register setting.
71 * The actual drive strength current of low, medium and high must be looked up
72 * from the corresponding device datasheet. This value is different for pins
73 * that are even in the same banks. It is also dependent on VCC.
74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
75 * strength when there is no dt config for it.
77 #define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
78 #define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
79 #define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
80 #define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
83 * struct at91_pmx_func - describes AT91 pinmux functions
84 * @name: the name of this specific function
85 * @groups: corresponding pin groups
86 * @ngroups: the number of groups
88 struct at91_pmx_func
{
96 AT91_MUX_PERIPH_A
= 1,
97 AT91_MUX_PERIPH_B
= 2,
98 AT91_MUX_PERIPH_C
= 3,
99 AT91_MUX_PERIPH_D
= 4,
103 * struct at91_pmx_pin - describes an At91 pin mux
104 * @bank: the bank of the pin
105 * @pin: the pin number in the @bank
106 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
107 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
109 struct at91_pmx_pin
{
117 * struct at91_pin_group - describes an At91 pin group
118 * @name: the name of this specific pin group
119 * @pins_conf: the mux mode for each pin in this group. The size of this
120 * array is the same as pins.
121 * @pins: an array of discrete physical pins used in this group, taken
122 * from the driver-local pin enumeration space
123 * @npins: the number of pins in this group array, i.e. the number of
124 * elements in .pins so we can iterate over that array
126 struct at91_pin_group
{
128 struct at91_pmx_pin
*pins_conf
;
134 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
135 * on new IP with support for periph C and D the way to mux in
136 * periph A and B has changed
137 * So provide the right call back
138 * if not present means the IP does not support it
139 * @get_periph: return the periph mode configured
140 * @mux_A_periph: mux as periph A
141 * @mux_B_periph: mux as periph B
142 * @mux_C_periph: mux as periph C
143 * @mux_D_periph: mux as periph D
144 * @get_deglitch: get deglitch status
145 * @set_deglitch: enable/disable deglitch
146 * @get_debounce: get debounce status
147 * @set_debounce: enable/disable debounce
148 * @get_pulldown: get pulldown status
149 * @set_pulldown: enable/disable pulldown
150 * @get_schmitt_trig: get schmitt trigger status
151 * @disable_schmitt_trig: disable schmitt trigger
152 * @irq_type: return irq type
154 struct at91_pinctrl_mux_ops
{
155 enum at91_mux (*get_periph
)(void __iomem
*pio
, unsigned mask
);
156 void (*mux_A_periph
)(void __iomem
*pio
, unsigned mask
);
157 void (*mux_B_periph
)(void __iomem
*pio
, unsigned mask
);
158 void (*mux_C_periph
)(void __iomem
*pio
, unsigned mask
);
159 void (*mux_D_periph
)(void __iomem
*pio
, unsigned mask
);
160 bool (*get_deglitch
)(void __iomem
*pio
, unsigned pin
);
161 void (*set_deglitch
)(void __iomem
*pio
, unsigned mask
, bool is_on
);
162 bool (*get_debounce
)(void __iomem
*pio
, unsigned pin
, u32
*div
);
163 void (*set_debounce
)(void __iomem
*pio
, unsigned mask
, bool is_on
, u32 div
);
164 bool (*get_pulldown
)(void __iomem
*pio
, unsigned pin
);
165 void (*set_pulldown
)(void __iomem
*pio
, unsigned mask
, bool is_on
);
166 bool (*get_schmitt_trig
)(void __iomem
*pio
, unsigned pin
);
167 void (*disable_schmitt_trig
)(void __iomem
*pio
, unsigned mask
);
168 unsigned (*get_drivestrength
)(void __iomem
*pio
, unsigned pin
);
169 void (*set_drivestrength
)(void __iomem
*pio
, unsigned pin
,
172 int (*irq_type
)(struct irq_data
*d
, unsigned type
);
175 static int gpio_irq_type(struct irq_data
*d
, unsigned type
);
176 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
);
178 struct at91_pinctrl
{
180 struct pinctrl_dev
*pctl
;
187 struct at91_pmx_func
*functions
;
190 struct at91_pin_group
*groups
;
193 struct at91_pinctrl_mux_ops
*ops
;
196 static const inline struct at91_pin_group
*at91_pinctrl_find_group_by_name(
197 const struct at91_pinctrl
*info
,
200 const struct at91_pin_group
*grp
= NULL
;
203 for (i
= 0; i
< info
->ngroups
; i
++) {
204 if (strcmp(info
->groups
[i
].name
, name
))
207 grp
= &info
->groups
[i
];
208 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
, grp
->pins
[0]);
215 static int at91_get_groups_count(struct pinctrl_dev
*pctldev
)
217 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
219 return info
->ngroups
;
222 static const char *at91_get_group_name(struct pinctrl_dev
*pctldev
,
225 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
227 return info
->groups
[selector
].name
;
230 static int at91_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
231 const unsigned **pins
,
234 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
236 if (selector
>= info
->ngroups
)
239 *pins
= info
->groups
[selector
].pins
;
240 *npins
= info
->groups
[selector
].npins
;
245 static void at91_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
248 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
251 static int at91_dt_node_to_map(struct pinctrl_dev
*pctldev
,
252 struct device_node
*np
,
253 struct pinctrl_map
**map
, unsigned *num_maps
)
255 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
256 const struct at91_pin_group
*grp
;
257 struct pinctrl_map
*new_map
;
258 struct device_node
*parent
;
263 * first find the group of this node and check if we need to create
264 * config maps for pins
266 grp
= at91_pinctrl_find_group_by_name(info
, np
->name
);
268 dev_err(info
->dev
, "unable to find group for node %s\n",
273 map_num
+= grp
->npins
;
274 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
, GFP_KERNEL
);
282 parent
= of_get_parent(np
);
284 devm_kfree(pctldev
->dev
, new_map
);
287 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
288 new_map
[0].data
.mux
.function
= parent
->name
;
289 new_map
[0].data
.mux
.group
= np
->name
;
292 /* create config map */
294 for (i
= 0; i
< grp
->npins
; i
++) {
295 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
296 new_map
[i
].data
.configs
.group_or_pin
=
297 pin_get_name(pctldev
, grp
->pins
[i
]);
298 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
299 new_map
[i
].data
.configs
.num_configs
= 1;
302 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
303 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
308 static void at91_dt_free_map(struct pinctrl_dev
*pctldev
,
309 struct pinctrl_map
*map
, unsigned num_maps
)
313 static const struct pinctrl_ops at91_pctrl_ops
= {
314 .get_groups_count
= at91_get_groups_count
,
315 .get_group_name
= at91_get_group_name
,
316 .get_group_pins
= at91_get_group_pins
,
317 .pin_dbg_show
= at91_pin_dbg_show
,
318 .dt_node_to_map
= at91_dt_node_to_map
,
319 .dt_free_map
= at91_dt_free_map
,
322 static void __iomem
*pin_to_controller(struct at91_pinctrl
*info
,
325 return gpio_chips
[bank
]->regbase
;
328 static inline int pin_to_bank(unsigned pin
)
330 return pin
/= MAX_NB_GPIO_PER_BANK
;
333 static unsigned pin_to_mask(unsigned int pin
)
338 static unsigned two_bit_pin_value_shift_amount(unsigned int pin
)
340 /* return the shift value for a pin for "two bit" per pin registers,
341 * i.e. drive strength */
342 return 2*((pin
>= MAX_NB_GPIO_PER_BANK
/2)
343 ? pin
- MAX_NB_GPIO_PER_BANK
/2 : pin
);
346 static unsigned sama5d3_get_drive_register(unsigned int pin
)
348 /* drive strength is split between two registers
349 * with two bits per pin */
350 return (pin
>= MAX_NB_GPIO_PER_BANK
/2)
351 ? SAMA5D3_PIO_DRIVER2
: SAMA5D3_PIO_DRIVER1
;
354 static unsigned at91sam9x5_get_drive_register(unsigned int pin
)
356 /* drive strength is split between two registers
357 * with two bits per pin */
358 return (pin
>= MAX_NB_GPIO_PER_BANK
/2)
359 ? AT91SAM9X5_PIO_DRIVER2
: AT91SAM9X5_PIO_DRIVER1
;
362 static void at91_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
364 writel_relaxed(mask
, pio
+ PIO_IDR
);
367 static unsigned at91_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
369 return !((readl_relaxed(pio
+ PIO_PUSR
) >> pin
) & 0x1);
372 static void at91_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
374 writel_relaxed(mask
, pio
+ (on
? PIO_PUER
: PIO_PUDR
));
377 static unsigned at91_mux_get_multidrive(void __iomem
*pio
, unsigned pin
)
379 return (readl_relaxed(pio
+ PIO_MDSR
) >> pin
) & 0x1;
382 static void at91_mux_set_multidrive(void __iomem
*pio
, unsigned mask
, bool on
)
384 writel_relaxed(mask
, pio
+ (on
? PIO_MDER
: PIO_MDDR
));
387 static void at91_mux_set_A_periph(void __iomem
*pio
, unsigned mask
)
389 writel_relaxed(mask
, pio
+ PIO_ASR
);
392 static void at91_mux_set_B_periph(void __iomem
*pio
, unsigned mask
)
394 writel_relaxed(mask
, pio
+ PIO_BSR
);
397 static void at91_mux_pio3_set_A_periph(void __iomem
*pio
, unsigned mask
)
400 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) & ~mask
,
402 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) & ~mask
,
406 static void at91_mux_pio3_set_B_periph(void __iomem
*pio
, unsigned mask
)
408 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) | mask
,
410 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) & ~mask
,
414 static void at91_mux_pio3_set_C_periph(void __iomem
*pio
, unsigned mask
)
416 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) & ~mask
, pio
+ PIO_ABCDSR1
);
417 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
420 static void at91_mux_pio3_set_D_periph(void __iomem
*pio
, unsigned mask
)
422 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) | mask
, pio
+ PIO_ABCDSR1
);
423 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
426 static enum at91_mux
at91_mux_pio3_get_periph(void __iomem
*pio
, unsigned mask
)
430 if (readl_relaxed(pio
+ PIO_PSR
) & mask
)
431 return AT91_MUX_GPIO
;
433 select
= !!(readl_relaxed(pio
+ PIO_ABCDSR1
) & mask
);
434 select
|= (!!(readl_relaxed(pio
+ PIO_ABCDSR2
) & mask
) << 1);
439 static enum at91_mux
at91_mux_get_periph(void __iomem
*pio
, unsigned mask
)
443 if (readl_relaxed(pio
+ PIO_PSR
) & mask
)
444 return AT91_MUX_GPIO
;
446 select
= readl_relaxed(pio
+ PIO_ABSR
) & mask
;
451 static bool at91_mux_get_deglitch(void __iomem
*pio
, unsigned pin
)
453 return (__raw_readl(pio
+ PIO_IFSR
) >> pin
) & 0x1;
456 static void at91_mux_set_deglitch(void __iomem
*pio
, unsigned mask
, bool is_on
)
458 __raw_writel(mask
, pio
+ (is_on
? PIO_IFER
: PIO_IFDR
));
461 static bool at91_mux_pio3_get_deglitch(void __iomem
*pio
, unsigned pin
)
463 if ((__raw_readl(pio
+ PIO_IFSR
) >> pin
) & 0x1)
464 return !((__raw_readl(pio
+ PIO_IFSCSR
) >> pin
) & 0x1);
469 static void at91_mux_pio3_set_deglitch(void __iomem
*pio
, unsigned mask
, bool is_on
)
472 __raw_writel(mask
, pio
+ PIO_IFSCDR
);
473 at91_mux_set_deglitch(pio
, mask
, is_on
);
476 static bool at91_mux_pio3_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
478 *div
= __raw_readl(pio
+ PIO_SCDR
);
480 return ((__raw_readl(pio
+ PIO_IFSR
) >> pin
) & 0x1) &&
481 ((__raw_readl(pio
+ PIO_IFSCSR
) >> pin
) & 0x1);
484 static void at91_mux_pio3_set_debounce(void __iomem
*pio
, unsigned mask
,
488 __raw_writel(mask
, pio
+ PIO_IFSCER
);
489 __raw_writel(div
& PIO_SCDR_DIV
, pio
+ PIO_SCDR
);
490 __raw_writel(mask
, pio
+ PIO_IFER
);
492 __raw_writel(mask
, pio
+ PIO_IFSCDR
);
495 static bool at91_mux_pio3_get_pulldown(void __iomem
*pio
, unsigned pin
)
497 return !((__raw_readl(pio
+ PIO_PPDSR
) >> pin
) & 0x1);
500 static void at91_mux_pio3_set_pulldown(void __iomem
*pio
, unsigned mask
, bool is_on
)
502 __raw_writel(mask
, pio
+ (is_on
? PIO_PPDER
: PIO_PPDDR
));
505 static void at91_mux_pio3_disable_schmitt_trig(void __iomem
*pio
, unsigned mask
)
507 __raw_writel(__raw_readl(pio
+ PIO_SCHMITT
) | mask
, pio
+ PIO_SCHMITT
);
510 static bool at91_mux_pio3_get_schmitt_trig(void __iomem
*pio
, unsigned pin
)
512 return (__raw_readl(pio
+ PIO_SCHMITT
) >> pin
) & 0x1;
515 static inline u32
read_drive_strength(void __iomem
*reg
, unsigned pin
)
517 unsigned tmp
= __raw_readl(reg
);
519 tmp
= tmp
>> two_bit_pin_value_shift_amount(pin
);
521 return tmp
& DRIVE_STRENGTH_MASK
;
524 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem
*pio
,
527 unsigned tmp
= read_drive_strength(pio
+
528 sama5d3_get_drive_register(pin
), pin
);
530 /* SAMA5 strength is 1:1 with our defines,
531 * except 0 is equivalent to low per datasheet */
533 tmp
= DRIVE_STRENGTH_LOW
;
538 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem
*pio
,
541 unsigned tmp
= read_drive_strength(pio
+
542 at91sam9x5_get_drive_register(pin
), pin
);
544 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
545 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
546 tmp
= DRIVE_STRENGTH_HI
- tmp
;
551 static void set_drive_strength(void __iomem
*reg
, unsigned pin
, u32 strength
)
553 unsigned tmp
= __raw_readl(reg
);
554 unsigned shift
= two_bit_pin_value_shift_amount(pin
);
556 tmp
&= ~(DRIVE_STRENGTH_MASK
<< shift
);
557 tmp
|= strength
<< shift
;
559 __raw_writel(tmp
, reg
);
562 static void at91_mux_sama5d3_set_drivestrength(void __iomem
*pio
, unsigned pin
,
565 /* do nothing if setting is zero */
569 /* strength is 1 to 1 with setting for SAMA5 */
570 set_drive_strength(pio
+ sama5d3_get_drive_register(pin
), pin
, setting
);
573 static void at91_mux_sam9x5_set_drivestrength(void __iomem
*pio
, unsigned pin
,
576 /* do nothing if setting is zero */
580 /* strength is inverse on SAM9x5s with our defines
581 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
582 setting
= DRIVE_STRENGTH_HI
- setting
;
584 set_drive_strength(pio
+ at91sam9x5_get_drive_register(pin
), pin
,
588 static struct at91_pinctrl_mux_ops at91rm9200_ops
= {
589 .get_periph
= at91_mux_get_periph
,
590 .mux_A_periph
= at91_mux_set_A_periph
,
591 .mux_B_periph
= at91_mux_set_B_periph
,
592 .get_deglitch
= at91_mux_get_deglitch
,
593 .set_deglitch
= at91_mux_set_deglitch
,
594 .irq_type
= gpio_irq_type
,
597 static struct at91_pinctrl_mux_ops at91sam9x5_ops
= {
598 .get_periph
= at91_mux_pio3_get_periph
,
599 .mux_A_periph
= at91_mux_pio3_set_A_periph
,
600 .mux_B_periph
= at91_mux_pio3_set_B_periph
,
601 .mux_C_periph
= at91_mux_pio3_set_C_periph
,
602 .mux_D_periph
= at91_mux_pio3_set_D_periph
,
603 .get_deglitch
= at91_mux_pio3_get_deglitch
,
604 .set_deglitch
= at91_mux_pio3_set_deglitch
,
605 .get_debounce
= at91_mux_pio3_get_debounce
,
606 .set_debounce
= at91_mux_pio3_set_debounce
,
607 .get_pulldown
= at91_mux_pio3_get_pulldown
,
608 .set_pulldown
= at91_mux_pio3_set_pulldown
,
609 .get_schmitt_trig
= at91_mux_pio3_get_schmitt_trig
,
610 .disable_schmitt_trig
= at91_mux_pio3_disable_schmitt_trig
,
611 .get_drivestrength
= at91_mux_sam9x5_get_drivestrength
,
612 .set_drivestrength
= at91_mux_sam9x5_set_drivestrength
,
613 .irq_type
= alt_gpio_irq_type
,
616 static struct at91_pinctrl_mux_ops sama5d3_ops
= {
617 .get_periph
= at91_mux_pio3_get_periph
,
618 .mux_A_periph
= at91_mux_pio3_set_A_periph
,
619 .mux_B_periph
= at91_mux_pio3_set_B_periph
,
620 .mux_C_periph
= at91_mux_pio3_set_C_periph
,
621 .mux_D_periph
= at91_mux_pio3_set_D_periph
,
622 .get_deglitch
= at91_mux_pio3_get_deglitch
,
623 .set_deglitch
= at91_mux_pio3_set_deglitch
,
624 .get_debounce
= at91_mux_pio3_get_debounce
,
625 .set_debounce
= at91_mux_pio3_set_debounce
,
626 .get_pulldown
= at91_mux_pio3_get_pulldown
,
627 .set_pulldown
= at91_mux_pio3_set_pulldown
,
628 .get_schmitt_trig
= at91_mux_pio3_get_schmitt_trig
,
629 .disable_schmitt_trig
= at91_mux_pio3_disable_schmitt_trig
,
630 .get_drivestrength
= at91_mux_sama5d3_get_drivestrength
,
631 .set_drivestrength
= at91_mux_sama5d3_set_drivestrength
,
632 .irq_type
= alt_gpio_irq_type
,
635 static void at91_pin_dbg(const struct device
*dev
, const struct at91_pmx_pin
*pin
)
638 dev_dbg(dev
, "pio%c%d configured as periph%c with conf = 0x%lu\n",
639 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A', pin
->conf
);
641 dev_dbg(dev
, "pio%c%d configured as gpio with conf = 0x%lu\n",
642 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
646 static int pin_check_config(struct at91_pinctrl
*info
, const char *name
,
647 int index
, const struct at91_pmx_pin
*pin
)
651 /* check if it's a valid config */
652 if (pin
->bank
>= info
->nbanks
) {
653 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
654 name
, index
, pin
->bank
, info
->nbanks
);
658 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
659 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
660 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
669 if (mux
>= info
->nmux
) {
670 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
671 name
, index
, mux
, info
->nmux
);
675 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
676 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
677 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
684 static void at91_mux_gpio_disable(void __iomem
*pio
, unsigned mask
)
686 writel_relaxed(mask
, pio
+ PIO_PDR
);
689 static void at91_mux_gpio_enable(void __iomem
*pio
, unsigned mask
, bool input
)
691 writel_relaxed(mask
, pio
+ PIO_PER
);
692 writel_relaxed(mask
, pio
+ (input
? PIO_ODR
: PIO_OER
));
695 static int at91_pmx_set(struct pinctrl_dev
*pctldev
, unsigned selector
,
698 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
699 const struct at91_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
700 const struct at91_pmx_pin
*pin
;
701 uint32_t npins
= info
->groups
[group
].npins
;
706 dev_dbg(info
->dev
, "enable function %s group %s\n",
707 info
->functions
[selector
].name
, info
->groups
[group
].name
);
709 /* first check that all the pins of the group are valid with a valid
711 for (i
= 0; i
< npins
; i
++) {
713 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
718 for (i
= 0; i
< npins
; i
++) {
720 at91_pin_dbg(info
->dev
, pin
);
721 pio
= pin_to_controller(info
, pin
->bank
);
722 mask
= pin_to_mask(pin
->pin
);
723 at91_mux_disable_interrupt(pio
, mask
);
726 at91_mux_gpio_enable(pio
, mask
, 1);
728 case AT91_MUX_PERIPH_A
:
729 info
->ops
->mux_A_periph(pio
, mask
);
731 case AT91_MUX_PERIPH_B
:
732 info
->ops
->mux_B_periph(pio
, mask
);
734 case AT91_MUX_PERIPH_C
:
735 if (!info
->ops
->mux_C_periph
)
737 info
->ops
->mux_C_periph(pio
, mask
);
739 case AT91_MUX_PERIPH_D
:
740 if (!info
->ops
->mux_D_periph
)
742 info
->ops
->mux_D_periph(pio
, mask
);
746 at91_mux_gpio_disable(pio
, mask
);
752 static int at91_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
754 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
756 return info
->nfunctions
;
759 static const char *at91_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
762 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
764 return info
->functions
[selector
].name
;
767 static int at91_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
768 const char * const **groups
,
769 unsigned * const num_groups
)
771 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
773 *groups
= info
->functions
[selector
].groups
;
774 *num_groups
= info
->functions
[selector
].ngroups
;
779 static int at91_gpio_request_enable(struct pinctrl_dev
*pctldev
,
780 struct pinctrl_gpio_range
*range
,
783 struct at91_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
784 struct at91_gpio_chip
*at91_chip
;
785 struct gpio_chip
*chip
;
789 dev_err(npct
->dev
, "invalid range\n");
793 dev_err(npct
->dev
, "missing GPIO chip in range\n");
797 at91_chip
= container_of(chip
, struct at91_gpio_chip
, chip
);
799 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
801 mask
= 1 << (offset
- chip
->base
);
803 dev_dbg(npct
->dev
, "enable pin %u as PIO%c%d 0x%x\n",
804 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
806 writel_relaxed(mask
, at91_chip
->regbase
+ PIO_PER
);
811 static void at91_gpio_disable_free(struct pinctrl_dev
*pctldev
,
812 struct pinctrl_gpio_range
*range
,
815 struct at91_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
817 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
818 /* Set the pin to some default state, GPIO is usually default */
821 static const struct pinmux_ops at91_pmx_ops
= {
822 .get_functions_count
= at91_pmx_get_funcs_count
,
823 .get_function_name
= at91_pmx_get_func_name
,
824 .get_function_groups
= at91_pmx_get_groups
,
825 .set_mux
= at91_pmx_set
,
826 .gpio_request_enable
= at91_gpio_request_enable
,
827 .gpio_disable_free
= at91_gpio_disable_free
,
830 static int at91_pinconf_get(struct pinctrl_dev
*pctldev
,
831 unsigned pin_id
, unsigned long *config
)
833 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
839 dev_dbg(info
->dev
, "%s:%d, pin_id=%d", __func__
, __LINE__
, pin_id
);
840 pio
= pin_to_controller(info
, pin_to_bank(pin_id
));
841 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
843 if (at91_mux_get_multidrive(pio
, pin
))
844 *config
|= MULTI_DRIVE
;
846 if (at91_mux_get_pullup(pio
, pin
))
849 if (info
->ops
->get_deglitch
&& info
->ops
->get_deglitch(pio
, pin
))
851 if (info
->ops
->get_debounce
&& info
->ops
->get_debounce(pio
, pin
, &div
))
852 *config
|= DEBOUNCE
| (div
<< DEBOUNCE_VAL_SHIFT
);
853 if (info
->ops
->get_pulldown
&& info
->ops
->get_pulldown(pio
, pin
))
854 *config
|= PULL_DOWN
;
855 if (info
->ops
->get_schmitt_trig
&& info
->ops
->get_schmitt_trig(pio
, pin
))
856 *config
|= DIS_SCHMIT
;
857 if (info
->ops
->get_drivestrength
)
858 *config
|= (info
->ops
->get_drivestrength(pio
, pin
)
859 << DRIVE_STRENGTH_SHIFT
);
864 static int at91_pinconf_set(struct pinctrl_dev
*pctldev
,
865 unsigned pin_id
, unsigned long *configs
,
866 unsigned num_configs
)
868 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
872 unsigned long config
;
875 for (i
= 0; i
< num_configs
; i
++) {
879 "%s:%d, pin_id=%d, config=0x%lx",
880 __func__
, __LINE__
, pin_id
, config
);
881 pio
= pin_to_controller(info
, pin_to_bank(pin_id
));
882 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
883 mask
= pin_to_mask(pin
);
885 if (config
& PULL_UP
&& config
& PULL_DOWN
)
888 at91_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
889 at91_mux_set_multidrive(pio
, mask
, config
& MULTI_DRIVE
);
890 if (info
->ops
->set_deglitch
)
891 info
->ops
->set_deglitch(pio
, mask
, config
& DEGLITCH
);
892 if (info
->ops
->set_debounce
)
893 info
->ops
->set_debounce(pio
, mask
, config
& DEBOUNCE
,
894 (config
& DEBOUNCE_VAL
) >> DEBOUNCE_VAL_SHIFT
);
895 if (info
->ops
->set_pulldown
)
896 info
->ops
->set_pulldown(pio
, mask
, config
& PULL_DOWN
);
897 if (info
->ops
->disable_schmitt_trig
&& config
& DIS_SCHMIT
)
898 info
->ops
->disable_schmitt_trig(pio
, mask
);
899 if (info
->ops
->set_drivestrength
)
900 info
->ops
->set_drivestrength(pio
, pin
,
901 (config
& DRIVE_STRENGTH
)
902 >> DRIVE_STRENGTH_SHIFT
);
904 } /* for each config */
909 #define DBG_SHOW_FLAG(flag) do { \
910 if (config & flag) { \
913 seq_puts(s, #flag); \
918 #define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
919 if ((config & mask) == flag) { \
922 seq_puts(s, #flag); \
927 static void at91_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
928 struct seq_file
*s
, unsigned pin_id
)
930 unsigned long config
;
931 int val
, num_conf
= 0;
933 at91_pinconf_get(pctldev
, pin_id
, &config
);
935 DBG_SHOW_FLAG(MULTI_DRIVE
);
936 DBG_SHOW_FLAG(PULL_UP
);
937 DBG_SHOW_FLAG(PULL_DOWN
);
938 DBG_SHOW_FLAG(DIS_SCHMIT
);
939 DBG_SHOW_FLAG(DEGLITCH
);
940 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_LOW
);
941 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_MED
);
942 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_HI
);
943 DBG_SHOW_FLAG(DEBOUNCE
);
944 if (config
& DEBOUNCE
) {
945 val
= config
>> DEBOUNCE_VAL_SHIFT
;
946 seq_printf(s
, "(%d)", val
);
952 static void at91_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
953 struct seq_file
*s
, unsigned group
)
957 static const struct pinconf_ops at91_pinconf_ops
= {
958 .pin_config_get
= at91_pinconf_get
,
959 .pin_config_set
= at91_pinconf_set
,
960 .pin_config_dbg_show
= at91_pinconf_dbg_show
,
961 .pin_config_group_dbg_show
= at91_pinconf_group_dbg_show
,
964 static struct pinctrl_desc at91_pinctrl_desc
= {
965 .pctlops
= &at91_pctrl_ops
,
966 .pmxops
= &at91_pmx_ops
,
967 .confops
= &at91_pinconf_ops
,
968 .owner
= THIS_MODULE
,
971 static const char *gpio_compat
= "atmel,at91rm9200-gpio";
973 static void at91_pinctrl_child_count(struct at91_pinctrl
*info
,
974 struct device_node
*np
)
976 struct device_node
*child
;
978 for_each_child_of_node(np
, child
) {
979 if (of_device_is_compatible(child
, gpio_compat
)) {
983 info
->ngroups
+= of_get_child_count(child
);
988 static int at91_pinctrl_mux_mask(struct at91_pinctrl
*info
,
989 struct device_node
*np
)
995 list
= of_get_property(np
, "atmel,mux-mask", &size
);
997 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
1001 size
/= sizeof(*list
);
1002 if (!size
|| size
% info
->nbanks
) {
1003 dev_err(info
->dev
, "wrong mux mask array should be by %d\n", info
->nbanks
);
1006 info
->nmux
= size
/ info
->nbanks
;
1008 info
->mux_mask
= devm_kzalloc(info
->dev
, sizeof(u32
) * size
, GFP_KERNEL
);
1009 if (!info
->mux_mask
) {
1010 dev_err(info
->dev
, "could not alloc mux_mask\n");
1014 ret
= of_property_read_u32_array(np
, "atmel,mux-mask",
1015 info
->mux_mask
, size
);
1017 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
1021 static int at91_pinctrl_parse_groups(struct device_node
*np
,
1022 struct at91_pin_group
*grp
,
1023 struct at91_pinctrl
*info
, u32 index
)
1025 struct at91_pmx_pin
*pin
;
1030 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
1032 /* Initialise group */
1033 grp
->name
= np
->name
;
1036 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1037 * do sanity check and calculate pins number
1039 list
= of_get_property(np
, "atmel,pins", &size
);
1040 /* we do not check return since it's safe node passed down */
1041 size
/= sizeof(*list
);
1042 if (!size
|| size
% 4) {
1043 dev_err(info
->dev
, "wrong pins number or pins and configs should be by 4\n");
1047 grp
->npins
= size
/ 4;
1048 pin
= grp
->pins_conf
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(struct at91_pmx_pin
),
1050 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
1052 if (!grp
->pins_conf
|| !grp
->pins
)
1055 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
1056 pin
->bank
= be32_to_cpu(*list
++);
1057 pin
->pin
= be32_to_cpu(*list
++);
1058 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
1059 pin
->mux
= be32_to_cpu(*list
++);
1060 pin
->conf
= be32_to_cpu(*list
++);
1062 at91_pin_dbg(info
->dev
, pin
);
1069 static int at91_pinctrl_parse_functions(struct device_node
*np
,
1070 struct at91_pinctrl
*info
, u32 index
)
1072 struct device_node
*child
;
1073 struct at91_pmx_func
*func
;
1074 struct at91_pin_group
*grp
;
1076 static u32 grp_index
;
1079 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
1081 func
= &info
->functions
[index
];
1083 /* Initialise function */
1084 func
->name
= np
->name
;
1085 func
->ngroups
= of_get_child_count(np
);
1086 if (func
->ngroups
== 0) {
1087 dev_err(info
->dev
, "no groups defined\n");
1090 func
->groups
= devm_kzalloc(info
->dev
,
1091 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
1095 for_each_child_of_node(np
, child
) {
1096 func
->groups
[i
] = child
->name
;
1097 grp
= &info
->groups
[grp_index
++];
1098 ret
= at91_pinctrl_parse_groups(child
, grp
, info
, i
++);
1106 static struct of_device_id at91_pinctrl_of_match
[] = {
1107 { .compatible
= "atmel,sama5d3-pinctrl", .data
= &sama5d3_ops
},
1108 { .compatible
= "atmel,at91sam9x5-pinctrl", .data
= &at91sam9x5_ops
},
1109 { .compatible
= "atmel,at91rm9200-pinctrl", .data
= &at91rm9200_ops
},
1113 static int at91_pinctrl_probe_dt(struct platform_device
*pdev
,
1114 struct at91_pinctrl
*info
)
1119 struct device_node
*np
= pdev
->dev
.of_node
;
1120 struct device_node
*child
;
1125 info
->dev
= &pdev
->dev
;
1126 info
->ops
= (struct at91_pinctrl_mux_ops
*)
1127 of_match_device(at91_pinctrl_of_match
, &pdev
->dev
)->data
;
1128 at91_pinctrl_child_count(info
, np
);
1130 if (info
->nbanks
< 1) {
1131 dev_err(&pdev
->dev
, "you need to specify at least one gpio-controller\n");
1135 ret
= at91_pinctrl_mux_mask(info
, np
);
1139 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
1141 dev_dbg(&pdev
->dev
, "mux-mask\n");
1142 tmp
= info
->mux_mask
;
1143 for (i
= 0; i
< info
->nbanks
; i
++) {
1144 for (j
= 0; j
< info
->nmux
; j
++, tmp
++) {
1145 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
1149 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1150 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1151 info
->functions
= devm_kzalloc(&pdev
->dev
, info
->nfunctions
* sizeof(struct at91_pmx_func
),
1153 if (!info
->functions
)
1156 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
* sizeof(struct at91_pin_group
),
1161 dev_dbg(&pdev
->dev
, "nbanks = %d\n", info
->nbanks
);
1162 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1163 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1167 for_each_child_of_node(np
, child
) {
1168 if (of_device_is_compatible(child
, gpio_compat
))
1170 ret
= at91_pinctrl_parse_functions(child
, info
, i
++);
1172 dev_err(&pdev
->dev
, "failed to parse function\n");
1180 static int at91_pinctrl_probe(struct platform_device
*pdev
)
1182 struct at91_pinctrl
*info
;
1183 struct pinctrl_pin_desc
*pdesc
;
1186 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
1190 ret
= at91_pinctrl_probe_dt(pdev
, info
);
1195 * We need all the GPIO drivers to probe FIRST, or we will not be able
1196 * to obtain references to the struct gpio_chip * for them, and we
1197 * need this to proceed.
1199 for (i
= 0; i
< info
->nbanks
; i
++) {
1200 if (!gpio_chips
[i
]) {
1201 dev_warn(&pdev
->dev
, "GPIO chip %d not registered yet\n", i
);
1202 devm_kfree(&pdev
->dev
, info
);
1203 return -EPROBE_DEFER
;
1207 at91_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
1208 at91_pinctrl_desc
.npins
= info
->nbanks
* MAX_NB_GPIO_PER_BANK
;
1209 at91_pinctrl_desc
.pins
= pdesc
=
1210 devm_kzalloc(&pdev
->dev
, sizeof(*pdesc
) * at91_pinctrl_desc
.npins
, GFP_KERNEL
);
1212 if (!at91_pinctrl_desc
.pins
)
1215 for (i
= 0 , k
= 0; i
< info
->nbanks
; i
++) {
1216 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
1218 pdesc
->name
= kasprintf(GFP_KERNEL
, "pio%c%d", i
+ 'A', j
);
1223 platform_set_drvdata(pdev
, info
);
1224 info
->pctl
= pinctrl_register(&at91_pinctrl_desc
, &pdev
->dev
, info
);
1227 dev_err(&pdev
->dev
, "could not register AT91 pinctrl driver\n");
1232 /* We will handle a range of GPIO pins */
1233 for (i
= 0; i
< info
->nbanks
; i
++)
1234 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
1236 dev_info(&pdev
->dev
, "initialized AT91 pinctrl driver\n");
1244 static int at91_pinctrl_remove(struct platform_device
*pdev
)
1246 struct at91_pinctrl
*info
= platform_get_drvdata(pdev
);
1248 pinctrl_unregister(info
->pctl
);
1253 static int at91_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1256 * Map back to global GPIO space and request muxing, the direction
1257 * parameter does not matter for this controller.
1259 int gpio
= chip
->base
+ offset
;
1260 int bank
= chip
->base
/ chip
->ngpio
;
1262 dev_dbg(chip
->dev
, "%s:%d pio%c%d(%d)\n", __func__
, __LINE__
,
1263 'A' + bank
, offset
, gpio
);
1265 return pinctrl_request_gpio(gpio
);
1268 static void at91_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1270 int gpio
= chip
->base
+ offset
;
1272 pinctrl_free_gpio(gpio
);
1275 static int at91_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
1277 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1278 void __iomem
*pio
= at91_gpio
->regbase
;
1279 unsigned mask
= 1 << offset
;
1282 osr
= readl_relaxed(pio
+ PIO_OSR
);
1283 return !(osr
& mask
);
1286 static int at91_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1288 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1289 void __iomem
*pio
= at91_gpio
->regbase
;
1290 unsigned mask
= 1 << offset
;
1292 writel_relaxed(mask
, pio
+ PIO_ODR
);
1296 static int at91_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1298 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1299 void __iomem
*pio
= at91_gpio
->regbase
;
1300 unsigned mask
= 1 << offset
;
1303 pdsr
= readl_relaxed(pio
+ PIO_PDSR
);
1304 return (pdsr
& mask
) != 0;
1307 static void at91_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1310 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1311 void __iomem
*pio
= at91_gpio
->regbase
;
1312 unsigned mask
= 1 << offset
;
1314 writel_relaxed(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
1317 static int at91_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1320 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1321 void __iomem
*pio
= at91_gpio
->regbase
;
1322 unsigned mask
= 1 << offset
;
1324 writel_relaxed(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
1325 writel_relaxed(mask
, pio
+ PIO_OER
);
1330 #ifdef CONFIG_DEBUG_FS
1331 static void at91_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1335 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
1336 void __iomem
*pio
= at91_gpio
->regbase
;
1338 for (i
= 0; i
< chip
->ngpio
; i
++) {
1339 unsigned mask
= pin_to_mask(i
);
1340 const char *gpio_label
;
1343 gpio_label
= gpiochip_is_requested(chip
, i
);
1346 mode
= at91_gpio
->ops
->get_periph(pio
, mask
);
1347 seq_printf(s
, "[%s] GPIO%s%d: ",
1348 gpio_label
, chip
->label
, i
);
1349 if (mode
== AT91_MUX_GPIO
) {
1350 pdsr
= readl_relaxed(pio
+ PIO_PDSR
);
1352 seq_printf(s
, "[gpio] %s\n",
1356 seq_printf(s
, "[periph %c]\n",
1362 #define at91_gpio_dbg_show NULL
1365 /* Several AIC controller irqs are dispatched through this GPIO handler.
1366 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1367 * at91_set_gpio_input() then maybe enable its glitch filter.
1368 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1370 * First implementation always triggers on rising and falling edges
1371 * whereas the newer PIO3 can be additionally configured to trigger on
1372 * level, edge with any polarity.
1374 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1375 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1376 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1379 static void gpio_irq_mask(struct irq_data
*d
)
1381 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1382 void __iomem
*pio
= at91_gpio
->regbase
;
1383 unsigned mask
= 1 << d
->hwirq
;
1386 writel_relaxed(mask
, pio
+ PIO_IDR
);
1389 static void gpio_irq_unmask(struct irq_data
*d
)
1391 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1392 void __iomem
*pio
= at91_gpio
->regbase
;
1393 unsigned mask
= 1 << d
->hwirq
;
1396 writel_relaxed(mask
, pio
+ PIO_IER
);
1399 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1403 case IRQ_TYPE_EDGE_BOTH
:
1410 /* Alternate irq type for PIO3 support */
1411 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
)
1413 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1414 void __iomem
*pio
= at91_gpio
->regbase
;
1415 unsigned mask
= 1 << d
->hwirq
;
1418 case IRQ_TYPE_EDGE_RISING
:
1419 __irq_set_handler_locked(d
->irq
, handle_simple_irq
);
1420 writel_relaxed(mask
, pio
+ PIO_ESR
);
1421 writel_relaxed(mask
, pio
+ PIO_REHLSR
);
1423 case IRQ_TYPE_EDGE_FALLING
:
1424 __irq_set_handler_locked(d
->irq
, handle_simple_irq
);
1425 writel_relaxed(mask
, pio
+ PIO_ESR
);
1426 writel_relaxed(mask
, pio
+ PIO_FELLSR
);
1428 case IRQ_TYPE_LEVEL_LOW
:
1429 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
1430 writel_relaxed(mask
, pio
+ PIO_LSR
);
1431 writel_relaxed(mask
, pio
+ PIO_FELLSR
);
1433 case IRQ_TYPE_LEVEL_HIGH
:
1434 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
1435 writel_relaxed(mask
, pio
+ PIO_LSR
);
1436 writel_relaxed(mask
, pio
+ PIO_REHLSR
);
1438 case IRQ_TYPE_EDGE_BOTH
:
1440 * disable additional interrupt modes:
1441 * fall back to default behavior
1443 __irq_set_handler_locked(d
->irq
, handle_simple_irq
);
1444 writel_relaxed(mask
, pio
+ PIO_AIMDR
);
1448 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d
->irq
));
1452 /* enable additional interrupt modes */
1453 writel_relaxed(mask
, pio
+ PIO_AIMER
);
1458 static void gpio_irq_ack(struct irq_data
*d
)
1460 /* the interrupt is already cleared before by reading ISR */
1463 static unsigned int gpio_irq_startup(struct irq_data
*d
)
1465 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1466 unsigned pin
= d
->hwirq
;
1469 ret
= gpio_lock_as_irq(&at91_gpio
->chip
, pin
);
1471 dev_err(at91_gpio
->chip
.dev
, "unable to lock pind %lu IRQ\n",
1479 static void gpio_irq_shutdown(struct irq_data
*d
)
1481 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1482 unsigned pin
= d
->hwirq
;
1485 gpio_unlock_as_irq(&at91_gpio
->chip
, pin
);
1490 static u32 wakeups
[MAX_GPIO_BANKS
];
1491 static u32 backups
[MAX_GPIO_BANKS
];
1493 static int gpio_irq_set_wake(struct irq_data
*d
, unsigned state
)
1495 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1496 unsigned bank
= at91_gpio
->pioc_idx
;
1497 unsigned mask
= 1 << d
->hwirq
;
1499 if (unlikely(bank
>= MAX_GPIO_BANKS
))
1503 wakeups
[bank
] |= mask
;
1505 wakeups
[bank
] &= ~mask
;
1507 irq_set_irq_wake(at91_gpio
->pioc_virq
, state
);
1512 void at91_pinctrl_gpio_suspend(void)
1516 for (i
= 0; i
< gpio_banks
; i
++) {
1522 pio
= gpio_chips
[i
]->regbase
;
1524 backups
[i
] = __raw_readl(pio
+ PIO_IMR
);
1525 __raw_writel(backups
[i
], pio
+ PIO_IDR
);
1526 __raw_writel(wakeups
[i
], pio
+ PIO_IER
);
1529 clk_disable_unprepare(gpio_chips
[i
]->clock
);
1531 printk(KERN_DEBUG
"GPIO-%c may wake for %08x\n",
1536 void at91_pinctrl_gpio_resume(void)
1540 for (i
= 0; i
< gpio_banks
; i
++) {
1546 pio
= gpio_chips
[i
]->regbase
;
1549 clk_prepare_enable(gpio_chips
[i
]->clock
);
1551 __raw_writel(wakeups
[i
], pio
+ PIO_IDR
);
1552 __raw_writel(backups
[i
], pio
+ PIO_IER
);
1557 #define gpio_irq_set_wake NULL
1558 #endif /* CONFIG_PM */
1560 static struct irq_chip gpio_irqchip
= {
1562 .irq_ack
= gpio_irq_ack
,
1563 .irq_startup
= gpio_irq_startup
,
1564 .irq_shutdown
= gpio_irq_shutdown
,
1565 .irq_disable
= gpio_irq_mask
,
1566 .irq_mask
= gpio_irq_mask
,
1567 .irq_unmask
= gpio_irq_unmask
,
1568 /* .irq_set_type is set dynamically */
1569 .irq_set_wake
= gpio_irq_set_wake
,
1572 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1574 struct irq_chip
*chip
= irq_get_chip(irq
);
1575 struct gpio_chip
*gpio_chip
= irq_desc_get_handler_data(desc
);
1576 struct at91_gpio_chip
*at91_gpio
= container_of(gpio_chip
,
1577 struct at91_gpio_chip
, chip
);
1579 void __iomem
*pio
= at91_gpio
->regbase
;
1583 chained_irq_enter(chip
, desc
);
1585 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1586 * When there are none pending, we're finished unless we need
1587 * to process multiple banks (like ID_PIOCDE on sam9263).
1589 isr
= readl_relaxed(pio
+ PIO_ISR
) & readl_relaxed(pio
+ PIO_IMR
);
1591 if (!at91_gpio
->next
)
1593 at91_gpio
= at91_gpio
->next
;
1594 pio
= at91_gpio
->regbase
;
1595 gpio_chip
= &at91_gpio
->chip
;
1599 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1600 generic_handle_irq(irq_find_mapping(
1601 gpio_chip
->irqdomain
, n
));
1604 chained_irq_exit(chip
, desc
);
1605 /* now it may re-trigger */
1608 static int at91_gpio_of_irq_setup(struct device_node
*node
,
1609 struct at91_gpio_chip
*at91_gpio
)
1611 struct at91_gpio_chip
*prev
= NULL
;
1612 struct irq_data
*d
= irq_get_irq_data(at91_gpio
->pioc_virq
);
1615 at91_gpio
->pioc_hwirq
= irqd_to_hwirq(d
);
1617 /* Setup proper .irq_set_type function */
1618 gpio_irqchip
.irq_set_type
= at91_gpio
->ops
->irq_type
;
1620 /* Disable irqs of this PIO controller */
1621 writel_relaxed(~0, at91_gpio
->regbase
+ PIO_IDR
);
1624 * Let the generic code handle this edge IRQ, the the chained
1625 * handler will perform the actual work of handling the parent
1628 ret
= gpiochip_irqchip_add(&at91_gpio
->chip
,
1632 IRQ_TYPE_EDGE_BOTH
);
1634 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1635 at91_gpio
->pioc_idx
);
1637 /* Setup chained handler */
1638 if (at91_gpio
->pioc_idx
)
1639 prev
= gpio_chips
[at91_gpio
->pioc_idx
- 1];
1641 /* The top level handler handles one bank of GPIOs, except
1642 * on some SoC it can handle up to three...
1643 * We only set up the handler for the first of the list.
1645 if (prev
&& prev
->next
== at91_gpio
)
1648 /* Then register the chain on the parent IRQ */
1649 gpiochip_set_chained_irqchip(&at91_gpio
->chip
,
1651 at91_gpio
->pioc_virq
,
1657 /* This structure is replicated for each GPIO block allocated at probe time */
1658 static struct gpio_chip at91_gpio_template
= {
1659 .request
= at91_gpio_request
,
1660 .free
= at91_gpio_free
,
1661 .get_direction
= at91_gpio_get_direction
,
1662 .direction_input
= at91_gpio_direction_input
,
1663 .get
= at91_gpio_get
,
1664 .direction_output
= at91_gpio_direction_output
,
1665 .set
= at91_gpio_set
,
1666 .dbg_show
= at91_gpio_dbg_show
,
1668 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1671 static void at91_gpio_probe_fixup(void)
1674 struct at91_gpio_chip
*at91_gpio
, *last
= NULL
;
1676 for (i
= 0; i
< gpio_banks
; i
++) {
1677 at91_gpio
= gpio_chips
[i
];
1680 * GPIO controller are grouped on some SoC:
1681 * PIOC, PIOD and PIOE can share the same IRQ line
1683 if (last
&& last
->pioc_virq
== at91_gpio
->pioc_virq
)
1684 last
->next
= at91_gpio
;
1689 static struct of_device_id at91_gpio_of_match
[] = {
1690 { .compatible
= "atmel,at91sam9x5-gpio", .data
= &at91sam9x5_ops
, },
1691 { .compatible
= "atmel,at91rm9200-gpio", .data
= &at91rm9200_ops
},
1695 static int at91_gpio_probe(struct platform_device
*pdev
)
1697 struct device_node
*np
= pdev
->dev
.of_node
;
1698 struct resource
*res
;
1699 struct at91_gpio_chip
*at91_chip
= NULL
;
1700 struct gpio_chip
*chip
;
1701 struct pinctrl_gpio_range
*range
;
1704 int alias_idx
= of_alias_get_id(np
, "gpio");
1708 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1709 if (gpio_chips
[alias_idx
]) {
1714 irq
= platform_get_irq(pdev
, 0);
1720 at91_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*at91_chip
), GFP_KERNEL
);
1726 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1727 at91_chip
->regbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1728 if (IS_ERR(at91_chip
->regbase
)) {
1729 ret
= PTR_ERR(at91_chip
->regbase
);
1733 at91_chip
->ops
= (struct at91_pinctrl_mux_ops
*)
1734 of_match_device(at91_gpio_of_match
, &pdev
->dev
)->data
;
1735 at91_chip
->pioc_virq
= irq
;
1736 at91_chip
->pioc_idx
= alias_idx
;
1738 at91_chip
->clock
= clk_get(&pdev
->dev
, NULL
);
1739 if (IS_ERR(at91_chip
->clock
)) {
1740 dev_err(&pdev
->dev
, "failed to get clock, ignoring.\n");
1744 if (clk_prepare(at91_chip
->clock
))
1747 /* enable PIO controller's clock */
1748 if (clk_enable(at91_chip
->clock
)) {
1749 dev_err(&pdev
->dev
, "failed to enable clock, ignoring.\n");
1753 at91_chip
->chip
= at91_gpio_template
;
1755 chip
= &at91_chip
->chip
;
1757 chip
->label
= dev_name(&pdev
->dev
);
1758 chip
->dev
= &pdev
->dev
;
1759 chip
->owner
= THIS_MODULE
;
1760 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1762 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1763 if (ngpio
>= MAX_NB_GPIO_PER_BANK
)
1764 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1765 alias_idx
, MAX_NB_GPIO_PER_BANK
, MAX_NB_GPIO_PER_BANK
);
1767 chip
->ngpio
= ngpio
;
1770 names
= devm_kzalloc(&pdev
->dev
, sizeof(char *) * chip
->ngpio
,
1778 for (i
= 0; i
< chip
->ngpio
; i
++)
1779 names
[i
] = kasprintf(GFP_KERNEL
, "pio%c%d", alias_idx
+ 'A', i
);
1781 chip
->names
= (const char *const *)names
;
1783 range
= &at91_chip
->range
;
1784 range
->name
= chip
->label
;
1785 range
->id
= alias_idx
;
1786 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1788 range
->npins
= chip
->ngpio
;
1791 ret
= gpiochip_add(chip
);
1795 gpio_chips
[alias_idx
] = at91_chip
;
1796 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1798 at91_gpio_probe_fixup();
1800 at91_gpio_of_irq_setup(np
, at91_chip
);
1802 dev_info(&pdev
->dev
, "at address %p\n", at91_chip
->regbase
);
1807 clk_unprepare(at91_chip
->clock
);
1809 clk_put(at91_chip
->clock
);
1811 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1816 static struct platform_driver at91_gpio_driver
= {
1818 .name
= "gpio-at91",
1819 .owner
= THIS_MODULE
,
1820 .of_match_table
= at91_gpio_of_match
,
1822 .probe
= at91_gpio_probe
,
1825 static struct platform_driver at91_pinctrl_driver
= {
1827 .name
= "pinctrl-at91",
1828 .owner
= THIS_MODULE
,
1829 .of_match_table
= at91_pinctrl_of_match
,
1831 .probe
= at91_pinctrl_probe
,
1832 .remove
= at91_pinctrl_remove
,
1835 static int __init
at91_pinctrl_init(void)
1839 ret
= platform_driver_register(&at91_gpio_driver
);
1842 return platform_driver_register(&at91_pinctrl_driver
);
1844 arch_initcall(at91_pinctrl_init
);
1846 static void __exit
at91_pinctrl_exit(void)
1848 platform_driver_unregister(&at91_pinctrl_driver
);
1851 module_exit(at91_pinctrl_exit
);
1852 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1853 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1854 MODULE_LICENSE("GPL v2");