2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
34 #include <asm/mach/irq.h>
36 #include <plat/pincfg.h>
37 #include <plat/gpio-nomadik.h>
39 #include "pinctrl-nomadik.h"
42 * The GPIO module in the Nomadik family of Systems-on-Chip is an
43 * AMBA device, managing 32 pins and alternate functions. The logic block
44 * is currently used in the Nomadik and ux500.
46 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
49 #define NMK_GPIO_PER_CHIP 32
51 struct nmk_gpio_chip
{
52 struct gpio_chip chip
;
53 struct irq_domain
*domain
;
57 unsigned int parent_irq
;
58 int secondary_parent_irq
;
59 u32 (*get_secondary_status
)(unsigned int bank
);
60 void (*set_ioforce
)(bool enable
);
63 /* Keep track of configured edges */
77 struct pinctrl_dev
*pctl
;
78 const struct nmk_pinctrl_soc_data
*soc
;
81 static struct nmk_gpio_chip
*
82 nmk_gpio_chips
[DIV_ROUND_UP(ARCH_NR_GPIOS
, NMK_GPIO_PER_CHIP
)];
84 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock
);
86 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
88 static void __nmk_gpio_set_mode(struct nmk_gpio_chip
*nmk_chip
,
89 unsigned offset
, int gpio_mode
)
91 u32 bit
= 1 << offset
;
94 afunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLA
) & ~bit
;
95 bfunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLB
) & ~bit
;
96 if (gpio_mode
& NMK_GPIO_ALT_A
)
98 if (gpio_mode
& NMK_GPIO_ALT_B
)
100 writel(afunc
, nmk_chip
->addr
+ NMK_GPIO_AFSLA
);
101 writel(bfunc
, nmk_chip
->addr
+ NMK_GPIO_AFSLB
);
104 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip
*nmk_chip
,
105 unsigned offset
, enum nmk_gpio_slpm mode
)
107 u32 bit
= 1 << offset
;
110 slpm
= readl(nmk_chip
->addr
+ NMK_GPIO_SLPC
);
111 if (mode
== NMK_GPIO_SLPM_NOCHANGE
)
115 writel(slpm
, nmk_chip
->addr
+ NMK_GPIO_SLPC
);
118 static void __nmk_gpio_set_pull(struct nmk_gpio_chip
*nmk_chip
,
119 unsigned offset
, enum nmk_gpio_pull pull
)
121 u32 bit
= 1 << offset
;
124 pdis
= readl(nmk_chip
->addr
+ NMK_GPIO_PDIS
);
125 if (pull
== NMK_GPIO_PULL_NONE
) {
127 nmk_chip
->pull_up
&= ~bit
;
132 writel(pdis
, nmk_chip
->addr
+ NMK_GPIO_PDIS
);
134 if (pull
== NMK_GPIO_PULL_UP
) {
135 nmk_chip
->pull_up
|= bit
;
136 writel(bit
, nmk_chip
->addr
+ NMK_GPIO_DATS
);
137 } else if (pull
== NMK_GPIO_PULL_DOWN
) {
138 nmk_chip
->pull_up
&= ~bit
;
139 writel(bit
, nmk_chip
->addr
+ NMK_GPIO_DATC
);
143 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip
*nmk_chip
,
144 unsigned offset
, bool lowemi
)
146 u32 bit
= BIT(offset
);
147 bool enabled
= nmk_chip
->lowemi
& bit
;
149 if (lowemi
== enabled
)
153 nmk_chip
->lowemi
|= bit
;
155 nmk_chip
->lowemi
&= ~bit
;
157 writel_relaxed(nmk_chip
->lowemi
,
158 nmk_chip
->addr
+ NMK_GPIO_LOWEMI
);
161 static void __nmk_gpio_make_input(struct nmk_gpio_chip
*nmk_chip
,
164 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRC
);
167 static void __nmk_gpio_set_output(struct nmk_gpio_chip
*nmk_chip
,
168 unsigned offset
, int val
)
171 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DATS
);
173 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DATC
);
176 static void __nmk_gpio_make_output(struct nmk_gpio_chip
*nmk_chip
,
177 unsigned offset
, int val
)
179 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRS
);
180 __nmk_gpio_set_output(nmk_chip
, offset
, val
);
183 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip
*nmk_chip
,
184 unsigned offset
, int gpio_mode
,
187 u32 rwimsc
= nmk_chip
->rwimsc
;
188 u32 fwimsc
= nmk_chip
->fwimsc
;
190 if (glitch
&& nmk_chip
->set_ioforce
) {
191 u32 bit
= BIT(offset
);
193 /* Prevent spurious wakeups */
194 writel(rwimsc
& ~bit
, nmk_chip
->addr
+ NMK_GPIO_RWIMSC
);
195 writel(fwimsc
& ~bit
, nmk_chip
->addr
+ NMK_GPIO_FWIMSC
);
197 nmk_chip
->set_ioforce(true);
200 __nmk_gpio_set_mode(nmk_chip
, offset
, gpio_mode
);
202 if (glitch
&& nmk_chip
->set_ioforce
) {
203 nmk_chip
->set_ioforce(false);
205 writel(rwimsc
, nmk_chip
->addr
+ NMK_GPIO_RWIMSC
);
206 writel(fwimsc
, nmk_chip
->addr
+ NMK_GPIO_FWIMSC
);
211 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip
*nmk_chip
, unsigned offset
)
213 u32 falling
= nmk_chip
->fimsc
& BIT(offset
);
214 u32 rising
= nmk_chip
->rimsc
& BIT(offset
);
215 int gpio
= nmk_chip
->chip
.base
+ offset
;
216 int irq
= NOMADIK_GPIO_TO_IRQ(gpio
);
217 struct irq_data
*d
= irq_get_irq_data(irq
);
219 if (!rising
&& !falling
)
222 if (!d
|| !irqd_irq_disabled(d
))
226 nmk_chip
->rimsc
&= ~BIT(offset
);
227 writel_relaxed(nmk_chip
->rimsc
,
228 nmk_chip
->addr
+ NMK_GPIO_RIMSC
);
232 nmk_chip
->fimsc
&= ~BIT(offset
);
233 writel_relaxed(nmk_chip
->fimsc
,
234 nmk_chip
->addr
+ NMK_GPIO_FIMSC
);
237 dev_dbg(nmk_chip
->chip
.dev
, "%d: clearing interrupt mask\n", gpio
);
240 static void __nmk_config_pin(struct nmk_gpio_chip
*nmk_chip
, unsigned offset
,
241 pin_cfg_t cfg
, bool sleep
, unsigned int *slpmregs
)
243 static const char *afnames
[] = {
244 [NMK_GPIO_ALT_GPIO
] = "GPIO",
245 [NMK_GPIO_ALT_A
] = "A",
246 [NMK_GPIO_ALT_B
] = "B",
247 [NMK_GPIO_ALT_C
] = "C"
249 static const char *pullnames
[] = {
250 [NMK_GPIO_PULL_NONE
] = "none",
251 [NMK_GPIO_PULL_UP
] = "up",
252 [NMK_GPIO_PULL_DOWN
] = "down",
253 [3] /* illegal */ = "??"
255 static const char *slpmnames
[] = {
256 [NMK_GPIO_SLPM_INPUT
] = "input/wakeup",
257 [NMK_GPIO_SLPM_NOCHANGE
] = "no-change/no-wakeup",
260 int pin
= PIN_NUM(cfg
);
261 int pull
= PIN_PULL(cfg
);
262 int af
= PIN_ALT(cfg
);
263 int slpm
= PIN_SLPM(cfg
);
264 int output
= PIN_DIR(cfg
);
265 int val
= PIN_VAL(cfg
);
266 bool glitch
= af
== NMK_GPIO_ALT_C
;
268 dev_dbg(nmk_chip
->chip
.dev
, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
269 pin
, cfg
, afnames
[af
], pullnames
[pull
], slpmnames
[slpm
],
270 output
? "output " : "input",
271 output
? (val
? "high" : "low") : "");
274 int slpm_pull
= PIN_SLPM_PULL(cfg
);
275 int slpm_output
= PIN_SLPM_DIR(cfg
);
276 int slpm_val
= PIN_SLPM_VAL(cfg
);
278 af
= NMK_GPIO_ALT_GPIO
;
281 * The SLPM_* values are normal values + 1 to allow zero to
282 * mean "same as normal".
285 pull
= slpm_pull
- 1;
287 output
= slpm_output
- 1;
291 dev_dbg(nmk_chip
->chip
.dev
, "pin %d: sleep pull %s, dir %s, val %s\n",
293 slpm_pull
? pullnames
[pull
] : "same",
294 slpm_output
? (output
? "output" : "input") : "same",
295 slpm_val
? (val
? "high" : "low") : "same");
299 __nmk_gpio_make_output(nmk_chip
, offset
, val
);
301 __nmk_gpio_make_input(nmk_chip
, offset
);
302 __nmk_gpio_set_pull(nmk_chip
, offset
, pull
);
305 __nmk_gpio_set_lowemi(nmk_chip
, offset
, PIN_LOWEMI(cfg
));
308 * If the pin is switching to altfunc, and there was an interrupt
309 * installed on it which has been lazy disabled, actually mask the
310 * interrupt to prevent spurious interrupts that would occur while the
311 * pin is under control of the peripheral. Only SKE does this.
313 if (af
!= NMK_GPIO_ALT_GPIO
)
314 nmk_gpio_disable_lazy_irq(nmk_chip
, offset
);
317 * If we've backed up the SLPM registers (glitch workaround), modify
318 * the backups since they will be restored.
321 if (slpm
== NMK_GPIO_SLPM_NOCHANGE
)
322 slpmregs
[nmk_chip
->bank
] |= BIT(offset
);
324 slpmregs
[nmk_chip
->bank
] &= ~BIT(offset
);
326 __nmk_gpio_set_slpm(nmk_chip
, offset
, slpm
);
328 __nmk_gpio_set_mode_safe(nmk_chip
, offset
, af
, glitch
);
332 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
333 * - Save SLPM registers
334 * - Set SLPM=0 for the IOs you want to switch and others to 1
335 * - Configure the GPIO registers for the IOs that are being switched
337 * - Modify the AFLSA/B registers for the IOs that are being switched
339 * - Restore SLPM registers
340 * - Any spurious wake up event during switch sequence to be ignored and
343 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm
)
347 for (i
= 0; i
< NUM_BANKS
; i
++) {
348 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
349 unsigned int temp
= slpm
[i
];
354 clk_enable(chip
->clk
);
356 slpm
[i
] = readl(chip
->addr
+ NMK_GPIO_SLPC
);
357 writel(temp
, chip
->addr
+ NMK_GPIO_SLPC
);
361 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm
)
365 for (i
= 0; i
< NUM_BANKS
; i
++) {
366 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
371 writel(slpm
[i
], chip
->addr
+ NMK_GPIO_SLPC
);
373 clk_disable(chip
->clk
);
377 static int __nmk_config_pins(pin_cfg_t
*cfgs
, int num
, bool sleep
)
379 static unsigned int slpm
[NUM_BANKS
];
385 for (i
= 0; i
< num
; i
++) {
386 if (PIN_ALT(cfgs
[i
]) == NMK_GPIO_ALT_C
) {
392 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
395 memset(slpm
, 0xff, sizeof(slpm
));
397 for (i
= 0; i
< num
; i
++) {
398 int pin
= PIN_NUM(cfgs
[i
]);
399 int offset
= pin
% NMK_GPIO_PER_CHIP
;
401 if (PIN_ALT(cfgs
[i
]) == NMK_GPIO_ALT_C
)
402 slpm
[pin
/ NMK_GPIO_PER_CHIP
] &= ~BIT(offset
);
405 nmk_gpio_glitch_slpm_init(slpm
);
408 for (i
= 0; i
< num
; i
++) {
409 struct nmk_gpio_chip
*nmk_chip
;
410 int pin
= PIN_NUM(cfgs
[i
]);
412 nmk_chip
= nmk_gpio_chips
[pin
/ NMK_GPIO_PER_CHIP
];
418 clk_enable(nmk_chip
->clk
);
419 spin_lock(&nmk_chip
->lock
);
420 __nmk_config_pin(nmk_chip
, pin
% NMK_GPIO_PER_CHIP
,
421 cfgs
[i
], sleep
, glitch
? slpm
: NULL
);
422 spin_unlock(&nmk_chip
->lock
);
423 clk_disable(nmk_chip
->clk
);
427 nmk_gpio_glitch_slpm_restore(slpm
);
429 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
435 * nmk_config_pin - configure a pin's mux attributes
436 * @cfg: pin confguration
437 * @sleep: Non-zero to apply the sleep mode configuration
438 * Configures a pin's mode (alternate function or GPIO), its pull up status,
439 * and its sleep mode based on the specified configuration. The @cfg is
440 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
441 * are constructed using, and can be further enhanced with, the macros in
444 * If a pin's mode is set to GPIO, it is configured as an input to avoid
445 * side-effects. The gpio can be manipulated later using standard GPIO API
448 int nmk_config_pin(pin_cfg_t cfg
, bool sleep
)
450 return __nmk_config_pins(&cfg
, 1, sleep
);
452 EXPORT_SYMBOL(nmk_config_pin
);
455 * nmk_config_pins - configure several pins at once
456 * @cfgs: array of pin configurations
457 * @num: number of elments in the array
459 * Configures several pins using nmk_config_pin(). Refer to that function for
460 * further information.
462 int nmk_config_pins(pin_cfg_t
*cfgs
, int num
)
464 return __nmk_config_pins(cfgs
, num
, false);
466 EXPORT_SYMBOL(nmk_config_pins
);
468 int nmk_config_pins_sleep(pin_cfg_t
*cfgs
, int num
)
470 return __nmk_config_pins(cfgs
, num
, true);
472 EXPORT_SYMBOL(nmk_config_pins_sleep
);
475 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
477 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
479 * This register is actually in the pinmux layer, not the GPIO block itself.
480 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
481 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
482 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
483 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
484 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
485 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
487 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
488 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
489 * entered) regardless of the altfunction selected. Also wake-up detection is
492 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
493 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
494 * (for altfunction GPIO) or respective on-chip peripherals (for other
495 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
497 * Note that enable_irq_wake() will automatically enable wakeup detection.
499 int nmk_gpio_set_slpm(int gpio
, enum nmk_gpio_slpm mode
)
501 struct nmk_gpio_chip
*nmk_chip
;
504 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
508 clk_enable(nmk_chip
->clk
);
509 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
510 spin_lock(&nmk_chip
->lock
);
512 __nmk_gpio_set_slpm(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
, mode
);
514 spin_unlock(&nmk_chip
->lock
);
515 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
516 clk_disable(nmk_chip
->clk
);
522 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
524 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
526 * Enables/disables pull up/down on a specified pin. This only takes effect if
527 * the pin is configured as an input (either explicitly or by the alternate
530 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
531 * configured as an input. Otherwise, due to the way the controller registers
532 * work, this function will change the value output on the pin.
534 int nmk_gpio_set_pull(int gpio
, enum nmk_gpio_pull pull
)
536 struct nmk_gpio_chip
*nmk_chip
;
539 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
543 clk_enable(nmk_chip
->clk
);
544 spin_lock_irqsave(&nmk_chip
->lock
, flags
);
545 __nmk_gpio_set_pull(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
, pull
);
546 spin_unlock_irqrestore(&nmk_chip
->lock
, flags
);
547 clk_disable(nmk_chip
->clk
);
554 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
556 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
557 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
559 * Sets the mode of the specified pin to one of the alternate functions or
562 int nmk_gpio_set_mode(int gpio
, int gpio_mode
)
564 struct nmk_gpio_chip
*nmk_chip
;
567 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
571 clk_enable(nmk_chip
->clk
);
572 spin_lock_irqsave(&nmk_chip
->lock
, flags
);
573 __nmk_gpio_set_mode(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
, gpio_mode
);
574 spin_unlock_irqrestore(&nmk_chip
->lock
, flags
);
575 clk_disable(nmk_chip
->clk
);
579 EXPORT_SYMBOL(nmk_gpio_set_mode
);
581 int nmk_gpio_get_mode(int gpio
)
583 struct nmk_gpio_chip
*nmk_chip
;
584 u32 afunc
, bfunc
, bit
;
586 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
590 bit
= 1 << (gpio
% NMK_GPIO_PER_CHIP
);
592 clk_enable(nmk_chip
->clk
);
594 afunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLA
) & bit
;
595 bfunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLB
) & bit
;
597 clk_disable(nmk_chip
->clk
);
599 return (afunc
? NMK_GPIO_ALT_A
: 0) | (bfunc
? NMK_GPIO_ALT_B
: 0);
601 EXPORT_SYMBOL(nmk_gpio_get_mode
);
605 static inline int nmk_gpio_get_bitmask(int gpio
)
607 return 1 << (gpio
% NMK_GPIO_PER_CHIP
);
610 static void nmk_gpio_irq_ack(struct irq_data
*d
)
612 struct nmk_gpio_chip
*nmk_chip
;
614 nmk_chip
= irq_data_get_irq_chip_data(d
);
618 clk_enable(nmk_chip
->clk
);
619 writel(nmk_gpio_get_bitmask(d
->hwirq
), nmk_chip
->addr
+ NMK_GPIO_IC
);
620 clk_disable(nmk_chip
->clk
);
623 enum nmk_gpio_irq_type
{
628 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip
*nmk_chip
,
629 int gpio
, enum nmk_gpio_irq_type which
,
632 u32 bitmask
= nmk_gpio_get_bitmask(gpio
);
638 if (which
== NORMAL
) {
639 rimscreg
= NMK_GPIO_RIMSC
;
640 fimscreg
= NMK_GPIO_FIMSC
;
641 rimscval
= &nmk_chip
->rimsc
;
642 fimscval
= &nmk_chip
->fimsc
;
644 rimscreg
= NMK_GPIO_RWIMSC
;
645 fimscreg
= NMK_GPIO_FWIMSC
;
646 rimscval
= &nmk_chip
->rwimsc
;
647 fimscval
= &nmk_chip
->fwimsc
;
650 /* we must individually set/clear the two edges */
651 if (nmk_chip
->edge_rising
& bitmask
) {
653 *rimscval
|= bitmask
;
655 *rimscval
&= ~bitmask
;
656 writel(*rimscval
, nmk_chip
->addr
+ rimscreg
);
658 if (nmk_chip
->edge_falling
& bitmask
) {
660 *fimscval
|= bitmask
;
662 *fimscval
&= ~bitmask
;
663 writel(*fimscval
, nmk_chip
->addr
+ fimscreg
);
667 static void __nmk_gpio_set_wake(struct nmk_gpio_chip
*nmk_chip
,
671 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
672 * disabled, since setting SLPM to 1 increases power consumption, and
673 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
675 if (nmk_chip
->sleepmode
&& on
) {
676 __nmk_gpio_set_slpm(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
,
677 NMK_GPIO_SLPM_WAKEUP_ENABLE
);
680 __nmk_gpio_irq_modify(nmk_chip
, gpio
, WAKE
, on
);
683 static int nmk_gpio_irq_maskunmask(struct irq_data
*d
, bool enable
)
685 struct nmk_gpio_chip
*nmk_chip
;
689 nmk_chip
= irq_data_get_irq_chip_data(d
);
690 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
694 clk_enable(nmk_chip
->clk
);
695 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
696 spin_lock(&nmk_chip
->lock
);
698 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, enable
);
700 if (!(nmk_chip
->real_wake
& bitmask
))
701 __nmk_gpio_set_wake(nmk_chip
, d
->hwirq
, enable
);
703 spin_unlock(&nmk_chip
->lock
);
704 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
705 clk_disable(nmk_chip
->clk
);
710 static void nmk_gpio_irq_mask(struct irq_data
*d
)
712 nmk_gpio_irq_maskunmask(d
, false);
715 static void nmk_gpio_irq_unmask(struct irq_data
*d
)
717 nmk_gpio_irq_maskunmask(d
, true);
720 static int nmk_gpio_irq_set_wake(struct irq_data
*d
, unsigned int on
)
722 struct nmk_gpio_chip
*nmk_chip
;
726 nmk_chip
= irq_data_get_irq_chip_data(d
);
729 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
731 clk_enable(nmk_chip
->clk
);
732 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
733 spin_lock(&nmk_chip
->lock
);
735 if (irqd_irq_disabled(d
))
736 __nmk_gpio_set_wake(nmk_chip
, d
->hwirq
, on
);
739 nmk_chip
->real_wake
|= bitmask
;
741 nmk_chip
->real_wake
&= ~bitmask
;
743 spin_unlock(&nmk_chip
->lock
);
744 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
745 clk_disable(nmk_chip
->clk
);
750 static int nmk_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
752 bool enabled
= !irqd_irq_disabled(d
);
753 bool wake
= irqd_is_wakeup_set(d
);
754 struct nmk_gpio_chip
*nmk_chip
;
758 nmk_chip
= irq_data_get_irq_chip_data(d
);
759 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
762 if (type
& IRQ_TYPE_LEVEL_HIGH
)
764 if (type
& IRQ_TYPE_LEVEL_LOW
)
767 clk_enable(nmk_chip
->clk
);
768 spin_lock_irqsave(&nmk_chip
->lock
, flags
);
771 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, false);
774 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, WAKE
, false);
776 nmk_chip
->edge_rising
&= ~bitmask
;
777 if (type
& IRQ_TYPE_EDGE_RISING
)
778 nmk_chip
->edge_rising
|= bitmask
;
780 nmk_chip
->edge_falling
&= ~bitmask
;
781 if (type
& IRQ_TYPE_EDGE_FALLING
)
782 nmk_chip
->edge_falling
|= bitmask
;
785 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, true);
788 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, WAKE
, true);
790 spin_unlock_irqrestore(&nmk_chip
->lock
, flags
);
791 clk_disable(nmk_chip
->clk
);
796 static unsigned int nmk_gpio_irq_startup(struct irq_data
*d
)
798 struct nmk_gpio_chip
*nmk_chip
= irq_data_get_irq_chip_data(d
);
800 clk_enable(nmk_chip
->clk
);
801 nmk_gpio_irq_unmask(d
);
805 static void nmk_gpio_irq_shutdown(struct irq_data
*d
)
807 struct nmk_gpio_chip
*nmk_chip
= irq_data_get_irq_chip_data(d
);
809 nmk_gpio_irq_mask(d
);
810 clk_disable(nmk_chip
->clk
);
813 static struct irq_chip nmk_gpio_irq_chip
= {
814 .name
= "Nomadik-GPIO",
815 .irq_ack
= nmk_gpio_irq_ack
,
816 .irq_mask
= nmk_gpio_irq_mask
,
817 .irq_unmask
= nmk_gpio_irq_unmask
,
818 .irq_set_type
= nmk_gpio_irq_set_type
,
819 .irq_set_wake
= nmk_gpio_irq_set_wake
,
820 .irq_startup
= nmk_gpio_irq_startup
,
821 .irq_shutdown
= nmk_gpio_irq_shutdown
,
824 static void __nmk_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
,
827 struct nmk_gpio_chip
*nmk_chip
;
828 struct irq_chip
*host_chip
= irq_get_chip(irq
);
829 unsigned int first_irq
;
831 chained_irq_enter(host_chip
, desc
);
833 nmk_chip
= irq_get_handler_data(irq
);
834 first_irq
= nmk_chip
->domain
->revmap_data
.legacy
.first_irq
;
836 int bit
= __ffs(status
);
838 generic_handle_irq(first_irq
+ bit
);
842 chained_irq_exit(host_chip
, desc
);
845 static void nmk_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
847 struct nmk_gpio_chip
*nmk_chip
= irq_get_handler_data(irq
);
850 clk_enable(nmk_chip
->clk
);
851 status
= readl(nmk_chip
->addr
+ NMK_GPIO_IS
);
852 clk_disable(nmk_chip
->clk
);
854 __nmk_gpio_irq_handler(irq
, desc
, status
);
857 static void nmk_gpio_secondary_irq_handler(unsigned int irq
,
858 struct irq_desc
*desc
)
860 struct nmk_gpio_chip
*nmk_chip
= irq_get_handler_data(irq
);
861 u32 status
= nmk_chip
->get_secondary_status(nmk_chip
->bank
);
863 __nmk_gpio_irq_handler(irq
, desc
, status
);
866 static int nmk_gpio_init_irq(struct nmk_gpio_chip
*nmk_chip
)
868 irq_set_chained_handler(nmk_chip
->parent_irq
, nmk_gpio_irq_handler
);
869 irq_set_handler_data(nmk_chip
->parent_irq
, nmk_chip
);
871 if (nmk_chip
->secondary_parent_irq
>= 0) {
872 irq_set_chained_handler(nmk_chip
->secondary_parent_irq
,
873 nmk_gpio_secondary_irq_handler
);
874 irq_set_handler_data(nmk_chip
->secondary_parent_irq
, nmk_chip
);
882 static int nmk_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
885 * Map back to global GPIO space and request muxing, the direction
886 * parameter does not matter for this controller.
888 int gpio
= chip
->base
+ offset
;
890 return pinctrl_request_gpio(gpio
);
893 static void nmk_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
895 int gpio
= chip
->base
+ offset
;
897 pinctrl_free_gpio(gpio
);
900 static int nmk_gpio_make_input(struct gpio_chip
*chip
, unsigned offset
)
902 struct nmk_gpio_chip
*nmk_chip
=
903 container_of(chip
, struct nmk_gpio_chip
, chip
);
905 clk_enable(nmk_chip
->clk
);
907 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRC
);
909 clk_disable(nmk_chip
->clk
);
914 static int nmk_gpio_get_input(struct gpio_chip
*chip
, unsigned offset
)
916 struct nmk_gpio_chip
*nmk_chip
=
917 container_of(chip
, struct nmk_gpio_chip
, chip
);
918 u32 bit
= 1 << offset
;
921 clk_enable(nmk_chip
->clk
);
923 value
= (readl(nmk_chip
->addr
+ NMK_GPIO_DAT
) & bit
) != 0;
925 clk_disable(nmk_chip
->clk
);
930 static void nmk_gpio_set_output(struct gpio_chip
*chip
, unsigned offset
,
933 struct nmk_gpio_chip
*nmk_chip
=
934 container_of(chip
, struct nmk_gpio_chip
, chip
);
936 clk_enable(nmk_chip
->clk
);
938 __nmk_gpio_set_output(nmk_chip
, offset
, val
);
940 clk_disable(nmk_chip
->clk
);
943 static int nmk_gpio_make_output(struct gpio_chip
*chip
, unsigned offset
,
946 struct nmk_gpio_chip
*nmk_chip
=
947 container_of(chip
, struct nmk_gpio_chip
, chip
);
949 clk_enable(nmk_chip
->clk
);
951 __nmk_gpio_make_output(nmk_chip
, offset
, val
);
953 clk_disable(nmk_chip
->clk
);
958 static int nmk_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
960 struct nmk_gpio_chip
*nmk_chip
=
961 container_of(chip
, struct nmk_gpio_chip
, chip
);
963 return irq_find_mapping(nmk_chip
->domain
, offset
);
966 #ifdef CONFIG_DEBUG_FS
968 #include <linux/seq_file.h>
970 static void nmk_gpio_dbg_show_one(struct seq_file
*s
, struct gpio_chip
*chip
,
971 unsigned offset
, unsigned gpio
)
973 const char *label
= gpiochip_is_requested(chip
, offset
);
974 struct nmk_gpio_chip
*nmk_chip
=
975 container_of(chip
, struct nmk_gpio_chip
, chip
);
979 u32 bit
= 1 << offset
;
980 const char *modes
[] = {
981 [NMK_GPIO_ALT_GPIO
] = "gpio",
982 [NMK_GPIO_ALT_A
] = "altA",
983 [NMK_GPIO_ALT_B
] = "altB",
984 [NMK_GPIO_ALT_C
] = "altC",
987 clk_enable(nmk_chip
->clk
);
988 is_out
= !!(readl(nmk_chip
->addr
+ NMK_GPIO_DIR
) & bit
);
989 pull
= !(readl(nmk_chip
->addr
+ NMK_GPIO_PDIS
) & bit
);
990 mode
= nmk_gpio_get_mode(gpio
);
992 seq_printf(s
, " gpio-%-3d (%-20.20s) %s %s %s %s",
993 gpio
, label
?: "(none)",
994 is_out
? "out" : "in ",
996 ? (chip
->get(chip
, offset
) ? "hi" : "lo")
998 (mode
< 0) ? "unknown" : modes
[mode
],
999 pull
? "pull" : "none");
1001 if (label
&& !is_out
) {
1002 int irq
= gpio_to_irq(gpio
);
1003 struct irq_desc
*desc
= irq_to_desc(irq
);
1005 /* This races with request_irq(), set_irq_type(),
1006 * and set_irq_wake() ... but those are "rare".
1008 if (irq
>= 0 && desc
->action
) {
1010 u32 bitmask
= nmk_gpio_get_bitmask(gpio
);
1012 if (nmk_chip
->edge_rising
& bitmask
)
1013 trigger
= "edge-rising";
1014 else if (nmk_chip
->edge_falling
& bitmask
)
1015 trigger
= "edge-falling";
1017 trigger
= "edge-undefined";
1019 seq_printf(s
, " irq-%d %s%s",
1021 irqd_is_wakeup_set(&desc
->irq_data
)
1025 clk_disable(nmk_chip
->clk
);
1028 static void nmk_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1031 unsigned gpio
= chip
->base
;
1033 for (i
= 0; i
< chip
->ngpio
; i
++, gpio
++) {
1034 nmk_gpio_dbg_show_one(s
, chip
, i
, gpio
);
1035 seq_printf(s
, "\n");
1040 static inline void nmk_gpio_dbg_show_one(struct seq_file
*s
,
1041 struct gpio_chip
*chip
,
1042 unsigned offset
, unsigned gpio
)
1045 #define nmk_gpio_dbg_show NULL
1048 /* This structure is replicated for each GPIO block allocated at probe time */
1049 static struct gpio_chip nmk_gpio_template
= {
1050 .request
= nmk_gpio_request
,
1051 .free
= nmk_gpio_free
,
1052 .direction_input
= nmk_gpio_make_input
,
1053 .get
= nmk_gpio_get_input
,
1054 .direction_output
= nmk_gpio_make_output
,
1055 .set
= nmk_gpio_set_output
,
1056 .to_irq
= nmk_gpio_to_irq
,
1057 .dbg_show
= nmk_gpio_dbg_show
,
1061 void nmk_gpio_clocks_enable(void)
1065 for (i
= 0; i
< NUM_BANKS
; i
++) {
1066 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1071 clk_enable(chip
->clk
);
1075 void nmk_gpio_clocks_disable(void)
1079 for (i
= 0; i
< NUM_BANKS
; i
++) {
1080 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1085 clk_disable(chip
->clk
);
1090 * Called from the suspend/resume path to only keep the real wakeup interrupts
1091 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1092 * and not the rest of the interrupts which we needed to have as wakeups for
1095 * PM ops are not used since this needs to be done at the end, after all the
1096 * other drivers are done with their suspend callbacks.
1098 void nmk_gpio_wakeups_suspend(void)
1102 for (i
= 0; i
< NUM_BANKS
; i
++) {
1103 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1108 clk_enable(chip
->clk
);
1110 writel(chip
->rwimsc
& chip
->real_wake
,
1111 chip
->addr
+ NMK_GPIO_RWIMSC
);
1112 writel(chip
->fwimsc
& chip
->real_wake
,
1113 chip
->addr
+ NMK_GPIO_FWIMSC
);
1115 clk_disable(chip
->clk
);
1119 void nmk_gpio_wakeups_resume(void)
1123 for (i
= 0; i
< NUM_BANKS
; i
++) {
1124 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
1129 clk_enable(chip
->clk
);
1131 writel(chip
->rwimsc
, chip
->addr
+ NMK_GPIO_RWIMSC
);
1132 writel(chip
->fwimsc
, chip
->addr
+ NMK_GPIO_FWIMSC
);
1134 clk_disable(chip
->clk
);
1139 * Read the pull up/pull down status.
1140 * A bit set in 'pull_up' means that pull up
1141 * is selected if pull is enabled in PDIS register.
1142 * Note: only pull up/down set via this driver can
1143 * be detected due to HW limitations.
1145 void nmk_gpio_read_pull(int gpio_bank
, u32
*pull_up
)
1147 if (gpio_bank
< NUM_BANKS
) {
1148 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[gpio_bank
];
1153 *pull_up
= chip
->pull_up
;
1157 int nmk_gpio_irq_map(struct irq_domain
*d
, unsigned int irq
,
1158 irq_hw_number_t hwirq
)
1160 struct nmk_gpio_chip
*nmk_chip
= d
->host_data
;
1165 irq_set_chip_and_handler(irq
, &nmk_gpio_irq_chip
, handle_edge_irq
);
1166 set_irq_flags(irq
, IRQF_VALID
);
1167 irq_set_chip_data(irq
, nmk_chip
);
1168 irq_set_irq_type(irq
, IRQ_TYPE_EDGE_FALLING
);
1173 const struct irq_domain_ops nmk_gpio_irq_simple_ops
= {
1174 .map
= nmk_gpio_irq_map
,
1175 .xlate
= irq_domain_xlate_twocell
,
1178 static int __devinit
nmk_gpio_probe(struct platform_device
*dev
)
1180 struct nmk_gpio_platform_data
*pdata
= dev
->dev
.platform_data
;
1181 struct device_node
*np
= dev
->dev
.of_node
;
1182 struct nmk_gpio_chip
*nmk_chip
;
1183 struct gpio_chip
*chip
;
1184 struct resource
*res
;
1191 if (!pdata
&& !np
) {
1192 dev_err(&dev
->dev
, "No platform data or device tree found\n");
1197 pdata
= devm_kzalloc(&dev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1201 if (of_get_property(np
, "st,supports-sleepmode", NULL
))
1202 pdata
->supports_sleepmode
= true;
1204 if (of_property_read_u32(np
, "gpio-bank", &dev
->id
)) {
1205 dev_err(&dev
->dev
, "gpio-bank property not found\n");
1210 pdata
->first_gpio
= dev
->id
* NMK_GPIO_PER_CHIP
;
1211 pdata
->num_gpio
= NMK_GPIO_PER_CHIP
;
1214 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1220 irq
= platform_get_irq(dev
, 0);
1226 secondary_irq
= platform_get_irq(dev
, 1);
1227 if (secondary_irq
>= 0 && !pdata
->get_secondary_status
) {
1232 base
= devm_request_and_ioremap(&dev
->dev
, res
);
1238 clk
= devm_clk_get(&dev
->dev
, NULL
);
1245 nmk_chip
= devm_kzalloc(&dev
->dev
, sizeof(*nmk_chip
), GFP_KERNEL
);
1252 * The virt address in nmk_chip->addr is in the nomadik register space,
1253 * so we can simply convert the resource address, without remapping
1255 nmk_chip
->bank
= dev
->id
;
1256 nmk_chip
->clk
= clk
;
1257 nmk_chip
->addr
= base
;
1258 nmk_chip
->chip
= nmk_gpio_template
;
1259 nmk_chip
->parent_irq
= irq
;
1260 nmk_chip
->secondary_parent_irq
= secondary_irq
;
1261 nmk_chip
->get_secondary_status
= pdata
->get_secondary_status
;
1262 nmk_chip
->set_ioforce
= pdata
->set_ioforce
;
1263 nmk_chip
->sleepmode
= pdata
->supports_sleepmode
;
1264 spin_lock_init(&nmk_chip
->lock
);
1266 chip
= &nmk_chip
->chip
;
1267 chip
->base
= pdata
->first_gpio
;
1268 chip
->ngpio
= pdata
->num_gpio
;
1269 chip
->label
= pdata
->name
?: dev_name(&dev
->dev
);
1270 chip
->dev
= &dev
->dev
;
1271 chip
->owner
= THIS_MODULE
;
1273 clk_enable(nmk_chip
->clk
);
1274 nmk_chip
->lowemi
= readl_relaxed(nmk_chip
->addr
+ NMK_GPIO_LOWEMI
);
1275 clk_disable(nmk_chip
->clk
);
1277 #ifdef CONFIG_OF_GPIO
1281 ret
= gpiochip_add(&nmk_chip
->chip
);
1285 BUG_ON(nmk_chip
->bank
>= ARRAY_SIZE(nmk_gpio_chips
));
1287 nmk_gpio_chips
[nmk_chip
->bank
] = nmk_chip
;
1289 platform_set_drvdata(dev
, nmk_chip
);
1291 nmk_chip
->domain
= irq_domain_add_legacy(np
, NMK_GPIO_PER_CHIP
,
1292 NOMADIK_GPIO_TO_IRQ(pdata
->first_gpio
),
1293 0, &nmk_gpio_irq_simple_ops
, nmk_chip
);
1294 if (!nmk_chip
->domain
) {
1295 pr_err("%s: Failed to create irqdomain\n", np
->full_name
);
1300 nmk_gpio_init_irq(nmk_chip
);
1302 dev_info(&dev
->dev
, "at address %p\n", nmk_chip
->addr
);
1307 dev_err(&dev
->dev
, "Failure %i for GPIO %i-%i\n", ret
,
1308 pdata
->first_gpio
, pdata
->first_gpio
+31);
1313 static int nmk_get_groups_cnt(struct pinctrl_dev
*pctldev
)
1315 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1317 return npct
->soc
->ngroups
;
1320 static const char *nmk_get_group_name(struct pinctrl_dev
*pctldev
,
1323 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1325 return npct
->soc
->groups
[selector
].name
;
1328 static int nmk_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
1329 const unsigned **pins
,
1332 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1334 *pins
= npct
->soc
->groups
[selector
].pins
;
1335 *num_pins
= npct
->soc
->groups
[selector
].npins
;
1339 static struct pinctrl_gpio_range
*
1340 nmk_match_gpio_range(struct pinctrl_dev
*pctldev
, unsigned offset
)
1342 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1345 for (i
= 0; i
< npct
->soc
->gpio_num_ranges
; i
++) {
1346 struct pinctrl_gpio_range
*range
;
1348 range
= &npct
->soc
->gpio_ranges
[i
];
1349 if (offset
>= range
->pin_base
&&
1350 offset
<= (range
->pin_base
+ range
->npins
- 1))
1356 static void nmk_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
1359 struct pinctrl_gpio_range
*range
;
1360 struct gpio_chip
*chip
;
1362 range
= nmk_match_gpio_range(pctldev
, offset
);
1363 if (!range
|| !range
->gc
) {
1364 seq_printf(s
, "invalid pin offset");
1368 nmk_gpio_dbg_show_one(s
, chip
, offset
- chip
->base
, offset
);
1371 static struct pinctrl_ops nmk_pinctrl_ops
= {
1372 .get_groups_count
= nmk_get_groups_cnt
,
1373 .get_group_name
= nmk_get_group_name
,
1374 .get_group_pins
= nmk_get_group_pins
,
1375 .pin_dbg_show
= nmk_pin_dbg_show
,
1378 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
1380 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1382 return npct
->soc
->nfunctions
;
1385 static const char *nmk_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
1388 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1390 return npct
->soc
->functions
[function
].name
;
1393 static int nmk_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
1395 const char * const **groups
,
1396 unsigned * const num_groups
)
1398 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1400 *groups
= npct
->soc
->functions
[function
].groups
;
1401 *num_groups
= npct
->soc
->functions
[function
].ngroups
;
1406 static int nmk_pmx_enable(struct pinctrl_dev
*pctldev
, unsigned function
,
1409 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1410 const struct nmk_pingroup
*g
;
1411 static unsigned int slpm
[NUM_BANKS
];
1412 unsigned long flags
;
1417 g
= &npct
->soc
->groups
[group
];
1419 if (g
->altsetting
< 0)
1422 dev_dbg(npct
->dev
, "enable group %s, %u pins\n", g
->name
, g
->npins
);
1425 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1426 * we may pass through an undesired state. In this case we take
1429 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1430 * - Save SLPM registers (since we have a shadow register in the
1431 * nmk_chip we're using that as backup)
1432 * - Set SLPM=0 for the IOs you want to switch and others to 1
1433 * - Configure the GPIO registers for the IOs that are being switched
1435 * - Modify the AFLSA/B registers for the IOs that are being switched
1437 * - Restore SLPM registers
1438 * - Any spurious wake up event during switch sequence to be ignored
1441 * We REALLY need to save ALL slpm registers, because the external
1442 * IOFORCE will switch *all* ports to their sleepmode setting to as
1443 * to avoid glitches. (Not just one port!)
1445 glitch
= (g
->altsetting
== NMK_GPIO_ALT_C
);
1448 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
1450 /* Initially don't put any pins to sleep when switching */
1451 memset(slpm
, 0xff, sizeof(slpm
));
1454 * Then mask the pins that need to be sleeping now when we're
1455 * switching to the ALT C function.
1457 for (i
= 0; i
< g
->npins
; i
++)
1458 slpm
[g
->pins
[i
] / NMK_GPIO_PER_CHIP
] &= ~BIT(g
->pins
[i
]);
1459 nmk_gpio_glitch_slpm_init(slpm
);
1462 for (i
= 0; i
< g
->npins
; i
++) {
1463 struct pinctrl_gpio_range
*range
;
1464 struct nmk_gpio_chip
*nmk_chip
;
1465 struct gpio_chip
*chip
;
1468 range
= nmk_match_gpio_range(pctldev
, g
->pins
[i
]);
1471 "invalid pin offset %d in group %s at index %d\n",
1472 g
->pins
[i
], g
->name
, i
);
1476 dev_err(npct
->dev
, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1477 g
->pins
[i
], g
->name
, i
);
1481 nmk_chip
= container_of(chip
, struct nmk_gpio_chip
, chip
);
1482 dev_dbg(npct
->dev
, "setting pin %d to altsetting %d\n", g
->pins
[i
], g
->altsetting
);
1484 clk_enable(nmk_chip
->clk
);
1485 bit
= g
->pins
[i
] % NMK_GPIO_PER_CHIP
;
1487 * If the pin is switching to altfunc, and there was an
1488 * interrupt installed on it which has been lazy disabled,
1489 * actually mask the interrupt to prevent spurious interrupts
1490 * that would occur while the pin is under control of the
1491 * peripheral. Only SKE does this.
1493 nmk_gpio_disable_lazy_irq(nmk_chip
, bit
);
1495 __nmk_gpio_set_mode_safe(nmk_chip
, bit
, g
->altsetting
, glitch
);
1496 clk_disable(nmk_chip
->clk
);
1499 /* When all pins are successfully reconfigured we get here */
1504 nmk_gpio_glitch_slpm_restore(slpm
);
1505 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
1511 static void nmk_pmx_disable(struct pinctrl_dev
*pctldev
,
1512 unsigned function
, unsigned group
)
1514 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1515 const struct nmk_pingroup
*g
;
1517 g
= &npct
->soc
->groups
[group
];
1519 if (g
->altsetting
< 0)
1522 /* Poke out the mux, set the pin to some default state? */
1523 dev_dbg(npct
->dev
, "disable group %s, %u pins\n", g
->name
, g
->npins
);
1526 int nmk_gpio_request_enable(struct pinctrl_dev
*pctldev
,
1527 struct pinctrl_gpio_range
*range
,
1530 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1531 struct nmk_gpio_chip
*nmk_chip
;
1532 struct gpio_chip
*chip
;
1536 dev_err(npct
->dev
, "invalid range\n");
1540 dev_err(npct
->dev
, "missing GPIO chip in range\n");
1544 nmk_chip
= container_of(chip
, struct nmk_gpio_chip
, chip
);
1546 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
1548 clk_enable(nmk_chip
->clk
);
1549 bit
= offset
% NMK_GPIO_PER_CHIP
;
1550 /* There is no glitch when converting any pin to GPIO */
1551 __nmk_gpio_set_mode(nmk_chip
, bit
, NMK_GPIO_ALT_GPIO
);
1552 clk_disable(nmk_chip
->clk
);
1557 void nmk_gpio_disable_free(struct pinctrl_dev
*pctldev
,
1558 struct pinctrl_gpio_range
*range
,
1561 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1563 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
1564 /* Set the pin to some default state, GPIO is usually default */
1567 static struct pinmux_ops nmk_pinmux_ops
= {
1568 .get_functions_count
= nmk_pmx_get_funcs_cnt
,
1569 .get_function_name
= nmk_pmx_get_func_name
,
1570 .get_function_groups
= nmk_pmx_get_func_groups
,
1571 .enable
= nmk_pmx_enable
,
1572 .disable
= nmk_pmx_disable
,
1573 .gpio_request_enable
= nmk_gpio_request_enable
,
1574 .gpio_disable_free
= nmk_gpio_disable_free
,
1577 int nmk_pin_config_get(struct pinctrl_dev
*pctldev
,
1579 unsigned long *config
)
1581 /* Not implemented */
1585 int nmk_pin_config_set(struct pinctrl_dev
*pctldev
,
1587 unsigned long config
)
1589 static const char *pullnames
[] = {
1590 [NMK_GPIO_PULL_NONE
] = "none",
1591 [NMK_GPIO_PULL_UP
] = "up",
1592 [NMK_GPIO_PULL_DOWN
] = "down",
1593 [3] /* illegal */ = "??"
1595 static const char *slpmnames
[] = {
1596 [NMK_GPIO_SLPM_INPUT
] = "input/wakeup",
1597 [NMK_GPIO_SLPM_NOCHANGE
] = "no-change/no-wakeup",
1599 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1600 struct nmk_gpio_chip
*nmk_chip
;
1601 struct pinctrl_gpio_range
*range
;
1602 struct gpio_chip
*chip
;
1606 * The pin config contains pin number and altfunction fields, here
1607 * we just ignore that part. It's being handled by the framework and
1608 * pinmux callback respectively.
1610 pin_cfg_t cfg
= (pin_cfg_t
) config
;
1611 int pull
= PIN_PULL(cfg
);
1612 int slpm
= PIN_SLPM(cfg
);
1613 int output
= PIN_DIR(cfg
);
1614 int val
= PIN_VAL(cfg
);
1615 bool lowemi
= PIN_LOWEMI(cfg
);
1616 bool gpiomode
= PIN_GPIOMODE(cfg
);
1617 bool sleep
= PIN_SLEEPMODE(cfg
);
1619 range
= nmk_match_gpio_range(pctldev
, pin
);
1621 dev_err(npct
->dev
, "invalid pin offset %d\n", pin
);
1625 dev_err(npct
->dev
, "GPIO chip missing in range for pin %d\n",
1630 nmk_chip
= container_of(chip
, struct nmk_gpio_chip
, chip
);
1633 int slpm_pull
= PIN_SLPM_PULL(cfg
);
1634 int slpm_output
= PIN_SLPM_DIR(cfg
);
1635 int slpm_val
= PIN_SLPM_VAL(cfg
);
1637 /* All pins go into GPIO mode at sleep */
1641 * The SLPM_* values are normal values + 1 to allow zero to
1642 * mean "same as normal".
1645 pull
= slpm_pull
- 1;
1647 output
= slpm_output
- 1;
1651 dev_dbg(nmk_chip
->chip
.dev
, "pin %d: sleep pull %s, dir %s, val %s\n",
1653 slpm_pull
? pullnames
[pull
] : "same",
1654 slpm_output
? (output
? "output" : "input") : "same",
1655 slpm_val
? (val
? "high" : "low") : "same");
1658 dev_dbg(nmk_chip
->chip
.dev
, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1659 pin
, cfg
, pullnames
[pull
], slpmnames
[slpm
],
1660 output
? "output " : "input",
1661 output
? (val
? "high" : "low") : "",
1662 lowemi
? "on" : "off" );
1664 clk_enable(nmk_chip
->clk
);
1665 bit
= pin
% NMK_GPIO_PER_CHIP
;
1667 /* No glitch when going to GPIO mode */
1668 __nmk_gpio_set_mode(nmk_chip
, bit
, NMK_GPIO_ALT_GPIO
);
1670 __nmk_gpio_make_output(nmk_chip
, bit
, val
);
1672 __nmk_gpio_make_input(nmk_chip
, bit
);
1673 __nmk_gpio_set_pull(nmk_chip
, bit
, pull
);
1675 /* TODO: isn't this only applicable on output pins? */
1676 __nmk_gpio_set_lowemi(nmk_chip
, bit
, lowemi
);
1678 __nmk_gpio_set_slpm(nmk_chip
, bit
, slpm
);
1679 clk_disable(nmk_chip
->clk
);
1683 static struct pinconf_ops nmk_pinconf_ops
= {
1684 .pin_config_get
= nmk_pin_config_get
,
1685 .pin_config_set
= nmk_pin_config_set
,
1688 static struct pinctrl_desc nmk_pinctrl_desc
= {
1689 .name
= "pinctrl-nomadik",
1690 .pctlops
= &nmk_pinctrl_ops
,
1691 .pmxops
= &nmk_pinmux_ops
,
1692 .confops
= &nmk_pinconf_ops
,
1693 .owner
= THIS_MODULE
,
1696 static const struct of_device_id nmk_pinctrl_match
[] = {
1698 .compatible
= "stericsson,nmk_pinctrl",
1699 .data
= (void *)PINCTRL_NMK_DB8500
,
1704 static int __devinit
nmk_pinctrl_probe(struct platform_device
*pdev
)
1706 const struct platform_device_id
*platid
= platform_get_device_id(pdev
);
1707 struct device_node
*np
= pdev
->dev
.of_node
;
1708 struct nmk_pinctrl
*npct
;
1709 unsigned int version
= 0;
1712 npct
= devm_kzalloc(&pdev
->dev
, sizeof(*npct
), GFP_KERNEL
);
1717 version
= platid
->driver_data
;
1719 version
= (unsigned int)
1720 of_match_device(nmk_pinctrl_match
, &pdev
->dev
)->data
;
1722 /* Poke in other ASIC variants here */
1723 if (version
== PINCTRL_NMK_DB8500
)
1724 nmk_pinctrl_db8500_init(&npct
->soc
);
1727 * We need all the GPIO drivers to probe FIRST, or we will not be able
1728 * to obtain references to the struct gpio_chip * for them, and we
1729 * need this to proceed.
1731 for (i
= 0; i
< npct
->soc
->gpio_num_ranges
; i
++) {
1732 if (!nmk_gpio_chips
[i
]) {
1733 dev_warn(&pdev
->dev
, "GPIO chip %d not registered yet\n", i
);
1734 devm_kfree(&pdev
->dev
, npct
);
1735 return -EPROBE_DEFER
;
1737 npct
->soc
->gpio_ranges
[i
].gc
= &nmk_gpio_chips
[i
]->chip
;
1740 nmk_pinctrl_desc
.pins
= npct
->soc
->pins
;
1741 nmk_pinctrl_desc
.npins
= npct
->soc
->npins
;
1742 npct
->dev
= &pdev
->dev
;
1743 npct
->pctl
= pinctrl_register(&nmk_pinctrl_desc
, &pdev
->dev
, npct
);
1745 dev_err(&pdev
->dev
, "could not register Nomadik pinctrl driver\n");
1749 /* We will handle a range of GPIO pins */
1750 for (i
= 0; i
< npct
->soc
->gpio_num_ranges
; i
++)
1751 pinctrl_add_gpio_range(npct
->pctl
, &npct
->soc
->gpio_ranges
[i
]);
1753 platform_set_drvdata(pdev
, npct
);
1754 dev_info(&pdev
->dev
, "initialized Nomadik pin control driver\n");
1759 static const struct of_device_id nmk_gpio_match
[] = {
1760 { .compatible
= "st,nomadik-gpio", },
1764 static struct platform_driver nmk_gpio_driver
= {
1766 .owner
= THIS_MODULE
,
1768 .of_match_table
= nmk_gpio_match
,
1770 .probe
= nmk_gpio_probe
,
1773 static const struct platform_device_id nmk_pinctrl_id
[] = {
1774 { "pinctrl-stn8815", PINCTRL_NMK_STN8815
},
1775 { "pinctrl-db8500", PINCTRL_NMK_DB8500
},
1778 static struct platform_driver nmk_pinctrl_driver
= {
1780 .owner
= THIS_MODULE
,
1781 .name
= "pinctrl-nomadik",
1782 .of_match_table
= nmk_pinctrl_match
,
1784 .probe
= nmk_pinctrl_probe
,
1785 .id_table
= nmk_pinctrl_id
,
1788 static int __init
nmk_gpio_init(void)
1792 ret
= platform_driver_register(&nmk_gpio_driver
);
1795 return platform_driver_register(&nmk_pinctrl_driver
);
1798 core_initcall(nmk_gpio_init
);
1800 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1801 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1802 MODULE_LICENSE("GPL");