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Merge branch 'for-jens' of git://git.drbd.org/linux-drbd into for-3.6/drivers
[deliverable/linux.git] / drivers / pinctrl / pinctrl-nomadik.c
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33
34 #include <asm/mach/irq.h>
35
36 #include <plat/pincfg.h>
37 #include <plat/gpio-nomadik.h>
38
39 #include "pinctrl-nomadik.h"
40
41 /*
42 * The GPIO module in the Nomadik family of Systems-on-Chip is an
43 * AMBA device, managing 32 pins and alternate functions. The logic block
44 * is currently used in the Nomadik and ux500.
45 *
46 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
47 */
48
49 #define NMK_GPIO_PER_CHIP 32
50
51 struct nmk_gpio_chip {
52 struct gpio_chip chip;
53 struct irq_domain *domain;
54 void __iomem *addr;
55 struct clk *clk;
56 unsigned int bank;
57 unsigned int parent_irq;
58 int secondary_parent_irq;
59 u32 (*get_secondary_status)(unsigned int bank);
60 void (*set_ioforce)(bool enable);
61 spinlock_t lock;
62 bool sleepmode;
63 /* Keep track of configured edges */
64 u32 edge_rising;
65 u32 edge_falling;
66 u32 real_wake;
67 u32 rwimsc;
68 u32 fwimsc;
69 u32 rimsc;
70 u32 fimsc;
71 u32 pull_up;
72 u32 lowemi;
73 };
74
75 struct nmk_pinctrl {
76 struct device *dev;
77 struct pinctrl_dev *pctl;
78 const struct nmk_pinctrl_soc_data *soc;
79 };
80
81 static struct nmk_gpio_chip *
82 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
83
84 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
85
86 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
87
88 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
89 unsigned offset, int gpio_mode)
90 {
91 u32 bit = 1 << offset;
92 u32 afunc, bfunc;
93
94 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
95 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
96 if (gpio_mode & NMK_GPIO_ALT_A)
97 afunc |= bit;
98 if (gpio_mode & NMK_GPIO_ALT_B)
99 bfunc |= bit;
100 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
101 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
102 }
103
104 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
105 unsigned offset, enum nmk_gpio_slpm mode)
106 {
107 u32 bit = 1 << offset;
108 u32 slpm;
109
110 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
111 if (mode == NMK_GPIO_SLPM_NOCHANGE)
112 slpm |= bit;
113 else
114 slpm &= ~bit;
115 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
116 }
117
118 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
119 unsigned offset, enum nmk_gpio_pull pull)
120 {
121 u32 bit = 1 << offset;
122 u32 pdis;
123
124 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
125 if (pull == NMK_GPIO_PULL_NONE) {
126 pdis |= bit;
127 nmk_chip->pull_up &= ~bit;
128 } else {
129 pdis &= ~bit;
130 }
131
132 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
133
134 if (pull == NMK_GPIO_PULL_UP) {
135 nmk_chip->pull_up |= bit;
136 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
137 } else if (pull == NMK_GPIO_PULL_DOWN) {
138 nmk_chip->pull_up &= ~bit;
139 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
140 }
141 }
142
143 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
144 unsigned offset, bool lowemi)
145 {
146 u32 bit = BIT(offset);
147 bool enabled = nmk_chip->lowemi & bit;
148
149 if (lowemi == enabled)
150 return;
151
152 if (lowemi)
153 nmk_chip->lowemi |= bit;
154 else
155 nmk_chip->lowemi &= ~bit;
156
157 writel_relaxed(nmk_chip->lowemi,
158 nmk_chip->addr + NMK_GPIO_LOWEMI);
159 }
160
161 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
162 unsigned offset)
163 {
164 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
165 }
166
167 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
168 unsigned offset, int val)
169 {
170 if (val)
171 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
172 else
173 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
174 }
175
176 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
177 unsigned offset, int val)
178 {
179 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
180 __nmk_gpio_set_output(nmk_chip, offset, val);
181 }
182
183 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
184 unsigned offset, int gpio_mode,
185 bool glitch)
186 {
187 u32 rwimsc = nmk_chip->rwimsc;
188 u32 fwimsc = nmk_chip->fwimsc;
189
190 if (glitch && nmk_chip->set_ioforce) {
191 u32 bit = BIT(offset);
192
193 /* Prevent spurious wakeups */
194 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
195 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
196
197 nmk_chip->set_ioforce(true);
198 }
199
200 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
201
202 if (glitch && nmk_chip->set_ioforce) {
203 nmk_chip->set_ioforce(false);
204
205 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
206 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
207 }
208 }
209
210 static void
211 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
212 {
213 u32 falling = nmk_chip->fimsc & BIT(offset);
214 u32 rising = nmk_chip->rimsc & BIT(offset);
215 int gpio = nmk_chip->chip.base + offset;
216 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
217 struct irq_data *d = irq_get_irq_data(irq);
218
219 if (!rising && !falling)
220 return;
221
222 if (!d || !irqd_irq_disabled(d))
223 return;
224
225 if (rising) {
226 nmk_chip->rimsc &= ~BIT(offset);
227 writel_relaxed(nmk_chip->rimsc,
228 nmk_chip->addr + NMK_GPIO_RIMSC);
229 }
230
231 if (falling) {
232 nmk_chip->fimsc &= ~BIT(offset);
233 writel_relaxed(nmk_chip->fimsc,
234 nmk_chip->addr + NMK_GPIO_FIMSC);
235 }
236
237 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
238 }
239
240 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
241 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
242 {
243 static const char *afnames[] = {
244 [NMK_GPIO_ALT_GPIO] = "GPIO",
245 [NMK_GPIO_ALT_A] = "A",
246 [NMK_GPIO_ALT_B] = "B",
247 [NMK_GPIO_ALT_C] = "C"
248 };
249 static const char *pullnames[] = {
250 [NMK_GPIO_PULL_NONE] = "none",
251 [NMK_GPIO_PULL_UP] = "up",
252 [NMK_GPIO_PULL_DOWN] = "down",
253 [3] /* illegal */ = "??"
254 };
255 static const char *slpmnames[] = {
256 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
257 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
258 };
259
260 int pin = PIN_NUM(cfg);
261 int pull = PIN_PULL(cfg);
262 int af = PIN_ALT(cfg);
263 int slpm = PIN_SLPM(cfg);
264 int output = PIN_DIR(cfg);
265 int val = PIN_VAL(cfg);
266 bool glitch = af == NMK_GPIO_ALT_C;
267
268 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
269 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
270 output ? "output " : "input",
271 output ? (val ? "high" : "low") : "");
272
273 if (sleep) {
274 int slpm_pull = PIN_SLPM_PULL(cfg);
275 int slpm_output = PIN_SLPM_DIR(cfg);
276 int slpm_val = PIN_SLPM_VAL(cfg);
277
278 af = NMK_GPIO_ALT_GPIO;
279
280 /*
281 * The SLPM_* values are normal values + 1 to allow zero to
282 * mean "same as normal".
283 */
284 if (slpm_pull)
285 pull = slpm_pull - 1;
286 if (slpm_output)
287 output = slpm_output - 1;
288 if (slpm_val)
289 val = slpm_val - 1;
290
291 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
292 pin,
293 slpm_pull ? pullnames[pull] : "same",
294 slpm_output ? (output ? "output" : "input") : "same",
295 slpm_val ? (val ? "high" : "low") : "same");
296 }
297
298 if (output)
299 __nmk_gpio_make_output(nmk_chip, offset, val);
300 else {
301 __nmk_gpio_make_input(nmk_chip, offset);
302 __nmk_gpio_set_pull(nmk_chip, offset, pull);
303 }
304
305 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
306
307 /*
308 * If the pin is switching to altfunc, and there was an interrupt
309 * installed on it which has been lazy disabled, actually mask the
310 * interrupt to prevent spurious interrupts that would occur while the
311 * pin is under control of the peripheral. Only SKE does this.
312 */
313 if (af != NMK_GPIO_ALT_GPIO)
314 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
315
316 /*
317 * If we've backed up the SLPM registers (glitch workaround), modify
318 * the backups since they will be restored.
319 */
320 if (slpmregs) {
321 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
322 slpmregs[nmk_chip->bank] |= BIT(offset);
323 else
324 slpmregs[nmk_chip->bank] &= ~BIT(offset);
325 } else
326 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
327
328 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
329 }
330
331 /*
332 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
333 * - Save SLPM registers
334 * - Set SLPM=0 for the IOs you want to switch and others to 1
335 * - Configure the GPIO registers for the IOs that are being switched
336 * - Set IOFORCE=1
337 * - Modify the AFLSA/B registers for the IOs that are being switched
338 * - Set IOFORCE=0
339 * - Restore SLPM registers
340 * - Any spurious wake up event during switch sequence to be ignored and
341 * cleared
342 */
343 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
344 {
345 int i;
346
347 for (i = 0; i < NUM_BANKS; i++) {
348 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
349 unsigned int temp = slpm[i];
350
351 if (!chip)
352 break;
353
354 clk_enable(chip->clk);
355
356 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
357 writel(temp, chip->addr + NMK_GPIO_SLPC);
358 }
359 }
360
361 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
362 {
363 int i;
364
365 for (i = 0; i < NUM_BANKS; i++) {
366 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
367
368 if (!chip)
369 break;
370
371 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
372
373 clk_disable(chip->clk);
374 }
375 }
376
377 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
378 {
379 static unsigned int slpm[NUM_BANKS];
380 unsigned long flags;
381 bool glitch = false;
382 int ret = 0;
383 int i;
384
385 for (i = 0; i < num; i++) {
386 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
387 glitch = true;
388 break;
389 }
390 }
391
392 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
393
394 if (glitch) {
395 memset(slpm, 0xff, sizeof(slpm));
396
397 for (i = 0; i < num; i++) {
398 int pin = PIN_NUM(cfgs[i]);
399 int offset = pin % NMK_GPIO_PER_CHIP;
400
401 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
402 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
403 }
404
405 nmk_gpio_glitch_slpm_init(slpm);
406 }
407
408 for (i = 0; i < num; i++) {
409 struct nmk_gpio_chip *nmk_chip;
410 int pin = PIN_NUM(cfgs[i]);
411
412 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
413 if (!nmk_chip) {
414 ret = -EINVAL;
415 break;
416 }
417
418 clk_enable(nmk_chip->clk);
419 spin_lock(&nmk_chip->lock);
420 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
421 cfgs[i], sleep, glitch ? slpm : NULL);
422 spin_unlock(&nmk_chip->lock);
423 clk_disable(nmk_chip->clk);
424 }
425
426 if (glitch)
427 nmk_gpio_glitch_slpm_restore(slpm);
428
429 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
430
431 return ret;
432 }
433
434 /**
435 * nmk_config_pin - configure a pin's mux attributes
436 * @cfg: pin confguration
437 *
438 * Configures a pin's mode (alternate function or GPIO), its pull up status,
439 * and its sleep mode based on the specified configuration. The @cfg is
440 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
441 * are constructed using, and can be further enhanced with, the macros in
442 * plat/pincfg.h.
443 *
444 * If a pin's mode is set to GPIO, it is configured as an input to avoid
445 * side-effects. The gpio can be manipulated later using standard GPIO API
446 * calls.
447 */
448 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
449 {
450 return __nmk_config_pins(&cfg, 1, sleep);
451 }
452 EXPORT_SYMBOL(nmk_config_pin);
453
454 /**
455 * nmk_config_pins - configure several pins at once
456 * @cfgs: array of pin configurations
457 * @num: number of elments in the array
458 *
459 * Configures several pins using nmk_config_pin(). Refer to that function for
460 * further information.
461 */
462 int nmk_config_pins(pin_cfg_t *cfgs, int num)
463 {
464 return __nmk_config_pins(cfgs, num, false);
465 }
466 EXPORT_SYMBOL(nmk_config_pins);
467
468 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
469 {
470 return __nmk_config_pins(cfgs, num, true);
471 }
472 EXPORT_SYMBOL(nmk_config_pins_sleep);
473
474 /**
475 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
476 * @gpio: pin number
477 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
478 *
479 * This register is actually in the pinmux layer, not the GPIO block itself.
480 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
481 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
482 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
483 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
484 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
485 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
486 *
487 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
488 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
489 * entered) regardless of the altfunction selected. Also wake-up detection is
490 * ENABLED.
491 *
492 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
493 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
494 * (for altfunction GPIO) or respective on-chip peripherals (for other
495 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
496 *
497 * Note that enable_irq_wake() will automatically enable wakeup detection.
498 */
499 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
500 {
501 struct nmk_gpio_chip *nmk_chip;
502 unsigned long flags;
503
504 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
505 if (!nmk_chip)
506 return -EINVAL;
507
508 clk_enable(nmk_chip->clk);
509 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
510 spin_lock(&nmk_chip->lock);
511
512 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
513
514 spin_unlock(&nmk_chip->lock);
515 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
516 clk_disable(nmk_chip->clk);
517
518 return 0;
519 }
520
521 /**
522 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
523 * @gpio: pin number
524 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
525 *
526 * Enables/disables pull up/down on a specified pin. This only takes effect if
527 * the pin is configured as an input (either explicitly or by the alternate
528 * function).
529 *
530 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
531 * configured as an input. Otherwise, due to the way the controller registers
532 * work, this function will change the value output on the pin.
533 */
534 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
535 {
536 struct nmk_gpio_chip *nmk_chip;
537 unsigned long flags;
538
539 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
540 if (!nmk_chip)
541 return -EINVAL;
542
543 clk_enable(nmk_chip->clk);
544 spin_lock_irqsave(&nmk_chip->lock, flags);
545 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
546 spin_unlock_irqrestore(&nmk_chip->lock, flags);
547 clk_disable(nmk_chip->clk);
548
549 return 0;
550 }
551
552 /* Mode functions */
553 /**
554 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
555 * @gpio: pin number
556 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
557 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
558 *
559 * Sets the mode of the specified pin to one of the alternate functions or
560 * plain GPIO.
561 */
562 int nmk_gpio_set_mode(int gpio, int gpio_mode)
563 {
564 struct nmk_gpio_chip *nmk_chip;
565 unsigned long flags;
566
567 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
568 if (!nmk_chip)
569 return -EINVAL;
570
571 clk_enable(nmk_chip->clk);
572 spin_lock_irqsave(&nmk_chip->lock, flags);
573 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
574 spin_unlock_irqrestore(&nmk_chip->lock, flags);
575 clk_disable(nmk_chip->clk);
576
577 return 0;
578 }
579 EXPORT_SYMBOL(nmk_gpio_set_mode);
580
581 int nmk_gpio_get_mode(int gpio)
582 {
583 struct nmk_gpio_chip *nmk_chip;
584 u32 afunc, bfunc, bit;
585
586 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
587 if (!nmk_chip)
588 return -EINVAL;
589
590 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
591
592 clk_enable(nmk_chip->clk);
593
594 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
595 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
596
597 clk_disable(nmk_chip->clk);
598
599 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
600 }
601 EXPORT_SYMBOL(nmk_gpio_get_mode);
602
603
604 /* IRQ functions */
605 static inline int nmk_gpio_get_bitmask(int gpio)
606 {
607 return 1 << (gpio % NMK_GPIO_PER_CHIP);
608 }
609
610 static void nmk_gpio_irq_ack(struct irq_data *d)
611 {
612 struct nmk_gpio_chip *nmk_chip;
613
614 nmk_chip = irq_data_get_irq_chip_data(d);
615 if (!nmk_chip)
616 return;
617
618 clk_enable(nmk_chip->clk);
619 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
620 clk_disable(nmk_chip->clk);
621 }
622
623 enum nmk_gpio_irq_type {
624 NORMAL,
625 WAKE,
626 };
627
628 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
629 int gpio, enum nmk_gpio_irq_type which,
630 bool enable)
631 {
632 u32 bitmask = nmk_gpio_get_bitmask(gpio);
633 u32 *rimscval;
634 u32 *fimscval;
635 u32 rimscreg;
636 u32 fimscreg;
637
638 if (which == NORMAL) {
639 rimscreg = NMK_GPIO_RIMSC;
640 fimscreg = NMK_GPIO_FIMSC;
641 rimscval = &nmk_chip->rimsc;
642 fimscval = &nmk_chip->fimsc;
643 } else {
644 rimscreg = NMK_GPIO_RWIMSC;
645 fimscreg = NMK_GPIO_FWIMSC;
646 rimscval = &nmk_chip->rwimsc;
647 fimscval = &nmk_chip->fwimsc;
648 }
649
650 /* we must individually set/clear the two edges */
651 if (nmk_chip->edge_rising & bitmask) {
652 if (enable)
653 *rimscval |= bitmask;
654 else
655 *rimscval &= ~bitmask;
656 writel(*rimscval, nmk_chip->addr + rimscreg);
657 }
658 if (nmk_chip->edge_falling & bitmask) {
659 if (enable)
660 *fimscval |= bitmask;
661 else
662 *fimscval &= ~bitmask;
663 writel(*fimscval, nmk_chip->addr + fimscreg);
664 }
665 }
666
667 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
668 int gpio, bool on)
669 {
670 /*
671 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
672 * disabled, since setting SLPM to 1 increases power consumption, and
673 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
674 */
675 if (nmk_chip->sleepmode && on) {
676 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
677 NMK_GPIO_SLPM_WAKEUP_ENABLE);
678 }
679
680 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
681 }
682
683 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
684 {
685 struct nmk_gpio_chip *nmk_chip;
686 unsigned long flags;
687 u32 bitmask;
688
689 nmk_chip = irq_data_get_irq_chip_data(d);
690 bitmask = nmk_gpio_get_bitmask(d->hwirq);
691 if (!nmk_chip)
692 return -EINVAL;
693
694 clk_enable(nmk_chip->clk);
695 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
696 spin_lock(&nmk_chip->lock);
697
698 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
699
700 if (!(nmk_chip->real_wake & bitmask))
701 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
702
703 spin_unlock(&nmk_chip->lock);
704 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
705 clk_disable(nmk_chip->clk);
706
707 return 0;
708 }
709
710 static void nmk_gpio_irq_mask(struct irq_data *d)
711 {
712 nmk_gpio_irq_maskunmask(d, false);
713 }
714
715 static void nmk_gpio_irq_unmask(struct irq_data *d)
716 {
717 nmk_gpio_irq_maskunmask(d, true);
718 }
719
720 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
721 {
722 struct nmk_gpio_chip *nmk_chip;
723 unsigned long flags;
724 u32 bitmask;
725
726 nmk_chip = irq_data_get_irq_chip_data(d);
727 if (!nmk_chip)
728 return -EINVAL;
729 bitmask = nmk_gpio_get_bitmask(d->hwirq);
730
731 clk_enable(nmk_chip->clk);
732 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
733 spin_lock(&nmk_chip->lock);
734
735 if (irqd_irq_disabled(d))
736 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
737
738 if (on)
739 nmk_chip->real_wake |= bitmask;
740 else
741 nmk_chip->real_wake &= ~bitmask;
742
743 spin_unlock(&nmk_chip->lock);
744 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
745 clk_disable(nmk_chip->clk);
746
747 return 0;
748 }
749
750 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
751 {
752 bool enabled = !irqd_irq_disabled(d);
753 bool wake = irqd_is_wakeup_set(d);
754 struct nmk_gpio_chip *nmk_chip;
755 unsigned long flags;
756 u32 bitmask;
757
758 nmk_chip = irq_data_get_irq_chip_data(d);
759 bitmask = nmk_gpio_get_bitmask(d->hwirq);
760 if (!nmk_chip)
761 return -EINVAL;
762 if (type & IRQ_TYPE_LEVEL_HIGH)
763 return -EINVAL;
764 if (type & IRQ_TYPE_LEVEL_LOW)
765 return -EINVAL;
766
767 clk_enable(nmk_chip->clk);
768 spin_lock_irqsave(&nmk_chip->lock, flags);
769
770 if (enabled)
771 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
772
773 if (enabled || wake)
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
775
776 nmk_chip->edge_rising &= ~bitmask;
777 if (type & IRQ_TYPE_EDGE_RISING)
778 nmk_chip->edge_rising |= bitmask;
779
780 nmk_chip->edge_falling &= ~bitmask;
781 if (type & IRQ_TYPE_EDGE_FALLING)
782 nmk_chip->edge_falling |= bitmask;
783
784 if (enabled)
785 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
786
787 if (enabled || wake)
788 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
789
790 spin_unlock_irqrestore(&nmk_chip->lock, flags);
791 clk_disable(nmk_chip->clk);
792
793 return 0;
794 }
795
796 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
797 {
798 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
799
800 clk_enable(nmk_chip->clk);
801 nmk_gpio_irq_unmask(d);
802 return 0;
803 }
804
805 static void nmk_gpio_irq_shutdown(struct irq_data *d)
806 {
807 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
808
809 nmk_gpio_irq_mask(d);
810 clk_disable(nmk_chip->clk);
811 }
812
813 static struct irq_chip nmk_gpio_irq_chip = {
814 .name = "Nomadik-GPIO",
815 .irq_ack = nmk_gpio_irq_ack,
816 .irq_mask = nmk_gpio_irq_mask,
817 .irq_unmask = nmk_gpio_irq_unmask,
818 .irq_set_type = nmk_gpio_irq_set_type,
819 .irq_set_wake = nmk_gpio_irq_set_wake,
820 .irq_startup = nmk_gpio_irq_startup,
821 .irq_shutdown = nmk_gpio_irq_shutdown,
822 };
823
824 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
825 u32 status)
826 {
827 struct nmk_gpio_chip *nmk_chip;
828 struct irq_chip *host_chip = irq_get_chip(irq);
829 unsigned int first_irq;
830
831 chained_irq_enter(host_chip, desc);
832
833 nmk_chip = irq_get_handler_data(irq);
834 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
835 while (status) {
836 int bit = __ffs(status);
837
838 generic_handle_irq(first_irq + bit);
839 status &= ~BIT(bit);
840 }
841
842 chained_irq_exit(host_chip, desc);
843 }
844
845 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
846 {
847 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
848 u32 status;
849
850 clk_enable(nmk_chip->clk);
851 status = readl(nmk_chip->addr + NMK_GPIO_IS);
852 clk_disable(nmk_chip->clk);
853
854 __nmk_gpio_irq_handler(irq, desc, status);
855 }
856
857 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
858 struct irq_desc *desc)
859 {
860 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
861 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
862
863 __nmk_gpio_irq_handler(irq, desc, status);
864 }
865
866 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
867 {
868 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
869 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
870
871 if (nmk_chip->secondary_parent_irq >= 0) {
872 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
873 nmk_gpio_secondary_irq_handler);
874 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
875 }
876
877 return 0;
878 }
879
880 /* I/O Functions */
881
882 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
883 {
884 /*
885 * Map back to global GPIO space and request muxing, the direction
886 * parameter does not matter for this controller.
887 */
888 int gpio = chip->base + offset;
889
890 return pinctrl_request_gpio(gpio);
891 }
892
893 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
894 {
895 int gpio = chip->base + offset;
896
897 pinctrl_free_gpio(gpio);
898 }
899
900 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
901 {
902 struct nmk_gpio_chip *nmk_chip =
903 container_of(chip, struct nmk_gpio_chip, chip);
904
905 clk_enable(nmk_chip->clk);
906
907 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
908
909 clk_disable(nmk_chip->clk);
910
911 return 0;
912 }
913
914 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
915 {
916 struct nmk_gpio_chip *nmk_chip =
917 container_of(chip, struct nmk_gpio_chip, chip);
918 u32 bit = 1 << offset;
919 int value;
920
921 clk_enable(nmk_chip->clk);
922
923 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
924
925 clk_disable(nmk_chip->clk);
926
927 return value;
928 }
929
930 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
931 int val)
932 {
933 struct nmk_gpio_chip *nmk_chip =
934 container_of(chip, struct nmk_gpio_chip, chip);
935
936 clk_enable(nmk_chip->clk);
937
938 __nmk_gpio_set_output(nmk_chip, offset, val);
939
940 clk_disable(nmk_chip->clk);
941 }
942
943 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
944 int val)
945 {
946 struct nmk_gpio_chip *nmk_chip =
947 container_of(chip, struct nmk_gpio_chip, chip);
948
949 clk_enable(nmk_chip->clk);
950
951 __nmk_gpio_make_output(nmk_chip, offset, val);
952
953 clk_disable(nmk_chip->clk);
954
955 return 0;
956 }
957
958 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
959 {
960 struct nmk_gpio_chip *nmk_chip =
961 container_of(chip, struct nmk_gpio_chip, chip);
962
963 return irq_find_mapping(nmk_chip->domain, offset);
964 }
965
966 #ifdef CONFIG_DEBUG_FS
967
968 #include <linux/seq_file.h>
969
970 static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
971 unsigned offset, unsigned gpio)
972 {
973 const char *label = gpiochip_is_requested(chip, offset);
974 struct nmk_gpio_chip *nmk_chip =
975 container_of(chip, struct nmk_gpio_chip, chip);
976 int mode;
977 bool is_out;
978 bool pull;
979 u32 bit = 1 << offset;
980 const char *modes[] = {
981 [NMK_GPIO_ALT_GPIO] = "gpio",
982 [NMK_GPIO_ALT_A] = "altA",
983 [NMK_GPIO_ALT_B] = "altB",
984 [NMK_GPIO_ALT_C] = "altC",
985 };
986
987 clk_enable(nmk_chip->clk);
988 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
989 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
990 mode = nmk_gpio_get_mode(gpio);
991
992 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
993 gpio, label ?: "(none)",
994 is_out ? "out" : "in ",
995 chip->get
996 ? (chip->get(chip, offset) ? "hi" : "lo")
997 : "? ",
998 (mode < 0) ? "unknown" : modes[mode],
999 pull ? "pull" : "none");
1000
1001 if (label && !is_out) {
1002 int irq = gpio_to_irq(gpio);
1003 struct irq_desc *desc = irq_to_desc(irq);
1004
1005 /* This races with request_irq(), set_irq_type(),
1006 * and set_irq_wake() ... but those are "rare".
1007 */
1008 if (irq >= 0 && desc->action) {
1009 char *trigger;
1010 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1011
1012 if (nmk_chip->edge_rising & bitmask)
1013 trigger = "edge-rising";
1014 else if (nmk_chip->edge_falling & bitmask)
1015 trigger = "edge-falling";
1016 else
1017 trigger = "edge-undefined";
1018
1019 seq_printf(s, " irq-%d %s%s",
1020 irq, trigger,
1021 irqd_is_wakeup_set(&desc->irq_data)
1022 ? " wakeup" : "");
1023 }
1024 }
1025 clk_disable(nmk_chip->clk);
1026 }
1027
1028 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1029 {
1030 unsigned i;
1031 unsigned gpio = chip->base;
1032
1033 for (i = 0; i < chip->ngpio; i++, gpio++) {
1034 nmk_gpio_dbg_show_one(s, chip, i, gpio);
1035 seq_printf(s, "\n");
1036 }
1037 }
1038
1039 #else
1040 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1041 struct gpio_chip *chip,
1042 unsigned offset, unsigned gpio)
1043 {
1044 }
1045 #define nmk_gpio_dbg_show NULL
1046 #endif
1047
1048 /* This structure is replicated for each GPIO block allocated at probe time */
1049 static struct gpio_chip nmk_gpio_template = {
1050 .request = nmk_gpio_request,
1051 .free = nmk_gpio_free,
1052 .direction_input = nmk_gpio_make_input,
1053 .get = nmk_gpio_get_input,
1054 .direction_output = nmk_gpio_make_output,
1055 .set = nmk_gpio_set_output,
1056 .to_irq = nmk_gpio_to_irq,
1057 .dbg_show = nmk_gpio_dbg_show,
1058 .can_sleep = 0,
1059 };
1060
1061 void nmk_gpio_clocks_enable(void)
1062 {
1063 int i;
1064
1065 for (i = 0; i < NUM_BANKS; i++) {
1066 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1067
1068 if (!chip)
1069 continue;
1070
1071 clk_enable(chip->clk);
1072 }
1073 }
1074
1075 void nmk_gpio_clocks_disable(void)
1076 {
1077 int i;
1078
1079 for (i = 0; i < NUM_BANKS; i++) {
1080 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1081
1082 if (!chip)
1083 continue;
1084
1085 clk_disable(chip->clk);
1086 }
1087 }
1088
1089 /*
1090 * Called from the suspend/resume path to only keep the real wakeup interrupts
1091 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1092 * and not the rest of the interrupts which we needed to have as wakeups for
1093 * cpuidle.
1094 *
1095 * PM ops are not used since this needs to be done at the end, after all the
1096 * other drivers are done with their suspend callbacks.
1097 */
1098 void nmk_gpio_wakeups_suspend(void)
1099 {
1100 int i;
1101
1102 for (i = 0; i < NUM_BANKS; i++) {
1103 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1104
1105 if (!chip)
1106 break;
1107
1108 clk_enable(chip->clk);
1109
1110 writel(chip->rwimsc & chip->real_wake,
1111 chip->addr + NMK_GPIO_RWIMSC);
1112 writel(chip->fwimsc & chip->real_wake,
1113 chip->addr + NMK_GPIO_FWIMSC);
1114
1115 clk_disable(chip->clk);
1116 }
1117 }
1118
1119 void nmk_gpio_wakeups_resume(void)
1120 {
1121 int i;
1122
1123 for (i = 0; i < NUM_BANKS; i++) {
1124 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1125
1126 if (!chip)
1127 break;
1128
1129 clk_enable(chip->clk);
1130
1131 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1132 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1133
1134 clk_disable(chip->clk);
1135 }
1136 }
1137
1138 /*
1139 * Read the pull up/pull down status.
1140 * A bit set in 'pull_up' means that pull up
1141 * is selected if pull is enabled in PDIS register.
1142 * Note: only pull up/down set via this driver can
1143 * be detected due to HW limitations.
1144 */
1145 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1146 {
1147 if (gpio_bank < NUM_BANKS) {
1148 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1149
1150 if (!chip)
1151 return;
1152
1153 *pull_up = chip->pull_up;
1154 }
1155 }
1156
1157 int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1158 irq_hw_number_t hwirq)
1159 {
1160 struct nmk_gpio_chip *nmk_chip = d->host_data;
1161
1162 if (!nmk_chip)
1163 return -EINVAL;
1164
1165 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1166 set_irq_flags(irq, IRQF_VALID);
1167 irq_set_chip_data(irq, nmk_chip);
1168 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1169
1170 return 0;
1171 }
1172
1173 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1174 .map = nmk_gpio_irq_map,
1175 .xlate = irq_domain_xlate_twocell,
1176 };
1177
1178 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1179 {
1180 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1181 struct device_node *np = dev->dev.of_node;
1182 struct nmk_gpio_chip *nmk_chip;
1183 struct gpio_chip *chip;
1184 struct resource *res;
1185 struct clk *clk;
1186 int secondary_irq;
1187 void __iomem *base;
1188 int irq;
1189 int ret;
1190
1191 if (!pdata && !np) {
1192 dev_err(&dev->dev, "No platform data or device tree found\n");
1193 return -ENODEV;
1194 }
1195
1196 if (np) {
1197 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1198 if (!pdata)
1199 return -ENOMEM;
1200
1201 if (of_get_property(np, "supports-sleepmode", NULL))
1202 pdata->supports_sleepmode = true;
1203
1204 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1205 dev_err(&dev->dev, "gpio-bank property not found\n");
1206 ret = -EINVAL;
1207 goto out;
1208 }
1209
1210 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1211 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1212 }
1213
1214 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1215 if (!res) {
1216 ret = -ENOENT;
1217 goto out;
1218 }
1219
1220 irq = platform_get_irq(dev, 0);
1221 if (irq < 0) {
1222 ret = irq;
1223 goto out;
1224 }
1225
1226 secondary_irq = platform_get_irq(dev, 1);
1227 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1228 ret = -EINVAL;
1229 goto out;
1230 }
1231
1232 if (request_mem_region(res->start, resource_size(res),
1233 dev_name(&dev->dev)) == NULL) {
1234 ret = -EBUSY;
1235 goto out;
1236 }
1237
1238 base = ioremap(res->start, resource_size(res));
1239 if (!base) {
1240 ret = -ENOMEM;
1241 goto out_release;
1242 }
1243
1244 clk = clk_get(&dev->dev, NULL);
1245 if (IS_ERR(clk)) {
1246 ret = PTR_ERR(clk);
1247 goto out_unmap;
1248 }
1249 clk_prepare(clk);
1250
1251 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1252 if (!nmk_chip) {
1253 ret = -ENOMEM;
1254 goto out_clk;
1255 }
1256
1257 /*
1258 * The virt address in nmk_chip->addr is in the nomadik register space,
1259 * so we can simply convert the resource address, without remapping
1260 */
1261 nmk_chip->bank = dev->id;
1262 nmk_chip->clk = clk;
1263 nmk_chip->addr = base;
1264 nmk_chip->chip = nmk_gpio_template;
1265 nmk_chip->parent_irq = irq;
1266 nmk_chip->secondary_parent_irq = secondary_irq;
1267 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1268 nmk_chip->set_ioforce = pdata->set_ioforce;
1269 nmk_chip->sleepmode = pdata->supports_sleepmode;
1270 spin_lock_init(&nmk_chip->lock);
1271
1272 chip = &nmk_chip->chip;
1273 chip->base = pdata->first_gpio;
1274 chip->ngpio = pdata->num_gpio;
1275 chip->label = pdata->name ?: dev_name(&dev->dev);
1276 chip->dev = &dev->dev;
1277 chip->owner = THIS_MODULE;
1278
1279 clk_enable(nmk_chip->clk);
1280 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1281 clk_disable(nmk_chip->clk);
1282
1283 #ifdef CONFIG_OF_GPIO
1284 chip->of_node = np;
1285 #endif
1286
1287 ret = gpiochip_add(&nmk_chip->chip);
1288 if (ret)
1289 goto out_free;
1290
1291 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1292
1293 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1294
1295 platform_set_drvdata(dev, nmk_chip);
1296
1297 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1298 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1299 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1300 if (!nmk_chip->domain) {
1301 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1302 ret = -ENOSYS;
1303 goto out_free;
1304 }
1305
1306 nmk_gpio_init_irq(nmk_chip);
1307
1308 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1309
1310 return 0;
1311
1312 out_free:
1313 kfree(nmk_chip);
1314 out_clk:
1315 clk_disable(clk);
1316 clk_put(clk);
1317 out_unmap:
1318 iounmap(base);
1319 out_release:
1320 release_mem_region(res->start, resource_size(res));
1321 out:
1322 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1323 pdata->first_gpio, pdata->first_gpio+31);
1324 if (np)
1325 kfree(pdata);
1326
1327 return ret;
1328 }
1329
1330 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1331 {
1332 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1333
1334 return npct->soc->ngroups;
1335 }
1336
1337 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1338 unsigned selector)
1339 {
1340 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1341
1342 return npct->soc->groups[selector].name;
1343 }
1344
1345 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1346 const unsigned **pins,
1347 unsigned *num_pins)
1348 {
1349 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1350
1351 *pins = npct->soc->groups[selector].pins;
1352 *num_pins = npct->soc->groups[selector].npins;
1353 return 0;
1354 }
1355
1356 static struct pinctrl_gpio_range *
1357 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1358 {
1359 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1360 int i;
1361
1362 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1363 struct pinctrl_gpio_range *range;
1364
1365 range = &npct->soc->gpio_ranges[i];
1366 if (offset >= range->pin_base &&
1367 offset <= (range->pin_base + range->npins - 1))
1368 return range;
1369 }
1370 return NULL;
1371 }
1372
1373 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1374 unsigned offset)
1375 {
1376 struct pinctrl_gpio_range *range;
1377 struct gpio_chip *chip;
1378
1379 range = nmk_match_gpio_range(pctldev, offset);
1380 if (!range || !range->gc) {
1381 seq_printf(s, "invalid pin offset");
1382 return;
1383 }
1384 chip = range->gc;
1385 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1386 }
1387
1388 static struct pinctrl_ops nmk_pinctrl_ops = {
1389 .get_groups_count = nmk_get_groups_cnt,
1390 .get_group_name = nmk_get_group_name,
1391 .get_group_pins = nmk_get_group_pins,
1392 .pin_dbg_show = nmk_pin_dbg_show,
1393 };
1394
1395 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1396 {
1397 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1398
1399 return npct->soc->nfunctions;
1400 }
1401
1402 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1403 unsigned function)
1404 {
1405 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1406
1407 return npct->soc->functions[function].name;
1408 }
1409
1410 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1411 unsigned function,
1412 const char * const **groups,
1413 unsigned * const num_groups)
1414 {
1415 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1416
1417 *groups = npct->soc->functions[function].groups;
1418 *num_groups = npct->soc->functions[function].ngroups;
1419
1420 return 0;
1421 }
1422
1423 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1424 unsigned group)
1425 {
1426 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1427 const struct nmk_pingroup *g;
1428 static unsigned int slpm[NUM_BANKS];
1429 unsigned long flags;
1430 bool glitch;
1431 int ret = -EINVAL;
1432 int i;
1433
1434 g = &npct->soc->groups[group];
1435
1436 if (g->altsetting < 0)
1437 return -EINVAL;
1438
1439 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1440
1441 /*
1442 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1443 * we may pass through an undesired state. In this case we take
1444 * some extra care.
1445 *
1446 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1447 * - Save SLPM registers (since we have a shadow register in the
1448 * nmk_chip we're using that as backup)
1449 * - Set SLPM=0 for the IOs you want to switch and others to 1
1450 * - Configure the GPIO registers for the IOs that are being switched
1451 * - Set IOFORCE=1
1452 * - Modify the AFLSA/B registers for the IOs that are being switched
1453 * - Set IOFORCE=0
1454 * - Restore SLPM registers
1455 * - Any spurious wake up event during switch sequence to be ignored
1456 * and cleared
1457 *
1458 * We REALLY need to save ALL slpm registers, because the external
1459 * IOFORCE will switch *all* ports to their sleepmode setting to as
1460 * to avoid glitches. (Not just one port!)
1461 */
1462 glitch = (g->altsetting == NMK_GPIO_ALT_C);
1463
1464 if (glitch) {
1465 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1466
1467 /* Initially don't put any pins to sleep when switching */
1468 memset(slpm, 0xff, sizeof(slpm));
1469
1470 /*
1471 * Then mask the pins that need to be sleeping now when we're
1472 * switching to the ALT C function.
1473 */
1474 for (i = 0; i < g->npins; i++)
1475 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1476 nmk_gpio_glitch_slpm_init(slpm);
1477 }
1478
1479 for (i = 0; i < g->npins; i++) {
1480 struct pinctrl_gpio_range *range;
1481 struct nmk_gpio_chip *nmk_chip;
1482 struct gpio_chip *chip;
1483 unsigned bit;
1484
1485 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1486 if (!range) {
1487 dev_err(npct->dev,
1488 "invalid pin offset %d in group %s at index %d\n",
1489 g->pins[i], g->name, i);
1490 goto out_glitch;
1491 }
1492 if (!range->gc) {
1493 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1494 g->pins[i], g->name, i);
1495 goto out_glitch;
1496 }
1497 chip = range->gc;
1498 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1499 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1500
1501 clk_enable(nmk_chip->clk);
1502 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1503 /*
1504 * If the pin is switching to altfunc, and there was an
1505 * interrupt installed on it which has been lazy disabled,
1506 * actually mask the interrupt to prevent spurious interrupts
1507 * that would occur while the pin is under control of the
1508 * peripheral. Only SKE does this.
1509 */
1510 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1511
1512 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
1513 clk_disable(nmk_chip->clk);
1514 }
1515
1516 /* When all pins are successfully reconfigured we get here */
1517 ret = 0;
1518
1519 out_glitch:
1520 if (glitch) {
1521 nmk_gpio_glitch_slpm_restore(slpm);
1522 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1523 }
1524
1525 return ret;
1526 }
1527
1528 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1529 unsigned function, unsigned group)
1530 {
1531 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1532 const struct nmk_pingroup *g;
1533
1534 g = &npct->soc->groups[group];
1535
1536 if (g->altsetting < 0)
1537 return;
1538
1539 /* Poke out the mux, set the pin to some default state? */
1540 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1541 }
1542
1543 int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1544 struct pinctrl_gpio_range *range,
1545 unsigned offset)
1546 {
1547 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1548 struct nmk_gpio_chip *nmk_chip;
1549 struct gpio_chip *chip;
1550 unsigned bit;
1551
1552 if (!range) {
1553 dev_err(npct->dev, "invalid range\n");
1554 return -EINVAL;
1555 }
1556 if (!range->gc) {
1557 dev_err(npct->dev, "missing GPIO chip in range\n");
1558 return -EINVAL;
1559 }
1560 chip = range->gc;
1561 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1562
1563 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1564
1565 clk_enable(nmk_chip->clk);
1566 bit = offset % NMK_GPIO_PER_CHIP;
1567 /* There is no glitch when converting any pin to GPIO */
1568 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1569 clk_disable(nmk_chip->clk);
1570
1571 return 0;
1572 }
1573
1574 void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1575 struct pinctrl_gpio_range *range,
1576 unsigned offset)
1577 {
1578 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1579
1580 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1581 /* Set the pin to some default state, GPIO is usually default */
1582 }
1583
1584 static struct pinmux_ops nmk_pinmux_ops = {
1585 .get_functions_count = nmk_pmx_get_funcs_cnt,
1586 .get_function_name = nmk_pmx_get_func_name,
1587 .get_function_groups = nmk_pmx_get_func_groups,
1588 .enable = nmk_pmx_enable,
1589 .disable = nmk_pmx_disable,
1590 .gpio_request_enable = nmk_gpio_request_enable,
1591 .gpio_disable_free = nmk_gpio_disable_free,
1592 };
1593
1594 int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1595 unsigned pin,
1596 unsigned long *config)
1597 {
1598 /* Not implemented */
1599 return -EINVAL;
1600 }
1601
1602 int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1603 unsigned pin,
1604 unsigned long config)
1605 {
1606 static const char *pullnames[] = {
1607 [NMK_GPIO_PULL_NONE] = "none",
1608 [NMK_GPIO_PULL_UP] = "up",
1609 [NMK_GPIO_PULL_DOWN] = "down",
1610 [3] /* illegal */ = "??"
1611 };
1612 static const char *slpmnames[] = {
1613 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1614 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1615 };
1616 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1617 struct nmk_gpio_chip *nmk_chip;
1618 struct pinctrl_gpio_range *range;
1619 struct gpio_chip *chip;
1620 unsigned bit;
1621
1622 /*
1623 * The pin config contains pin number and altfunction fields, here
1624 * we just ignore that part. It's being handled by the framework and
1625 * pinmux callback respectively.
1626 */
1627 pin_cfg_t cfg = (pin_cfg_t) config;
1628 int pull = PIN_PULL(cfg);
1629 int slpm = PIN_SLPM(cfg);
1630 int output = PIN_DIR(cfg);
1631 int val = PIN_VAL(cfg);
1632 bool lowemi = PIN_LOWEMI(cfg);
1633 bool gpiomode = PIN_GPIOMODE(cfg);
1634 bool sleep = PIN_SLEEPMODE(cfg);
1635
1636 range = nmk_match_gpio_range(pctldev, pin);
1637 if (!range) {
1638 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1639 return -EINVAL;
1640 }
1641 if (!range->gc) {
1642 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1643 pin);
1644 return -EINVAL;
1645 }
1646 chip = range->gc;
1647 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1648
1649 if (sleep) {
1650 int slpm_pull = PIN_SLPM_PULL(cfg);
1651 int slpm_output = PIN_SLPM_DIR(cfg);
1652 int slpm_val = PIN_SLPM_VAL(cfg);
1653
1654 /* All pins go into GPIO mode at sleep */
1655 gpiomode = true;
1656
1657 /*
1658 * The SLPM_* values are normal values + 1 to allow zero to
1659 * mean "same as normal".
1660 */
1661 if (slpm_pull)
1662 pull = slpm_pull - 1;
1663 if (slpm_output)
1664 output = slpm_output - 1;
1665 if (slpm_val)
1666 val = slpm_val - 1;
1667
1668 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1669 pin,
1670 slpm_pull ? pullnames[pull] : "same",
1671 slpm_output ? (output ? "output" : "input") : "same",
1672 slpm_val ? (val ? "high" : "low") : "same");
1673 }
1674
1675 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1676 pin, cfg, pullnames[pull], slpmnames[slpm],
1677 output ? "output " : "input",
1678 output ? (val ? "high" : "low") : "",
1679 lowemi ? "on" : "off" );
1680
1681 clk_enable(nmk_chip->clk);
1682 bit = pin % NMK_GPIO_PER_CHIP;
1683 if (gpiomode)
1684 /* No glitch when going to GPIO mode */
1685 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1686 if (output)
1687 __nmk_gpio_make_output(nmk_chip, bit, val);
1688 else {
1689 __nmk_gpio_make_input(nmk_chip, bit);
1690 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1691 }
1692 /* TODO: isn't this only applicable on output pins? */
1693 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1694
1695 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1696 clk_disable(nmk_chip->clk);
1697 return 0;
1698 }
1699
1700 static struct pinconf_ops nmk_pinconf_ops = {
1701 .pin_config_get = nmk_pin_config_get,
1702 .pin_config_set = nmk_pin_config_set,
1703 };
1704
1705 static struct pinctrl_desc nmk_pinctrl_desc = {
1706 .name = "pinctrl-nomadik",
1707 .pctlops = &nmk_pinctrl_ops,
1708 .pmxops = &nmk_pinmux_ops,
1709 .confops = &nmk_pinconf_ops,
1710 .owner = THIS_MODULE,
1711 };
1712
1713 static const struct of_device_id nmk_pinctrl_match[] = {
1714 {
1715 .compatible = "stericsson,nmk_pinctrl",
1716 .data = (void *)PINCTRL_NMK_DB8500,
1717 },
1718 {},
1719 };
1720
1721 static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1722 {
1723 const struct platform_device_id *platid = platform_get_device_id(pdev);
1724 struct device_node *np = pdev->dev.of_node;
1725 struct nmk_pinctrl *npct;
1726 unsigned int version = 0;
1727 int i;
1728
1729 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1730 if (!npct)
1731 return -ENOMEM;
1732
1733 if (platid)
1734 version = platid->driver_data;
1735 else if (np)
1736 version = (unsigned int)
1737 of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
1738
1739 /* Poke in other ASIC variants here */
1740 if (version == PINCTRL_NMK_DB8500)
1741 nmk_pinctrl_db8500_init(&npct->soc);
1742
1743 /*
1744 * We need all the GPIO drivers to probe FIRST, or we will not be able
1745 * to obtain references to the struct gpio_chip * for them, and we
1746 * need this to proceed.
1747 */
1748 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1749 if (!nmk_gpio_chips[i]) {
1750 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1751 devm_kfree(&pdev->dev, npct);
1752 return -EPROBE_DEFER;
1753 }
1754 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1755 }
1756
1757 nmk_pinctrl_desc.pins = npct->soc->pins;
1758 nmk_pinctrl_desc.npins = npct->soc->npins;
1759 npct->dev = &pdev->dev;
1760 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1761 if (!npct->pctl) {
1762 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1763 return -EINVAL;
1764 }
1765
1766 /* We will handle a range of GPIO pins */
1767 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1768 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1769
1770 platform_set_drvdata(pdev, npct);
1771 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1772
1773 return 0;
1774 }
1775
1776 static const struct of_device_id nmk_gpio_match[] = {
1777 { .compatible = "st,nomadik-gpio", },
1778 {}
1779 };
1780
1781 static struct platform_driver nmk_gpio_driver = {
1782 .driver = {
1783 .owner = THIS_MODULE,
1784 .name = "gpio",
1785 .of_match_table = nmk_gpio_match,
1786 },
1787 .probe = nmk_gpio_probe,
1788 };
1789
1790 static const struct platform_device_id nmk_pinctrl_id[] = {
1791 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1792 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1793 };
1794
1795 static struct platform_driver nmk_pinctrl_driver = {
1796 .driver = {
1797 .owner = THIS_MODULE,
1798 .name = "pinctrl-nomadik",
1799 .of_match_table = nmk_pinctrl_match,
1800 },
1801 .probe = nmk_pinctrl_probe,
1802 .id_table = nmk_pinctrl_id,
1803 };
1804
1805 static int __init nmk_gpio_init(void)
1806 {
1807 int ret;
1808
1809 ret = platform_driver_register(&nmk_gpio_driver);
1810 if (ret)
1811 return ret;
1812 return platform_driver_register(&nmk_pinctrl_driver);
1813 }
1814
1815 core_initcall(nmk_gpio_init);
1816
1817 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1818 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1819 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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