2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
61 enum rockchip_pinctrl_type
{
69 * Encode variants of iomux registers into a type variable
71 #define IOMUX_GPIO_ONLY BIT(0)
72 #define IOMUX_WIDTH_4BIT BIT(1)
73 #define IOMUX_SOURCE_PMU BIT(2)
74 #define IOMUX_UNROUTED BIT(3)
77 * @type: iomux variant using IOMUX_* constants
78 * @offset: if initialized to -1 it will be autocalculated, by specifying
79 * an initial offset value the relevant source offset can be reset
80 * to a new value for autocalculating the following iomux registers.
82 struct rockchip_iomux
{
88 * @reg_base: register base of the gpio bank
89 * @reg_pull: optional separate register for additional pull settings
90 * @clk: clock of the gpio bank
91 * @irq: interrupt of the gpio bank
92 * @pin_base: first pin number
93 * @nr_pins: number of pins in this bank
94 * @name: name of the bank
95 * @bank_num: number of the bank, to account for holes
96 * @iomux: array describing the 4 iomux sources of the bank
97 * @valid: are all necessary informations present
98 * @of_node: dt node of this bank
99 * @drvdata: common pinctrl basedata
100 * @domain: irqdomain of the gpio bank
101 * @gpio_chip: gpiolib chip
102 * @grange: gpio range
103 * @slock: spinlock for the gpio bank
105 struct rockchip_pin_bank
{
106 void __iomem
*reg_base
;
107 struct regmap
*regmap_pull
;
114 struct rockchip_iomux iomux
[4];
116 struct device_node
*of_node
;
117 struct rockchip_pinctrl
*drvdata
;
118 struct irq_domain
*domain
;
119 struct gpio_chip gpio_chip
;
120 struct pinctrl_gpio_range grange
;
122 u32 toggle_edge_mode
;
125 #define PIN_BANK(id, pins, label) \
138 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
144 { .type = iom0, .offset = -1 }, \
145 { .type = iom1, .offset = -1 }, \
146 { .type = iom2, .offset = -1 }, \
147 { .type = iom3, .offset = -1 }, \
153 struct rockchip_pin_ctrl
{
154 struct rockchip_pin_bank
*pin_banks
;
158 enum rockchip_pinctrl_type type
;
161 void (*pull_calc_reg
)(struct rockchip_pin_bank
*bank
,
162 int pin_num
, struct regmap
**regmap
,
166 struct rockchip_pin_config
{
168 unsigned long *configs
;
169 unsigned int nconfigs
;
173 * struct rockchip_pin_group: represent group of pins of a pinmux function.
174 * @name: name of the pin group, used to lookup the group.
175 * @pins: the pins included in this group.
176 * @npins: number of pins included in this group.
177 * @func: the mux function number to be programmed when selected.
178 * @configs: the config values to be set for each pin
179 * @nconfigs: number of configs for each pin
181 struct rockchip_pin_group
{
185 struct rockchip_pin_config
*data
;
189 * struct rockchip_pmx_func: represent a pin function.
190 * @name: name of the pin function, used to lookup the function.
191 * @groups: one or more names of pin groups that provide this function.
192 * @num_groups: number of groups included in @groups.
194 struct rockchip_pmx_func
{
200 struct rockchip_pinctrl
{
201 struct regmap
*regmap_base
;
203 struct regmap
*regmap_pull
;
204 struct regmap
*regmap_pmu
;
206 struct rockchip_pin_ctrl
*ctrl
;
207 struct pinctrl_desc pctl
;
208 struct pinctrl_dev
*pctl_dev
;
209 struct rockchip_pin_group
*groups
;
210 unsigned int ngroups
;
211 struct rockchip_pmx_func
*functions
;
212 unsigned int nfunctions
;
215 static struct regmap_config rockchip_regmap_config
= {
221 static inline struct rockchip_pin_bank
*gc_to_pin_bank(struct gpio_chip
*gc
)
223 return container_of(gc
, struct rockchip_pin_bank
, gpio_chip
);
226 static const inline struct rockchip_pin_group
*pinctrl_name_to_group(
227 const struct rockchip_pinctrl
*info
,
232 for (i
= 0; i
< info
->ngroups
; i
++) {
233 if (!strcmp(info
->groups
[i
].name
, name
))
234 return &info
->groups
[i
];
241 * given a pin number that is local to a pin controller, find out the pin bank
242 * and the register base of the pin bank.
244 static struct rockchip_pin_bank
*pin_to_bank(struct rockchip_pinctrl
*info
,
247 struct rockchip_pin_bank
*b
= info
->ctrl
->pin_banks
;
249 while (pin
>= (b
->pin_base
+ b
->nr_pins
))
255 static struct rockchip_pin_bank
*bank_num_to_bank(
256 struct rockchip_pinctrl
*info
,
259 struct rockchip_pin_bank
*b
= info
->ctrl
->pin_banks
;
262 for (i
= 0; i
< info
->ctrl
->nr_banks
; i
++, b
++) {
263 if (b
->bank_num
== num
)
267 return ERR_PTR(-EINVAL
);
271 * Pinctrl_ops handling
274 static int rockchip_get_groups_count(struct pinctrl_dev
*pctldev
)
276 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
278 return info
->ngroups
;
281 static const char *rockchip_get_group_name(struct pinctrl_dev
*pctldev
,
284 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
286 return info
->groups
[selector
].name
;
289 static int rockchip_get_group_pins(struct pinctrl_dev
*pctldev
,
290 unsigned selector
, const unsigned **pins
,
293 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
295 if (selector
>= info
->ngroups
)
298 *pins
= info
->groups
[selector
].pins
;
299 *npins
= info
->groups
[selector
].npins
;
304 static int rockchip_dt_node_to_map(struct pinctrl_dev
*pctldev
,
305 struct device_node
*np
,
306 struct pinctrl_map
**map
, unsigned *num_maps
)
308 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
309 const struct rockchip_pin_group
*grp
;
310 struct pinctrl_map
*new_map
;
311 struct device_node
*parent
;
316 * first find the group of this node and check if we need to create
317 * config maps for pins
319 grp
= pinctrl_name_to_group(info
, np
->name
);
321 dev_err(info
->dev
, "unable to find group for node %s\n",
326 map_num
+= grp
->npins
;
327 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
,
336 parent
= of_get_parent(np
);
338 devm_kfree(pctldev
->dev
, new_map
);
341 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
342 new_map
[0].data
.mux
.function
= parent
->name
;
343 new_map
[0].data
.mux
.group
= np
->name
;
346 /* create config map */
348 for (i
= 0; i
< grp
->npins
; i
++) {
349 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
350 new_map
[i
].data
.configs
.group_or_pin
=
351 pin_get_name(pctldev
, grp
->pins
[i
]);
352 new_map
[i
].data
.configs
.configs
= grp
->data
[i
].configs
;
353 new_map
[i
].data
.configs
.num_configs
= grp
->data
[i
].nconfigs
;
356 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
357 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
362 static void rockchip_dt_free_map(struct pinctrl_dev
*pctldev
,
363 struct pinctrl_map
*map
, unsigned num_maps
)
367 static const struct pinctrl_ops rockchip_pctrl_ops
= {
368 .get_groups_count
= rockchip_get_groups_count
,
369 .get_group_name
= rockchip_get_group_name
,
370 .get_group_pins
= rockchip_get_group_pins
,
371 .dt_node_to_map
= rockchip_dt_node_to_map
,
372 .dt_free_map
= rockchip_dt_free_map
,
379 static int rockchip_get_mux(struct rockchip_pin_bank
*bank
, int pin
)
381 struct rockchip_pinctrl
*info
= bank
->drvdata
;
382 int iomux_num
= (pin
/ 8);
383 struct regmap
*regmap
;
391 if (bank
->iomux
[iomux_num
].type
& IOMUX_UNROUTED
) {
392 dev_err(info
->dev
, "pin %d is unrouted\n", pin
);
396 if (bank
->iomux
[iomux_num
].type
& IOMUX_GPIO_ONLY
)
399 regmap
= (bank
->iomux
[iomux_num
].type
& IOMUX_SOURCE_PMU
)
400 ? info
->regmap_pmu
: info
->regmap_base
;
402 /* get basic quadrupel of mux registers and the correct reg inside */
403 mask
= (bank
->iomux
[iomux_num
].type
& IOMUX_WIDTH_4BIT
) ? 0xf : 0x3;
404 reg
= bank
->iomux
[iomux_num
].offset
;
405 if (bank
->iomux
[iomux_num
].type
& IOMUX_WIDTH_4BIT
) {
413 ret
= regmap_read(regmap
, reg
, &val
);
417 return ((val
>> bit
) & mask
);
421 * Set a new mux function for a pin.
423 * The register is divided into the upper and lower 16 bit. When changing
424 * a value, the previous register value is not read and changed. Instead
425 * it seems the changed bits are marked in the upper 16 bit, while the
426 * changed value gets set in the same offset in the lower 16 bit.
427 * All pin settings seem to be 2 bit wide in both the upper and lower
429 * @bank: pin bank to change
430 * @pin: pin to change
431 * @mux: new mux function to set
433 static int rockchip_set_mux(struct rockchip_pin_bank
*bank
, int pin
, int mux
)
435 struct rockchip_pinctrl
*info
= bank
->drvdata
;
436 int iomux_num
= (pin
/ 8);
437 struct regmap
*regmap
;
446 if (bank
->iomux
[iomux_num
].type
& IOMUX_UNROUTED
) {
447 dev_err(info
->dev
, "pin %d is unrouted\n", pin
);
451 if (bank
->iomux
[iomux_num
].type
& IOMUX_GPIO_ONLY
) {
452 if (mux
!= RK_FUNC_GPIO
) {
454 "pin %d only supports a gpio mux\n", pin
);
461 dev_dbg(info
->dev
, "setting mux of GPIO%d-%d to %d\n",
462 bank
->bank_num
, pin
, mux
);
464 regmap
= (bank
->iomux
[iomux_num
].type
& IOMUX_SOURCE_PMU
)
465 ? info
->regmap_pmu
: info
->regmap_base
;
467 /* get basic quadrupel of mux registers and the correct reg inside */
468 mask
= (bank
->iomux
[iomux_num
].type
& IOMUX_WIDTH_4BIT
) ? 0xf : 0x3;
469 reg
= bank
->iomux
[iomux_num
].offset
;
470 if (bank
->iomux
[iomux_num
].type
& IOMUX_WIDTH_4BIT
) {
478 spin_lock_irqsave(&bank
->slock
, flags
);
480 data
= (mask
<< (bit
+ 16));
481 rmask
= data
| (data
>> 16);
482 data
|= (mux
& mask
) << bit
;
483 ret
= regmap_update_bits(regmap
, reg
, rmask
, data
);
485 spin_unlock_irqrestore(&bank
->slock
, flags
);
490 #define RK2928_PULL_OFFSET 0x118
491 #define RK2928_PULL_PINS_PER_REG 16
492 #define RK2928_PULL_BANK_STRIDE 8
494 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank
*bank
,
495 int pin_num
, struct regmap
**regmap
,
498 struct rockchip_pinctrl
*info
= bank
->drvdata
;
500 *regmap
= info
->regmap_base
;
501 *reg
= RK2928_PULL_OFFSET
;
502 *reg
+= bank
->bank_num
* RK2928_PULL_BANK_STRIDE
;
503 *reg
+= (pin_num
/ RK2928_PULL_PINS_PER_REG
) * 4;
505 *bit
= pin_num
% RK2928_PULL_PINS_PER_REG
;
508 #define RK3188_PULL_OFFSET 0x164
509 #define RK3188_PULL_BITS_PER_PIN 2
510 #define RK3188_PULL_PINS_PER_REG 8
511 #define RK3188_PULL_BANK_STRIDE 16
512 #define RK3188_PULL_PMU_OFFSET 0x64
514 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank
*bank
,
515 int pin_num
, struct regmap
**regmap
,
518 struct rockchip_pinctrl
*info
= bank
->drvdata
;
520 /* The first 12 pins of the first bank are located elsewhere */
521 if (bank
->bank_num
== 0 && pin_num
< 12) {
522 *regmap
= info
->regmap_pmu
? info
->regmap_pmu
524 *reg
= info
->regmap_pmu
? RK3188_PULL_PMU_OFFSET
: 0;
525 *reg
+= ((pin_num
/ RK3188_PULL_PINS_PER_REG
) * 4);
526 *bit
= pin_num
% RK3188_PULL_PINS_PER_REG
;
527 *bit
*= RK3188_PULL_BITS_PER_PIN
;
529 *regmap
= info
->regmap_pull
? info
->regmap_pull
531 *reg
= info
->regmap_pull
? 0 : RK3188_PULL_OFFSET
;
533 /* correct the offset, as it is the 2nd pull register */
535 *reg
+= bank
->bank_num
* RK3188_PULL_BANK_STRIDE
;
536 *reg
+= ((pin_num
/ RK3188_PULL_PINS_PER_REG
) * 4);
539 * The bits in these registers have an inverse ordering
540 * with the lowest pin being in bits 15:14 and the highest
543 *bit
= 7 - (pin_num
% RK3188_PULL_PINS_PER_REG
);
544 *bit
*= RK3188_PULL_BITS_PER_PIN
;
548 #define RK3288_PULL_OFFSET 0x140
549 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank
*bank
,
550 int pin_num
, struct regmap
**regmap
,
553 struct rockchip_pinctrl
*info
= bank
->drvdata
;
555 /* The first 24 pins of the first bank are located in PMU */
556 if (bank
->bank_num
== 0) {
557 *regmap
= info
->regmap_pmu
;
558 *reg
= RK3188_PULL_PMU_OFFSET
;
560 *reg
+= ((pin_num
/ RK3188_PULL_PINS_PER_REG
) * 4);
561 *bit
= pin_num
% RK3188_PULL_PINS_PER_REG
;
562 *bit
*= RK3188_PULL_BITS_PER_PIN
;
564 *regmap
= info
->regmap_base
;
565 *reg
= RK3288_PULL_OFFSET
;
567 /* correct the offset, as we're starting with the 2nd bank */
569 *reg
+= bank
->bank_num
* RK3188_PULL_BANK_STRIDE
;
570 *reg
+= ((pin_num
/ RK3188_PULL_PINS_PER_REG
) * 4);
572 *bit
= (pin_num
% RK3188_PULL_PINS_PER_REG
);
573 *bit
*= RK3188_PULL_BITS_PER_PIN
;
577 #define RK3288_DRV_PMU_OFFSET 0x70
578 #define RK3288_DRV_GRF_OFFSET 0x1c0
579 #define RK3288_DRV_BITS_PER_PIN 2
580 #define RK3288_DRV_PINS_PER_REG 8
581 #define RK3288_DRV_BANK_STRIDE 16
582 static int rk3288_drv_list
[] = { 2, 4, 8, 12 };
584 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank
*bank
,
585 int pin_num
, struct regmap
**regmap
,
588 struct rockchip_pinctrl
*info
= bank
->drvdata
;
590 /* The first 24 pins of the first bank are located in PMU */
591 if (bank
->bank_num
== 0) {
592 *regmap
= info
->regmap_pmu
;
593 *reg
= RK3288_DRV_PMU_OFFSET
;
595 *reg
+= ((pin_num
/ RK3288_DRV_PINS_PER_REG
) * 4);
596 *bit
= pin_num
% RK3288_DRV_PINS_PER_REG
;
597 *bit
*= RK3288_DRV_BITS_PER_PIN
;
599 *regmap
= info
->regmap_base
;
600 *reg
= RK3288_DRV_GRF_OFFSET
;
602 /* correct the offset, as we're starting with the 2nd bank */
604 *reg
+= bank
->bank_num
* RK3288_DRV_BANK_STRIDE
;
605 *reg
+= ((pin_num
/ RK3288_DRV_PINS_PER_REG
) * 4);
607 *bit
= (pin_num
% RK3288_DRV_PINS_PER_REG
);
608 *bit
*= RK3288_DRV_BITS_PER_PIN
;
612 static int rk3288_get_drive(struct rockchip_pin_bank
*bank
, int pin_num
)
614 struct regmap
*regmap
;
619 rk3288_calc_drv_reg_and_bit(bank
, pin_num
, ®map
, ®
, &bit
);
621 ret
= regmap_read(regmap
, reg
, &data
);
626 data
&= (1 << RK3288_DRV_BITS_PER_PIN
) - 1;
628 return rk3288_drv_list
[data
];
631 static int rk3288_set_drive(struct rockchip_pin_bank
*bank
, int pin_num
,
634 struct rockchip_pinctrl
*info
= bank
->drvdata
;
635 struct regmap
*regmap
;
641 rk3288_calc_drv_reg_and_bit(bank
, pin_num
, ®map
, ®
, &bit
);
644 for (i
= 0; i
< ARRAY_SIZE(rk3288_drv_list
); i
++) {
645 if (rk3288_drv_list
[i
] == strength
) {
652 dev_err(info
->dev
, "unsupported driver strength %d\n",
657 spin_lock_irqsave(&bank
->slock
, flags
);
659 /* enable the write to the equivalent lower bits */
660 data
= ((1 << RK3288_DRV_BITS_PER_PIN
) - 1) << (bit
+ 16);
661 rmask
= data
| (data
>> 16);
662 data
|= (ret
<< bit
);
664 ret
= regmap_update_bits(regmap
, reg
, rmask
, data
);
665 spin_unlock_irqrestore(&bank
->slock
, flags
);
670 static int rockchip_get_pull(struct rockchip_pin_bank
*bank
, int pin_num
)
672 struct rockchip_pinctrl
*info
= bank
->drvdata
;
673 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
674 struct regmap
*regmap
;
679 /* rk3066b does support any pulls */
680 if (ctrl
->type
== RK3066B
)
681 return PIN_CONFIG_BIAS_DISABLE
;
683 ctrl
->pull_calc_reg(bank
, pin_num
, ®map
, ®
, &bit
);
685 ret
= regmap_read(regmap
, reg
, &data
);
689 switch (ctrl
->type
) {
691 return !(data
& BIT(bit
))
692 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
693 : PIN_CONFIG_BIAS_DISABLE
;
697 data
&= (1 << RK3188_PULL_BITS_PER_PIN
) - 1;
701 return PIN_CONFIG_BIAS_DISABLE
;
703 return PIN_CONFIG_BIAS_PULL_UP
;
705 return PIN_CONFIG_BIAS_PULL_DOWN
;
707 return PIN_CONFIG_BIAS_BUS_HOLD
;
710 dev_err(info
->dev
, "unknown pull setting\n");
713 dev_err(info
->dev
, "unsupported pinctrl type\n");
718 static int rockchip_set_pull(struct rockchip_pin_bank
*bank
,
719 int pin_num
, int pull
)
721 struct rockchip_pinctrl
*info
= bank
->drvdata
;
722 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
723 struct regmap
*regmap
;
729 dev_dbg(info
->dev
, "setting pull of GPIO%d-%d to %d\n",
730 bank
->bank_num
, pin_num
, pull
);
732 /* rk3066b does support any pulls */
733 if (ctrl
->type
== RK3066B
)
734 return pull
? -EINVAL
: 0;
736 ctrl
->pull_calc_reg(bank
, pin_num
, ®map
, ®
, &bit
);
738 switch (ctrl
->type
) {
740 spin_lock_irqsave(&bank
->slock
, flags
);
742 data
= BIT(bit
+ 16);
743 if (pull
== PIN_CONFIG_BIAS_DISABLE
)
745 ret
= regmap_write(regmap
, reg
, data
);
747 spin_unlock_irqrestore(&bank
->slock
, flags
);
751 spin_lock_irqsave(&bank
->slock
, flags
);
753 /* enable the write to the equivalent lower bits */
754 data
= ((1 << RK3188_PULL_BITS_PER_PIN
) - 1) << (bit
+ 16);
755 rmask
= data
| (data
>> 16);
758 case PIN_CONFIG_BIAS_DISABLE
:
760 case PIN_CONFIG_BIAS_PULL_UP
:
763 case PIN_CONFIG_BIAS_PULL_DOWN
:
766 case PIN_CONFIG_BIAS_BUS_HOLD
:
770 spin_unlock_irqrestore(&bank
->slock
, flags
);
771 dev_err(info
->dev
, "unsupported pull setting %d\n",
776 ret
= regmap_update_bits(regmap
, reg
, rmask
, data
);
778 spin_unlock_irqrestore(&bank
->slock
, flags
);
781 dev_err(info
->dev
, "unsupported pinctrl type\n");
789 * Pinmux_ops handling
792 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
794 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
796 return info
->nfunctions
;
799 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
802 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
804 return info
->functions
[selector
].name
;
807 static int rockchip_pmx_get_groups(struct pinctrl_dev
*pctldev
,
808 unsigned selector
, const char * const **groups
,
809 unsigned * const num_groups
)
811 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
813 *groups
= info
->functions
[selector
].groups
;
814 *num_groups
= info
->functions
[selector
].ngroups
;
819 static int rockchip_pmx_set(struct pinctrl_dev
*pctldev
, unsigned selector
,
822 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
823 const unsigned int *pins
= info
->groups
[group
].pins
;
824 const struct rockchip_pin_config
*data
= info
->groups
[group
].data
;
825 struct rockchip_pin_bank
*bank
;
828 dev_dbg(info
->dev
, "enable function %s group %s\n",
829 info
->functions
[selector
].name
, info
->groups
[group
].name
);
832 * for each pin in the pin group selected, program the correspoding pin
833 * pin function number in the config register.
835 for (cnt
= 0; cnt
< info
->groups
[group
].npins
; cnt
++) {
836 bank
= pin_to_bank(info
, pins
[cnt
]);
837 ret
= rockchip_set_mux(bank
, pins
[cnt
] - bank
->pin_base
,
844 /* revert the already done pin settings */
845 for (cnt
--; cnt
>= 0; cnt
--)
846 rockchip_set_mux(bank
, pins
[cnt
] - bank
->pin_base
, 0);
855 * The calls to gpio_direction_output() and gpio_direction_input()
856 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
857 * function called from the gpiolib interface).
859 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
860 struct pinctrl_gpio_range
*range
,
861 unsigned offset
, bool input
)
863 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
864 struct rockchip_pin_bank
*bank
;
865 struct gpio_chip
*chip
;
870 bank
= gc_to_pin_bank(chip
);
871 pin
= offset
- chip
->base
;
873 dev_dbg(info
->dev
, "gpio_direction for pin %u as %s-%d to %s\n",
874 offset
, range
->name
, pin
, input
? "input" : "output");
876 ret
= rockchip_set_mux(bank
, pin
, RK_FUNC_GPIO
);
880 data
= readl_relaxed(bank
->reg_base
+ GPIO_SWPORT_DDR
);
881 /* set bit to 1 for output, 0 for input */
886 writel_relaxed(data
, bank
->reg_base
+ GPIO_SWPORT_DDR
);
891 static const struct pinmux_ops rockchip_pmx_ops
= {
892 .get_functions_count
= rockchip_pmx_get_funcs_count
,
893 .get_function_name
= rockchip_pmx_get_func_name
,
894 .get_function_groups
= rockchip_pmx_get_groups
,
895 .set_mux
= rockchip_pmx_set
,
896 .gpio_set_direction
= rockchip_pmx_gpio_set_direction
,
900 * Pinconf_ops handling
903 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl
*ctrl
,
904 enum pin_config_param pull
)
906 switch (ctrl
->type
) {
908 return (pull
== PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
||
909 pull
== PIN_CONFIG_BIAS_DISABLE
);
911 return pull
? false : true;
914 return (pull
!= PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
);
920 static int rockchip_gpio_direction_output(struct gpio_chip
*gc
,
921 unsigned offset
, int value
);
922 static int rockchip_gpio_get(struct gpio_chip
*gc
, unsigned offset
);
924 /* set the pin config settings for a specified pin */
925 static int rockchip_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned int pin
,
926 unsigned long *configs
, unsigned num_configs
)
928 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
929 struct rockchip_pin_bank
*bank
= pin_to_bank(info
, pin
);
930 enum pin_config_param param
;
935 for (i
= 0; i
< num_configs
; i
++) {
936 param
= pinconf_to_config_param(configs
[i
]);
937 arg
= pinconf_to_config_argument(configs
[i
]);
940 case PIN_CONFIG_BIAS_DISABLE
:
941 rc
= rockchip_set_pull(bank
, pin
- bank
->pin_base
,
946 case PIN_CONFIG_BIAS_PULL_UP
:
947 case PIN_CONFIG_BIAS_PULL_DOWN
:
948 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
:
949 case PIN_CONFIG_BIAS_BUS_HOLD
:
950 if (!rockchip_pinconf_pull_valid(info
->ctrl
, param
))
956 rc
= rockchip_set_pull(bank
, pin
- bank
->pin_base
,
961 case PIN_CONFIG_OUTPUT
:
962 rc
= rockchip_gpio_direction_output(&bank
->gpio_chip
,
963 pin
- bank
->pin_base
,
968 case PIN_CONFIG_DRIVE_STRENGTH
:
969 /* rk3288 is the first with per-pin drive-strength */
970 if (info
->ctrl
->type
!= RK3288
)
973 rc
= rk3288_set_drive(bank
, pin
- bank
->pin_base
, arg
);
981 } /* for each config */
986 /* get the pin config settings for a specified pin */
987 static int rockchip_pinconf_get(struct pinctrl_dev
*pctldev
, unsigned int pin
,
988 unsigned long *config
)
990 struct rockchip_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
991 struct rockchip_pin_bank
*bank
= pin_to_bank(info
, pin
);
992 enum pin_config_param param
= pinconf_to_config_param(*config
);
997 case PIN_CONFIG_BIAS_DISABLE
:
998 if (rockchip_get_pull(bank
, pin
- bank
->pin_base
) != param
)
1003 case PIN_CONFIG_BIAS_PULL_UP
:
1004 case PIN_CONFIG_BIAS_PULL_DOWN
:
1005 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
:
1006 case PIN_CONFIG_BIAS_BUS_HOLD
:
1007 if (!rockchip_pinconf_pull_valid(info
->ctrl
, param
))
1010 if (rockchip_get_pull(bank
, pin
- bank
->pin_base
) != param
)
1015 case PIN_CONFIG_OUTPUT
:
1016 rc
= rockchip_get_mux(bank
, pin
- bank
->pin_base
);
1017 if (rc
!= RK_FUNC_GPIO
)
1020 rc
= rockchip_gpio_get(&bank
->gpio_chip
, pin
- bank
->pin_base
);
1026 case PIN_CONFIG_DRIVE_STRENGTH
:
1027 /* rk3288 is the first with per-pin drive-strength */
1028 if (info
->ctrl
->type
!= RK3288
)
1031 rc
= rk3288_get_drive(bank
, pin
- bank
->pin_base
);
1042 *config
= pinconf_to_config_packed(param
, arg
);
1047 static const struct pinconf_ops rockchip_pinconf_ops
= {
1048 .pin_config_get
= rockchip_pinconf_get
,
1049 .pin_config_set
= rockchip_pinconf_set
,
1053 static const struct of_device_id rockchip_bank_match
[] = {
1054 { .compatible
= "rockchip,gpio-bank" },
1055 { .compatible
= "rockchip,rk3188-gpio-bank0" },
1059 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl
*info
,
1060 struct device_node
*np
)
1062 struct device_node
*child
;
1064 for_each_child_of_node(np
, child
) {
1065 if (of_match_node(rockchip_bank_match
, child
))
1069 info
->ngroups
+= of_get_child_count(child
);
1073 static int rockchip_pinctrl_parse_groups(struct device_node
*np
,
1074 struct rockchip_pin_group
*grp
,
1075 struct rockchip_pinctrl
*info
,
1078 struct rockchip_pin_bank
*bank
;
1085 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
1087 /* Initialise group */
1088 grp
->name
= np
->name
;
1091 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1092 * do sanity check and calculate pins number
1094 list
= of_get_property(np
, "rockchip,pins", &size
);
1095 /* we do not check return since it's safe node passed down */
1096 size
/= sizeof(*list
);
1097 if (!size
|| size
% 4) {
1098 dev_err(info
->dev
, "wrong pins number or pins and configs should be by 4\n");
1102 grp
->npins
= size
/ 4;
1104 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
1106 grp
->data
= devm_kzalloc(info
->dev
, grp
->npins
*
1107 sizeof(struct rockchip_pin_config
),
1109 if (!grp
->pins
|| !grp
->data
)
1112 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
1113 const __be32
*phandle
;
1114 struct device_node
*np_config
;
1116 num
= be32_to_cpu(*list
++);
1117 bank
= bank_num_to_bank(info
, num
);
1119 return PTR_ERR(bank
);
1121 grp
->pins
[j
] = bank
->pin_base
+ be32_to_cpu(*list
++);
1122 grp
->data
[j
].func
= be32_to_cpu(*list
++);
1128 np_config
= of_find_node_by_phandle(be32_to_cpup(phandle
));
1129 ret
= pinconf_generic_parse_dt_config(np_config
,
1130 &grp
->data
[j
].configs
, &grp
->data
[j
].nconfigs
);
1138 static int rockchip_pinctrl_parse_functions(struct device_node
*np
,
1139 struct rockchip_pinctrl
*info
,
1142 struct device_node
*child
;
1143 struct rockchip_pmx_func
*func
;
1144 struct rockchip_pin_group
*grp
;
1146 static u32 grp_index
;
1149 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
1151 func
= &info
->functions
[index
];
1153 /* Initialise function */
1154 func
->name
= np
->name
;
1155 func
->ngroups
= of_get_child_count(np
);
1156 if (func
->ngroups
<= 0)
1159 func
->groups
= devm_kzalloc(info
->dev
,
1160 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
1164 for_each_child_of_node(np
, child
) {
1165 func
->groups
[i
] = child
->name
;
1166 grp
= &info
->groups
[grp_index
++];
1167 ret
= rockchip_pinctrl_parse_groups(child
, grp
, info
, i
++);
1175 static int rockchip_pinctrl_parse_dt(struct platform_device
*pdev
,
1176 struct rockchip_pinctrl
*info
)
1178 struct device
*dev
= &pdev
->dev
;
1179 struct device_node
*np
= dev
->of_node
;
1180 struct device_node
*child
;
1184 rockchip_pinctrl_child_count(info
, np
);
1186 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1187 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1189 info
->functions
= devm_kzalloc(dev
, info
->nfunctions
*
1190 sizeof(struct rockchip_pmx_func
),
1192 if (!info
->functions
) {
1193 dev_err(dev
, "failed to allocate memory for function list\n");
1197 info
->groups
= devm_kzalloc(dev
, info
->ngroups
*
1198 sizeof(struct rockchip_pin_group
),
1200 if (!info
->groups
) {
1201 dev_err(dev
, "failed allocate memory for ping group list\n");
1207 for_each_child_of_node(np
, child
) {
1208 if (of_match_node(rockchip_bank_match
, child
))
1211 ret
= rockchip_pinctrl_parse_functions(child
, info
, i
++);
1213 dev_err(&pdev
->dev
, "failed to parse function\n");
1221 static int rockchip_pinctrl_register(struct platform_device
*pdev
,
1222 struct rockchip_pinctrl
*info
)
1224 struct pinctrl_desc
*ctrldesc
= &info
->pctl
;
1225 struct pinctrl_pin_desc
*pindesc
, *pdesc
;
1226 struct rockchip_pin_bank
*pin_bank
;
1230 ctrldesc
->name
= "rockchip-pinctrl";
1231 ctrldesc
->owner
= THIS_MODULE
;
1232 ctrldesc
->pctlops
= &rockchip_pctrl_ops
;
1233 ctrldesc
->pmxops
= &rockchip_pmx_ops
;
1234 ctrldesc
->confops
= &rockchip_pinconf_ops
;
1236 pindesc
= devm_kzalloc(&pdev
->dev
, sizeof(*pindesc
) *
1237 info
->ctrl
->nr_pins
, GFP_KERNEL
);
1239 dev_err(&pdev
->dev
, "mem alloc for pin descriptors failed\n");
1242 ctrldesc
->pins
= pindesc
;
1243 ctrldesc
->npins
= info
->ctrl
->nr_pins
;
1246 for (bank
= 0 , k
= 0; bank
< info
->ctrl
->nr_banks
; bank
++) {
1247 pin_bank
= &info
->ctrl
->pin_banks
[bank
];
1248 for (pin
= 0; pin
< pin_bank
->nr_pins
; pin
++, k
++) {
1250 pdesc
->name
= kasprintf(GFP_KERNEL
, "%s-%d",
1251 pin_bank
->name
, pin
);
1256 info
->pctl_dev
= pinctrl_register(ctrldesc
, &pdev
->dev
, info
);
1257 if (!info
->pctl_dev
) {
1258 dev_err(&pdev
->dev
, "could not register pinctrl driver\n");
1262 for (bank
= 0; bank
< info
->ctrl
->nr_banks
; ++bank
) {
1263 pin_bank
= &info
->ctrl
->pin_banks
[bank
];
1264 pin_bank
->grange
.name
= pin_bank
->name
;
1265 pin_bank
->grange
.id
= bank
;
1266 pin_bank
->grange
.pin_base
= pin_bank
->pin_base
;
1267 pin_bank
->grange
.base
= pin_bank
->gpio_chip
.base
;
1268 pin_bank
->grange
.npins
= pin_bank
->gpio_chip
.ngpio
;
1269 pin_bank
->grange
.gc
= &pin_bank
->gpio_chip
;
1270 pinctrl_add_gpio_range(info
->pctl_dev
, &pin_bank
->grange
);
1273 ret
= rockchip_pinctrl_parse_dt(pdev
, info
);
1275 pinctrl_unregister(info
->pctl_dev
);
1286 static int rockchip_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1288 return pinctrl_request_gpio(chip
->base
+ offset
);
1291 static void rockchip_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1293 pinctrl_free_gpio(chip
->base
+ offset
);
1296 static void rockchip_gpio_set(struct gpio_chip
*gc
, unsigned offset
, int value
)
1298 struct rockchip_pin_bank
*bank
= gc_to_pin_bank(gc
);
1299 void __iomem
*reg
= bank
->reg_base
+ GPIO_SWPORT_DR
;
1300 unsigned long flags
;
1303 spin_lock_irqsave(&bank
->slock
, flags
);
1306 data
&= ~BIT(offset
);
1308 data
|= BIT(offset
);
1311 spin_unlock_irqrestore(&bank
->slock
, flags
);
1315 * Returns the level of the pin for input direction and setting of the DR
1316 * register for output gpios.
1318 static int rockchip_gpio_get(struct gpio_chip
*gc
, unsigned offset
)
1320 struct rockchip_pin_bank
*bank
= gc_to_pin_bank(gc
);
1323 data
= readl(bank
->reg_base
+ GPIO_EXT_PORT
);
1330 * gpiolib gpio_direction_input callback function. The setting of the pin
1331 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1334 static int rockchip_gpio_direction_input(struct gpio_chip
*gc
, unsigned offset
)
1336 return pinctrl_gpio_direction_input(gc
->base
+ offset
);
1340 * gpiolib gpio_direction_output callback function. The setting of the pin
1341 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1344 static int rockchip_gpio_direction_output(struct gpio_chip
*gc
,
1345 unsigned offset
, int value
)
1347 rockchip_gpio_set(gc
, offset
, value
);
1348 return pinctrl_gpio_direction_output(gc
->base
+ offset
);
1352 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1353 * and a virtual IRQ, if not already present.
1355 static int rockchip_gpio_to_irq(struct gpio_chip
*gc
, unsigned offset
)
1357 struct rockchip_pin_bank
*bank
= gc_to_pin_bank(gc
);
1363 virq
= irq_create_mapping(bank
->domain
, offset
);
1365 return (virq
) ? : -ENXIO
;
1368 static const struct gpio_chip rockchip_gpiolib_chip
= {
1369 .request
= rockchip_gpio_request
,
1370 .free
= rockchip_gpio_free
,
1371 .set
= rockchip_gpio_set
,
1372 .get
= rockchip_gpio_get
,
1373 .direction_input
= rockchip_gpio_direction_input
,
1374 .direction_output
= rockchip_gpio_direction_output
,
1375 .to_irq
= rockchip_gpio_to_irq
,
1376 .owner
= THIS_MODULE
,
1380 * Interrupt handling
1383 static void rockchip_irq_demux(unsigned int irq
, struct irq_desc
*desc
)
1385 struct irq_chip
*chip
= irq_get_chip(irq
);
1386 struct rockchip_pin_bank
*bank
= irq_get_handler_data(irq
);
1387 u32 polarity
= 0, data
= 0;
1389 bool edge_changed
= false;
1391 dev_dbg(bank
->drvdata
->dev
, "got irq for bank %s\n", bank
->name
);
1393 chained_irq_enter(chip
, desc
);
1395 pend
= readl_relaxed(bank
->reg_base
+ GPIO_INT_STATUS
);
1397 if (bank
->toggle_edge_mode
) {
1398 polarity
= readl_relaxed(bank
->reg_base
+
1400 data
= readl_relaxed(bank
->reg_base
+ GPIO_EXT_PORT
);
1408 virq
= irq_linear_revmap(bank
->domain
, irq
);
1411 dev_err(bank
->drvdata
->dev
, "unmapped irq %d\n", irq
);
1415 dev_dbg(bank
->drvdata
->dev
, "handling irq %d\n", irq
);
1418 * Triggering IRQ on both rising and falling edge
1419 * needs manual intervention.
1421 if (bank
->toggle_edge_mode
& BIT(irq
)) {
1422 if (data
& BIT(irq
))
1423 polarity
&= ~BIT(irq
);
1425 polarity
|= BIT(irq
);
1427 edge_changed
= true;
1430 generic_handle_irq(virq
);
1433 if (bank
->toggle_edge_mode
&& edge_changed
) {
1434 /* Interrupt params should only be set with ints disabled */
1435 data
= readl_relaxed(bank
->reg_base
+ GPIO_INTEN
);
1436 writel_relaxed(0, bank
->reg_base
+ GPIO_INTEN
);
1437 writel(polarity
, bank
->reg_base
+ GPIO_INT_POLARITY
);
1438 writel(data
, bank
->reg_base
+ GPIO_INTEN
);
1441 chained_irq_exit(chip
, desc
);
1444 static int rockchip_irq_set_type(struct irq_data
*d
, unsigned int type
)
1446 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
1447 struct rockchip_pin_bank
*bank
= gc
->private;
1448 u32 mask
= BIT(d
->hwirq
);
1454 /* make sure the pin is configured as gpio input */
1455 ret
= rockchip_set_mux(bank
, d
->hwirq
, RK_FUNC_GPIO
);
1459 data
= readl_relaxed(bank
->reg_base
+ GPIO_SWPORT_DDR
);
1461 writel_relaxed(data
, bank
->reg_base
+ GPIO_SWPORT_DDR
);
1463 if (type
& IRQ_TYPE_EDGE_BOTH
)
1464 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
1466 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
1470 level
= readl_relaxed(gc
->reg_base
+ GPIO_INTTYPE_LEVEL
);
1471 polarity
= readl_relaxed(gc
->reg_base
+ GPIO_INT_POLARITY
);
1474 case IRQ_TYPE_EDGE_BOTH
:
1475 bank
->toggle_edge_mode
|= mask
;
1479 * Determine gpio state. If 1 next interrupt should be falling
1482 data
= readl(bank
->reg_base
+ GPIO_EXT_PORT
);
1488 case IRQ_TYPE_EDGE_RISING
:
1489 bank
->toggle_edge_mode
&= ~mask
;
1493 case IRQ_TYPE_EDGE_FALLING
:
1494 bank
->toggle_edge_mode
&= ~mask
;
1498 case IRQ_TYPE_LEVEL_HIGH
:
1499 bank
->toggle_edge_mode
&= ~mask
;
1503 case IRQ_TYPE_LEVEL_LOW
:
1504 bank
->toggle_edge_mode
&= ~mask
;
1513 writel_relaxed(level
, gc
->reg_base
+ GPIO_INTTYPE_LEVEL
);
1514 writel_relaxed(polarity
, gc
->reg_base
+ GPIO_INT_POLARITY
);
1521 static int rockchip_interrupts_register(struct platform_device
*pdev
,
1522 struct rockchip_pinctrl
*info
)
1524 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
1525 struct rockchip_pin_bank
*bank
= ctrl
->pin_banks
;
1526 unsigned int clr
= IRQ_NOREQUEST
| IRQ_NOPROBE
| IRQ_NOAUTOEN
;
1527 struct irq_chip_generic
*gc
;
1531 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1533 dev_warn(&pdev
->dev
, "bank %s is not valid\n",
1538 bank
->domain
= irq_domain_add_linear(bank
->of_node
, 32,
1539 &irq_generic_chip_ops
, NULL
);
1540 if (!bank
->domain
) {
1541 dev_warn(&pdev
->dev
, "could not initialize irq domain for bank %s\n",
1546 ret
= irq_alloc_domain_generic_chips(bank
->domain
, 32, 1,
1547 "rockchip_gpio_irq", handle_level_irq
,
1548 clr
, 0, IRQ_GC_INIT_MASK_CACHE
);
1550 dev_err(&pdev
->dev
, "could not alloc generic chips for bank %s\n",
1552 irq_domain_remove(bank
->domain
);
1556 gc
= irq_get_domain_generic_chip(bank
->domain
, 0);
1557 gc
->reg_base
= bank
->reg_base
;
1559 gc
->chip_types
[0].regs
.mask
= GPIO_INTEN
;
1560 gc
->chip_types
[0].regs
.ack
= GPIO_PORTS_EOI
;
1561 gc
->chip_types
[0].chip
.irq_ack
= irq_gc_ack_set_bit
;
1562 gc
->chip_types
[0].chip
.irq_mask
= irq_gc_mask_clr_bit
;
1563 gc
->chip_types
[0].chip
.irq_unmask
= irq_gc_mask_set_bit
;
1564 gc
->chip_types
[0].chip
.irq_set_wake
= irq_gc_set_wake
;
1565 gc
->chip_types
[0].chip
.irq_set_type
= rockchip_irq_set_type
;
1567 irq_set_handler_data(bank
->irq
, bank
);
1568 irq_set_chained_handler(bank
->irq
, rockchip_irq_demux
);
1574 static int rockchip_gpiolib_register(struct platform_device
*pdev
,
1575 struct rockchip_pinctrl
*info
)
1577 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
1578 struct rockchip_pin_bank
*bank
= ctrl
->pin_banks
;
1579 struct gpio_chip
*gc
;
1583 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1585 dev_warn(&pdev
->dev
, "bank %s is not valid\n",
1590 bank
->gpio_chip
= rockchip_gpiolib_chip
;
1592 gc
= &bank
->gpio_chip
;
1593 gc
->base
= bank
->pin_base
;
1594 gc
->ngpio
= bank
->nr_pins
;
1595 gc
->dev
= &pdev
->dev
;
1596 gc
->of_node
= bank
->of_node
;
1597 gc
->label
= bank
->name
;
1599 ret
= gpiochip_add(gc
);
1601 dev_err(&pdev
->dev
, "failed to register gpio_chip %s, error code: %d\n",
1607 rockchip_interrupts_register(pdev
, info
);
1612 for (--i
, --bank
; i
>= 0; --i
, --bank
) {
1615 gpiochip_remove(&bank
->gpio_chip
);
1620 static int rockchip_gpiolib_unregister(struct platform_device
*pdev
,
1621 struct rockchip_pinctrl
*info
)
1623 struct rockchip_pin_ctrl
*ctrl
= info
->ctrl
;
1624 struct rockchip_pin_bank
*bank
= ctrl
->pin_banks
;
1627 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1630 gpiochip_remove(&bank
->gpio_chip
);
1636 static int rockchip_get_bank_data(struct rockchip_pin_bank
*bank
,
1637 struct rockchip_pinctrl
*info
)
1639 struct resource res
;
1642 if (of_address_to_resource(bank
->of_node
, 0, &res
)) {
1643 dev_err(info
->dev
, "cannot find IO resource for bank\n");
1647 bank
->reg_base
= devm_ioremap_resource(info
->dev
, &res
);
1648 if (IS_ERR(bank
->reg_base
))
1649 return PTR_ERR(bank
->reg_base
);
1652 * special case, where parts of the pull setting-registers are
1653 * part of the PMU register space
1655 if (of_device_is_compatible(bank
->of_node
,
1656 "rockchip,rk3188-gpio-bank0")) {
1657 struct device_node
*node
;
1659 node
= of_parse_phandle(bank
->of_node
->parent
,
1662 if (of_address_to_resource(bank
->of_node
, 1, &res
)) {
1663 dev_err(info
->dev
, "cannot find IO resource for bank\n");
1667 base
= devm_ioremap_resource(info
->dev
, &res
);
1669 return PTR_ERR(base
);
1670 rockchip_regmap_config
.max_register
=
1671 resource_size(&res
) - 4;
1672 rockchip_regmap_config
.name
=
1673 "rockchip,rk3188-gpio-bank0-pull";
1674 bank
->regmap_pull
= devm_regmap_init_mmio(info
->dev
,
1676 &rockchip_regmap_config
);
1680 bank
->irq
= irq_of_parse_and_map(bank
->of_node
, 0);
1682 bank
->clk
= of_clk_get(bank
->of_node
, 0);
1683 if (IS_ERR(bank
->clk
))
1684 return PTR_ERR(bank
->clk
);
1686 return clk_prepare_enable(bank
->clk
);
1689 static const struct of_device_id rockchip_pinctrl_dt_match
[];
1691 /* retrieve the soc specific data */
1692 static struct rockchip_pin_ctrl
*rockchip_pinctrl_get_soc_data(
1693 struct rockchip_pinctrl
*d
,
1694 struct platform_device
*pdev
)
1696 const struct of_device_id
*match
;
1697 struct device_node
*node
= pdev
->dev
.of_node
;
1698 struct device_node
*np
;
1699 struct rockchip_pin_ctrl
*ctrl
;
1700 struct rockchip_pin_bank
*bank
;
1701 int grf_offs
, pmu_offs
, i
, j
;
1703 match
= of_match_node(rockchip_pinctrl_dt_match
, node
);
1704 ctrl
= (struct rockchip_pin_ctrl
*)match
->data
;
1706 for_each_child_of_node(node
, np
) {
1707 if (!of_find_property(np
, "gpio-controller", NULL
))
1710 bank
= ctrl
->pin_banks
;
1711 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1712 if (!strcmp(bank
->name
, np
->name
)) {
1715 if (!rockchip_get_bank_data(bank
, d
))
1723 grf_offs
= ctrl
->grf_mux_offset
;
1724 pmu_offs
= ctrl
->pmu_mux_offset
;
1725 bank
= ctrl
->pin_banks
;
1726 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
) {
1729 spin_lock_init(&bank
->slock
);
1731 bank
->pin_base
= ctrl
->nr_pins
;
1732 ctrl
->nr_pins
+= bank
->nr_pins
;
1734 /* calculate iomux offsets */
1735 for (j
= 0; j
< 4; j
++) {
1736 struct rockchip_iomux
*iom
= &bank
->iomux
[j
];
1739 if (bank_pins
>= bank
->nr_pins
)
1742 /* preset offset value, set new start value */
1743 if (iom
->offset
>= 0) {
1744 if (iom
->type
& IOMUX_SOURCE_PMU
)
1745 pmu_offs
= iom
->offset
;
1747 grf_offs
= iom
->offset
;
1748 } else { /* set current offset */
1749 iom
->offset
= (iom
->type
& IOMUX_SOURCE_PMU
) ?
1750 pmu_offs
: grf_offs
;
1753 dev_dbg(d
->dev
, "bank %d, iomux %d has offset 0x%x\n",
1757 * Increase offset according to iomux width.
1758 * 4bit iomux'es are spread over two registers.
1760 inc
= (iom
->type
& IOMUX_WIDTH_4BIT
) ? 8 : 4;
1761 if (iom
->type
& IOMUX_SOURCE_PMU
)
1773 static int rockchip_pinctrl_probe(struct platform_device
*pdev
)
1775 struct rockchip_pinctrl
*info
;
1776 struct device
*dev
= &pdev
->dev
;
1777 struct rockchip_pin_ctrl
*ctrl
;
1778 struct device_node
*np
= pdev
->dev
.of_node
, *node
;
1779 struct resource
*res
;
1783 if (!dev
->of_node
) {
1784 dev_err(dev
, "device tree node not found\n");
1788 info
= devm_kzalloc(dev
, sizeof(struct rockchip_pinctrl
), GFP_KERNEL
);
1794 ctrl
= rockchip_pinctrl_get_soc_data(info
, pdev
);
1796 dev_err(dev
, "driver data not available\n");
1801 node
= of_parse_phandle(np
, "rockchip,grf", 0);
1803 info
->regmap_base
= syscon_node_to_regmap(node
);
1804 if (IS_ERR(info
->regmap_base
))
1805 return PTR_ERR(info
->regmap_base
);
1807 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1808 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1810 return PTR_ERR(base
);
1812 rockchip_regmap_config
.max_register
= resource_size(res
) - 4;
1813 rockchip_regmap_config
.name
= "rockchip,pinctrl";
1814 info
->regmap_base
= devm_regmap_init_mmio(&pdev
->dev
, base
,
1815 &rockchip_regmap_config
);
1817 /* to check for the old dt-bindings */
1818 info
->reg_size
= resource_size(res
);
1820 /* Honor the old binding, with pull registers as 2nd resource */
1821 if (ctrl
->type
== RK3188
&& info
->reg_size
< 0x200) {
1822 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1823 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1825 return PTR_ERR(base
);
1827 rockchip_regmap_config
.max_register
=
1828 resource_size(res
) - 4;
1829 rockchip_regmap_config
.name
= "rockchip,pinctrl-pull";
1830 info
->regmap_pull
= devm_regmap_init_mmio(&pdev
->dev
,
1832 &rockchip_regmap_config
);
1836 /* try to find the optional reference to the pmu syscon */
1837 node
= of_parse_phandle(np
, "rockchip,pmu", 0);
1839 info
->regmap_pmu
= syscon_node_to_regmap(node
);
1840 if (IS_ERR(info
->regmap_pmu
))
1841 return PTR_ERR(info
->regmap_pmu
);
1844 ret
= rockchip_gpiolib_register(pdev
, info
);
1848 ret
= rockchip_pinctrl_register(pdev
, info
);
1850 rockchip_gpiolib_unregister(pdev
, info
);
1854 platform_set_drvdata(pdev
, info
);
1859 static struct rockchip_pin_bank rk2928_pin_banks
[] = {
1860 PIN_BANK(0, 32, "gpio0"),
1861 PIN_BANK(1, 32, "gpio1"),
1862 PIN_BANK(2, 32, "gpio2"),
1863 PIN_BANK(3, 32, "gpio3"),
1866 static struct rockchip_pin_ctrl rk2928_pin_ctrl
= {
1867 .pin_banks
= rk2928_pin_banks
,
1868 .nr_banks
= ARRAY_SIZE(rk2928_pin_banks
),
1869 .label
= "RK2928-GPIO",
1871 .grf_mux_offset
= 0xa8,
1872 .pull_calc_reg
= rk2928_calc_pull_reg_and_bit
,
1875 static struct rockchip_pin_bank rk3066a_pin_banks
[] = {
1876 PIN_BANK(0, 32, "gpio0"),
1877 PIN_BANK(1, 32, "gpio1"),
1878 PIN_BANK(2, 32, "gpio2"),
1879 PIN_BANK(3, 32, "gpio3"),
1880 PIN_BANK(4, 32, "gpio4"),
1881 PIN_BANK(6, 16, "gpio6"),
1884 static struct rockchip_pin_ctrl rk3066a_pin_ctrl
= {
1885 .pin_banks
= rk3066a_pin_banks
,
1886 .nr_banks
= ARRAY_SIZE(rk3066a_pin_banks
),
1887 .label
= "RK3066a-GPIO",
1889 .grf_mux_offset
= 0xa8,
1890 .pull_calc_reg
= rk2928_calc_pull_reg_and_bit
,
1893 static struct rockchip_pin_bank rk3066b_pin_banks
[] = {
1894 PIN_BANK(0, 32, "gpio0"),
1895 PIN_BANK(1, 32, "gpio1"),
1896 PIN_BANK(2, 32, "gpio2"),
1897 PIN_BANK(3, 32, "gpio3"),
1900 static struct rockchip_pin_ctrl rk3066b_pin_ctrl
= {
1901 .pin_banks
= rk3066b_pin_banks
,
1902 .nr_banks
= ARRAY_SIZE(rk3066b_pin_banks
),
1903 .label
= "RK3066b-GPIO",
1905 .grf_mux_offset
= 0x60,
1908 static struct rockchip_pin_bank rk3188_pin_banks
[] = {
1909 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY
, 0, 0, 0),
1910 PIN_BANK(1, 32, "gpio1"),
1911 PIN_BANK(2, 32, "gpio2"),
1912 PIN_BANK(3, 32, "gpio3"),
1915 static struct rockchip_pin_ctrl rk3188_pin_ctrl
= {
1916 .pin_banks
= rk3188_pin_banks
,
1917 .nr_banks
= ARRAY_SIZE(rk3188_pin_banks
),
1918 .label
= "RK3188-GPIO",
1920 .grf_mux_offset
= 0x60,
1921 .pull_calc_reg
= rk3188_calc_pull_reg_and_bit
,
1924 static struct rockchip_pin_bank rk3288_pin_banks
[] = {
1925 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU
,
1930 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED
,
1935 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED
),
1936 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT
),
1937 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT
,
1942 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED
,
1947 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED
),
1948 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
1953 PIN_BANK(8, 16, "gpio8"),
1956 static struct rockchip_pin_ctrl rk3288_pin_ctrl
= {
1957 .pin_banks
= rk3288_pin_banks
,
1958 .nr_banks
= ARRAY_SIZE(rk3288_pin_banks
),
1959 .label
= "RK3288-GPIO",
1961 .grf_mux_offset
= 0x0,
1962 .pmu_mux_offset
= 0x84,
1963 .pull_calc_reg
= rk3288_calc_pull_reg_and_bit
,
1966 static const struct of_device_id rockchip_pinctrl_dt_match
[] = {
1967 { .compatible
= "rockchip,rk2928-pinctrl",
1968 .data
= (void *)&rk2928_pin_ctrl
},
1969 { .compatible
= "rockchip,rk3066a-pinctrl",
1970 .data
= (void *)&rk3066a_pin_ctrl
},
1971 { .compatible
= "rockchip,rk3066b-pinctrl",
1972 .data
= (void *)&rk3066b_pin_ctrl
},
1973 { .compatible
= "rockchip,rk3188-pinctrl",
1974 .data
= (void *)&rk3188_pin_ctrl
},
1975 { .compatible
= "rockchip,rk3288-pinctrl",
1976 .data
= (void *)&rk3288_pin_ctrl
},
1979 MODULE_DEVICE_TABLE(of
, rockchip_pinctrl_dt_match
);
1981 static struct platform_driver rockchip_pinctrl_driver
= {
1982 .probe
= rockchip_pinctrl_probe
,
1984 .name
= "rockchip-pinctrl",
1985 .owner
= THIS_MODULE
,
1986 .of_match_table
= rockchip_pinctrl_dt_match
,
1990 static int __init
rockchip_pinctrl_drv_register(void)
1992 return platform_driver_register(&rockchip_pinctrl_driver
);
1994 postcore_initcall(rockchip_pinctrl_drv_register
);
1996 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1997 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1998 MODULE_LICENSE("GPL v2");