projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'mac80211-for-davem-2015-01-15' of git://git.kernel.org/pub/scm/linux/kerne...
[deliverable/linux.git] / drivers / pinctrl / pinctrl-rockchip.c
1 /*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
43
44 #include "core.h"
45 #include "pinconf.h"
46
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
60
61 enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
65 RK3288,
66 };
67
68 /**
69 * Encode variants of iomux registers into a type variable
70 */
71 #define IOMUX_GPIO_ONLY BIT(0)
72 #define IOMUX_WIDTH_4BIT BIT(1)
73 #define IOMUX_SOURCE_PMU BIT(2)
74 #define IOMUX_UNROUTED BIT(3)
75
76 /**
77 * @type: iomux variant using IOMUX_* constants
78 * @offset: if initialized to -1 it will be autocalculated, by specifying
79 * an initial offset value the relevant source offset can be reset
80 * to a new value for autocalculating the following iomux registers.
81 */
82 struct rockchip_iomux {
83 int type;
84 int offset;
85 };
86
87 /**
88 * @reg_base: register base of the gpio bank
89 * @reg_pull: optional separate register for additional pull settings
90 * @clk: clock of the gpio bank
91 * @irq: interrupt of the gpio bank
92 * @saved_enables: Saved content of GPIO_INTEN at suspend time.
93 * @pin_base: first pin number
94 * @nr_pins: number of pins in this bank
95 * @name: name of the bank
96 * @bank_num: number of the bank, to account for holes
97 * @iomux: array describing the 4 iomux sources of the bank
98 * @valid: are all necessary informations present
99 * @of_node: dt node of this bank
100 * @drvdata: common pinctrl basedata
101 * @domain: irqdomain of the gpio bank
102 * @gpio_chip: gpiolib chip
103 * @grange: gpio range
104 * @slock: spinlock for the gpio bank
105 */
106 struct rockchip_pin_bank {
107 void __iomem *reg_base;
108 struct regmap *regmap_pull;
109 struct clk *clk;
110 int irq;
111 u32 saved_enables;
112 u32 pin_base;
113 u8 nr_pins;
114 char *name;
115 u8 bank_num;
116 struct rockchip_iomux iomux[4];
117 bool valid;
118 struct device_node *of_node;
119 struct rockchip_pinctrl *drvdata;
120 struct irq_domain *domain;
121 struct gpio_chip gpio_chip;
122 struct pinctrl_gpio_range grange;
123 spinlock_t slock;
124 u32 toggle_edge_mode;
125 };
126
127 #define PIN_BANK(id, pins, label) \
128 { \
129 .bank_num = id, \
130 .nr_pins = pins, \
131 .name = label, \
132 .iomux = { \
133 { .offset = -1 }, \
134 { .offset = -1 }, \
135 { .offset = -1 }, \
136 { .offset = -1 }, \
137 }, \
138 }
139
140 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
141 { \
142 .bank_num = id, \
143 .nr_pins = pins, \
144 .name = label, \
145 .iomux = { \
146 { .type = iom0, .offset = -1 }, \
147 { .type = iom1, .offset = -1 }, \
148 { .type = iom2, .offset = -1 }, \
149 { .type = iom3, .offset = -1 }, \
150 }, \
151 }
152
153 /**
154 */
155 struct rockchip_pin_ctrl {
156 struct rockchip_pin_bank *pin_banks;
157 u32 nr_banks;
158 u32 nr_pins;
159 char *label;
160 enum rockchip_pinctrl_type type;
161 int grf_mux_offset;
162 int pmu_mux_offset;
163 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
164 int pin_num, struct regmap **regmap,
165 int *reg, u8 *bit);
166 };
167
168 struct rockchip_pin_config {
169 unsigned int func;
170 unsigned long *configs;
171 unsigned int nconfigs;
172 };
173
174 /**
175 * struct rockchip_pin_group: represent group of pins of a pinmux function.
176 * @name: name of the pin group, used to lookup the group.
177 * @pins: the pins included in this group.
178 * @npins: number of pins included in this group.
179 * @func: the mux function number to be programmed when selected.
180 * @configs: the config values to be set for each pin
181 * @nconfigs: number of configs for each pin
182 */
183 struct rockchip_pin_group {
184 const char *name;
185 unsigned int npins;
186 unsigned int *pins;
187 struct rockchip_pin_config *data;
188 };
189
190 /**
191 * struct rockchip_pmx_func: represent a pin function.
192 * @name: name of the pin function, used to lookup the function.
193 * @groups: one or more names of pin groups that provide this function.
194 * @num_groups: number of groups included in @groups.
195 */
196 struct rockchip_pmx_func {
197 const char *name;
198 const char **groups;
199 u8 ngroups;
200 };
201
202 struct rockchip_pinctrl {
203 struct regmap *regmap_base;
204 int reg_size;
205 struct regmap *regmap_pull;
206 struct regmap *regmap_pmu;
207 struct device *dev;
208 struct rockchip_pin_ctrl *ctrl;
209 struct pinctrl_desc pctl;
210 struct pinctrl_dev *pctl_dev;
211 struct rockchip_pin_group *groups;
212 unsigned int ngroups;
213 struct rockchip_pmx_func *functions;
214 unsigned int nfunctions;
215 };
216
217 static struct regmap_config rockchip_regmap_config = {
218 .reg_bits = 32,
219 .val_bits = 32,
220 .reg_stride = 4,
221 };
222
223 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
224 {
225 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
226 }
227
228 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
229 const struct rockchip_pinctrl *info,
230 const char *name)
231 {
232 int i;
233
234 for (i = 0; i < info->ngroups; i++) {
235 if (!strcmp(info->groups[i].name, name))
236 return &info->groups[i];
237 }
238
239 return NULL;
240 }
241
242 /*
243 * given a pin number that is local to a pin controller, find out the pin bank
244 * and the register base of the pin bank.
245 */
246 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
247 unsigned pin)
248 {
249 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
250
251 while (pin >= (b->pin_base + b->nr_pins))
252 b++;
253
254 return b;
255 }
256
257 static struct rockchip_pin_bank *bank_num_to_bank(
258 struct rockchip_pinctrl *info,
259 unsigned num)
260 {
261 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
262 int i;
263
264 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
265 if (b->bank_num == num)
266 return b;
267 }
268
269 return ERR_PTR(-EINVAL);
270 }
271
272 /*
273 * Pinctrl_ops handling
274 */
275
276 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
277 {
278 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
279
280 return info->ngroups;
281 }
282
283 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
284 unsigned selector)
285 {
286 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
287
288 return info->groups[selector].name;
289 }
290
291 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
292 unsigned selector, const unsigned **pins,
293 unsigned *npins)
294 {
295 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
296
297 if (selector >= info->ngroups)
298 return -EINVAL;
299
300 *pins = info->groups[selector].pins;
301 *npins = info->groups[selector].npins;
302
303 return 0;
304 }
305
306 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
307 struct device_node *np,
308 struct pinctrl_map **map, unsigned *num_maps)
309 {
310 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
311 const struct rockchip_pin_group *grp;
312 struct pinctrl_map *new_map;
313 struct device_node *parent;
314 int map_num = 1;
315 int i;
316
317 /*
318 * first find the group of this node and check if we need to create
319 * config maps for pins
320 */
321 grp = pinctrl_name_to_group(info, np->name);
322 if (!grp) {
323 dev_err(info->dev, "unable to find group for node %s\n",
324 np->name);
325 return -EINVAL;
326 }
327
328 map_num += grp->npins;
329 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
330 GFP_KERNEL);
331 if (!new_map)
332 return -ENOMEM;
333
334 *map = new_map;
335 *num_maps = map_num;
336
337 /* create mux map */
338 parent = of_get_parent(np);
339 if (!parent) {
340 devm_kfree(pctldev->dev, new_map);
341 return -EINVAL;
342 }
343 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
344 new_map[0].data.mux.function = parent->name;
345 new_map[0].data.mux.group = np->name;
346 of_node_put(parent);
347
348 /* create config map */
349 new_map++;
350 for (i = 0; i < grp->npins; i++) {
351 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
352 new_map[i].data.configs.group_or_pin =
353 pin_get_name(pctldev, grp->pins[i]);
354 new_map[i].data.configs.configs = grp->data[i].configs;
355 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
356 }
357
358 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
359 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
360
361 return 0;
362 }
363
364 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
365 struct pinctrl_map *map, unsigned num_maps)
366 {
367 }
368
369 static const struct pinctrl_ops rockchip_pctrl_ops = {
370 .get_groups_count = rockchip_get_groups_count,
371 .get_group_name = rockchip_get_group_name,
372 .get_group_pins = rockchip_get_group_pins,
373 .dt_node_to_map = rockchip_dt_node_to_map,
374 .dt_free_map = rockchip_dt_free_map,
375 };
376
377 /*
378 * Hardware access
379 */
380
381 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
382 {
383 struct rockchip_pinctrl *info = bank->drvdata;
384 int iomux_num = (pin / 8);
385 struct regmap *regmap;
386 unsigned int val;
387 int reg, ret, mask;
388 u8 bit;
389
390 if (iomux_num > 3)
391 return -EINVAL;
392
393 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
394 dev_err(info->dev, "pin %d is unrouted\n", pin);
395 return -EINVAL;
396 }
397
398 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
399 return RK_FUNC_GPIO;
400
401 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
402 ? info->regmap_pmu : info->regmap_base;
403
404 /* get basic quadrupel of mux registers and the correct reg inside */
405 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
406 reg = bank->iomux[iomux_num].offset;
407 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
408 if ((pin % 8) >= 4)
409 reg += 0x4;
410 bit = (pin % 4) * 4;
411 } else {
412 bit = (pin % 8) * 2;
413 }
414
415 ret = regmap_read(regmap, reg, &val);
416 if (ret)
417 return ret;
418
419 return ((val >> bit) & mask);
420 }
421
422 /*
423 * Set a new mux function for a pin.
424 *
425 * The register is divided into the upper and lower 16 bit. When changing
426 * a value, the previous register value is not read and changed. Instead
427 * it seems the changed bits are marked in the upper 16 bit, while the
428 * changed value gets set in the same offset in the lower 16 bit.
429 * All pin settings seem to be 2 bit wide in both the upper and lower
430 * parts.
431 * @bank: pin bank to change
432 * @pin: pin to change
433 * @mux: new mux function to set
434 */
435 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
436 {
437 struct rockchip_pinctrl *info = bank->drvdata;
438 int iomux_num = (pin / 8);
439 struct regmap *regmap;
440 int reg, ret, mask;
441 unsigned long flags;
442 u8 bit;
443 u32 data, rmask;
444
445 if (iomux_num > 3)
446 return -EINVAL;
447
448 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
449 dev_err(info->dev, "pin %d is unrouted\n", pin);
450 return -EINVAL;
451 }
452
453 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
454 if (mux != RK_FUNC_GPIO) {
455 dev_err(info->dev,
456 "pin %d only supports a gpio mux\n", pin);
457 return -ENOTSUPP;
458 } else {
459 return 0;
460 }
461 }
462
463 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
464 bank->bank_num, pin, mux);
465
466 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
467 ? info->regmap_pmu : info->regmap_base;
468
469 /* get basic quadrupel of mux registers and the correct reg inside */
470 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
471 reg = bank->iomux[iomux_num].offset;
472 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
473 if ((pin % 8) >= 4)
474 reg += 0x4;
475 bit = (pin % 4) * 4;
476 } else {
477 bit = (pin % 8) * 2;
478 }
479
480 spin_lock_irqsave(&bank->slock, flags);
481
482 data = (mask << (bit + 16));
483 rmask = data | (data >> 16);
484 data |= (mux & mask) << bit;
485 ret = regmap_update_bits(regmap, reg, rmask, data);
486
487 spin_unlock_irqrestore(&bank->slock, flags);
488
489 return ret;
490 }
491
492 #define RK2928_PULL_OFFSET 0x118
493 #define RK2928_PULL_PINS_PER_REG 16
494 #define RK2928_PULL_BANK_STRIDE 8
495
496 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
497 int pin_num, struct regmap **regmap,
498 int *reg, u8 *bit)
499 {
500 struct rockchip_pinctrl *info = bank->drvdata;
501
502 *regmap = info->regmap_base;
503 *reg = RK2928_PULL_OFFSET;
504 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
505 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
506
507 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
508 };
509
510 #define RK3188_PULL_OFFSET 0x164
511 #define RK3188_PULL_BITS_PER_PIN 2
512 #define RK3188_PULL_PINS_PER_REG 8
513 #define RK3188_PULL_BANK_STRIDE 16
514 #define RK3188_PULL_PMU_OFFSET 0x64
515
516 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
517 int pin_num, struct regmap **regmap,
518 int *reg, u8 *bit)
519 {
520 struct rockchip_pinctrl *info = bank->drvdata;
521
522 /* The first 12 pins of the first bank are located elsewhere */
523 if (bank->bank_num == 0 && pin_num < 12) {
524 *regmap = info->regmap_pmu ? info->regmap_pmu
525 : bank->regmap_pull;
526 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
527 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
528 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
529 *bit *= RK3188_PULL_BITS_PER_PIN;
530 } else {
531 *regmap = info->regmap_pull ? info->regmap_pull
532 : info->regmap_base;
533 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
534
535 /* correct the offset, as it is the 2nd pull register */
536 *reg -= 4;
537 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
538 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
539
540 /*
541 * The bits in these registers have an inverse ordering
542 * with the lowest pin being in bits 15:14 and the highest
543 * pin in bits 1:0
544 */
545 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
546 *bit *= RK3188_PULL_BITS_PER_PIN;
547 }
548 }
549
550 #define RK3288_PULL_OFFSET 0x140
551 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
552 int pin_num, struct regmap **regmap,
553 int *reg, u8 *bit)
554 {
555 struct rockchip_pinctrl *info = bank->drvdata;
556
557 /* The first 24 pins of the first bank are located in PMU */
558 if (bank->bank_num == 0) {
559 *regmap = info->regmap_pmu;
560 *reg = RK3188_PULL_PMU_OFFSET;
561
562 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
563 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
564 *bit *= RK3188_PULL_BITS_PER_PIN;
565 } else {
566 *regmap = info->regmap_base;
567 *reg = RK3288_PULL_OFFSET;
568
569 /* correct the offset, as we're starting with the 2nd bank */
570 *reg -= 0x10;
571 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
572 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
573
574 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
575 *bit *= RK3188_PULL_BITS_PER_PIN;
576 }
577 }
578
579 #define RK3288_DRV_PMU_OFFSET 0x70
580 #define RK3288_DRV_GRF_OFFSET 0x1c0
581 #define RK3288_DRV_BITS_PER_PIN 2
582 #define RK3288_DRV_PINS_PER_REG 8
583 #define RK3288_DRV_BANK_STRIDE 16
584 static int rk3288_drv_list[] = { 2, 4, 8, 12 };
585
586 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
587 int pin_num, struct regmap **regmap,
588 int *reg, u8 *bit)
589 {
590 struct rockchip_pinctrl *info = bank->drvdata;
591
592 /* The first 24 pins of the first bank are located in PMU */
593 if (bank->bank_num == 0) {
594 *regmap = info->regmap_pmu;
595 *reg = RK3288_DRV_PMU_OFFSET;
596
597 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
598 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
599 *bit *= RK3288_DRV_BITS_PER_PIN;
600 } else {
601 *regmap = info->regmap_base;
602 *reg = RK3288_DRV_GRF_OFFSET;
603
604 /* correct the offset, as we're starting with the 2nd bank */
605 *reg -= 0x10;
606 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
607 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
608
609 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
610 *bit *= RK3288_DRV_BITS_PER_PIN;
611 }
612 }
613
614 static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
615 {
616 struct regmap *regmap;
617 int reg, ret;
618 u32 data;
619 u8 bit;
620
621 rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
622
623 ret = regmap_read(regmap, reg, &data);
624 if (ret)
625 return ret;
626
627 data >>= bit;
628 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
629
630 return rk3288_drv_list[data];
631 }
632
633 static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
634 int strength)
635 {
636 struct rockchip_pinctrl *info = bank->drvdata;
637 struct regmap *regmap;
638 unsigned long flags;
639 int reg, ret, i;
640 u32 data, rmask;
641 u8 bit;
642
643 rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
644
645 ret = -EINVAL;
646 for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
647 if (rk3288_drv_list[i] == strength) {
648 ret = i;
649 break;
650 }
651 }
652
653 if (ret < 0) {
654 dev_err(info->dev, "unsupported driver strength %d\n",
655 strength);
656 return ret;
657 }
658
659 spin_lock_irqsave(&bank->slock, flags);
660
661 /* enable the write to the equivalent lower bits */
662 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
663 rmask = data | (data >> 16);
664 data |= (ret << bit);
665
666 ret = regmap_update_bits(regmap, reg, rmask, data);
667 spin_unlock_irqrestore(&bank->slock, flags);
668
669 return ret;
670 }
671
672 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
673 {
674 struct rockchip_pinctrl *info = bank->drvdata;
675 struct rockchip_pin_ctrl *ctrl = info->ctrl;
676 struct regmap *regmap;
677 int reg, ret;
678 u8 bit;
679 u32 data;
680
681 /* rk3066b does support any pulls */
682 if (ctrl->type == RK3066B)
683 return PIN_CONFIG_BIAS_DISABLE;
684
685 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
686
687 ret = regmap_read(regmap, reg, &data);
688 if (ret)
689 return ret;
690
691 switch (ctrl->type) {
692 case RK2928:
693 return !(data & BIT(bit))
694 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
695 : PIN_CONFIG_BIAS_DISABLE;
696 case RK3188:
697 case RK3288:
698 data >>= bit;
699 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
700
701 switch (data) {
702 case 0:
703 return PIN_CONFIG_BIAS_DISABLE;
704 case 1:
705 return PIN_CONFIG_BIAS_PULL_UP;
706 case 2:
707 return PIN_CONFIG_BIAS_PULL_DOWN;
708 case 3:
709 return PIN_CONFIG_BIAS_BUS_HOLD;
710 }
711
712 dev_err(info->dev, "unknown pull setting\n");
713 return -EIO;
714 default:
715 dev_err(info->dev, "unsupported pinctrl type\n");
716 return -EINVAL;
717 };
718 }
719
720 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
721 int pin_num, int pull)
722 {
723 struct rockchip_pinctrl *info = bank->drvdata;
724 struct rockchip_pin_ctrl *ctrl = info->ctrl;
725 struct regmap *regmap;
726 int reg, ret;
727 unsigned long flags;
728 u8 bit;
729 u32 data, rmask;
730
731 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
732 bank->bank_num, pin_num, pull);
733
734 /* rk3066b does support any pulls */
735 if (ctrl->type == RK3066B)
736 return pull ? -EINVAL : 0;
737
738 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
739
740 switch (ctrl->type) {
741 case RK2928:
742 spin_lock_irqsave(&bank->slock, flags);
743
744 data = BIT(bit + 16);
745 if (pull == PIN_CONFIG_BIAS_DISABLE)
746 data |= BIT(bit);
747 ret = regmap_write(regmap, reg, data);
748
749 spin_unlock_irqrestore(&bank->slock, flags);
750 break;
751 case RK3188:
752 case RK3288:
753 spin_lock_irqsave(&bank->slock, flags);
754
755 /* enable the write to the equivalent lower bits */
756 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
757 rmask = data | (data >> 16);
758
759 switch (pull) {
760 case PIN_CONFIG_BIAS_DISABLE:
761 break;
762 case PIN_CONFIG_BIAS_PULL_UP:
763 data |= (1 << bit);
764 break;
765 case PIN_CONFIG_BIAS_PULL_DOWN:
766 data |= (2 << bit);
767 break;
768 case PIN_CONFIG_BIAS_BUS_HOLD:
769 data |= (3 << bit);
770 break;
771 default:
772 spin_unlock_irqrestore(&bank->slock, flags);
773 dev_err(info->dev, "unsupported pull setting %d\n",
774 pull);
775 return -EINVAL;
776 }
777
778 ret = regmap_update_bits(regmap, reg, rmask, data);
779
780 spin_unlock_irqrestore(&bank->slock, flags);
781 break;
782 default:
783 dev_err(info->dev, "unsupported pinctrl type\n");
784 return -EINVAL;
785 }
786
787 return ret;
788 }
789
790 /*
791 * Pinmux_ops handling
792 */
793
794 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
795 {
796 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
797
798 return info->nfunctions;
799 }
800
801 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
802 unsigned selector)
803 {
804 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
805
806 return info->functions[selector].name;
807 }
808
809 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
810 unsigned selector, const char * const **groups,
811 unsigned * const num_groups)
812 {
813 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
814
815 *groups = info->functions[selector].groups;
816 *num_groups = info->functions[selector].ngroups;
817
818 return 0;
819 }
820
821 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
822 unsigned group)
823 {
824 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
825 const unsigned int *pins = info->groups[group].pins;
826 const struct rockchip_pin_config *data = info->groups[group].data;
827 struct rockchip_pin_bank *bank;
828 int cnt, ret = 0;
829
830 dev_dbg(info->dev, "enable function %s group %s\n",
831 info->functions[selector].name, info->groups[group].name);
832
833 /*
834 * for each pin in the pin group selected, program the correspoding pin
835 * pin function number in the config register.
836 */
837 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
838 bank = pin_to_bank(info, pins[cnt]);
839 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
840 data[cnt].func);
841 if (ret)
842 break;
843 }
844
845 if (ret) {
846 /* revert the already done pin settings */
847 for (cnt--; cnt >= 0; cnt--)
848 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
849
850 return ret;
851 }
852
853 return 0;
854 }
855
856 /*
857 * The calls to gpio_direction_output() and gpio_direction_input()
858 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
859 * function called from the gpiolib interface).
860 */
861 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
862 int pin, bool input)
863 {
864 struct rockchip_pin_bank *bank;
865 int ret;
866 unsigned long flags;
867 u32 data;
868
869 bank = gc_to_pin_bank(chip);
870
871 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
872 if (ret < 0)
873 return ret;
874
875 spin_lock_irqsave(&bank->slock, flags);
876
877 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
878 /* set bit to 1 for output, 0 for input */
879 if (!input)
880 data |= BIT(pin);
881 else
882 data &= ~BIT(pin);
883 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
884
885 spin_unlock_irqrestore(&bank->slock, flags);
886
887 return 0;
888 }
889
890 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
891 struct pinctrl_gpio_range *range,
892 unsigned offset, bool input)
893 {
894 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
895 struct gpio_chip *chip;
896 int pin;
897
898 chip = range->gc;
899 pin = offset - chip->base;
900 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
901 offset, range->name, pin, input ? "input" : "output");
902
903 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
904 input);
905 }
906
907 static const struct pinmux_ops rockchip_pmx_ops = {
908 .get_functions_count = rockchip_pmx_get_funcs_count,
909 .get_function_name = rockchip_pmx_get_func_name,
910 .get_function_groups = rockchip_pmx_get_groups,
911 .set_mux = rockchip_pmx_set,
912 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
913 };
914
915 /*
916 * Pinconf_ops handling
917 */
918
919 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
920 enum pin_config_param pull)
921 {
922 switch (ctrl->type) {
923 case RK2928:
924 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
925 pull == PIN_CONFIG_BIAS_DISABLE);
926 case RK3066B:
927 return pull ? false : true;
928 case RK3188:
929 case RK3288:
930 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
931 }
932
933 return false;
934 }
935
936 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
937 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
938
939 /* set the pin config settings for a specified pin */
940 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
941 unsigned long *configs, unsigned num_configs)
942 {
943 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
944 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
945 enum pin_config_param param;
946 u16 arg;
947 int i;
948 int rc;
949
950 for (i = 0; i < num_configs; i++) {
951 param = pinconf_to_config_param(configs[i]);
952 arg = pinconf_to_config_argument(configs[i]);
953
954 switch (param) {
955 case PIN_CONFIG_BIAS_DISABLE:
956 rc = rockchip_set_pull(bank, pin - bank->pin_base,
957 param);
958 if (rc)
959 return rc;
960 break;
961 case PIN_CONFIG_BIAS_PULL_UP:
962 case PIN_CONFIG_BIAS_PULL_DOWN:
963 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
964 case PIN_CONFIG_BIAS_BUS_HOLD:
965 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
966 return -ENOTSUPP;
967
968 if (!arg)
969 return -EINVAL;
970
971 rc = rockchip_set_pull(bank, pin - bank->pin_base,
972 param);
973 if (rc)
974 return rc;
975 break;
976 case PIN_CONFIG_OUTPUT:
977 rockchip_gpio_set(&bank->gpio_chip,
978 pin - bank->pin_base, arg);
979 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
980 pin - bank->pin_base, false);
981 if (rc)
982 return rc;
983 break;
984 case PIN_CONFIG_DRIVE_STRENGTH:
985 /* rk3288 is the first with per-pin drive-strength */
986 if (info->ctrl->type != RK3288)
987 return -ENOTSUPP;
988
989 rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
990 if (rc < 0)
991 return rc;
992 break;
993 default:
994 return -ENOTSUPP;
995 break;
996 }
997 } /* for each config */
998
999 return 0;
1000 }
1001
1002 /* get the pin config settings for a specified pin */
1003 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1004 unsigned long *config)
1005 {
1006 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1007 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1008 enum pin_config_param param = pinconf_to_config_param(*config);
1009 u16 arg;
1010 int rc;
1011
1012 switch (param) {
1013 case PIN_CONFIG_BIAS_DISABLE:
1014 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1015 return -EINVAL;
1016
1017 arg = 0;
1018 break;
1019 case PIN_CONFIG_BIAS_PULL_UP:
1020 case PIN_CONFIG_BIAS_PULL_DOWN:
1021 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1022 case PIN_CONFIG_BIAS_BUS_HOLD:
1023 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1024 return -ENOTSUPP;
1025
1026 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1027 return -EINVAL;
1028
1029 arg = 1;
1030 break;
1031 case PIN_CONFIG_OUTPUT:
1032 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1033 if (rc != RK_FUNC_GPIO)
1034 return -EINVAL;
1035
1036 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1037 if (rc < 0)
1038 return rc;
1039
1040 arg = rc ? 1 : 0;
1041 break;
1042 case PIN_CONFIG_DRIVE_STRENGTH:
1043 /* rk3288 is the first with per-pin drive-strength */
1044 if (info->ctrl->type != RK3288)
1045 return -ENOTSUPP;
1046
1047 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1048 if (rc < 0)
1049 return rc;
1050
1051 arg = rc;
1052 break;
1053 default:
1054 return -ENOTSUPP;
1055 break;
1056 }
1057
1058 *config = pinconf_to_config_packed(param, arg);
1059
1060 return 0;
1061 }
1062
1063 static const struct pinconf_ops rockchip_pinconf_ops = {
1064 .pin_config_get = rockchip_pinconf_get,
1065 .pin_config_set = rockchip_pinconf_set,
1066 .is_generic = true,
1067 };
1068
1069 static const struct of_device_id rockchip_bank_match[] = {
1070 { .compatible = "rockchip,gpio-bank" },
1071 { .compatible = "rockchip,rk3188-gpio-bank0" },
1072 {},
1073 };
1074
1075 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1076 struct device_node *np)
1077 {
1078 struct device_node *child;
1079
1080 for_each_child_of_node(np, child) {
1081 if (of_match_node(rockchip_bank_match, child))
1082 continue;
1083
1084 info->nfunctions++;
1085 info->ngroups += of_get_child_count(child);
1086 }
1087 }
1088
1089 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1090 struct rockchip_pin_group *grp,
1091 struct rockchip_pinctrl *info,
1092 u32 index)
1093 {
1094 struct rockchip_pin_bank *bank;
1095 int size;
1096 const __be32 *list;
1097 int num;
1098 int i, j;
1099 int ret;
1100
1101 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1102
1103 /* Initialise group */
1104 grp->name = np->name;
1105
1106 /*
1107 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1108 * do sanity check and calculate pins number
1109 */
1110 list = of_get_property(np, "rockchip,pins", &size);
1111 /* we do not check return since it's safe node passed down */
1112 size /= sizeof(*list);
1113 if (!size || size % 4) {
1114 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1115 return -EINVAL;
1116 }
1117
1118 grp->npins = size / 4;
1119
1120 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1121 GFP_KERNEL);
1122 grp->data = devm_kzalloc(info->dev, grp->npins *
1123 sizeof(struct rockchip_pin_config),
1124 GFP_KERNEL);
1125 if (!grp->pins || !grp->data)
1126 return -ENOMEM;
1127
1128 for (i = 0, j = 0; i < size; i += 4, j++) {
1129 const __be32 *phandle;
1130 struct device_node *np_config;
1131
1132 num = be32_to_cpu(*list++);
1133 bank = bank_num_to_bank(info, num);
1134 if (IS_ERR(bank))
1135 return PTR_ERR(bank);
1136
1137 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1138 grp->data[j].func = be32_to_cpu(*list++);
1139
1140 phandle = list++;
1141 if (!phandle)
1142 return -EINVAL;
1143
1144 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1145 ret = pinconf_generic_parse_dt_config(np_config,
1146 &grp->data[j].configs, &grp->data[j].nconfigs);
1147 if (ret)
1148 return ret;
1149 }
1150
1151 return 0;
1152 }
1153
1154 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1155 struct rockchip_pinctrl *info,
1156 u32 index)
1157 {
1158 struct device_node *child;
1159 struct rockchip_pmx_func *func;
1160 struct rockchip_pin_group *grp;
1161 int ret;
1162 static u32 grp_index;
1163 u32 i = 0;
1164
1165 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1166
1167 func = &info->functions[index];
1168
1169 /* Initialise function */
1170 func->name = np->name;
1171 func->ngroups = of_get_child_count(np);
1172 if (func->ngroups <= 0)
1173 return 0;
1174
1175 func->groups = devm_kzalloc(info->dev,
1176 func->ngroups * sizeof(char *), GFP_KERNEL);
1177 if (!func->groups)
1178 return -ENOMEM;
1179
1180 for_each_child_of_node(np, child) {
1181 func->groups[i] = child->name;
1182 grp = &info->groups[grp_index++];
1183 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1184 if (ret)
1185 return ret;
1186 }
1187
1188 return 0;
1189 }
1190
1191 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1192 struct rockchip_pinctrl *info)
1193 {
1194 struct device *dev = &pdev->dev;
1195 struct device_node *np = dev->of_node;
1196 struct device_node *child;
1197 int ret;
1198 int i;
1199
1200 rockchip_pinctrl_child_count(info, np);
1201
1202 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1203 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1204
1205 info->functions = devm_kzalloc(dev, info->nfunctions *
1206 sizeof(struct rockchip_pmx_func),
1207 GFP_KERNEL);
1208 if (!info->functions) {
1209 dev_err(dev, "failed to allocate memory for function list\n");
1210 return -EINVAL;
1211 }
1212
1213 info->groups = devm_kzalloc(dev, info->ngroups *
1214 sizeof(struct rockchip_pin_group),
1215 GFP_KERNEL);
1216 if (!info->groups) {
1217 dev_err(dev, "failed allocate memory for ping group list\n");
1218 return -EINVAL;
1219 }
1220
1221 i = 0;
1222
1223 for_each_child_of_node(np, child) {
1224 if (of_match_node(rockchip_bank_match, child))
1225 continue;
1226
1227 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1228 if (ret) {
1229 dev_err(&pdev->dev, "failed to parse function\n");
1230 return ret;
1231 }
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int rockchip_pinctrl_register(struct platform_device *pdev,
1238 struct rockchip_pinctrl *info)
1239 {
1240 struct pinctrl_desc *ctrldesc = &info->pctl;
1241 struct pinctrl_pin_desc *pindesc, *pdesc;
1242 struct rockchip_pin_bank *pin_bank;
1243 int pin, bank, ret;
1244 int k;
1245
1246 ctrldesc->name = "rockchip-pinctrl";
1247 ctrldesc->owner = THIS_MODULE;
1248 ctrldesc->pctlops = &rockchip_pctrl_ops;
1249 ctrldesc->pmxops = &rockchip_pmx_ops;
1250 ctrldesc->confops = &rockchip_pinconf_ops;
1251
1252 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1253 info->ctrl->nr_pins, GFP_KERNEL);
1254 if (!pindesc) {
1255 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1256 return -ENOMEM;
1257 }
1258 ctrldesc->pins = pindesc;
1259 ctrldesc->npins = info->ctrl->nr_pins;
1260
1261 pdesc = pindesc;
1262 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1263 pin_bank = &info->ctrl->pin_banks[bank];
1264 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1265 pdesc->number = k;
1266 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1267 pin_bank->name, pin);
1268 pdesc++;
1269 }
1270 }
1271
1272 ret = rockchip_pinctrl_parse_dt(pdev, info);
1273 if (ret)
1274 return ret;
1275
1276 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1277 if (!info->pctl_dev) {
1278 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1279 return -EINVAL;
1280 }
1281
1282 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1283 pin_bank = &info->ctrl->pin_banks[bank];
1284 pin_bank->grange.name = pin_bank->name;
1285 pin_bank->grange.id = bank;
1286 pin_bank->grange.pin_base = pin_bank->pin_base;
1287 pin_bank->grange.base = pin_bank->gpio_chip.base;
1288 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1289 pin_bank->grange.gc = &pin_bank->gpio_chip;
1290 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1291 }
1292
1293 return 0;
1294 }
1295
1296 /*
1297 * GPIO handling
1298 */
1299
1300 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1301 {
1302 return pinctrl_request_gpio(chip->base + offset);
1303 }
1304
1305 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1306 {
1307 pinctrl_free_gpio(chip->base + offset);
1308 }
1309
1310 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1311 {
1312 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1313 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1314 unsigned long flags;
1315 u32 data;
1316
1317 spin_lock_irqsave(&bank->slock, flags);
1318
1319 data = readl(reg);
1320 data &= ~BIT(offset);
1321 if (value)
1322 data |= BIT(offset);
1323 writel(data, reg);
1324
1325 spin_unlock_irqrestore(&bank->slock, flags);
1326 }
1327
1328 /*
1329 * Returns the level of the pin for input direction and setting of the DR
1330 * register for output gpios.
1331 */
1332 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1333 {
1334 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1335 u32 data;
1336
1337 data = readl(bank->reg_base + GPIO_EXT_PORT);
1338 data >>= offset;
1339 data &= 1;
1340 return data;
1341 }
1342
1343 /*
1344 * gpiolib gpio_direction_input callback function. The setting of the pin
1345 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1346 * interface.
1347 */
1348 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1349 {
1350 return pinctrl_gpio_direction_input(gc->base + offset);
1351 }
1352
1353 /*
1354 * gpiolib gpio_direction_output callback function. The setting of the pin
1355 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1356 * interface.
1357 */
1358 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1359 unsigned offset, int value)
1360 {
1361 rockchip_gpio_set(gc, offset, value);
1362 return pinctrl_gpio_direction_output(gc->base + offset);
1363 }
1364
1365 /*
1366 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1367 * and a virtual IRQ, if not already present.
1368 */
1369 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1370 {
1371 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1372 unsigned int virq;
1373
1374 if (!bank->domain)
1375 return -ENXIO;
1376
1377 virq = irq_create_mapping(bank->domain, offset);
1378
1379 return (virq) ? : -ENXIO;
1380 }
1381
1382 static const struct gpio_chip rockchip_gpiolib_chip = {
1383 .request = rockchip_gpio_request,
1384 .free = rockchip_gpio_free,
1385 .set = rockchip_gpio_set,
1386 .get = rockchip_gpio_get,
1387 .direction_input = rockchip_gpio_direction_input,
1388 .direction_output = rockchip_gpio_direction_output,
1389 .to_irq = rockchip_gpio_to_irq,
1390 .owner = THIS_MODULE,
1391 };
1392
1393 /*
1394 * Interrupt handling
1395 */
1396
1397 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1398 {
1399 struct irq_chip *chip = irq_get_chip(irq);
1400 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1401 u32 polarity = 0, data = 0;
1402 u32 pend;
1403 bool edge_changed = false;
1404 unsigned long flags;
1405
1406 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1407
1408 chained_irq_enter(chip, desc);
1409
1410 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1411
1412 if (bank->toggle_edge_mode) {
1413 polarity = readl_relaxed(bank->reg_base +
1414 GPIO_INT_POLARITY);
1415 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1416 }
1417
1418 while (pend) {
1419 unsigned int virq;
1420
1421 irq = __ffs(pend);
1422 pend &= ~BIT(irq);
1423 virq = irq_linear_revmap(bank->domain, irq);
1424
1425 if (!virq) {
1426 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1427 continue;
1428 }
1429
1430 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1431
1432 /*
1433 * Triggering IRQ on both rising and falling edge
1434 * needs manual intervention.
1435 */
1436 if (bank->toggle_edge_mode & BIT(irq)) {
1437 if (data & BIT(irq))
1438 polarity &= ~BIT(irq);
1439 else
1440 polarity |= BIT(irq);
1441
1442 edge_changed = true;
1443 }
1444
1445 generic_handle_irq(virq);
1446 }
1447
1448 if (bank->toggle_edge_mode && edge_changed) {
1449 /* Interrupt params should only be set with ints disabled */
1450 spin_lock_irqsave(&bank->slock, flags);
1451
1452 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1453 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1454 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1455 writel(data, bank->reg_base + GPIO_INTEN);
1456
1457 spin_unlock_irqrestore(&bank->slock, flags);
1458 }
1459
1460 chained_irq_exit(chip, desc);
1461 }
1462
1463 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1464 {
1465 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1466 struct rockchip_pin_bank *bank = gc->private;
1467 u32 mask = BIT(d->hwirq);
1468 u32 polarity;
1469 u32 level;
1470 u32 data;
1471 unsigned long flags;
1472 int ret;
1473
1474 /* make sure the pin is configured as gpio input */
1475 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1476 if (ret < 0)
1477 return ret;
1478
1479 spin_lock_irqsave(&bank->slock, flags);
1480
1481 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1482 data &= ~mask;
1483 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1484
1485 spin_unlock_irqrestore(&bank->slock, flags);
1486
1487 if (type & IRQ_TYPE_EDGE_BOTH)
1488 __irq_set_handler_locked(d->irq, handle_edge_irq);
1489 else
1490 __irq_set_handler_locked(d->irq, handle_level_irq);
1491
1492 spin_lock_irqsave(&bank->slock, flags);
1493 irq_gc_lock(gc);
1494
1495 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1496 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1497
1498 switch (type) {
1499 case IRQ_TYPE_EDGE_BOTH:
1500 bank->toggle_edge_mode |= mask;
1501 level |= mask;
1502
1503 /*
1504 * Determine gpio state. If 1 next interrupt should be falling
1505 * otherwise rising.
1506 */
1507 data = readl(bank->reg_base + GPIO_EXT_PORT);
1508 if (data & mask)
1509 polarity &= ~mask;
1510 else
1511 polarity |= mask;
1512 break;
1513 case IRQ_TYPE_EDGE_RISING:
1514 bank->toggle_edge_mode &= ~mask;
1515 level |= mask;
1516 polarity |= mask;
1517 break;
1518 case IRQ_TYPE_EDGE_FALLING:
1519 bank->toggle_edge_mode &= ~mask;
1520 level |= mask;
1521 polarity &= ~mask;
1522 break;
1523 case IRQ_TYPE_LEVEL_HIGH:
1524 bank->toggle_edge_mode &= ~mask;
1525 level &= ~mask;
1526 polarity |= mask;
1527 break;
1528 case IRQ_TYPE_LEVEL_LOW:
1529 bank->toggle_edge_mode &= ~mask;
1530 level &= ~mask;
1531 polarity &= ~mask;
1532 break;
1533 default:
1534 irq_gc_unlock(gc);
1535 spin_unlock_irqrestore(&bank->slock, flags);
1536 return -EINVAL;
1537 }
1538
1539 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1540 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1541
1542 irq_gc_unlock(gc);
1543 spin_unlock_irqrestore(&bank->slock, flags);
1544
1545 return 0;
1546 }
1547
1548 static void rockchip_irq_suspend(struct irq_data *d)
1549 {
1550 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1551 struct rockchip_pin_bank *bank = gc->private;
1552
1553 bank->saved_enables = irq_reg_readl(gc, GPIO_INTEN);
1554 irq_reg_writel(gc, gc->wake_active, GPIO_INTEN);
1555 }
1556
1557 static void rockchip_irq_resume(struct irq_data *d)
1558 {
1559 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1560 struct rockchip_pin_bank *bank = gc->private;
1561
1562 irq_reg_writel(gc, bank->saved_enables, GPIO_INTEN);
1563 }
1564
1565 static void rockchip_irq_disable(struct irq_data *d)
1566 {
1567 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1568 u32 val;
1569
1570 irq_gc_lock(gc);
1571
1572 val = irq_reg_readl(gc, GPIO_INTEN);
1573 val &= ~d->mask;
1574 irq_reg_writel(gc, val, GPIO_INTEN);
1575
1576 irq_gc_unlock(gc);
1577 }
1578
1579 static void rockchip_irq_enable(struct irq_data *d)
1580 {
1581 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1582 u32 val;
1583
1584 irq_gc_lock(gc);
1585
1586 val = irq_reg_readl(gc, GPIO_INTEN);
1587 val |= d->mask;
1588 irq_reg_writel(gc, val, GPIO_INTEN);
1589
1590 irq_gc_unlock(gc);
1591 }
1592
1593 static int rockchip_interrupts_register(struct platform_device *pdev,
1594 struct rockchip_pinctrl *info)
1595 {
1596 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1597 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1598 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1599 struct irq_chip_generic *gc;
1600 int ret;
1601 int i;
1602
1603 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1604 if (!bank->valid) {
1605 dev_warn(&pdev->dev, "bank %s is not valid\n",
1606 bank->name);
1607 continue;
1608 }
1609
1610 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1611 &irq_generic_chip_ops, NULL);
1612 if (!bank->domain) {
1613 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1614 bank->name);
1615 continue;
1616 }
1617
1618 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1619 "rockchip_gpio_irq", handle_level_irq,
1620 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1621 if (ret) {
1622 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1623 bank->name);
1624 irq_domain_remove(bank->domain);
1625 continue;
1626 }
1627
1628 gc = irq_get_domain_generic_chip(bank->domain, 0);
1629 gc->reg_base = bank->reg_base;
1630 gc->private = bank;
1631 gc->chip_types[0].regs.mask = GPIO_INTMASK;
1632 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1633 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1634 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
1635 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
1636 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
1637 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
1638 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1639 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1640 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
1641 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1642 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
1643
1644 irq_set_handler_data(bank->irq, bank);
1645 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1646 }
1647
1648 return 0;
1649 }
1650
1651 static int rockchip_gpiolib_register(struct platform_device *pdev,
1652 struct rockchip_pinctrl *info)
1653 {
1654 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1655 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1656 struct gpio_chip *gc;
1657 int ret;
1658 int i;
1659
1660 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1661 if (!bank->valid) {
1662 dev_warn(&pdev->dev, "bank %s is not valid\n",
1663 bank->name);
1664 continue;
1665 }
1666
1667 bank->gpio_chip = rockchip_gpiolib_chip;
1668
1669 gc = &bank->gpio_chip;
1670 gc->base = bank->pin_base;
1671 gc->ngpio = bank->nr_pins;
1672 gc->dev = &pdev->dev;
1673 gc->of_node = bank->of_node;
1674 gc->label = bank->name;
1675
1676 ret = gpiochip_add(gc);
1677 if (ret) {
1678 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1679 gc->label, ret);
1680 goto fail;
1681 }
1682 }
1683
1684 rockchip_interrupts_register(pdev, info);
1685
1686 return 0;
1687
1688 fail:
1689 for (--i, --bank; i >= 0; --i, --bank) {
1690 if (!bank->valid)
1691 continue;
1692 gpiochip_remove(&bank->gpio_chip);
1693 }
1694 return ret;
1695 }
1696
1697 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1698 struct rockchip_pinctrl *info)
1699 {
1700 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1701 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1702 int i;
1703
1704 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1705 if (!bank->valid)
1706 continue;
1707 gpiochip_remove(&bank->gpio_chip);
1708 }
1709
1710 return 0;
1711 }
1712
1713 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1714 struct rockchip_pinctrl *info)
1715 {
1716 struct resource res;
1717 void __iomem *base;
1718
1719 if (of_address_to_resource(bank->of_node, 0, &res)) {
1720 dev_err(info->dev, "cannot find IO resource for bank\n");
1721 return -ENOENT;
1722 }
1723
1724 bank->reg_base = devm_ioremap_resource(info->dev, &res);
1725 if (IS_ERR(bank->reg_base))
1726 return PTR_ERR(bank->reg_base);
1727
1728 /*
1729 * special case, where parts of the pull setting-registers are
1730 * part of the PMU register space
1731 */
1732 if (of_device_is_compatible(bank->of_node,
1733 "rockchip,rk3188-gpio-bank0")) {
1734 struct device_node *node;
1735
1736 node = of_parse_phandle(bank->of_node->parent,
1737 "rockchip,pmu", 0);
1738 if (!node) {
1739 if (of_address_to_resource(bank->of_node, 1, &res)) {
1740 dev_err(info->dev, "cannot find IO resource for bank\n");
1741 return -ENOENT;
1742 }
1743
1744 base = devm_ioremap_resource(info->dev, &res);
1745 if (IS_ERR(base))
1746 return PTR_ERR(base);
1747 rockchip_regmap_config.max_register =
1748 resource_size(&res) - 4;
1749 rockchip_regmap_config.name =
1750 "rockchip,rk3188-gpio-bank0-pull";
1751 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1752 base,
1753 &rockchip_regmap_config);
1754 }
1755 }
1756
1757 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1758
1759 bank->clk = of_clk_get(bank->of_node, 0);
1760 if (IS_ERR(bank->clk))
1761 return PTR_ERR(bank->clk);
1762
1763 return clk_prepare_enable(bank->clk);
1764 }
1765
1766 static const struct of_device_id rockchip_pinctrl_dt_match[];
1767
1768 /* retrieve the soc specific data */
1769 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1770 struct rockchip_pinctrl *d,
1771 struct platform_device *pdev)
1772 {
1773 const struct of_device_id *match;
1774 struct device_node *node = pdev->dev.of_node;
1775 struct device_node *np;
1776 struct rockchip_pin_ctrl *ctrl;
1777 struct rockchip_pin_bank *bank;
1778 int grf_offs, pmu_offs, i, j;
1779
1780 match = of_match_node(rockchip_pinctrl_dt_match, node);
1781 ctrl = (struct rockchip_pin_ctrl *)match->data;
1782
1783 for_each_child_of_node(node, np) {
1784 if (!of_find_property(np, "gpio-controller", NULL))
1785 continue;
1786
1787 bank = ctrl->pin_banks;
1788 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1789 if (!strcmp(bank->name, np->name)) {
1790 bank->of_node = np;
1791
1792 if (!rockchip_get_bank_data(bank, d))
1793 bank->valid = true;
1794
1795 break;
1796 }
1797 }
1798 }
1799
1800 grf_offs = ctrl->grf_mux_offset;
1801 pmu_offs = ctrl->pmu_mux_offset;
1802 bank = ctrl->pin_banks;
1803 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1804 int bank_pins = 0;
1805
1806 spin_lock_init(&bank->slock);
1807 bank->drvdata = d;
1808 bank->pin_base = ctrl->nr_pins;
1809 ctrl->nr_pins += bank->nr_pins;
1810
1811 /* calculate iomux offsets */
1812 for (j = 0; j < 4; j++) {
1813 struct rockchip_iomux *iom = &bank->iomux[j];
1814 int inc;
1815
1816 if (bank_pins >= bank->nr_pins)
1817 break;
1818
1819 /* preset offset value, set new start value */
1820 if (iom->offset >= 0) {
1821 if (iom->type & IOMUX_SOURCE_PMU)
1822 pmu_offs = iom->offset;
1823 else
1824 grf_offs = iom->offset;
1825 } else { /* set current offset */
1826 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1827 pmu_offs : grf_offs;
1828 }
1829
1830 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1831 i, j, iom->offset);
1832
1833 /*
1834 * Increase offset according to iomux width.
1835 * 4bit iomux'es are spread over two registers.
1836 */
1837 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1838 if (iom->type & IOMUX_SOURCE_PMU)
1839 pmu_offs += inc;
1840 else
1841 grf_offs += inc;
1842
1843 bank_pins += 8;
1844 }
1845 }
1846
1847 return ctrl;
1848 }
1849
1850 #define RK3288_GRF_GPIO6C_IOMUX 0x64
1851 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
1852
1853 static u32 rk3288_grf_gpio6c_iomux;
1854
1855 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
1856 {
1857 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
1858 int ret = pinctrl_force_sleep(info->pctl_dev);
1859
1860 if (ret)
1861 return ret;
1862
1863 /*
1864 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
1865 * the setting here, and restore it at resume.
1866 */
1867 if (info->ctrl->type == RK3288) {
1868 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1869 &rk3288_grf_gpio6c_iomux);
1870 if (ret) {
1871 pinctrl_force_default(info->pctl_dev);
1872 return ret;
1873 }
1874 }
1875
1876 return 0;
1877 }
1878
1879 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
1880 {
1881 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
1882 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1883 rk3288_grf_gpio6c_iomux |
1884 GPIO6C6_SEL_WRITE_ENABLE);
1885
1886 if (ret)
1887 return ret;
1888
1889 return pinctrl_force_default(info->pctl_dev);
1890 }
1891
1892 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
1893 rockchip_pinctrl_resume);
1894
1895 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1896 {
1897 struct rockchip_pinctrl *info;
1898 struct device *dev = &pdev->dev;
1899 struct rockchip_pin_ctrl *ctrl;
1900 struct device_node *np = pdev->dev.of_node, *node;
1901 struct resource *res;
1902 void __iomem *base;
1903 int ret;
1904
1905 if (!dev->of_node) {
1906 dev_err(dev, "device tree node not found\n");
1907 return -ENODEV;
1908 }
1909
1910 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1911 if (!info)
1912 return -ENOMEM;
1913
1914 info->dev = dev;
1915
1916 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1917 if (!ctrl) {
1918 dev_err(dev, "driver data not available\n");
1919 return -EINVAL;
1920 }
1921 info->ctrl = ctrl;
1922
1923 node = of_parse_phandle(np, "rockchip,grf", 0);
1924 if (node) {
1925 info->regmap_base = syscon_node_to_regmap(node);
1926 if (IS_ERR(info->regmap_base))
1927 return PTR_ERR(info->regmap_base);
1928 } else {
1929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1930 base = devm_ioremap_resource(&pdev->dev, res);
1931 if (IS_ERR(base))
1932 return PTR_ERR(base);
1933
1934 rockchip_regmap_config.max_register = resource_size(res) - 4;
1935 rockchip_regmap_config.name = "rockchip,pinctrl";
1936 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1937 &rockchip_regmap_config);
1938
1939 /* to check for the old dt-bindings */
1940 info->reg_size = resource_size(res);
1941
1942 /* Honor the old binding, with pull registers as 2nd resource */
1943 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1944 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1945 base = devm_ioremap_resource(&pdev->dev, res);
1946 if (IS_ERR(base))
1947 return PTR_ERR(base);
1948
1949 rockchip_regmap_config.max_register =
1950 resource_size(res) - 4;
1951 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1952 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1953 base,
1954 &rockchip_regmap_config);
1955 }
1956 }
1957
1958 /* try to find the optional reference to the pmu syscon */
1959 node = of_parse_phandle(np, "rockchip,pmu", 0);
1960 if (node) {
1961 info->regmap_pmu = syscon_node_to_regmap(node);
1962 if (IS_ERR(info->regmap_pmu))
1963 return PTR_ERR(info->regmap_pmu);
1964 }
1965
1966 ret = rockchip_gpiolib_register(pdev, info);
1967 if (ret)
1968 return ret;
1969
1970 ret = rockchip_pinctrl_register(pdev, info);
1971 if (ret) {
1972 rockchip_gpiolib_unregister(pdev, info);
1973 return ret;
1974 }
1975
1976 platform_set_drvdata(pdev, info);
1977
1978 return 0;
1979 }
1980
1981 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1982 PIN_BANK(0, 32, "gpio0"),
1983 PIN_BANK(1, 32, "gpio1"),
1984 PIN_BANK(2, 32, "gpio2"),
1985 PIN_BANK(3, 32, "gpio3"),
1986 };
1987
1988 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1989 .pin_banks = rk2928_pin_banks,
1990 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1991 .label = "RK2928-GPIO",
1992 .type = RK2928,
1993 .grf_mux_offset = 0xa8,
1994 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1995 };
1996
1997 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1998 PIN_BANK(0, 32, "gpio0"),
1999 PIN_BANK(1, 32, "gpio1"),
2000 PIN_BANK(2, 32, "gpio2"),
2001 PIN_BANK(3, 32, "gpio3"),
2002 PIN_BANK(4, 32, "gpio4"),
2003 PIN_BANK(6, 16, "gpio6"),
2004 };
2005
2006 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2007 .pin_banks = rk3066a_pin_banks,
2008 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2009 .label = "RK3066a-GPIO",
2010 .type = RK2928,
2011 .grf_mux_offset = 0xa8,
2012 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2013 };
2014
2015 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2016 PIN_BANK(0, 32, "gpio0"),
2017 PIN_BANK(1, 32, "gpio1"),
2018 PIN_BANK(2, 32, "gpio2"),
2019 PIN_BANK(3, 32, "gpio3"),
2020 };
2021
2022 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2023 .pin_banks = rk3066b_pin_banks,
2024 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2025 .label = "RK3066b-GPIO",
2026 .type = RK3066B,
2027 .grf_mux_offset = 0x60,
2028 };
2029
2030 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2031 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2032 PIN_BANK(1, 32, "gpio1"),
2033 PIN_BANK(2, 32, "gpio2"),
2034 PIN_BANK(3, 32, "gpio3"),
2035 };
2036
2037 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2038 .pin_banks = rk3188_pin_banks,
2039 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2040 .label = "RK3188-GPIO",
2041 .type = RK3188,
2042 .grf_mux_offset = 0x60,
2043 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2044 };
2045
2046 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2047 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2048 IOMUX_SOURCE_PMU,
2049 IOMUX_SOURCE_PMU,
2050 IOMUX_UNROUTED
2051 ),
2052 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2053 IOMUX_UNROUTED,
2054 IOMUX_UNROUTED,
2055 0
2056 ),
2057 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2058 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2059 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2060 IOMUX_WIDTH_4BIT,
2061 0,
2062 0
2063 ),
2064 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2065 0,
2066 0,
2067 IOMUX_UNROUTED
2068 ),
2069 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2070 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2071 0,
2072 IOMUX_WIDTH_4BIT,
2073 IOMUX_UNROUTED
2074 ),
2075 PIN_BANK(8, 16, "gpio8"),
2076 };
2077
2078 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2079 .pin_banks = rk3288_pin_banks,
2080 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2081 .label = "RK3288-GPIO",
2082 .type = RK3288,
2083 .grf_mux_offset = 0x0,
2084 .pmu_mux_offset = 0x84,
2085 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2086 };
2087
2088 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2089 { .compatible = "rockchip,rk2928-pinctrl",
2090 .data = (void *)&rk2928_pin_ctrl },
2091 { .compatible = "rockchip,rk3066a-pinctrl",
2092 .data = (void *)&rk3066a_pin_ctrl },
2093 { .compatible = "rockchip,rk3066b-pinctrl",
2094 .data = (void *)&rk3066b_pin_ctrl },
2095 { .compatible = "rockchip,rk3188-pinctrl",
2096 .data = (void *)&rk3188_pin_ctrl },
2097 { .compatible = "rockchip,rk3288-pinctrl",
2098 .data = (void *)&rk3288_pin_ctrl },
2099 {},
2100 };
2101 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2102
2103 static struct platform_driver rockchip_pinctrl_driver = {
2104 .probe = rockchip_pinctrl_probe,
2105 .driver = {
2106 .name = "rockchip-pinctrl",
2107 .pm = &rockchip_pinctrl_dev_pm_ops,
2108 .of_match_table = rockchip_pinctrl_dt_match,
2109 },
2110 };
2111
2112 static int __init rockchip_pinctrl_drv_register(void)
2113 {
2114 return platform_driver_register(&rockchip_pinctrl_driver);
2115 }
2116 postcore_initcall(rockchip_pinctrl_drv_register);
2117
2118 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2119 MODULE_DESCRIPTION("Rockchip pinctrl driver");
2120 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.076329 seconds and 5 git commands to generate.