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nfsd4: fix buflen calculation after read encoding
[deliverable/linux.git] / drivers / pinctrl / pinctrl-single.c
1 /*
2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/io.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
19
20 #include <linux/irqchip/chained_irq.h>
21
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30
31 #include <linux/platform_data/pinctrl-single.h>
32
33 #include "core.h"
34 #include "pinconf.h"
35
36 #define DRIVER_NAME "pinctrl-single"
37 #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
38 #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
39 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3)
40 #define PCS_OFF_DISABLED ~0U
41
42 /**
43 * struct pcs_pingroup - pingroups for a function
44 * @np: pingroup device node pointer
45 * @name: pingroup name
46 * @gpins: array of the pins in the group
47 * @ngpins: number of pins in the group
48 * @node: list node
49 */
50 struct pcs_pingroup {
51 struct device_node *np;
52 const char *name;
53 int *gpins;
54 int ngpins;
55 struct list_head node;
56 };
57
58 /**
59 * struct pcs_func_vals - mux function register offset and value pair
60 * @reg: register virtual address
61 * @val: register value
62 */
63 struct pcs_func_vals {
64 void __iomem *reg;
65 unsigned val;
66 unsigned mask;
67 };
68
69 /**
70 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * and value, enable, disable, mask
72 * @param: config parameter
73 * @val: user input bits in the pinconf register
74 * @enable: enable bits in the pinconf register
75 * @disable: disable bits in the pinconf register
76 * @mask: mask bits in the register value
77 */
78 struct pcs_conf_vals {
79 enum pin_config_param param;
80 unsigned val;
81 unsigned enable;
82 unsigned disable;
83 unsigned mask;
84 };
85
86 /**
87 * struct pcs_conf_type - pinconf property name, pinconf param pair
88 * @name: property name in DTS file
89 * @param: config parameter
90 */
91 struct pcs_conf_type {
92 const char *name;
93 enum pin_config_param param;
94 };
95
96 /**
97 * struct pcs_function - pinctrl function
98 * @name: pinctrl function name
99 * @vals: register and vals array
100 * @nvals: number of entries in vals array
101 * @pgnames: array of pingroup names the function uses
102 * @npgnames: number of pingroup names the function uses
103 * @node: list node
104 */
105 struct pcs_function {
106 const char *name;
107 struct pcs_func_vals *vals;
108 unsigned nvals;
109 const char **pgnames;
110 int npgnames;
111 struct pcs_conf_vals *conf;
112 int nconfs;
113 struct list_head node;
114 };
115
116 /**
117 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
118 * @offset: offset base of pins
119 * @npins: number pins with the same mux value of gpio function
120 * @gpiofunc: mux value of gpio function
121 * @node: list node
122 */
123 struct pcs_gpiofunc_range {
124 unsigned offset;
125 unsigned npins;
126 unsigned gpiofunc;
127 struct list_head node;
128 };
129
130 /**
131 * struct pcs_data - wrapper for data needed by pinctrl framework
132 * @pa: pindesc array
133 * @cur: index to current element
134 *
135 * REVISIT: We should be able to drop this eventually by adding
136 * support for registering pins individually in the pinctrl
137 * framework for those drivers that don't need a static array.
138 */
139 struct pcs_data {
140 struct pinctrl_pin_desc *pa;
141 int cur;
142 };
143
144 /**
145 * struct pcs_name - register name for a pin
146 * @name: name of the pinctrl register
147 *
148 * REVISIT: We may want to make names optional in the pinctrl
149 * framework as some drivers may not care about pin names to
150 * avoid kernel bloat. The pin names can be deciphered by user
151 * space tools using debugfs based on the register address and
152 * SoC packaging information.
153 */
154 struct pcs_name {
155 char name[PCS_REG_NAME_LEN];
156 };
157
158 /**
159 * struct pcs_soc_data - SoC specific settings
160 * @flags: initial SoC specific PCS_FEAT_xxx values
161 * @irq: optional interrupt for the controller
162 * @irq_enable_mask: optional SoC specific interrupt enable mask
163 * @irq_status_mask: optional SoC specific interrupt status mask
164 * @rearm: optional SoC specific wake-up rearm function
165 */
166 struct pcs_soc_data {
167 unsigned flags;
168 int irq;
169 unsigned irq_enable_mask;
170 unsigned irq_status_mask;
171 void (*rearm)(void);
172 };
173
174 /**
175 * struct pcs_device - pinctrl device instance
176 * @res: resources
177 * @base: virtual address of the controller
178 * @size: size of the ioremapped area
179 * @dev: device entry
180 * @pctl: pin controller device
181 * @flags: mask of PCS_FEAT_xxx values
182 * @lock: spinlock for register access
183 * @mutex: mutex protecting the lists
184 * @width: bits per mux register
185 * @fmask: function register mask
186 * @fshift: function register shift
187 * @foff: value to turn mux off
188 * @fmax: max number of functions in fmask
189 * @bits_per_pin:number of bits per pin
190 * @names: array of register names for pins
191 * @pins: physical pins on the SoC
192 * @pgtree: pingroup index radix tree
193 * @ftree: function index radix tree
194 * @pingroups: list of pingroups
195 * @functions: list of functions
196 * @gpiofuncs: list of gpio functions
197 * @irqs: list of interrupt registers
198 * @chip: chip container for this instance
199 * @domain: IRQ domain for this instance
200 * @ngroups: number of pingroups
201 * @nfuncs: number of functions
202 * @desc: pin controller descriptor
203 * @read: register read function to use
204 * @write: register write function to use
205 */
206 struct pcs_device {
207 struct resource *res;
208 void __iomem *base;
209 unsigned size;
210 struct device *dev;
211 struct pinctrl_dev *pctl;
212 unsigned flags;
213 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
214 #define PCS_FEAT_IRQ (1 << 1)
215 #define PCS_FEAT_PINCONF (1 << 0)
216 struct pcs_soc_data socdata;
217 raw_spinlock_t lock;
218 struct mutex mutex;
219 unsigned width;
220 unsigned fmask;
221 unsigned fshift;
222 unsigned foff;
223 unsigned fmax;
224 bool bits_per_mux;
225 unsigned bits_per_pin;
226 struct pcs_name *names;
227 struct pcs_data pins;
228 struct radix_tree_root pgtree;
229 struct radix_tree_root ftree;
230 struct list_head pingroups;
231 struct list_head functions;
232 struct list_head gpiofuncs;
233 struct list_head irqs;
234 struct irq_chip chip;
235 struct irq_domain *domain;
236 unsigned ngroups;
237 unsigned nfuncs;
238 struct pinctrl_desc desc;
239 unsigned (*read)(void __iomem *reg);
240 void (*write)(unsigned val, void __iomem *reg);
241 };
242
243 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
244 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
245 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
246
247 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
248 unsigned long *config);
249 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
250 unsigned long *configs, unsigned num_configs);
251
252 static enum pin_config_param pcs_bias[] = {
253 PIN_CONFIG_BIAS_PULL_DOWN,
254 PIN_CONFIG_BIAS_PULL_UP,
255 };
256
257 /*
258 * REVISIT: Reads and writes could eventually use regmap or something
259 * generic. But at least on omaps, some mux registers are performance
260 * critical as they may need to be remuxed every time before and after
261 * idle. Adding tests for register access width for every read and
262 * write like regmap is doing is not desired, and caching the registers
263 * does not help in this case.
264 */
265
266 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
267 {
268 return readb(reg);
269 }
270
271 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
272 {
273 return readw(reg);
274 }
275
276 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
277 {
278 return readl(reg);
279 }
280
281 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
282 {
283 writeb(val, reg);
284 }
285
286 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
287 {
288 writew(val, reg);
289 }
290
291 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
292 {
293 writel(val, reg);
294 }
295
296 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
297 {
298 struct pcs_device *pcs;
299
300 pcs = pinctrl_dev_get_drvdata(pctldev);
301
302 return pcs->ngroups;
303 }
304
305 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
306 unsigned gselector)
307 {
308 struct pcs_device *pcs;
309 struct pcs_pingroup *group;
310
311 pcs = pinctrl_dev_get_drvdata(pctldev);
312 group = radix_tree_lookup(&pcs->pgtree, gselector);
313 if (!group) {
314 dev_err(pcs->dev, "%s could not find pingroup%i\n",
315 __func__, gselector);
316 return NULL;
317 }
318
319 return group->name;
320 }
321
322 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
323 unsigned gselector,
324 const unsigned **pins,
325 unsigned *npins)
326 {
327 struct pcs_device *pcs;
328 struct pcs_pingroup *group;
329
330 pcs = pinctrl_dev_get_drvdata(pctldev);
331 group = radix_tree_lookup(&pcs->pgtree, gselector);
332 if (!group) {
333 dev_err(pcs->dev, "%s could not find pingroup%i\n",
334 __func__, gselector);
335 return -EINVAL;
336 }
337
338 *pins = group->gpins;
339 *npins = group->ngpins;
340
341 return 0;
342 }
343
344 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
345 struct seq_file *s,
346 unsigned pin)
347 {
348 struct pcs_device *pcs;
349 unsigned val, mux_bytes;
350
351 pcs = pinctrl_dev_get_drvdata(pctldev);
352
353 mux_bytes = pcs->width / BITS_PER_BYTE;
354 val = pcs->read(pcs->base + pin * mux_bytes);
355
356 seq_printf(s, "%08x %s " , val, DRIVER_NAME);
357 }
358
359 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
360 struct pinctrl_map *map, unsigned num_maps)
361 {
362 struct pcs_device *pcs;
363
364 pcs = pinctrl_dev_get_drvdata(pctldev);
365 devm_kfree(pcs->dev, map);
366 }
367
368 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
369 struct device_node *np_config,
370 struct pinctrl_map **map, unsigned *num_maps);
371
372 static const struct pinctrl_ops pcs_pinctrl_ops = {
373 .get_groups_count = pcs_get_groups_count,
374 .get_group_name = pcs_get_group_name,
375 .get_group_pins = pcs_get_group_pins,
376 .pin_dbg_show = pcs_pin_dbg_show,
377 .dt_node_to_map = pcs_dt_node_to_map,
378 .dt_free_map = pcs_dt_free_map,
379 };
380
381 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
382 {
383 struct pcs_device *pcs;
384
385 pcs = pinctrl_dev_get_drvdata(pctldev);
386
387 return pcs->nfuncs;
388 }
389
390 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
391 unsigned fselector)
392 {
393 struct pcs_device *pcs;
394 struct pcs_function *func;
395
396 pcs = pinctrl_dev_get_drvdata(pctldev);
397 func = radix_tree_lookup(&pcs->ftree, fselector);
398 if (!func) {
399 dev_err(pcs->dev, "%s could not find function%i\n",
400 __func__, fselector);
401 return NULL;
402 }
403
404 return func->name;
405 }
406
407 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
408 unsigned fselector,
409 const char * const **groups,
410 unsigned * const ngroups)
411 {
412 struct pcs_device *pcs;
413 struct pcs_function *func;
414
415 pcs = pinctrl_dev_get_drvdata(pctldev);
416 func = radix_tree_lookup(&pcs->ftree, fselector);
417 if (!func) {
418 dev_err(pcs->dev, "%s could not find function%i\n",
419 __func__, fselector);
420 return -EINVAL;
421 }
422 *groups = func->pgnames;
423 *ngroups = func->npgnames;
424
425 return 0;
426 }
427
428 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
429 struct pcs_function **func)
430 {
431 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
432 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
433 const struct pinctrl_setting_mux *setting;
434 unsigned fselector;
435
436 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
437 setting = pdesc->mux_setting;
438 if (!setting)
439 return -ENOTSUPP;
440 fselector = setting->func;
441 *func = radix_tree_lookup(&pcs->ftree, fselector);
442 if (!(*func)) {
443 dev_err(pcs->dev, "%s could not find function%i\n",
444 __func__, fselector);
445 return -ENOTSUPP;
446 }
447 return 0;
448 }
449
450 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
451 unsigned group)
452 {
453 struct pcs_device *pcs;
454 struct pcs_function *func;
455 int i;
456
457 pcs = pinctrl_dev_get_drvdata(pctldev);
458 /* If function mask is null, needn't enable it. */
459 if (!pcs->fmask)
460 return 0;
461 func = radix_tree_lookup(&pcs->ftree, fselector);
462 if (!func)
463 return -EINVAL;
464
465 dev_dbg(pcs->dev, "enabling %s function%i\n",
466 func->name, fselector);
467
468 for (i = 0; i < func->nvals; i++) {
469 struct pcs_func_vals *vals;
470 unsigned long flags;
471 unsigned val, mask;
472
473 vals = &func->vals[i];
474 raw_spin_lock_irqsave(&pcs->lock, flags);
475 val = pcs->read(vals->reg);
476
477 if (pcs->bits_per_mux)
478 mask = vals->mask;
479 else
480 mask = pcs->fmask;
481
482 val &= ~mask;
483 val |= (vals->val & mask);
484 pcs->write(val, vals->reg);
485 raw_spin_unlock_irqrestore(&pcs->lock, flags);
486 }
487
488 return 0;
489 }
490
491 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
492 unsigned group)
493 {
494 struct pcs_device *pcs;
495 struct pcs_function *func;
496 int i;
497
498 pcs = pinctrl_dev_get_drvdata(pctldev);
499 /* If function mask is null, needn't disable it. */
500 if (!pcs->fmask)
501 return;
502
503 func = radix_tree_lookup(&pcs->ftree, fselector);
504 if (!func) {
505 dev_err(pcs->dev, "%s could not find function%i\n",
506 __func__, fselector);
507 return;
508 }
509
510 /*
511 * Ignore disable if function-off is not specified. Some hardware
512 * does not have clearly defined disable function. For pin specific
513 * off modes, you can use alternate named states as described in
514 * pinctrl-bindings.txt.
515 */
516 if (pcs->foff == PCS_OFF_DISABLED) {
517 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
518 func->name, fselector);
519 return;
520 }
521
522 dev_dbg(pcs->dev, "disabling function%i %s\n",
523 fselector, func->name);
524
525 for (i = 0; i < func->nvals; i++) {
526 struct pcs_func_vals *vals;
527 unsigned long flags;
528 unsigned val, mask;
529
530 vals = &func->vals[i];
531 raw_spin_lock_irqsave(&pcs->lock, flags);
532 val = pcs->read(vals->reg);
533
534 if (pcs->bits_per_mux)
535 mask = vals->mask;
536 else
537 mask = pcs->fmask;
538
539 val &= ~mask;
540 val |= pcs->foff << pcs->fshift;
541 pcs->write(val, vals->reg);
542 raw_spin_unlock_irqrestore(&pcs->lock, flags);
543 }
544 }
545
546 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
547 struct pinctrl_gpio_range *range, unsigned pin)
548 {
549 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
550 struct pcs_gpiofunc_range *frange = NULL;
551 struct list_head *pos, *tmp;
552 int mux_bytes = 0;
553 unsigned data;
554
555 /* If function mask is null, return directly. */
556 if (!pcs->fmask)
557 return -ENOTSUPP;
558
559 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
560 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
561 if (pin >= frange->offset + frange->npins
562 || pin < frange->offset)
563 continue;
564 mux_bytes = pcs->width / BITS_PER_BYTE;
565 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
566 data |= frange->gpiofunc;
567 pcs->write(data, pcs->base + pin * mux_bytes);
568 break;
569 }
570 return 0;
571 }
572
573 static const struct pinmux_ops pcs_pinmux_ops = {
574 .get_functions_count = pcs_get_functions_count,
575 .get_function_name = pcs_get_function_name,
576 .get_function_groups = pcs_get_function_groups,
577 .enable = pcs_enable,
578 .disable = pcs_disable,
579 .gpio_request_enable = pcs_request_gpio,
580 };
581
582 /* Clear BIAS value */
583 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
584 {
585 unsigned long config;
586 int i;
587 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
588 config = pinconf_to_config_packed(pcs_bias[i], 0);
589 pcs_pinconf_set(pctldev, pin, &config, 1);
590 }
591 }
592
593 /*
594 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
595 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
596 */
597 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
598 {
599 unsigned long config;
600 int i;
601
602 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
603 config = pinconf_to_config_packed(pcs_bias[i], 0);
604 if (!pcs_pinconf_get(pctldev, pin, &config))
605 goto out;
606 }
607 return true;
608 out:
609 return false;
610 }
611
612 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
613 unsigned pin, unsigned long *config)
614 {
615 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
616 struct pcs_function *func;
617 enum pin_config_param param;
618 unsigned offset = 0, data = 0, i, j, ret;
619
620 ret = pcs_get_function(pctldev, pin, &func);
621 if (ret)
622 return ret;
623
624 for (i = 0; i < func->nconfs; i++) {
625 param = pinconf_to_config_param(*config);
626 if (param == PIN_CONFIG_BIAS_DISABLE) {
627 if (pcs_pinconf_bias_disable(pctldev, pin)) {
628 *config = 0;
629 return 0;
630 } else {
631 return -ENOTSUPP;
632 }
633 } else if (param != func->conf[i].param) {
634 continue;
635 }
636
637 offset = pin * (pcs->width / BITS_PER_BYTE);
638 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
639 switch (func->conf[i].param) {
640 /* 4 parameters */
641 case PIN_CONFIG_BIAS_PULL_DOWN:
642 case PIN_CONFIG_BIAS_PULL_UP:
643 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
644 if ((data != func->conf[i].enable) ||
645 (data == func->conf[i].disable))
646 return -ENOTSUPP;
647 *config = 0;
648 break;
649 /* 2 parameters */
650 case PIN_CONFIG_INPUT_SCHMITT:
651 for (j = 0; j < func->nconfs; j++) {
652 switch (func->conf[j].param) {
653 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
654 if (data != func->conf[j].enable)
655 return -ENOTSUPP;
656 break;
657 default:
658 break;
659 }
660 }
661 *config = data;
662 break;
663 case PIN_CONFIG_DRIVE_STRENGTH:
664 case PIN_CONFIG_SLEW_RATE:
665 case PIN_CONFIG_LOW_POWER_MODE:
666 default:
667 *config = data;
668 break;
669 }
670 return 0;
671 }
672 return -ENOTSUPP;
673 }
674
675 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
676 unsigned pin, unsigned long *configs,
677 unsigned num_configs)
678 {
679 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
680 struct pcs_function *func;
681 unsigned offset = 0, shift = 0, i, data, ret;
682 u16 arg;
683 int j;
684
685 ret = pcs_get_function(pctldev, pin, &func);
686 if (ret)
687 return ret;
688
689 for (j = 0; j < num_configs; j++) {
690 for (i = 0; i < func->nconfs; i++) {
691 if (pinconf_to_config_param(configs[j])
692 != func->conf[i].param)
693 continue;
694
695 offset = pin * (pcs->width / BITS_PER_BYTE);
696 data = pcs->read(pcs->base + offset);
697 arg = pinconf_to_config_argument(configs[j]);
698 switch (func->conf[i].param) {
699 /* 2 parameters */
700 case PIN_CONFIG_INPUT_SCHMITT:
701 case PIN_CONFIG_DRIVE_STRENGTH:
702 case PIN_CONFIG_SLEW_RATE:
703 case PIN_CONFIG_LOW_POWER_MODE:
704 shift = ffs(func->conf[i].mask) - 1;
705 data &= ~func->conf[i].mask;
706 data |= (arg << shift) & func->conf[i].mask;
707 break;
708 /* 4 parameters */
709 case PIN_CONFIG_BIAS_DISABLE:
710 pcs_pinconf_clear_bias(pctldev, pin);
711 break;
712 case PIN_CONFIG_BIAS_PULL_DOWN:
713 case PIN_CONFIG_BIAS_PULL_UP:
714 if (arg)
715 pcs_pinconf_clear_bias(pctldev, pin);
716 /* fall through */
717 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
718 data &= ~func->conf[i].mask;
719 if (arg)
720 data |= func->conf[i].enable;
721 else
722 data |= func->conf[i].disable;
723 break;
724 default:
725 return -ENOTSUPP;
726 }
727 pcs->write(data, pcs->base + offset);
728
729 break;
730 }
731 if (i >= func->nconfs)
732 return -ENOTSUPP;
733 } /* for each config */
734
735 return 0;
736 }
737
738 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
739 unsigned group, unsigned long *config)
740 {
741 const unsigned *pins;
742 unsigned npins, old = 0;
743 int i, ret;
744
745 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
746 if (ret)
747 return ret;
748 for (i = 0; i < npins; i++) {
749 if (pcs_pinconf_get(pctldev, pins[i], config))
750 return -ENOTSUPP;
751 /* configs do not match between two pins */
752 if (i && (old != *config))
753 return -ENOTSUPP;
754 old = *config;
755 }
756 return 0;
757 }
758
759 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
760 unsigned group, unsigned long *configs,
761 unsigned num_configs)
762 {
763 const unsigned *pins;
764 unsigned npins;
765 int i, ret;
766
767 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
768 if (ret)
769 return ret;
770 for (i = 0; i < npins; i++) {
771 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
772 return -ENOTSUPP;
773 }
774 return 0;
775 }
776
777 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
778 struct seq_file *s, unsigned pin)
779 {
780 }
781
782 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
783 struct seq_file *s, unsigned selector)
784 {
785 }
786
787 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
788 struct seq_file *s,
789 unsigned long config)
790 {
791 pinconf_generic_dump_config(pctldev, s, config);
792 }
793
794 static const struct pinconf_ops pcs_pinconf_ops = {
795 .pin_config_get = pcs_pinconf_get,
796 .pin_config_set = pcs_pinconf_set,
797 .pin_config_group_get = pcs_pinconf_group_get,
798 .pin_config_group_set = pcs_pinconf_group_set,
799 .pin_config_dbg_show = pcs_pinconf_dbg_show,
800 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
801 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
802 .is_generic = true,
803 };
804
805 /**
806 * pcs_add_pin() - add a pin to the static per controller pin array
807 * @pcs: pcs driver instance
808 * @offset: register offset from base
809 */
810 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
811 unsigned pin_pos)
812 {
813 struct pinctrl_pin_desc *pin;
814 struct pcs_name *pn;
815 int i;
816
817 i = pcs->pins.cur;
818 if (i >= pcs->desc.npins) {
819 dev_err(pcs->dev, "too many pins, max %i\n",
820 pcs->desc.npins);
821 return -ENOMEM;
822 }
823
824 pin = &pcs->pins.pa[i];
825 pn = &pcs->names[i];
826 sprintf(pn->name, "%lx.%d",
827 (unsigned long)pcs->res->start + offset, pin_pos);
828 pin->name = pn->name;
829 pin->number = i;
830 pcs->pins.cur++;
831
832 return i;
833 }
834
835 /**
836 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
837 * @pcs: pcs driver instance
838 *
839 * In case of errors, resources are freed in pcs_free_resources.
840 *
841 * If your hardware needs holes in the address space, then just set
842 * up multiple driver instances.
843 */
844 static int pcs_allocate_pin_table(struct pcs_device *pcs)
845 {
846 int mux_bytes, nr_pins, i;
847 int num_pins_in_register = 0;
848
849 mux_bytes = pcs->width / BITS_PER_BYTE;
850
851 if (pcs->bits_per_mux) {
852 pcs->bits_per_pin = fls(pcs->fmask);
853 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
854 num_pins_in_register = pcs->width / pcs->bits_per_pin;
855 } else {
856 nr_pins = pcs->size / mux_bytes;
857 }
858
859 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
860 pcs->pins.pa = devm_kzalloc(pcs->dev,
861 sizeof(*pcs->pins.pa) * nr_pins,
862 GFP_KERNEL);
863 if (!pcs->pins.pa)
864 return -ENOMEM;
865
866 pcs->names = devm_kzalloc(pcs->dev,
867 sizeof(struct pcs_name) * nr_pins,
868 GFP_KERNEL);
869 if (!pcs->names)
870 return -ENOMEM;
871
872 pcs->desc.pins = pcs->pins.pa;
873 pcs->desc.npins = nr_pins;
874
875 for (i = 0; i < pcs->desc.npins; i++) {
876 unsigned offset;
877 int res;
878 int byte_num;
879 int pin_pos = 0;
880
881 if (pcs->bits_per_mux) {
882 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
883 offset = (byte_num / mux_bytes) * mux_bytes;
884 pin_pos = i % num_pins_in_register;
885 } else {
886 offset = i * mux_bytes;
887 }
888 res = pcs_add_pin(pcs, offset, pin_pos);
889 if (res < 0) {
890 dev_err(pcs->dev, "error adding pins: %i\n", res);
891 return res;
892 }
893 }
894
895 return 0;
896 }
897
898 /**
899 * pcs_add_function() - adds a new function to the function list
900 * @pcs: pcs driver instance
901 * @np: device node of the mux entry
902 * @name: name of the function
903 * @vals: array of mux register value pairs used by the function
904 * @nvals: number of mux register value pairs
905 * @pgnames: array of pingroup names for the function
906 * @npgnames: number of pingroup names
907 */
908 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
909 struct device_node *np,
910 const char *name,
911 struct pcs_func_vals *vals,
912 unsigned nvals,
913 const char **pgnames,
914 unsigned npgnames)
915 {
916 struct pcs_function *function;
917
918 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
919 if (!function)
920 return NULL;
921
922 function->name = name;
923 function->vals = vals;
924 function->nvals = nvals;
925 function->pgnames = pgnames;
926 function->npgnames = npgnames;
927
928 mutex_lock(&pcs->mutex);
929 list_add_tail(&function->node, &pcs->functions);
930 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
931 pcs->nfuncs++;
932 mutex_unlock(&pcs->mutex);
933
934 return function;
935 }
936
937 static void pcs_remove_function(struct pcs_device *pcs,
938 struct pcs_function *function)
939 {
940 int i;
941
942 mutex_lock(&pcs->mutex);
943 for (i = 0; i < pcs->nfuncs; i++) {
944 struct pcs_function *found;
945
946 found = radix_tree_lookup(&pcs->ftree, i);
947 if (found == function)
948 radix_tree_delete(&pcs->ftree, i);
949 }
950 list_del(&function->node);
951 mutex_unlock(&pcs->mutex);
952 }
953
954 /**
955 * pcs_add_pingroup() - add a pingroup to the pingroup list
956 * @pcs: pcs driver instance
957 * @np: device node of the mux entry
958 * @name: name of the pingroup
959 * @gpins: array of the pins that belong to the group
960 * @ngpins: number of pins in the group
961 */
962 static int pcs_add_pingroup(struct pcs_device *pcs,
963 struct device_node *np,
964 const char *name,
965 int *gpins,
966 int ngpins)
967 {
968 struct pcs_pingroup *pingroup;
969
970 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
971 if (!pingroup)
972 return -ENOMEM;
973
974 pingroup->name = name;
975 pingroup->np = np;
976 pingroup->gpins = gpins;
977 pingroup->ngpins = ngpins;
978
979 mutex_lock(&pcs->mutex);
980 list_add_tail(&pingroup->node, &pcs->pingroups);
981 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
982 pcs->ngroups++;
983 mutex_unlock(&pcs->mutex);
984
985 return 0;
986 }
987
988 /**
989 * pcs_get_pin_by_offset() - get a pin index based on the register offset
990 * @pcs: pcs driver instance
991 * @offset: register offset from the base
992 *
993 * Note that this is OK as long as the pins are in a static array.
994 */
995 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
996 {
997 unsigned index;
998
999 if (offset >= pcs->size) {
1000 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
1001 offset, pcs->size);
1002 return -EINVAL;
1003 }
1004
1005 if (pcs->bits_per_mux)
1006 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
1007 else
1008 index = offset / (pcs->width / BITS_PER_BYTE);
1009
1010 return index;
1011 }
1012
1013 /*
1014 * check whether data matches enable bits or disable bits
1015 * Return value: 1 for matching enable bits, 0 for matching disable bits,
1016 * and negative value for matching failure.
1017 */
1018 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
1019 {
1020 int ret = -EINVAL;
1021
1022 if (data == enable)
1023 ret = 1;
1024 else if (data == disable)
1025 ret = 0;
1026 return ret;
1027 }
1028
1029 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
1030 unsigned value, unsigned enable, unsigned disable,
1031 unsigned mask)
1032 {
1033 (*conf)->param = param;
1034 (*conf)->val = value;
1035 (*conf)->enable = enable;
1036 (*conf)->disable = disable;
1037 (*conf)->mask = mask;
1038 (*conf)++;
1039 }
1040
1041 static void add_setting(unsigned long **setting, enum pin_config_param param,
1042 unsigned arg)
1043 {
1044 **setting = pinconf_to_config_packed(param, arg);
1045 (*setting)++;
1046 }
1047
1048 /* add pinconf setting with 2 parameters */
1049 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1050 const char *name, enum pin_config_param param,
1051 struct pcs_conf_vals **conf, unsigned long **settings)
1052 {
1053 unsigned value[2], shift;
1054 int ret;
1055
1056 ret = of_property_read_u32_array(np, name, value, 2);
1057 if (ret)
1058 return;
1059 /* set value & mask */
1060 value[0] &= value[1];
1061 shift = ffs(value[1]) - 1;
1062 /* skip enable & disable */
1063 add_config(conf, param, value[0], 0, 0, value[1]);
1064 add_setting(settings, param, value[0] >> shift);
1065 }
1066
1067 /* add pinconf setting with 4 parameters */
1068 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1069 const char *name, enum pin_config_param param,
1070 struct pcs_conf_vals **conf, unsigned long **settings)
1071 {
1072 unsigned value[4];
1073 int ret;
1074
1075 /* value to set, enable, disable, mask */
1076 ret = of_property_read_u32_array(np, name, value, 4);
1077 if (ret)
1078 return;
1079 if (!value[3]) {
1080 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1081 return;
1082 }
1083 value[0] &= value[3];
1084 value[1] &= value[3];
1085 value[2] &= value[3];
1086 ret = pcs_config_match(value[0], value[1], value[2]);
1087 if (ret < 0)
1088 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1089 add_config(conf, param, value[0], value[1], value[2], value[3]);
1090 add_setting(settings, param, ret);
1091 }
1092
1093 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1094 struct pcs_function *func,
1095 struct pinctrl_map **map)
1096
1097 {
1098 struct pinctrl_map *m = *map;
1099 int i = 0, nconfs = 0;
1100 unsigned long *settings = NULL, *s = NULL;
1101 struct pcs_conf_vals *conf = NULL;
1102 struct pcs_conf_type prop2[] = {
1103 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1104 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1105 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1106 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
1107 };
1108 struct pcs_conf_type prop4[] = {
1109 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1110 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1111 { "pinctrl-single,input-schmitt-enable",
1112 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1113 };
1114
1115 /* If pinconf isn't supported, don't parse properties in below. */
1116 if (!PCS_HAS_PINCONF)
1117 return 0;
1118
1119 /* cacluate how much properties are supported in current node */
1120 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1121 if (of_find_property(np, prop2[i].name, NULL))
1122 nconfs++;
1123 }
1124 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1125 if (of_find_property(np, prop4[i].name, NULL))
1126 nconfs++;
1127 }
1128 if (!nconfs)
1129 return 0;
1130
1131 func->conf = devm_kzalloc(pcs->dev,
1132 sizeof(struct pcs_conf_vals) * nconfs,
1133 GFP_KERNEL);
1134 if (!func->conf)
1135 return -ENOMEM;
1136 func->nconfs = nconfs;
1137 conf = &(func->conf[0]);
1138 m++;
1139 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1140 GFP_KERNEL);
1141 if (!settings)
1142 return -ENOMEM;
1143 s = &settings[0];
1144
1145 for (i = 0; i < ARRAY_SIZE(prop2); i++)
1146 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1147 &conf, &s);
1148 for (i = 0; i < ARRAY_SIZE(prop4); i++)
1149 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1150 &conf, &s);
1151 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1152 m->data.configs.group_or_pin = np->name;
1153 m->data.configs.configs = settings;
1154 m->data.configs.num_configs = nconfs;
1155 return 0;
1156 }
1157
1158 static void pcs_free_pingroups(struct pcs_device *pcs);
1159
1160 /**
1161 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1162 * @pcs: pinctrl driver instance
1163 * @np: device node of the mux entry
1164 * @map: map entry
1165 * @num_maps: number of map
1166 * @pgnames: pingroup names
1167 *
1168 * Note that this binding currently supports only sets of one register + value.
1169 *
1170 * Also note that this driver tries to avoid understanding pin and function
1171 * names because of the extra bloat they would cause especially in the case of
1172 * a large number of pins. This driver just sets what is specified for the board
1173 * in the .dts file. Further user space debugging tools can be developed to
1174 * decipher the pin and function names using debugfs.
1175 *
1176 * If you are concerned about the boot time, set up the static pins in
1177 * the bootloader, and only set up selected pins as device tree entries.
1178 */
1179 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1180 struct device_node *np,
1181 struct pinctrl_map **map,
1182 unsigned *num_maps,
1183 const char **pgnames)
1184 {
1185 struct pcs_func_vals *vals;
1186 const __be32 *mux;
1187 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1188 struct pcs_function *function;
1189
1190 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1191 if ((!mux) || (size < sizeof(*mux) * 2)) {
1192 dev_err(pcs->dev, "bad data for mux %s\n",
1193 np->name);
1194 return -EINVAL;
1195 }
1196
1197 size /= sizeof(*mux); /* Number of elements in array */
1198 rows = size / 2;
1199
1200 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1201 if (!vals)
1202 return -ENOMEM;
1203
1204 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1205 if (!pins)
1206 goto free_vals;
1207
1208 while (index < size) {
1209 unsigned offset, val;
1210 int pin;
1211
1212 offset = be32_to_cpup(mux + index++);
1213 val = be32_to_cpup(mux + index++);
1214 vals[found].reg = pcs->base + offset;
1215 vals[found].val = val;
1216
1217 pin = pcs_get_pin_by_offset(pcs, offset);
1218 if (pin < 0) {
1219 dev_err(pcs->dev,
1220 "could not add functions for %s %ux\n",
1221 np->name, offset);
1222 break;
1223 }
1224 pins[found++] = pin;
1225 }
1226
1227 pgnames[0] = np->name;
1228 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1229 if (!function)
1230 goto free_pins;
1231
1232 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1233 if (res < 0)
1234 goto free_function;
1235
1236 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1237 (*map)->data.mux.group = np->name;
1238 (*map)->data.mux.function = np->name;
1239
1240 if (PCS_HAS_PINCONF) {
1241 res = pcs_parse_pinconf(pcs, np, function, map);
1242 if (res)
1243 goto free_pingroups;
1244 *num_maps = 2;
1245 } else {
1246 *num_maps = 1;
1247 }
1248 return 0;
1249
1250 free_pingroups:
1251 pcs_free_pingroups(pcs);
1252 *num_maps = 1;
1253 free_function:
1254 pcs_remove_function(pcs, function);
1255
1256 free_pins:
1257 devm_kfree(pcs->dev, pins);
1258
1259 free_vals:
1260 devm_kfree(pcs->dev, vals);
1261
1262 return res;
1263 }
1264
1265 #define PARAMS_FOR_BITS_PER_MUX 3
1266
1267 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1268 struct device_node *np,
1269 struct pinctrl_map **map,
1270 unsigned *num_maps,
1271 const char **pgnames)
1272 {
1273 struct pcs_func_vals *vals;
1274 const __be32 *mux;
1275 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1276 int npins_in_row;
1277 struct pcs_function *function;
1278
1279 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1280
1281 if (!mux) {
1282 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1283 return -EINVAL;
1284 }
1285
1286 if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1287 dev_err(pcs->dev, "bad data for %s\n", np->name);
1288 return -EINVAL;
1289 }
1290
1291 /* Number of elements in array */
1292 size /= sizeof(*mux);
1293
1294 rows = size / PARAMS_FOR_BITS_PER_MUX;
1295 npins_in_row = pcs->width / pcs->bits_per_pin;
1296
1297 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1298 GFP_KERNEL);
1299 if (!vals)
1300 return -ENOMEM;
1301
1302 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1303 GFP_KERNEL);
1304 if (!pins)
1305 goto free_vals;
1306
1307 while (index < size) {
1308 unsigned offset, val;
1309 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1310 unsigned pin_num_from_lsb;
1311 int pin;
1312
1313 offset = be32_to_cpup(mux + index++);
1314 val = be32_to_cpup(mux + index++);
1315 mask = be32_to_cpup(mux + index++);
1316
1317 /* Parse pins in each row from LSB */
1318 while (mask) {
1319 bit_pos = ffs(mask);
1320 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1321 mask_pos = ((pcs->fmask) << (bit_pos - 1));
1322 val_pos = val & mask_pos;
1323 submask = mask & mask_pos;
1324
1325 if ((mask & mask_pos) == 0) {
1326 dev_err(pcs->dev,
1327 "Invalid mask for %s at 0x%x\n",
1328 np->name, offset);
1329 break;
1330 }
1331
1332 mask &= ~mask_pos;
1333
1334 if (submask != mask_pos) {
1335 dev_warn(pcs->dev,
1336 "Invalid submask 0x%x for %s at 0x%x\n",
1337 submask, np->name, offset);
1338 continue;
1339 }
1340
1341 vals[found].mask = submask;
1342 vals[found].reg = pcs->base + offset;
1343 vals[found].val = val_pos;
1344
1345 pin = pcs_get_pin_by_offset(pcs, offset);
1346 if (pin < 0) {
1347 dev_err(pcs->dev,
1348 "could not add functions for %s %ux\n",
1349 np->name, offset);
1350 break;
1351 }
1352 pins[found++] = pin + pin_num_from_lsb;
1353 }
1354 }
1355
1356 pgnames[0] = np->name;
1357 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1358 if (!function)
1359 goto free_pins;
1360
1361 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1362 if (res < 0)
1363 goto free_function;
1364
1365 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1366 (*map)->data.mux.group = np->name;
1367 (*map)->data.mux.function = np->name;
1368
1369 if (PCS_HAS_PINCONF) {
1370 dev_err(pcs->dev, "pinconf not supported\n");
1371 goto free_pingroups;
1372 }
1373
1374 *num_maps = 1;
1375 return 0;
1376
1377 free_pingroups:
1378 pcs_free_pingroups(pcs);
1379 *num_maps = 1;
1380 free_function:
1381 pcs_remove_function(pcs, function);
1382
1383 free_pins:
1384 devm_kfree(pcs->dev, pins);
1385
1386 free_vals:
1387 devm_kfree(pcs->dev, vals);
1388
1389 return res;
1390 }
1391 /**
1392 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1393 * @pctldev: pinctrl instance
1394 * @np_config: device tree pinmux entry
1395 * @map: array of map entries
1396 * @num_maps: number of maps
1397 */
1398 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1399 struct device_node *np_config,
1400 struct pinctrl_map **map, unsigned *num_maps)
1401 {
1402 struct pcs_device *pcs;
1403 const char **pgnames;
1404 int ret;
1405
1406 pcs = pinctrl_dev_get_drvdata(pctldev);
1407
1408 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1409 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1410 if (!*map)
1411 return -ENOMEM;
1412
1413 *num_maps = 0;
1414
1415 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1416 if (!pgnames) {
1417 ret = -ENOMEM;
1418 goto free_map;
1419 }
1420
1421 if (pcs->bits_per_mux) {
1422 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1423 num_maps, pgnames);
1424 if (ret < 0) {
1425 dev_err(pcs->dev, "no pins entries for %s\n",
1426 np_config->name);
1427 goto free_pgnames;
1428 }
1429 } else {
1430 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1431 num_maps, pgnames);
1432 if (ret < 0) {
1433 dev_err(pcs->dev, "no pins entries for %s\n",
1434 np_config->name);
1435 goto free_pgnames;
1436 }
1437 }
1438
1439 return 0;
1440
1441 free_pgnames:
1442 devm_kfree(pcs->dev, pgnames);
1443 free_map:
1444 devm_kfree(pcs->dev, *map);
1445
1446 return ret;
1447 }
1448
1449 /**
1450 * pcs_free_funcs() - free memory used by functions
1451 * @pcs: pcs driver instance
1452 */
1453 static void pcs_free_funcs(struct pcs_device *pcs)
1454 {
1455 struct list_head *pos, *tmp;
1456 int i;
1457
1458 mutex_lock(&pcs->mutex);
1459 for (i = 0; i < pcs->nfuncs; i++) {
1460 struct pcs_function *func;
1461
1462 func = radix_tree_lookup(&pcs->ftree, i);
1463 if (!func)
1464 continue;
1465 radix_tree_delete(&pcs->ftree, i);
1466 }
1467 list_for_each_safe(pos, tmp, &pcs->functions) {
1468 struct pcs_function *function;
1469
1470 function = list_entry(pos, struct pcs_function, node);
1471 list_del(&function->node);
1472 }
1473 mutex_unlock(&pcs->mutex);
1474 }
1475
1476 /**
1477 * pcs_free_pingroups() - free memory used by pingroups
1478 * @pcs: pcs driver instance
1479 */
1480 static void pcs_free_pingroups(struct pcs_device *pcs)
1481 {
1482 struct list_head *pos, *tmp;
1483 int i;
1484
1485 mutex_lock(&pcs->mutex);
1486 for (i = 0; i < pcs->ngroups; i++) {
1487 struct pcs_pingroup *pingroup;
1488
1489 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1490 if (!pingroup)
1491 continue;
1492 radix_tree_delete(&pcs->pgtree, i);
1493 }
1494 list_for_each_safe(pos, tmp, &pcs->pingroups) {
1495 struct pcs_pingroup *pingroup;
1496
1497 pingroup = list_entry(pos, struct pcs_pingroup, node);
1498 list_del(&pingroup->node);
1499 }
1500 mutex_unlock(&pcs->mutex);
1501 }
1502
1503 /**
1504 * pcs_irq_free() - free interrupt
1505 * @pcs: pcs driver instance
1506 */
1507 static void pcs_irq_free(struct pcs_device *pcs)
1508 {
1509 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1510
1511 if (pcs_soc->irq < 0)
1512 return;
1513
1514 if (pcs->domain)
1515 irq_domain_remove(pcs->domain);
1516
1517 if (PCS_QUIRK_HAS_SHARED_IRQ)
1518 free_irq(pcs_soc->irq, pcs_soc);
1519 else
1520 irq_set_chained_handler(pcs_soc->irq, NULL);
1521 }
1522
1523 /**
1524 * pcs_free_resources() - free memory used by this driver
1525 * @pcs: pcs driver instance
1526 */
1527 static void pcs_free_resources(struct pcs_device *pcs)
1528 {
1529 pcs_irq_free(pcs);
1530
1531 if (pcs->pctl)
1532 pinctrl_unregister(pcs->pctl);
1533
1534 pcs_free_funcs(pcs);
1535 pcs_free_pingroups(pcs);
1536 }
1537
1538 #define PCS_GET_PROP_U32(name, reg, err) \
1539 do { \
1540 ret = of_property_read_u32(np, name, reg); \
1541 if (ret) { \
1542 dev_err(pcs->dev, err); \
1543 return ret; \
1544 } \
1545 } while (0);
1546
1547 static struct of_device_id pcs_of_match[];
1548
1549 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1550 {
1551 const char *propname = "pinctrl-single,gpio-range";
1552 const char *cellname = "#pinctrl-single,gpio-range-cells";
1553 struct of_phandle_args gpiospec;
1554 struct pcs_gpiofunc_range *range;
1555 int ret, i;
1556
1557 for (i = 0; ; i++) {
1558 ret = of_parse_phandle_with_args(node, propname, cellname,
1559 i, &gpiospec);
1560 /* Do not treat it as error. Only treat it as end condition. */
1561 if (ret) {
1562 ret = 0;
1563 break;
1564 }
1565 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1566 if (!range) {
1567 ret = -ENOMEM;
1568 break;
1569 }
1570 range->offset = gpiospec.args[0];
1571 range->npins = gpiospec.args[1];
1572 range->gpiofunc = gpiospec.args[2];
1573 mutex_lock(&pcs->mutex);
1574 list_add_tail(&range->node, &pcs->gpiofuncs);
1575 mutex_unlock(&pcs->mutex);
1576 }
1577 return ret;
1578 }
1579 /**
1580 * @reg: virtual address of interrupt register
1581 * @hwirq: hardware irq number
1582 * @irq: virtual irq number
1583 * @node: list node
1584 */
1585 struct pcs_interrupt {
1586 void __iomem *reg;
1587 irq_hw_number_t hwirq;
1588 unsigned int irq;
1589 struct list_head node;
1590 };
1591
1592 /**
1593 * pcs_irq_set() - enables or disables an interrupt
1594 *
1595 * Note that this currently assumes one interrupt per pinctrl
1596 * register that is typically used for wake-up events.
1597 */
1598 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1599 int irq, const bool enable)
1600 {
1601 struct pcs_device *pcs;
1602 struct list_head *pos;
1603 unsigned mask;
1604
1605 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1606 list_for_each(pos, &pcs->irqs) {
1607 struct pcs_interrupt *pcswi;
1608 unsigned soc_mask;
1609
1610 pcswi = list_entry(pos, struct pcs_interrupt, node);
1611 if (irq != pcswi->irq)
1612 continue;
1613
1614 soc_mask = pcs_soc->irq_enable_mask;
1615 raw_spin_lock(&pcs->lock);
1616 mask = pcs->read(pcswi->reg);
1617 if (enable)
1618 mask |= soc_mask;
1619 else
1620 mask &= ~soc_mask;
1621 pcs->write(mask, pcswi->reg);
1622 raw_spin_unlock(&pcs->lock);
1623 }
1624
1625 if (pcs_soc->rearm)
1626 pcs_soc->rearm();
1627 }
1628
1629 /**
1630 * pcs_irq_mask() - mask pinctrl interrupt
1631 * @d: interrupt data
1632 */
1633 static void pcs_irq_mask(struct irq_data *d)
1634 {
1635 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1636
1637 pcs_irq_set(pcs_soc, d->irq, false);
1638 }
1639
1640 /**
1641 * pcs_irq_unmask() - unmask pinctrl interrupt
1642 * @d: interrupt data
1643 */
1644 static void pcs_irq_unmask(struct irq_data *d)
1645 {
1646 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1647
1648 pcs_irq_set(pcs_soc, d->irq, true);
1649 }
1650
1651 /**
1652 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1653 * @d: interrupt data
1654 * @state: wake-up state
1655 *
1656 * Note that this should be called only for suspend and resume.
1657 * For runtime PM, the wake-up events should be enabled by default.
1658 */
1659 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1660 {
1661 if (state)
1662 pcs_irq_unmask(d);
1663 else
1664 pcs_irq_mask(d);
1665
1666 return 0;
1667 }
1668
1669 /**
1670 * pcs_irq_handle() - common interrupt handler
1671 * @pcs_irq: interrupt data
1672 *
1673 * Note that this currently assumes we have one interrupt bit per
1674 * mux register. This interrupt is typically used for wake-up events.
1675 * For more complex interrupts different handlers can be specified.
1676 */
1677 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1678 {
1679 struct pcs_device *pcs;
1680 struct list_head *pos;
1681 int count = 0;
1682
1683 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1684 list_for_each(pos, &pcs->irqs) {
1685 struct pcs_interrupt *pcswi;
1686 unsigned mask;
1687
1688 pcswi = list_entry(pos, struct pcs_interrupt, node);
1689 raw_spin_lock(&pcs->lock);
1690 mask = pcs->read(pcswi->reg);
1691 raw_spin_unlock(&pcs->lock);
1692 if (mask & pcs_soc->irq_status_mask) {
1693 generic_handle_irq(irq_find_mapping(pcs->domain,
1694 pcswi->hwirq));
1695 count++;
1696 }
1697 }
1698
1699 return count;
1700 }
1701
1702 /**
1703 * pcs_irq_handler() - handler for the shared interrupt case
1704 * @irq: interrupt
1705 * @d: data
1706 *
1707 * Use this for cases where multiple instances of
1708 * pinctrl-single share a single interrupt like on omaps.
1709 */
1710 static irqreturn_t pcs_irq_handler(int irq, void *d)
1711 {
1712 struct pcs_soc_data *pcs_soc = d;
1713
1714 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1715 }
1716
1717 /**
1718 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1719 * @irq: interrupt
1720 * @desc: interrupt descriptor
1721 *
1722 * Use this if you have a separate interrupt for each
1723 * pinctrl-single instance.
1724 */
1725 static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1726 {
1727 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1728 struct irq_chip *chip;
1729 int res;
1730
1731 chip = irq_get_chip(irq);
1732 chained_irq_enter(chip, desc);
1733 res = pcs_irq_handle(pcs_soc);
1734 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1735 chained_irq_exit(chip, desc);
1736
1737 return;
1738 }
1739
1740 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1741 irq_hw_number_t hwirq)
1742 {
1743 struct pcs_soc_data *pcs_soc = d->host_data;
1744 struct pcs_device *pcs;
1745 struct pcs_interrupt *pcswi;
1746
1747 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1748 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1749 if (!pcswi)
1750 return -ENOMEM;
1751
1752 pcswi->reg = pcs->base + hwirq;
1753 pcswi->hwirq = hwirq;
1754 pcswi->irq = irq;
1755
1756 mutex_lock(&pcs->mutex);
1757 list_add_tail(&pcswi->node, &pcs->irqs);
1758 mutex_unlock(&pcs->mutex);
1759
1760 irq_set_chip_data(irq, pcs_soc);
1761 irq_set_chip_and_handler(irq, &pcs->chip,
1762 handle_level_irq);
1763
1764 #ifdef CONFIG_ARM
1765 set_irq_flags(irq, IRQF_VALID);
1766 #else
1767 irq_set_noprobe(irq);
1768 #endif
1769
1770 return 0;
1771 }
1772
1773 static struct irq_domain_ops pcs_irqdomain_ops = {
1774 .map = pcs_irqdomain_map,
1775 .xlate = irq_domain_xlate_onecell,
1776 };
1777
1778 /**
1779 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1780 * @pcs: pcs driver instance
1781 * @np: device node pointer
1782 */
1783 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1784 struct device_node *np)
1785 {
1786 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1787 const char *name = "pinctrl";
1788 int num_irqs;
1789
1790 if (!pcs_soc->irq_enable_mask ||
1791 !pcs_soc->irq_status_mask) {
1792 pcs_soc->irq = -1;
1793 return -EINVAL;
1794 }
1795
1796 INIT_LIST_HEAD(&pcs->irqs);
1797 pcs->chip.name = name;
1798 pcs->chip.irq_ack = pcs_irq_mask;
1799 pcs->chip.irq_mask = pcs_irq_mask;
1800 pcs->chip.irq_unmask = pcs_irq_unmask;
1801 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1802
1803 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1804 int res;
1805
1806 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1807 IRQF_SHARED | IRQF_NO_SUSPEND,
1808 name, pcs_soc);
1809 if (res) {
1810 pcs_soc->irq = -1;
1811 return res;
1812 }
1813 } else {
1814 irq_set_handler_data(pcs_soc->irq, pcs_soc);
1815 irq_set_chained_handler(pcs_soc->irq,
1816 pcs_irq_chain_handler);
1817 }
1818
1819 /*
1820 * We can use the register offset as the hardirq
1821 * number as irq_domain_add_simple maps them lazily.
1822 * This way we can easily support more than one
1823 * interrupt per function if needed.
1824 */
1825 num_irqs = pcs->size;
1826
1827 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1828 &pcs_irqdomain_ops,
1829 pcs_soc);
1830 if (!pcs->domain) {
1831 irq_set_chained_handler(pcs_soc->irq, NULL);
1832 return -EINVAL;
1833 }
1834
1835 return 0;
1836 }
1837
1838 #ifdef CONFIG_PM
1839 static int pinctrl_single_suspend(struct platform_device *pdev,
1840 pm_message_t state)
1841 {
1842 struct pcs_device *pcs;
1843
1844 pcs = platform_get_drvdata(pdev);
1845 if (!pcs)
1846 return -EINVAL;
1847
1848 return pinctrl_force_sleep(pcs->pctl);
1849 }
1850
1851 static int pinctrl_single_resume(struct platform_device *pdev)
1852 {
1853 struct pcs_device *pcs;
1854
1855 pcs = platform_get_drvdata(pdev);
1856 if (!pcs)
1857 return -EINVAL;
1858
1859 return pinctrl_force_default(pcs->pctl);
1860 }
1861 #endif
1862
1863 static int pcs_probe(struct platform_device *pdev)
1864 {
1865 struct device_node *np = pdev->dev.of_node;
1866 const struct of_device_id *match;
1867 struct pcs_pdata *pdata;
1868 struct resource *res;
1869 struct pcs_device *pcs;
1870 const struct pcs_soc_data *soc;
1871 int ret;
1872
1873 match = of_match_device(pcs_of_match, &pdev->dev);
1874 if (!match)
1875 return -EINVAL;
1876
1877 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1878 if (!pcs) {
1879 dev_err(&pdev->dev, "could not allocate\n");
1880 return -ENOMEM;
1881 }
1882 pcs->dev = &pdev->dev;
1883 raw_spin_lock_init(&pcs->lock);
1884 mutex_init(&pcs->mutex);
1885 INIT_LIST_HEAD(&pcs->pingroups);
1886 INIT_LIST_HEAD(&pcs->functions);
1887 INIT_LIST_HEAD(&pcs->gpiofuncs);
1888 soc = match->data;
1889 pcs->flags = soc->flags;
1890 memcpy(&pcs->socdata, soc, sizeof(*soc));
1891
1892 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1893 "register width not specified\n");
1894
1895 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1896 &pcs->fmask);
1897 if (!ret) {
1898 pcs->fshift = ffs(pcs->fmask) - 1;
1899 pcs->fmax = pcs->fmask >> pcs->fshift;
1900 } else {
1901 /* If mask property doesn't exist, function mux is invalid. */
1902 pcs->fmask = 0;
1903 pcs->fshift = 0;
1904 pcs->fmax = 0;
1905 }
1906
1907 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1908 &pcs->foff);
1909 if (ret)
1910 pcs->foff = PCS_OFF_DISABLED;
1911
1912 pcs->bits_per_mux = of_property_read_bool(np,
1913 "pinctrl-single,bit-per-mux");
1914
1915 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1916 if (!res) {
1917 dev_err(pcs->dev, "could not get resource\n");
1918 return -ENODEV;
1919 }
1920
1921 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1922 resource_size(res), DRIVER_NAME);
1923 if (!pcs->res) {
1924 dev_err(pcs->dev, "could not get mem_region\n");
1925 return -EBUSY;
1926 }
1927
1928 pcs->size = resource_size(pcs->res);
1929 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1930 if (!pcs->base) {
1931 dev_err(pcs->dev, "could not ioremap\n");
1932 return -ENODEV;
1933 }
1934
1935 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1936 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1937 platform_set_drvdata(pdev, pcs);
1938
1939 switch (pcs->width) {
1940 case 8:
1941 pcs->read = pcs_readb;
1942 pcs->write = pcs_writeb;
1943 break;
1944 case 16:
1945 pcs->read = pcs_readw;
1946 pcs->write = pcs_writew;
1947 break;
1948 case 32:
1949 pcs->read = pcs_readl;
1950 pcs->write = pcs_writel;
1951 break;
1952 default:
1953 break;
1954 }
1955
1956 pcs->desc.name = DRIVER_NAME;
1957 pcs->desc.pctlops = &pcs_pinctrl_ops;
1958 pcs->desc.pmxops = &pcs_pinmux_ops;
1959 if (PCS_HAS_PINCONF)
1960 pcs->desc.confops = &pcs_pinconf_ops;
1961 pcs->desc.owner = THIS_MODULE;
1962
1963 ret = pcs_allocate_pin_table(pcs);
1964 if (ret < 0)
1965 goto free;
1966
1967 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1968 if (!pcs->pctl) {
1969 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1970 ret = -EINVAL;
1971 goto free;
1972 }
1973
1974 ret = pcs_add_gpio_func(np, pcs);
1975 if (ret < 0)
1976 goto free;
1977
1978 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1979 if (pcs->socdata.irq)
1980 pcs->flags |= PCS_FEAT_IRQ;
1981
1982 /* We still need auxdata for some omaps for PRM interrupts */
1983 pdata = dev_get_platdata(&pdev->dev);
1984 if (pdata) {
1985 if (pdata->rearm)
1986 pcs->socdata.rearm = pdata->rearm;
1987 if (pdata->irq) {
1988 pcs->socdata.irq = pdata->irq;
1989 pcs->flags |= PCS_FEAT_IRQ;
1990 }
1991 }
1992
1993 if (PCS_HAS_IRQ) {
1994 ret = pcs_irq_init_chained_handler(pcs, np);
1995 if (ret < 0)
1996 dev_warn(pcs->dev, "initialized with no interrupts\n");
1997 }
1998
1999 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
2000 pcs->desc.npins, pcs->base, pcs->size);
2001
2002 return 0;
2003
2004 free:
2005 pcs_free_resources(pcs);
2006
2007 return ret;
2008 }
2009
2010 static int pcs_remove(struct platform_device *pdev)
2011 {
2012 struct pcs_device *pcs = platform_get_drvdata(pdev);
2013
2014 if (!pcs)
2015 return 0;
2016
2017 pcs_free_resources(pcs);
2018
2019 return 0;
2020 }
2021
2022 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
2023 .flags = PCS_QUIRK_SHARED_IRQ,
2024 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
2025 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
2026 };
2027
2028 static const struct pcs_soc_data pinctrl_single = {
2029 };
2030
2031 static const struct pcs_soc_data pinconf_single = {
2032 .flags = PCS_FEAT_PINCONF,
2033 };
2034
2035 static struct of_device_id pcs_of_match[] = {
2036 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2037 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2038 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2039 { .compatible = "pinctrl-single", .data = &pinctrl_single },
2040 { .compatible = "pinconf-single", .data = &pinconf_single },
2041 { },
2042 };
2043 MODULE_DEVICE_TABLE(of, pcs_of_match);
2044
2045 static struct platform_driver pcs_driver = {
2046 .probe = pcs_probe,
2047 .remove = pcs_remove,
2048 .driver = {
2049 .owner = THIS_MODULE,
2050 .name = DRIVER_NAME,
2051 .of_match_table = pcs_of_match,
2052 },
2053 #ifdef CONFIG_PM
2054 .suspend = pinctrl_single_suspend,
2055 .resume = pinctrl_single_resume,
2056 #endif
2057 };
2058
2059 module_platform_driver(pcs_driver);
2060
2061 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2062 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2063 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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