drivers/pinctrl/qcom/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pinctrl/machine.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/slab.h>
  26 #include <linux/gpio.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/spinlock.h>
  29
  30 #include "../core.h"
  31 #include "../pinconf.h"
  32 #include "pinctrl-msm.h"
  33 #include "../pinctrl-utils.h"
  34
  35 #define MAX_NR_GPIO 300
  36
  37 /**
  38  * struct msm_pinctrl - state for a pinctrl-msm device
  39  * @dev:            device handle.
  40  * @pctrl:          pinctrl handle.
  41  * @chip:           gpiochip handle.
  42  * @irq:            parent irq for the TLMM irq_chip.
  43  * @lock:           Spinlock to protect register resources as well
  44  *                  as msm_pinctrl data structures.
  45  * @enabled_irqs:   Bitmap of currently enabled irqs.
  46  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  47  *                  detection.
  48  * @soc;            Reference to soc_data of platform specific data.
  49  * @regs:           Base address for the TLMM register map.
  50  */
  51 struct msm_pinctrl {
  52         struct device *dev;
  53         struct pinctrl_dev *pctrl;
  54         struct gpio_chip chip;
  55         int irq;
  56
  57         spinlock_t lock;
  58
  59         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  60         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  61
  62         const struct msm_pinctrl_soc_data *soc;
  63         void __iomem *regs;
  64 };
  65
  66 static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
  67 {
  68         return container_of(gc, struct msm_pinctrl, chip);
  69 }
  70
  71 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  72 {
  73         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  74
  75         return pctrl->soc->ngroups;
  76 }
  77
  78 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  79                                       unsigned group)
  80 {
  81         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  82
  83         return pctrl->soc->groups[group].name;
  84 }
  85
  86 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  87                               unsigned group,
  88                               const unsigned **pins,
  89                               unsigned *num_pins)
  90 {
  91         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  92
  93         *pins = pctrl->soc->groups[group].pins;
  94         *num_pins = pctrl->soc->groups[group].npins;
  95         return 0;
  96 }
  97
  98 static const struct pinctrl_ops msm_pinctrl_ops = {
  99         .get_groups_count       = msm_get_groups_count,
 100         .get_group_name         = msm_get_group_name,
 101         .get_group_pins         = msm_get_group_pins,
 102         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 103         .dt_free_map            = pinctrl_utils_dt_free_map,
 104 };
 105
 106 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 107 {
 108         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 109
 110         return pctrl->soc->nfunctions;
 111 }
 112
 113 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 114                                          unsigned function)
 115 {
 116         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 117
 118         return pctrl->soc->functions[function].name;
 119 }
 120
 121 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 122                                    unsigned function,
 123                                    const char * const **groups,
 124                                    unsigned * const num_groups)
 125 {
 126         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 127
 128         *groups = pctrl->soc->functions[function].groups;
 129         *num_groups = pctrl->soc->functions[function].ngroups;
 130         return 0;
 131 }
 132
 133 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
 134                              unsigned function,
 135                              unsigned group)
 136 {
 137         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 138         const struct msm_pingroup *g;
 139         unsigned long flags;
 140         u32 val;
 141         int i;
 142
 143         g = &pctrl->soc->groups[group];
 144
 145         if (WARN_ON(g->mux_bit < 0))
 146                 return -EINVAL;
 147
 148         for (i = 0; i < g->nfuncs; i++) {
 149                 if (g->funcs[i] == function)
 150                         break;
 151         }
 152
 153         if (WARN_ON(i == g->nfuncs))
 154                 return -EINVAL;
 155
 156         spin_lock_irqsave(&pctrl->lock, flags);
 157
 158         val = readl(pctrl->regs + g->ctl_reg);
 159         val &= ~(0x7 << g->mux_bit);
 160         val |= i << g->mux_bit;
 161         writel(val, pctrl->regs + g->ctl_reg);
 162
 163         spin_unlock_irqrestore(&pctrl->lock, flags);
 164
 165         return 0;
 166 }
 167
 168 static const struct pinmux_ops msm_pinmux_ops = {
 169         .get_functions_count    = msm_get_functions_count,
 170         .get_function_name      = msm_get_function_name,
 171         .get_function_groups    = msm_get_function_groups,
 172         .enable                 = msm_pinmux_enable,
 173 };
 174
 175 static int msm_config_reg(struct msm_pinctrl *pctrl,
 176                           const struct msm_pingroup *g,
 177                           unsigned param,
 178                           unsigned *mask,
 179                           unsigned *bit)
 180 {
 181         switch (param) {
 182         case PIN_CONFIG_BIAS_DISABLE:
 183         case PIN_CONFIG_BIAS_PULL_DOWN:
 184         case PIN_CONFIG_BIAS_BUS_HOLD:
 185         case PIN_CONFIG_BIAS_PULL_UP:
 186                 *bit = g->pull_bit;
 187                 *mask = 3;
 188                 break;
 189         case PIN_CONFIG_DRIVE_STRENGTH:
 190                 *bit = g->drv_bit;
 191                 *mask = 7;
 192                 break;
 193         case PIN_CONFIG_OUTPUT:
 194                 *bit = g->oe_bit;
 195                 *mask = 1;
 196                 break;
 197         default:
 198                 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
 199                 return -ENOTSUPP;
 200         }
 201
 202         return 0;
 203 }
 204
 205 static int msm_config_get(struct pinctrl_dev *pctldev,
 206                           unsigned int pin,
 207                           unsigned long *config)
 208 {
 209         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 210         return -ENOTSUPP;
 211 }
 212
 213 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 214                                 unsigned long *configs, unsigned num_configs)
 215 {
 216         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 217         return -ENOTSUPP;
 218 }
 219
 220 #define MSM_NO_PULL     0
 221 #define MSM_PULL_DOWN   1
 222 #define MSM_KEEPER      2
 223 #define MSM_PULL_UP     3
 224
 225 static unsigned msm_regval_to_drive(u32 val)
 226 {
 227         return (val + 1) * 2;
 228 }
 229
 230 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 231                                 unsigned int group,
 232                                 unsigned long *config)
 233 {
 234         const struct msm_pingroup *g;
 235         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 236         unsigned param = pinconf_to_config_param(*config);
 237         unsigned mask;
 238         unsigned arg;
 239         unsigned bit;
 240         int ret;
 241         u32 val;
 242
 243         g = &pctrl->soc->groups[group];
 244
 245         ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 246         if (ret < 0)
 247                 return ret;
 248
 249         val = readl(pctrl->regs + g->ctl_reg);
 250         arg = (val >> bit) & mask;
 251
 252         /* Convert register value to pinconf value */
 253         switch (param) {
 254         case PIN_CONFIG_BIAS_DISABLE:
 255                 arg = arg == MSM_NO_PULL;
 256                 break;
 257         case PIN_CONFIG_BIAS_PULL_DOWN:
 258                 arg = arg == MSM_PULL_DOWN;
 259                 break;
 260         case PIN_CONFIG_BIAS_BUS_HOLD:
 261                 arg = arg == MSM_KEEPER;
 262                 break;
 263         case PIN_CONFIG_BIAS_PULL_UP:
 264                 arg = arg == MSM_PULL_UP;
 265                 break;
 266         case PIN_CONFIG_DRIVE_STRENGTH:
 267                 arg = msm_regval_to_drive(arg);
 268                 break;
 269         case PIN_CONFIG_OUTPUT:
 270                 /* Pin is not output */
 271                 if (!arg)
 272                         return -EINVAL;
 273
 274                 val = readl(pctrl->regs + g->io_reg);
 275                 arg = !!(val & BIT(g->in_bit));
 276                 break;
 277         default:
 278                 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 279                         param);
 280                 return -EINVAL;
 281         }
 282
 283         *config = pinconf_to_config_packed(param, arg);
 284
 285         return 0;
 286 }
 287
 288 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 289                                 unsigned group,
 290                                 unsigned long *configs,
 291                                 unsigned num_configs)
 292 {
 293         const struct msm_pingroup *g;
 294         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 295         unsigned long flags;
 296         unsigned param;
 297         unsigned mask;
 298         unsigned arg;
 299         unsigned bit;
 300         int ret;
 301         u32 val;
 302         int i;
 303
 304         g = &pctrl->soc->groups[group];
 305
 306         for (i = 0; i < num_configs; i++) {
 307                 param = pinconf_to_config_param(configs[i]);
 308                 arg = pinconf_to_config_argument(configs[i]);
 309
 310                 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 311                 if (ret < 0)
 312                         return ret;
 313
 314                 /* Convert pinconf values to register values */
 315                 switch (param) {
 316                 case PIN_CONFIG_BIAS_DISABLE:
 317                         arg = MSM_NO_PULL;
 318                         break;
 319                 case PIN_CONFIG_BIAS_PULL_DOWN:
 320                         arg = MSM_PULL_DOWN;
 321                         break;
 322                 case PIN_CONFIG_BIAS_BUS_HOLD:
 323                         arg = MSM_KEEPER;
 324                         break;
 325                 case PIN_CONFIG_BIAS_PULL_UP:
 326                         arg = MSM_PULL_UP;
 327                         break;
 328                 case PIN_CONFIG_DRIVE_STRENGTH:
 329                         /* Check for invalid values */
 330                         if (arg > 16 || arg < 2 || (arg % 2) != 0)
 331                                 arg = -1;
 332                         else
 333                                 arg = (arg / 2) - 1;
 334                         break;
 335                 case PIN_CONFIG_OUTPUT:
 336                         /* set output value */
 337                         spin_lock_irqsave(&pctrl->lock, flags);
 338                         val = readl(pctrl->regs + g->io_reg);
 339                         if (arg)
 340                                 val |= BIT(g->out_bit);
 341                         else
 342                                 val &= ~BIT(g->out_bit);
 343                         writel(val, pctrl->regs + g->io_reg);
 344                         spin_unlock_irqrestore(&pctrl->lock, flags);
 345
 346                         /* enable output */
 347                         arg = 1;
 348                         break;
 349                 default:
 350                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 351                                 param);
 352                         return -EINVAL;
 353                 }
 354
 355                 /* Range-check user-supplied value */
 356                 if (arg & ~mask) {
 357                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 358                         return -EINVAL;
 359                 }
 360
 361                 spin_lock_irqsave(&pctrl->lock, flags);
 362                 val = readl(pctrl->regs + g->ctl_reg);
 363                 val &= ~(mask << bit);
 364                 val |= arg << bit;
 365                 writel(val, pctrl->regs + g->ctl_reg);
 366                 spin_unlock_irqrestore(&pctrl->lock, flags);
 367         }
 368
 369         return 0;
 370 }
 371
 372 static const struct pinconf_ops msm_pinconf_ops = {
 373         .pin_config_get         = msm_config_get,
 374         .pin_config_set         = msm_config_set,
 375         .pin_config_group_get   = msm_config_group_get,
 376         .pin_config_group_set   = msm_config_group_set,
 377 };
 378
 379 static struct pinctrl_desc msm_pinctrl_desc = {
 380         .pctlops = &msm_pinctrl_ops,
 381         .pmxops = &msm_pinmux_ops,
 382         .confops = &msm_pinconf_ops,
 383         .owner = THIS_MODULE,
 384 };
 385
 386 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 387 {
 388         const struct msm_pingroup *g;
 389         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 390         unsigned long flags;
 391         u32 val;
 392
 393         g = &pctrl->soc->groups[offset];
 394
 395         spin_lock_irqsave(&pctrl->lock, flags);
 396
 397         val = readl(pctrl->regs + g->ctl_reg);
 398         val &= ~BIT(g->oe_bit);
 399         writel(val, pctrl->regs + g->ctl_reg);
 400
 401         spin_unlock_irqrestore(&pctrl->lock, flags);
 402
 403         return 0;
 404 }
 405
 406 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 407 {
 408         const struct msm_pingroup *g;
 409         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 410         unsigned long flags;
 411         u32 val;
 412
 413         g = &pctrl->soc->groups[offset];
 414
 415         spin_lock_irqsave(&pctrl->lock, flags);
 416
 417         val = readl(pctrl->regs + g->io_reg);
 418         if (value)
 419                 val |= BIT(g->out_bit);
 420         else
 421                 val &= ~BIT(g->out_bit);
 422         writel(val, pctrl->regs + g->io_reg);
 423
 424         val = readl(pctrl->regs + g->ctl_reg);
 425         val |= BIT(g->oe_bit);
 426         writel(val, pctrl->regs + g->ctl_reg);
 427
 428         spin_unlock_irqrestore(&pctrl->lock, flags);
 429
 430         return 0;
 431 }
 432
 433 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 434 {
 435         const struct msm_pingroup *g;
 436         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 437         u32 val;
 438
 439         g = &pctrl->soc->groups[offset];
 440
 441         val = readl(pctrl->regs + g->io_reg);
 442         return !!(val & BIT(g->in_bit));
 443 }
 444
 445 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 446 {
 447         const struct msm_pingroup *g;
 448         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 449         unsigned long flags;
 450         u32 val;
 451
 452         g = &pctrl->soc->groups[offset];
 453
 454         spin_lock_irqsave(&pctrl->lock, flags);
 455
 456         val = readl(pctrl->regs + g->io_reg);
 457         if (value)
 458                 val |= BIT(g->out_bit);
 459         else
 460                 val &= ~BIT(g->out_bit);
 461         writel(val, pctrl->regs + g->io_reg);
 462
 463         spin_unlock_irqrestore(&pctrl->lock, flags);
 464 }
 465
 466 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
 467 {
 468         int gpio = chip->base + offset;
 469         return pinctrl_request_gpio(gpio);
 470 }
 471
 472 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 473 {
 474         int gpio = chip->base + offset;
 475         return pinctrl_free_gpio(gpio);
 476 }
 477
 478 #ifdef CONFIG_DEBUG_FS
 479 #include <linux/seq_file.h>
 480
 481 static void msm_gpio_dbg_show_one(struct seq_file *s,
 482                                   struct pinctrl_dev *pctldev,
 483                                   struct gpio_chip *chip,
 484                                   unsigned offset,
 485                                   unsigned gpio)
 486 {
 487         const struct msm_pingroup *g;
 488         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 489         unsigned func;
 490         int is_out;
 491         int drive;
 492         int pull;
 493         u32 ctl_reg;
 494
 495         static const char * const pulls[] = {
 496                 "no pull",
 497                 "pull down",
 498                 "keeper",
 499                 "pull up"
 500         };
 501
 502         g = &pctrl->soc->groups[offset];
 503         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 504
 505         is_out = !!(ctl_reg & BIT(g->oe_bit));
 506         func = (ctl_reg >> g->mux_bit) & 7;
 507         drive = (ctl_reg >> g->drv_bit) & 7;
 508         pull = (ctl_reg >> g->pull_bit) & 3;
 509
 510         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 511         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 512         seq_printf(s, " %s", pulls[pull]);
 513 }
 514
 515 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 516 {
 517         unsigned gpio = chip->base;
 518         unsigned i;
 519
 520         for (i = 0; i < chip->ngpio; i++, gpio++) {
 521                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 522                 seq_puts(s, "\n");
 523         }
 524 }
 525
 526 #else
 527 #define msm_gpio_dbg_show NULL
 528 #endif
 529
 530 static struct gpio_chip msm_gpio_template = {
 531         .direction_input  = msm_gpio_direction_input,
 532         .direction_output = msm_gpio_direction_output,
 533         .get              = msm_gpio_get,
 534         .set              = msm_gpio_set,
 535         .request          = msm_gpio_request,
 536         .free             = msm_gpio_free,
 537         .dbg_show         = msm_gpio_dbg_show,
 538 };
 539
 540 /* For dual-edge interrupts in software, since some hardware has no
 541  * such support:
 542  *
 543  * At appropriate moments, this function may be called to flip the polarity
 544  * settings of both-edge irq lines to try and catch the next edge.
 545  *
 546  * The attempt is considered successful if:
 547  * - the status bit goes high, indicating that an edge was caught, or
 548  * - the input value of the gpio doesn't change during the attempt.
 549  * If the value changes twice during the process, that would cause the first
 550  * test to fail but would force the second, as two opposite
 551  * transitions would cause a detection no matter the polarity setting.
 552  *
 553  * The do-loop tries to sledge-hammer closed the timing hole between
 554  * the initial value-read and the polarity-write - if the line value changes
 555  * during that window, an interrupt is lost, the new polarity setting is
 556  * incorrect, and the first success test will fail, causing a retry.
 557  *
 558  * Algorithm comes from Google's msmgpio driver.
 559  */
 560 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 561                                           const struct msm_pingroup *g,
 562                                           struct irq_data *d)
 563 {
 564         int loop_limit = 100;
 565         unsigned val, val2, intstat;
 566         unsigned pol;
 567
 568         do {
 569                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 570
 571                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 572                 pol ^= BIT(g->intr_polarity_bit);
 573                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 574
 575                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 576                 intstat = readl(pctrl->regs + g->intr_status_reg);
 577                 if (intstat || (val == val2))
 578                         return;
 579         } while (loop_limit-- > 0);
 580         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 581                 val, val2);
 582 }
 583
 584 static void msm_gpio_irq_mask(struct irq_data *d)
 585 {
 586         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 587         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 588         const struct msm_pingroup *g;
 589         unsigned long flags;
 590         u32 val;
 591
 592         g = &pctrl->soc->groups[d->hwirq];
 593
 594         spin_lock_irqsave(&pctrl->lock, flags);
 595
 596         val = readl(pctrl->regs + g->intr_cfg_reg);
 597         val &= ~BIT(g->intr_enable_bit);
 598         writel(val, pctrl->regs + g->intr_cfg_reg);
 599
 600         clear_bit(d->hwirq, pctrl->enabled_irqs);
 601
 602         spin_unlock_irqrestore(&pctrl->lock, flags);
 603 }
 604
 605 static void msm_gpio_irq_unmask(struct irq_data *d)
 606 {
 607         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 608         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 609         const struct msm_pingroup *g;
 610         unsigned long flags;
 611         u32 val;
 612
 613         g = &pctrl->soc->groups[d->hwirq];
 614
 615         spin_lock_irqsave(&pctrl->lock, flags);
 616
 617         val = readl(pctrl->regs + g->intr_status_reg);
 618         val &= ~BIT(g->intr_status_bit);
 619         writel(val, pctrl->regs + g->intr_status_reg);
 620
 621         val = readl(pctrl->regs + g->intr_cfg_reg);
 622         val |= BIT(g->intr_enable_bit);
 623         writel(val, pctrl->regs + g->intr_cfg_reg);
 624
 625         set_bit(d->hwirq, pctrl->enabled_irqs);
 626
 627         spin_unlock_irqrestore(&pctrl->lock, flags);
 628 }
 629
 630 static void msm_gpio_irq_ack(struct irq_data *d)
 631 {
 632         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 633         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 634         const struct msm_pingroup *g;
 635         unsigned long flags;
 636         u32 val;
 637
 638         g = &pctrl->soc->groups[d->hwirq];
 639
 640         spin_lock_irqsave(&pctrl->lock, flags);
 641
 642         val = readl(pctrl->regs + g->intr_status_reg);
 643         if (g->intr_ack_high)
 644                 val |= BIT(g->intr_status_bit);
 645         else
 646                 val &= ~BIT(g->intr_status_bit);
 647         writel(val, pctrl->regs + g->intr_status_reg);
 648
 649         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 650                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 651
 652         spin_unlock_irqrestore(&pctrl->lock, flags);
 653 }
 654
 655 #define INTR_TARGET_PROC_APPS    4
 656
 657 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 658 {
 659         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 660         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 661         const struct msm_pingroup *g;
 662         unsigned long flags;
 663         u32 val;
 664
 665         g = &pctrl->soc->groups[d->hwirq];
 666
 667         spin_lock_irqsave(&pctrl->lock, flags);
 668
 669         /*
 670          * For hw without possibility of detecting both edges
 671          */
 672         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 673                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 674         else
 675                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 676
 677         /* Route interrupts to application cpu */
 678         val = readl(pctrl->regs + g->intr_target_reg);
 679         val &= ~(7 << g->intr_target_bit);
 680         val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
 681         writel(val, pctrl->regs + g->intr_target_reg);
 682
 683         /* Update configuration for gpio.
 684          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 685          * internal circuitry of TLMM, toggling the RAW_STATUS
 686          * could cause the INTR_STATUS to be set for EDGE interrupts.
 687          */
 688         val = readl(pctrl->regs + g->intr_cfg_reg);
 689         val |= BIT(g->intr_raw_status_bit);
 690         if (g->intr_detection_width == 2) {
 691                 val &= ~(3 << g->intr_detection_bit);
 692                 val &= ~(1 << g->intr_polarity_bit);
 693                 switch (type) {
 694                 case IRQ_TYPE_EDGE_RISING:
 695                         val |= 1 << g->intr_detection_bit;
 696                         val |= BIT(g->intr_polarity_bit);
 697                         break;
 698                 case IRQ_TYPE_EDGE_FALLING:
 699                         val |= 2 << g->intr_detection_bit;
 700                         val |= BIT(g->intr_polarity_bit);
 701                         break;
 702                 case IRQ_TYPE_EDGE_BOTH:
 703                         val |= 3 << g->intr_detection_bit;
 704                         val |= BIT(g->intr_polarity_bit);
 705                         break;
 706                 case IRQ_TYPE_LEVEL_LOW:
 707                         break;
 708                 case IRQ_TYPE_LEVEL_HIGH:
 709                         val |= BIT(g->intr_polarity_bit);
 710                         break;
 711                 }
 712         } else if (g->intr_detection_width == 1) {
 713                 val &= ~(1 << g->intr_detection_bit);
 714                 val &= ~(1 << g->intr_polarity_bit);
 715                 switch (type) {
 716                 case IRQ_TYPE_EDGE_RISING:
 717                         val |= BIT(g->intr_detection_bit);
 718                         val |= BIT(g->intr_polarity_bit);
 719                         break;
 720                 case IRQ_TYPE_EDGE_FALLING:
 721                         val |= BIT(g->intr_detection_bit);
 722                         break;
 723                 case IRQ_TYPE_EDGE_BOTH:
 724                         val |= BIT(g->intr_detection_bit);
 725                         val |= BIT(g->intr_polarity_bit);
 726                         break;
 727                 case IRQ_TYPE_LEVEL_LOW:
 728                         break;
 729                 case IRQ_TYPE_LEVEL_HIGH:
 730                         val |= BIT(g->intr_polarity_bit);
 731                         break;
 732                 }
 733         } else {
 734                 BUG();
 735         }
 736         writel(val, pctrl->regs + g->intr_cfg_reg);
 737
 738         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 739                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 740
 741         spin_unlock_irqrestore(&pctrl->lock, flags);
 742
 743         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 744                 __irq_set_handler_locked(d->irq, handle_level_irq);
 745         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 746                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 747
 748         return 0;
 749 }
 750
 751 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 752 {
 753         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 754         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 755         unsigned long flags;
 756
 757         spin_lock_irqsave(&pctrl->lock, flags);
 758
 759         irq_set_irq_wake(pctrl->irq, on);
 760
 761         spin_unlock_irqrestore(&pctrl->lock, flags);
 762
 763         return 0;
 764 }
 765
 766 static struct irq_chip msm_gpio_irq_chip = {
 767         .name           = "msmgpio",
 768         .irq_mask       = msm_gpio_irq_mask,
 769         .irq_unmask     = msm_gpio_irq_unmask,
 770         .irq_ack        = msm_gpio_irq_ack,
 771         .irq_set_type   = msm_gpio_irq_set_type,
 772         .irq_set_wake   = msm_gpio_irq_set_wake,
 773 };
 774
 775 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 776 {
 777         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 778         const struct msm_pingroup *g;
 779         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 780         struct irq_chip *chip = irq_get_chip(irq);
 781         int irq_pin;
 782         int handled = 0;
 783         u32 val;
 784         int i;
 785
 786         chained_irq_enter(chip, desc);
 787
 788         /*
 789          * Each pin has it's own IRQ status register, so use
 790          * enabled_irq bitmap to limit the number of reads.
 791          */
 792         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 793                 g = &pctrl->soc->groups[i];
 794                 val = readl(pctrl->regs + g->intr_status_reg);
 795                 if (val & BIT(g->intr_status_bit)) {
 796                         irq_pin = irq_find_mapping(gc->irqdomain, i);
 797                         generic_handle_irq(irq_pin);
 798                         handled++;
 799                 }
 800         }
 801
 802         /* No interrupts were flagged */
 803         if (handled == 0)
 804                 handle_bad_irq(irq, desc);
 805
 806         chained_irq_exit(chip, desc);
 807 }
 808
 809 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 810 {
 811         struct gpio_chip *chip;
 812         int ret;
 813         unsigned ngpio = pctrl->soc->ngpios;
 814
 815         if (WARN_ON(ngpio > MAX_NR_GPIO))
 816                 return -EINVAL;
 817
 818         chip = &pctrl->chip;
 819         chip->base = 0;
 820         chip->ngpio = ngpio;
 821         chip->label = dev_name(pctrl->dev);
 822         chip->dev = pctrl->dev;
 823         chip->owner = THIS_MODULE;
 824         chip->of_node = pctrl->dev->of_node;
 825
 826         ret = gpiochip_add(&pctrl->chip);
 827         if (ret) {
 828                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 829                 return ret;
 830         }
 831
 832         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
 833         if (ret) {
 834                 dev_err(pctrl->dev, "Failed to add pin range\n");
 835                 return ret;
 836         }
 837
 838         ret = gpiochip_irqchip_add(chip,
 839                                    &msm_gpio_irq_chip,
 840                                    0,
 841                                    handle_edge_irq,
 842                                    IRQ_TYPE_NONE);
 843         if (ret) {
 844                 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
 845                 return -ENOSYS;
 846         }
 847
 848         gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
 849                                      msm_gpio_irq_handler);
 850
 851         return 0;
 852 }
 853
 854 int msm_pinctrl_probe(struct platform_device *pdev,
 855                       const struct msm_pinctrl_soc_data *soc_data)
 856 {
 857         struct msm_pinctrl *pctrl;
 858         struct resource *res;
 859         int ret;
 860
 861         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 862         if (!pctrl) {
 863                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 864                 return -ENOMEM;
 865         }
 866         pctrl->dev = &pdev->dev;
 867         pctrl->soc = soc_data;
 868         pctrl->chip = msm_gpio_template;
 869
 870         spin_lock_init(&pctrl->lock);
 871
 872         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 873         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 874         if (IS_ERR(pctrl->regs))
 875                 return PTR_ERR(pctrl->regs);
 876
 877         pctrl->irq = platform_get_irq(pdev, 0);
 878         if (pctrl->irq < 0) {
 879                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 880                 return pctrl->irq;
 881         }
 882
 883         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 884         msm_pinctrl_desc.pins = pctrl->soc->pins;
 885         msm_pinctrl_desc.npins = pctrl->soc->npins;
 886         pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
 887         if (!pctrl->pctrl) {
 888                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 889                 return -ENODEV;
 890         }
 891
 892         ret = msm_gpio_init(pctrl);
 893         if (ret) {
 894                 pinctrl_unregister(pctrl->pctrl);
 895                 return ret;
 896         }
 897
 898         platform_set_drvdata(pdev, pctrl);
 899
 900         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 901
 902         return 0;
 903 }
 904 EXPORT_SYMBOL(msm_pinctrl_probe);
 905
 906 int msm_pinctrl_remove(struct platform_device *pdev)
 907 {
 908         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
 909         int ret;
 910
 911         ret = gpiochip_remove(&pctrl->chip);
 912         if (ret) {
 913                 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
 914                 return ret;
 915         }
 916
 917         pinctrl_unregister(pctrl->pctrl);
 918
 919         return 0;
 920 }
 921 EXPORT_SYMBOL(msm_pinctrl_remove);
 922