drivers/pinctrl/samsung/pinctrl-exynos.c

   1 /*
   2  * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2012 Linaro Ltd
   7  *              http://www.linaro.org
   8  *
   9  * Author: Thomas Abraham <thomas.ab@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This file contains the Samsung Exynos specific information required by the
  17  * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  18  * external gpio and wakeup interrupt support.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/irq.h>
  26 #include <linux/irqchip/chained_irq.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/err.h>
  32
  33 #include "pinctrl-samsung.h"
  34 #include "pinctrl-exynos.h"
  35
  36 struct exynos_irq_chip {
  37         struct irq_chip chip;
  38
  39         u32 eint_con;
  40         u32 eint_mask;
  41         u32 eint_pend;
  42 };
  43
  44 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
  45 {
  46         return container_of(chip, struct exynos_irq_chip, chip);
  47 }
  48
  49 static const struct samsung_pin_bank_type bank_type_off = {
  50         .fld_width = { 4, 1, 2, 2, 2, 2, },
  51         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  52 };
  53
  54 static const struct samsung_pin_bank_type bank_type_alive = {
  55         .fld_width = { 4, 1, 2, 2, },
  56         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  57 };
  58
  59 static void exynos_irq_mask(struct irq_data *irqd)
  60 {
  61         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  62         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  63         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  64         struct samsung_pinctrl_drv_data *d = bank->drvdata;
  65         unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
  66         unsigned long mask;
  67         unsigned long flags;
  68
  69         spin_lock_irqsave(&bank->slock, flags);
  70
  71         mask = readl(d->virt_base + reg_mask);
  72         mask |= 1 << irqd->hwirq;
  73         writel(mask, d->virt_base + reg_mask);
  74
  75         spin_unlock_irqrestore(&bank->slock, flags);
  76 }
  77
  78 static void exynos_irq_ack(struct irq_data *irqd)
  79 {
  80         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  81         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  82         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  83         struct samsung_pinctrl_drv_data *d = bank->drvdata;
  84         unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
  85
  86         writel(1 << irqd->hwirq, d->virt_base + reg_pend);
  87 }
  88
  89 static void exynos_irq_unmask(struct irq_data *irqd)
  90 {
  91         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  92         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  93         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  94         struct samsung_pinctrl_drv_data *d = bank->drvdata;
  95         unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
  96         unsigned long mask;
  97         unsigned long flags;
  98
  99         /*
 100          * Ack level interrupts right before unmask
 101          *
 102          * If we don't do this we'll get a double-interrupt.  Level triggered
 103          * interrupts must not fire an interrupt if the level is not
 104          * _currently_ active, even if it was active while the interrupt was
 105          * masked.
 106          */
 107         if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
 108                 exynos_irq_ack(irqd);
 109
 110         spin_lock_irqsave(&bank->slock, flags);
 111
 112         mask = readl(d->virt_base + reg_mask);
 113         mask &= ~(1 << irqd->hwirq);
 114         writel(mask, d->virt_base + reg_mask);
 115
 116         spin_unlock_irqrestore(&bank->slock, flags);
 117 }
 118
 119 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
 120 {
 121         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 122         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 123         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 124         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 125         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 126         unsigned int con, trig_type;
 127         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 128
 129         switch (type) {
 130         case IRQ_TYPE_EDGE_RISING:
 131                 trig_type = EXYNOS_EINT_EDGE_RISING;
 132                 break;
 133         case IRQ_TYPE_EDGE_FALLING:
 134                 trig_type = EXYNOS_EINT_EDGE_FALLING;
 135                 break;
 136         case IRQ_TYPE_EDGE_BOTH:
 137                 trig_type = EXYNOS_EINT_EDGE_BOTH;
 138                 break;
 139         case IRQ_TYPE_LEVEL_HIGH:
 140                 trig_type = EXYNOS_EINT_LEVEL_HIGH;
 141                 break;
 142         case IRQ_TYPE_LEVEL_LOW:
 143                 trig_type = EXYNOS_EINT_LEVEL_LOW;
 144                 break;
 145         default:
 146                 pr_err("unsupported external interrupt type\n");
 147                 return -EINVAL;
 148         }
 149
 150         if (type & IRQ_TYPE_EDGE_BOTH)
 151                 irq_set_handler_locked(irqd, handle_edge_irq);
 152         else
 153                 irq_set_handler_locked(irqd, handle_level_irq);
 154
 155         con = readl(d->virt_base + reg_con);
 156         con &= ~(EXYNOS_EINT_CON_MASK << shift);
 157         con |= trig_type << shift;
 158         writel(con, d->virt_base + reg_con);
 159
 160         return 0;
 161 }
 162
 163 static int exynos_irq_request_resources(struct irq_data *irqd)
 164 {
 165         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 166         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 167         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 168         const struct samsung_pin_bank_type *bank_type = bank->type;
 169         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 170         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 171         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 172         unsigned long flags;
 173         unsigned int mask;
 174         unsigned int con;
 175         int ret;
 176
 177         ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
 178         if (ret) {
 179                 dev_err(bank->gpio_chip.dev, "unable to lock pin %s-%lu IRQ\n",
 180                         bank->name, irqd->hwirq);
 181                 return ret;
 182         }
 183
 184         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 185         shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 186         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 187
 188         spin_lock_irqsave(&bank->slock, flags);
 189
 190         con = readl(d->virt_base + reg_con);
 191         con &= ~(mask << shift);
 192         con |= EXYNOS_EINT_FUNC << shift;
 193         writel(con, d->virt_base + reg_con);
 194
 195         spin_unlock_irqrestore(&bank->slock, flags);
 196
 197         exynos_irq_unmask(irqd);
 198
 199         return 0;
 200 }
 201
 202 static void exynos_irq_release_resources(struct irq_data *irqd)
 203 {
 204         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 205         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 206         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 207         const struct samsung_pin_bank_type *bank_type = bank->type;
 208         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 209         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 210         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 211         unsigned long flags;
 212         unsigned int mask;
 213         unsigned int con;
 214
 215         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 216         shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 217         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 218
 219         exynos_irq_mask(irqd);
 220
 221         spin_lock_irqsave(&bank->slock, flags);
 222
 223         con = readl(d->virt_base + reg_con);
 224         con &= ~(mask << shift);
 225         con |= FUNC_INPUT << shift;
 226         writel(con, d->virt_base + reg_con);
 227
 228         spin_unlock_irqrestore(&bank->slock, flags);
 229
 230         gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
 231 }
 232
 233 /*
 234  * irq_chip for gpio interrupts.
 235  */
 236 static struct exynos_irq_chip exynos_gpio_irq_chip = {
 237         .chip = {
 238                 .name = "exynos_gpio_irq_chip",
 239                 .irq_unmask = exynos_irq_unmask,
 240                 .irq_mask = exynos_irq_mask,
 241                 .irq_ack = exynos_irq_ack,
 242                 .irq_set_type = exynos_irq_set_type,
 243                 .irq_request_resources = exynos_irq_request_resources,
 244                 .irq_release_resources = exynos_irq_release_resources,
 245         },
 246         .eint_con = EXYNOS_GPIO_ECON_OFFSET,
 247         .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
 248         .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
 249 };
 250
 251 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
 252                                         irq_hw_number_t hw)
 253 {
 254         struct samsung_pin_bank *b = h->host_data;
 255
 256         irq_set_chip_data(virq, b);
 257         irq_set_chip_and_handler(virq, &b->irq_chip->chip,
 258                                         handle_level_irq);
 259         return 0;
 260 }
 261
 262 /*
 263  * irq domain callbacks for external gpio and wakeup interrupt controllers.
 264  */
 265 static const struct irq_domain_ops exynos_eint_irqd_ops = {
 266         .map    = exynos_eint_irq_map,
 267         .xlate  = irq_domain_xlate_twocell,
 268 };
 269
 270 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 271 {
 272         struct samsung_pinctrl_drv_data *d = data;
 273         struct samsung_pin_bank *bank = d->pin_banks;
 274         unsigned int svc, group, pin, virq;
 275
 276         svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
 277         group = EXYNOS_SVC_GROUP(svc);
 278         pin = svc & EXYNOS_SVC_NUM_MASK;
 279
 280         if (!group)
 281                 return IRQ_HANDLED;
 282         bank += (group - 1);
 283
 284         virq = irq_linear_revmap(bank->irq_domain, pin);
 285         if (!virq)
 286                 return IRQ_NONE;
 287         generic_handle_irq(virq);
 288         return IRQ_HANDLED;
 289 }
 290
 291 struct exynos_eint_gpio_save {
 292         u32 eint_con;
 293         u32 eint_fltcon0;
 294         u32 eint_fltcon1;
 295 };
 296
 297 /*
 298  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
 299  * @d: driver data of samsung pinctrl driver.
 300  */
 301 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 302 {
 303         struct samsung_pin_bank *bank;
 304         struct device *dev = d->dev;
 305         int ret;
 306         int i;
 307
 308         if (!d->irq) {
 309                 dev_err(dev, "irq number not available\n");
 310                 return -EINVAL;
 311         }
 312
 313         ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
 314                                         0, dev_name(dev), d);
 315         if (ret) {
 316                 dev_err(dev, "irq request failed\n");
 317                 return -ENXIO;
 318         }
 319
 320         bank = d->pin_banks;
 321         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 322                 if (bank->eint_type != EINT_TYPE_GPIO)
 323                         continue;
 324                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 325                                 bank->nr_pins, &exynos_eint_irqd_ops, bank);
 326                 if (!bank->irq_domain) {
 327                         dev_err(dev, "gpio irq domain add failed\n");
 328                         ret = -ENXIO;
 329                         goto err_domains;
 330                 }
 331
 332                 bank->soc_priv = devm_kzalloc(d->dev,
 333                         sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
 334                 if (!bank->soc_priv) {
 335                         irq_domain_remove(bank->irq_domain);
 336                         ret = -ENOMEM;
 337                         goto err_domains;
 338                 }
 339
 340                 bank->irq_chip = &exynos_gpio_irq_chip;
 341         }
 342
 343         return 0;
 344
 345 err_domains:
 346         for (--i, --bank; i >= 0; --i, --bank) {
 347                 if (bank->eint_type != EINT_TYPE_GPIO)
 348                         continue;
 349                 irq_domain_remove(bank->irq_domain);
 350         }
 351
 352         return ret;
 353 }
 354
 355 static u32 exynos_eint_wake_mask = 0xffffffff;
 356
 357 u32 exynos_get_eint_wake_mask(void)
 358 {
 359         return exynos_eint_wake_mask;
 360 }
 361
 362 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
 363 {
 364         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 365         unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
 366
 367         pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
 368
 369         if (!on)
 370                 exynos_eint_wake_mask |= bit;
 371         else
 372                 exynos_eint_wake_mask &= ~bit;
 373
 374         return 0;
 375 }
 376
 377 /*
 378  * irq_chip for wakeup interrupts
 379  */
 380 static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
 381         .chip = {
 382                 .name = "exynos4210_wkup_irq_chip",
 383                 .irq_unmask = exynos_irq_unmask,
 384                 .irq_mask = exynos_irq_mask,
 385                 .irq_ack = exynos_irq_ack,
 386                 .irq_set_type = exynos_irq_set_type,
 387                 .irq_set_wake = exynos_wkup_irq_set_wake,
 388                 .irq_request_resources = exynos_irq_request_resources,
 389                 .irq_release_resources = exynos_irq_release_resources,
 390         },
 391         .eint_con = EXYNOS_WKUP_ECON_OFFSET,
 392         .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
 393         .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
 394 };
 395
 396 static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
 397         .chip = {
 398                 .name = "exynos7_wkup_irq_chip",
 399                 .irq_unmask = exynos_irq_unmask,
 400                 .irq_mask = exynos_irq_mask,
 401                 .irq_ack = exynos_irq_ack,
 402                 .irq_set_type = exynos_irq_set_type,
 403                 .irq_set_wake = exynos_wkup_irq_set_wake,
 404                 .irq_request_resources = exynos_irq_request_resources,
 405                 .irq_release_resources = exynos_irq_release_resources,
 406         },
 407         .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
 408         .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
 409         .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
 410 };
 411
 412 /* list of external wakeup controllers supported */
 413 static const struct of_device_id exynos_wkup_irq_ids[] = {
 414         { .compatible = "samsung,exynos4210-wakeup-eint",
 415                         .data = &exynos4210_wkup_irq_chip },
 416         { .compatible = "samsung,exynos7-wakeup-eint",
 417                         .data = &exynos7_wkup_irq_chip },
 418         { }
 419 };
 420
 421 /* interrupt handler for wakeup interrupts 0..15 */
 422 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 423 {
 424         struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
 425         struct samsung_pin_bank *bank = eintd->bank;
 426         struct irq_chip *chip = irq_desc_get_chip(desc);
 427         int eint_irq;
 428
 429         chained_irq_enter(chip, desc);
 430         chip->irq_mask(&desc->irq_data);
 431
 432         if (chip->irq_ack)
 433                 chip->irq_ack(&desc->irq_data);
 434
 435         eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
 436         generic_handle_irq(eint_irq);
 437         chip->irq_unmask(&desc->irq_data);
 438         chained_irq_exit(chip, desc);
 439 }
 440
 441 static inline void exynos_irq_demux_eint(unsigned long pend,
 442                                                 struct irq_domain *domain)
 443 {
 444         unsigned int irq;
 445
 446         while (pend) {
 447                 irq = fls(pend) - 1;
 448                 generic_handle_irq(irq_find_mapping(domain, irq));
 449                 pend &= ~(1 << irq);
 450         }
 451 }
 452
 453 /* interrupt handler for wakeup interrupt 16 */
 454 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 455 {
 456         struct irq_chip *chip = irq_desc_get_chip(desc);
 457         struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
 458         struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
 459         unsigned long pend;
 460         unsigned long mask;
 461         int i;
 462
 463         chained_irq_enter(chip, desc);
 464
 465         for (i = 0; i < eintd->nr_banks; ++i) {
 466                 struct samsung_pin_bank *b = eintd->banks[i];
 467                 pend = readl(d->virt_base + b->irq_chip->eint_pend
 468                                 + b->eint_offset);
 469                 mask = readl(d->virt_base + b->irq_chip->eint_mask
 470                                 + b->eint_offset);
 471                 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
 472         }
 473
 474         chained_irq_exit(chip, desc);
 475 }
 476
 477 /*
 478  * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
 479  * @d: driver data of samsung pinctrl driver.
 480  */
 481 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 482 {
 483         struct device *dev = d->dev;
 484         struct device_node *wkup_np = NULL;
 485         struct device_node *np;
 486         struct samsung_pin_bank *bank;
 487         struct exynos_weint_data *weint_data;
 488         struct exynos_muxed_weint_data *muxed_data;
 489         struct exynos_irq_chip *irq_chip;
 490         unsigned int muxed_banks = 0;
 491         unsigned int i;
 492         int idx, irq;
 493
 494         for_each_child_of_node(dev->of_node, np) {
 495                 const struct of_device_id *match;
 496
 497                 match = of_match_node(exynos_wkup_irq_ids, np);
 498                 if (match) {
 499                         irq_chip = kmemdup(match->data,
 500                                 sizeof(*irq_chip), GFP_KERNEL);
 501                         wkup_np = np;
 502                         break;
 503                 }
 504         }
 505         if (!wkup_np)
 506                 return -ENODEV;
 507
 508         bank = d->pin_banks;
 509         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 510                 if (bank->eint_type != EINT_TYPE_WKUP)
 511                         continue;
 512
 513                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 514                                 bank->nr_pins, &exynos_eint_irqd_ops, bank);
 515                 if (!bank->irq_domain) {
 516                         dev_err(dev, "wkup irq domain add failed\n");
 517                         return -ENXIO;
 518                 }
 519
 520                 bank->irq_chip = irq_chip;
 521
 522                 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
 523                         bank->eint_type = EINT_TYPE_WKUP_MUX;
 524                         ++muxed_banks;
 525                         continue;
 526                 }
 527
 528                 weint_data = devm_kzalloc(dev, bank->nr_pins
 529                                         * sizeof(*weint_data), GFP_KERNEL);
 530                 if (!weint_data) {
 531                         dev_err(dev, "could not allocate memory for weint_data\n");
 532                         return -ENOMEM;
 533                 }
 534
 535                 for (idx = 0; idx < bank->nr_pins; ++idx) {
 536                         irq = irq_of_parse_and_map(bank->of_node, idx);
 537                         if (!irq) {
 538                                 dev_err(dev, "irq number for eint-%s-%d not found\n",
 539                                                         bank->name, idx);
 540                                 continue;
 541                         }
 542                         weint_data[idx].irq = idx;
 543                         weint_data[idx].bank = bank;
 544                         irq_set_chained_handler_and_data(irq,
 545                                                          exynos_irq_eint0_15,
 546                                                          &weint_data[idx]);
 547                 }
 548         }
 549
 550         if (!muxed_banks)
 551                 return 0;
 552
 553         irq = irq_of_parse_and_map(wkup_np, 0);
 554         if (!irq) {
 555                 dev_err(dev, "irq number for muxed EINTs not found\n");
 556                 return 0;
 557         }
 558
 559         muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
 560                 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
 561         if (!muxed_data) {
 562                 dev_err(dev, "could not allocate memory for muxed_data\n");
 563                 return -ENOMEM;
 564         }
 565
 566         irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
 567                                          muxed_data);
 568
 569         bank = d->pin_banks;
 570         idx = 0;
 571         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 572                 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
 573                         continue;
 574
 575                 muxed_data->banks[idx++] = bank;
 576         }
 577         muxed_data->nr_banks = muxed_banks;
 578
 579         return 0;
 580 }
 581
 582 static void exynos_pinctrl_suspend_bank(
 583                                 struct samsung_pinctrl_drv_data *drvdata,
 584                                 struct samsung_pin_bank *bank)
 585 {
 586         struct exynos_eint_gpio_save *save = bank->soc_priv;
 587         void __iomem *regs = drvdata->virt_base;
 588
 589         save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
 590                                                 + bank->eint_offset);
 591         save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 592                                                 + 2 * bank->eint_offset);
 593         save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 594                                                 + 2 * bank->eint_offset + 4);
 595
 596         pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
 597         pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
 598         pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
 599 }
 600
 601 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
 602 {
 603         struct samsung_pin_bank *bank = drvdata->pin_banks;
 604         int i;
 605
 606         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
 607                 if (bank->eint_type == EINT_TYPE_GPIO)
 608                         exynos_pinctrl_suspend_bank(drvdata, bank);
 609 }
 610
 611 static void exynos_pinctrl_resume_bank(
 612                                 struct samsung_pinctrl_drv_data *drvdata,
 613                                 struct samsung_pin_bank *bank)
 614 {
 615         struct exynos_eint_gpio_save *save = bank->soc_priv;
 616         void __iomem *regs = drvdata->virt_base;
 617
 618         pr_debug("%s:     con %#010x => %#010x\n", bank->name,
 619                         readl(regs + EXYNOS_GPIO_ECON_OFFSET
 620                         + bank->eint_offset), save->eint_con);
 621         pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
 622                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 623                         + 2 * bank->eint_offset), save->eint_fltcon0);
 624         pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
 625                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 626                         + 2 * bank->eint_offset + 4), save->eint_fltcon1);
 627
 628         writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
 629                                                 + bank->eint_offset);
 630         writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 631                                                 + 2 * bank->eint_offset);
 632         writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 633                                                 + 2 * bank->eint_offset + 4);
 634 }
 635
 636 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
 637 {
 638         struct samsung_pin_bank *bank = drvdata->pin_banks;
 639         int i;
 640
 641         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
 642                 if (bank->eint_type == EINT_TYPE_GPIO)
 643                         exynos_pinctrl_resume_bank(drvdata, bank);
 644 }
 645
 646 /* pin banks of s5pv210 pin-controller */
 647 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
 648         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 649         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
 650         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 651         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 652         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 653         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 654         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
 655         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
 656         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
 657         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
 658         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
 659         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
 660         EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
 661         EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
 662         EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
 663         EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
 664         EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
 665         EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
 666         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
 667         EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
 668         EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
 669         EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
 670         EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
 671         EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
 672         EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
 673         EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
 674         EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
 675         EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
 676         EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
 677         EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
 678         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
 679         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
 680         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
 681         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
 682 };
 683
 684 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
 685         {
 686                 /* pin-controller instance 0 data */
 687                 .pin_banks      = s5pv210_pin_bank,
 688                 .nr_banks       = ARRAY_SIZE(s5pv210_pin_bank),
 689                 .eint_gpio_init = exynos_eint_gpio_init,
 690                 .eint_wkup_init = exynos_eint_wkup_init,
 691                 .suspend        = exynos_pinctrl_suspend,
 692                 .resume         = exynos_pinctrl_resume,
 693         },
 694 };
 695
 696 /* pin banks of exynos3250 pin-controller 0 */
 697 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
 698         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 699         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 700         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
 701         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 702         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 703         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 704         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
 705 };
 706
 707 /* pin banks of exynos3250 pin-controller 1 */
 708 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
 709         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
 710         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
 711         EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
 712         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
 713         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 714         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 715         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
 716         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 717         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 718         EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
 719         EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
 720         EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
 721         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
 722         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
 723         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
 724         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
 725 };
 726
 727 /*
 728  * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
 729  * two gpio/pin-mux/pinconfig controllers.
 730  */
 731 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
 732         {
 733                 /* pin-controller instance 0 data */
 734                 .pin_banks      = exynos3250_pin_banks0,
 735                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks0),
 736                 .eint_gpio_init = exynos_eint_gpio_init,
 737                 .suspend        = exynos_pinctrl_suspend,
 738                 .resume         = exynos_pinctrl_resume,
 739         }, {
 740                 /* pin-controller instance 1 data */
 741                 .pin_banks      = exynos3250_pin_banks1,
 742                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks1),
 743                 .eint_gpio_init = exynos_eint_gpio_init,
 744                 .eint_wkup_init = exynos_eint_wkup_init,
 745                 .suspend        = exynos_pinctrl_suspend,
 746                 .resume         = exynos_pinctrl_resume,
 747         },
 748 };
 749
 750 /* pin banks of exynos4210 pin-controller 0 */
 751 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
 752         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 753         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 754         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 755         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 756         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 757         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 758         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 759         EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
 760         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
 761         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
 762         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
 763         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
 764         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 765         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 766         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 767         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 768 };
 769
 770 /* pin banks of exynos4210 pin-controller 1 */
 771 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
 772         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
 773         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
 774         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 775         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 776         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 777         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 778         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
 779         EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
 780         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 781         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 782         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 783         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 784         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 785         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 786         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 787         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 788         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 789         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 790         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 791         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 792 };
 793
 794 /* pin banks of exynos4210 pin-controller 2 */
 795 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
 796         EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
 797 };
 798
 799 /*
 800  * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
 801  * three gpio/pin-mux/pinconfig controllers.
 802  */
 803 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
 804         {
 805                 /* pin-controller instance 0 data */
 806                 .pin_banks      = exynos4210_pin_banks0,
 807                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks0),
 808                 .eint_gpio_init = exynos_eint_gpio_init,
 809                 .suspend        = exynos_pinctrl_suspend,
 810                 .resume         = exynos_pinctrl_resume,
 811         }, {
 812                 /* pin-controller instance 1 data */
 813                 .pin_banks      = exynos4210_pin_banks1,
 814                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks1),
 815                 .eint_gpio_init = exynos_eint_gpio_init,
 816                 .eint_wkup_init = exynos_eint_wkup_init,
 817                 .suspend        = exynos_pinctrl_suspend,
 818                 .resume         = exynos_pinctrl_resume,
 819         }, {
 820                 /* pin-controller instance 2 data */
 821                 .pin_banks      = exynos4210_pin_banks2,
 822                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks2),
 823         },
 824 };
 825
 826 /* pin banks of exynos4x12 pin-controller 0 */
 827 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
 828         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 829         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 830         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 831         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 832         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 833         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 834         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 835         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 836         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 837         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 838         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 839         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
 840         EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
 841 };
 842
 843 /* pin banks of exynos4x12 pin-controller 1 */
 844 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
 845         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 846         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 847         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 848         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 849         EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
 850         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
 851         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 852         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 853         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 854         EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
 855         EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
 856         EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
 857         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 858         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 859         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 860         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 861         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 862         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 863         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 864         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 865         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 866         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 867         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 868 };
 869
 870 /* pin banks of exynos4x12 pin-controller 2 */
 871 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
 872         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 873 };
 874
 875 /* pin banks of exynos4x12 pin-controller 3 */
 876 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
 877         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 878         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 879         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
 880         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
 881         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
 882 };
 883
 884 /*
 885  * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
 886  * four gpio/pin-mux/pinconfig controllers.
 887  */
 888 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
 889         {
 890                 /* pin-controller instance 0 data */
 891                 .pin_banks      = exynos4x12_pin_banks0,
 892                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks0),
 893                 .eint_gpio_init = exynos_eint_gpio_init,
 894                 .suspend        = exynos_pinctrl_suspend,
 895                 .resume         = exynos_pinctrl_resume,
 896         }, {
 897                 /* pin-controller instance 1 data */
 898                 .pin_banks      = exynos4x12_pin_banks1,
 899                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks1),
 900                 .eint_gpio_init = exynos_eint_gpio_init,
 901                 .eint_wkup_init = exynos_eint_wkup_init,
 902                 .suspend        = exynos_pinctrl_suspend,
 903                 .resume         = exynos_pinctrl_resume,
 904         }, {
 905                 /* pin-controller instance 2 data */
 906                 .pin_banks      = exynos4x12_pin_banks2,
 907                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks2),
 908                 .eint_gpio_init = exynos_eint_gpio_init,
 909                 .suspend        = exynos_pinctrl_suspend,
 910                 .resume         = exynos_pinctrl_resume,
 911         }, {
 912                 /* pin-controller instance 3 data */
 913                 .pin_banks      = exynos4x12_pin_banks3,
 914                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks3),
 915                 .eint_gpio_init = exynos_eint_gpio_init,
 916                 .suspend        = exynos_pinctrl_suspend,
 917                 .resume         = exynos_pinctrl_resume,
 918         },
 919 };
 920
 921 /* pin banks of exynos4415 pin-controller 0 */
 922 static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = {
 923         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 924         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 925         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 926         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 927         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 928         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 929         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 930         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 931         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 932         EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38),
 933 };
 934
 935 /* pin banks of exynos4415 pin-controller 1 */
 936 static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = {
 937         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
 938         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 939         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 940         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 941         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18),
 942         EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"),
 943         EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"),
 944         EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"),
 945         EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"),
 946         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"),
 947         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"),
 948         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"),
 949         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 950         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 951         EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
 952         EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
 953         EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
 954         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 955         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 956         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 957         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 958 };
 959
 960 /* pin banks of exynos4415 pin-controller 2 */
 961 static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = {
 962         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 963         EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"),
 964 };
 965
 966 /*
 967  * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes
 968  * three gpio/pin-mux/pinconfig controllers.
 969  */
 970 const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = {
 971         {
 972                 /* pin-controller instance 0 data */
 973                 .pin_banks      = exynos4415_pin_banks0,
 974                 .nr_banks       = ARRAY_SIZE(exynos4415_pin_banks0),
 975                 .eint_gpio_init = exynos_eint_gpio_init,
 976                 .suspend        = exynos_pinctrl_suspend,
 977                 .resume         = exynos_pinctrl_resume,
 978         }, {
 979                 /* pin-controller instance 1 data */
 980                 .pin_banks      = exynos4415_pin_banks1,
 981                 .nr_banks       = ARRAY_SIZE(exynos4415_pin_banks1),
 982                 .eint_gpio_init = exynos_eint_gpio_init,
 983                 .eint_wkup_init = exynos_eint_wkup_init,
 984                 .suspend        = exynos_pinctrl_suspend,
 985                 .resume         = exynos_pinctrl_resume,
 986         }, {
 987                 /* pin-controller instance 2 data */
 988                 .pin_banks      = exynos4415_pin_banks2,
 989                 .nr_banks       = ARRAY_SIZE(exynos4415_pin_banks2),
 990                 .eint_gpio_init = exynos_eint_gpio_init,
 991                 .suspend        = exynos_pinctrl_suspend,
 992                 .resume         = exynos_pinctrl_resume,
 993         },
 994 };
 995
 996 /* pin banks of exynos5250 pin-controller 0 */
 997 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
 998         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 999         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1000         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1001         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1002         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1003         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1004         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
1005         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
1006         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
1007         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
1008         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
1009         EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
1010         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
1011         EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
1012         EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
1013         EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
1014         EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
1015         EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
1016         EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
1017         EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
1018         EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
1019         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1020         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1021         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1022         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1023 };
1024
1025 /* pin banks of exynos5250 pin-controller 1 */
1026 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
1027         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1028         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1029         EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
1030         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
1031         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1032         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1033         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1034         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
1035         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
1036 };
1037
1038 /* pin banks of exynos5250 pin-controller 2 */
1039 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
1040         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
1041         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
1042         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
1043         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
1044         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
1045 };
1046
1047 /* pin banks of exynos5250 pin-controller 3 */
1048 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
1049         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1050 };
1051
1052 /*
1053  * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
1054  * four gpio/pin-mux/pinconfig controllers.
1055  */
1056 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
1057         {
1058                 /* pin-controller instance 0 data */
1059                 .pin_banks      = exynos5250_pin_banks0,
1060                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks0),
1061                 .eint_gpio_init = exynos_eint_gpio_init,
1062                 .eint_wkup_init = exynos_eint_wkup_init,
1063                 .suspend        = exynos_pinctrl_suspend,
1064                 .resume         = exynos_pinctrl_resume,
1065         }, {
1066                 /* pin-controller instance 1 data */
1067                 .pin_banks      = exynos5250_pin_banks1,
1068                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks1),
1069                 .eint_gpio_init = exynos_eint_gpio_init,
1070                 .suspend        = exynos_pinctrl_suspend,
1071                 .resume         = exynos_pinctrl_resume,
1072         }, {
1073                 /* pin-controller instance 2 data */
1074                 .pin_banks      = exynos5250_pin_banks2,
1075                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks2),
1076                 .eint_gpio_init = exynos_eint_gpio_init,
1077                 .suspend        = exynos_pinctrl_suspend,
1078                 .resume         = exynos_pinctrl_resume,
1079         }, {
1080                 /* pin-controller instance 3 data */
1081                 .pin_banks      = exynos5250_pin_banks3,
1082                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks3),
1083                 .eint_gpio_init = exynos_eint_gpio_init,
1084                 .suspend        = exynos_pinctrl_suspend,
1085                 .resume         = exynos_pinctrl_resume,
1086         },
1087 };
1088
1089 /* pin banks of exynos5260 pin-controller 0 */
1090 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
1091         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1092         EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1093         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1094         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1095         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1096         EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1097         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1098         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1099         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1100         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1101         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1102         EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1103         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1104         EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1105         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1106         EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1107         EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1108         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1109         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1110         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1111         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1112 };
1113
1114 /* pin banks of exynos5260 pin-controller 1 */
1115 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
1116         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1117         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1118         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1119         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1120         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1121 };
1122
1123 /* pin banks of exynos5260 pin-controller 2 */
1124 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
1125         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1126         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1127 };
1128
1129 /*
1130  * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1131  * three gpio/pin-mux/pinconfig controllers.
1132  */
1133 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
1134         {
1135                 /* pin-controller instance 0 data */
1136                 .pin_banks      = exynos5260_pin_banks0,
1137                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks0),
1138                 .eint_gpio_init = exynos_eint_gpio_init,
1139                 .eint_wkup_init = exynos_eint_wkup_init,
1140         }, {
1141                 /* pin-controller instance 1 data */
1142                 .pin_banks      = exynos5260_pin_banks1,
1143                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks1),
1144                 .eint_gpio_init = exynos_eint_gpio_init,
1145         }, {
1146                 /* pin-controller instance 2 data */
1147                 .pin_banks      = exynos5260_pin_banks2,
1148                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks2),
1149                 .eint_gpio_init = exynos_eint_gpio_init,
1150         },
1151 };
1152
1153 /* pin banks of exynos5420 pin-controller 0 */
1154 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
1155         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1156         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1157         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1158         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1159         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1160 };
1161
1162 /* pin banks of exynos5420 pin-controller 1 */
1163 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
1164         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1165         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1166         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1167         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1168         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1169         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1170         EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1171         EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1172         EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1173         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1174         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1175         EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1176         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1177 };
1178
1179 /* pin banks of exynos5420 pin-controller 2 */
1180 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
1181         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1182         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1183         EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1184         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1185         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1186         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1187         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1188         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1189 };
1190
1191 /* pin banks of exynos5420 pin-controller 3 */
1192 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
1193         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1194         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1195         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1196         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1197         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1198         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1199         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1200         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1201         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1202 };
1203
1204 /* pin banks of exynos5420 pin-controller 4 */
1205 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
1206         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1207 };
1208
1209 /*
1210  * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1211  * four gpio/pin-mux/pinconfig controllers.
1212  */
1213 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
1214         {
1215                 /* pin-controller instance 0 data */
1216                 .pin_banks      = exynos5420_pin_banks0,
1217                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks0),
1218                 .eint_gpio_init = exynos_eint_gpio_init,
1219                 .eint_wkup_init = exynos_eint_wkup_init,
1220         }, {
1221                 /* pin-controller instance 1 data */
1222                 .pin_banks      = exynos5420_pin_banks1,
1223                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks1),
1224                 .eint_gpio_init = exynos_eint_gpio_init,
1225         }, {
1226                 /* pin-controller instance 2 data */
1227                 .pin_banks      = exynos5420_pin_banks2,
1228                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks2),
1229                 .eint_gpio_init = exynos_eint_gpio_init,
1230         }, {
1231                 /* pin-controller instance 3 data */
1232                 .pin_banks      = exynos5420_pin_banks3,
1233                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks3),
1234                 .eint_gpio_init = exynos_eint_gpio_init,
1235         }, {
1236                 /* pin-controller instance 4 data */
1237                 .pin_banks      = exynos5420_pin_banks4,
1238                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks4),
1239                 .eint_gpio_init = exynos_eint_gpio_init,
1240         },
1241 };
1242
1243 /* pin banks of exynos5433 pin-controller - ALIVE */
1244 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
1245         EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1246         EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1247         EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1248         EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1249 };
1250
1251 /* pin banks of exynos5433 pin-controller - AUD */
1252 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
1253         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1254         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1255 };
1256
1257 /* pin banks of exynos5433 pin-controller - CPIF */
1258 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
1259         EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1260 };
1261
1262 /* pin banks of exynos5433 pin-controller - eSE */
1263 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
1264         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1265 };
1266
1267 /* pin banks of exynos5433 pin-controller - FINGER */
1268 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
1269         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1270 };
1271
1272 /* pin banks of exynos5433 pin-controller - FSYS */
1273 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
1274         EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1275         EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1276         EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1277         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1278         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1279         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1280 };
1281
1282 /* pin banks of exynos5433 pin-controller - IMEM */
1283 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
1284         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1285 };
1286
1287 /* pin banks of exynos5433 pin-controller - NFC */
1288 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
1289         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1290 };
1291
1292 /* pin banks of exynos5433 pin-controller - PERIC */
1293 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
1294         EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1295         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1296         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1297         EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1298         EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1299         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1300         EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1301         EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1302         EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1303         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1304         EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1305         EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1306         EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1307         EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1308         EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1309         EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1310         EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1311 };
1312
1313 /* pin banks of exynos5433 pin-controller - TOUCH */
1314 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
1315         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1316 };
1317
1318 /*
1319  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
1320  * ten gpio/pin-mux/pinconfig controllers.
1321  */
1322 const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
1323         {
1324                 /* pin-controller instance 0 data */
1325                 .pin_banks      = exynos5433_pin_banks0,
1326                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks0),
1327                 .eint_wkup_init = exynos_eint_wkup_init,
1328                 .suspend        = exynos_pinctrl_suspend,
1329                 .resume         = exynos_pinctrl_resume,
1330         }, {
1331                 /* pin-controller instance 1 data */
1332                 .pin_banks      = exynos5433_pin_banks1,
1333                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks1),
1334                 .eint_gpio_init = exynos_eint_gpio_init,
1335                 .suspend        = exynos_pinctrl_suspend,
1336                 .resume         = exynos_pinctrl_resume,
1337         }, {
1338                 /* pin-controller instance 2 data */
1339                 .pin_banks      = exynos5433_pin_banks2,
1340                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks2),
1341                 .eint_gpio_init = exynos_eint_gpio_init,
1342                 .suspend        = exynos_pinctrl_suspend,
1343                 .resume         = exynos_pinctrl_resume,
1344         }, {
1345                 /* pin-controller instance 3 data */
1346                 .pin_banks      = exynos5433_pin_banks3,
1347                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks3),
1348                 .eint_gpio_init = exynos_eint_gpio_init,
1349                 .suspend        = exynos_pinctrl_suspend,
1350                 .resume         = exynos_pinctrl_resume,
1351         }, {
1352                 /* pin-controller instance 4 data */
1353                 .pin_banks      = exynos5433_pin_banks4,
1354                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks4),
1355                 .eint_gpio_init = exynos_eint_gpio_init,
1356                 .suspend        = exynos_pinctrl_suspend,
1357                 .resume         = exynos_pinctrl_resume,
1358         }, {
1359                 /* pin-controller instance 5 data */
1360                 .pin_banks      = exynos5433_pin_banks5,
1361                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks5),
1362                 .eint_gpio_init = exynos_eint_gpio_init,
1363                 .suspend        = exynos_pinctrl_suspend,
1364                 .resume         = exynos_pinctrl_resume,
1365         }, {
1366                 /* pin-controller instance 6 data */
1367                 .pin_banks      = exynos5433_pin_banks6,
1368                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks6),
1369                 .eint_gpio_init = exynos_eint_gpio_init,
1370                 .suspend        = exynos_pinctrl_suspend,
1371                 .resume         = exynos_pinctrl_resume,
1372         }, {
1373                 /* pin-controller instance 7 data */
1374                 .pin_banks      = exynos5433_pin_banks7,
1375                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks7),
1376                 .eint_gpio_init = exynos_eint_gpio_init,
1377                 .suspend        = exynos_pinctrl_suspend,
1378                 .resume         = exynos_pinctrl_resume,
1379         }, {
1380                 /* pin-controller instance 8 data */
1381                 .pin_banks      = exynos5433_pin_banks8,
1382                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks8),
1383                 .eint_gpio_init = exynos_eint_gpio_init,
1384                 .suspend        = exynos_pinctrl_suspend,
1385                 .resume         = exynos_pinctrl_resume,
1386         }, {
1387                 /* pin-controller instance 9 data */
1388                 .pin_banks      = exynos5433_pin_banks9,
1389                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks9),
1390                 .eint_gpio_init = exynos_eint_gpio_init,
1391                 .suspend        = exynos_pinctrl_suspend,
1392                 .resume         = exynos_pinctrl_resume,
1393         },
1394 };
1395
1396 /* pin banks of exynos7 pin-controller - ALIVE */
1397 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
1398         EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1399         EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1400         EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1401         EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1402 };
1403
1404 /* pin banks of exynos7 pin-controller - BUS0 */
1405 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
1406         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
1407         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
1408         EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
1409         EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
1410         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
1411         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
1412         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
1413         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
1414         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
1415         EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
1416         EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
1417         EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
1418         EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
1419         EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
1420         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
1421 };
1422
1423 /* pin banks of exynos7 pin-controller - NFC */
1424 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
1425         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1426 };
1427
1428 /* pin banks of exynos7 pin-controller - TOUCH */
1429 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
1430         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1431 };
1432
1433 /* pin banks of exynos7 pin-controller - FF */
1434 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
1435         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
1436 };
1437
1438 /* pin banks of exynos7 pin-controller - ESE */
1439 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
1440         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
1441 };
1442
1443 /* pin banks of exynos7 pin-controller - FSYS0 */
1444 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
1445         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
1446 };
1447
1448 /* pin banks of exynos7 pin-controller - FSYS1 */
1449 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
1450         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
1451         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
1452         EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
1453         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
1454 };
1455
1456 /* pin banks of exynos7 pin-controller - BUS1 */
1457 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
1458         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
1459         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
1460         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
1461         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
1462         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
1463         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
1464         EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
1465         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
1466         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
1467         EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
1468 };
1469
1470 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
1471         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1472         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1473 };
1474
1475 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1476         {
1477                 /* pin-controller instance 0 Alive data */
1478                 .pin_banks      = exynos7_pin_banks0,
1479                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks0),
1480                 .eint_wkup_init = exynos_eint_wkup_init,
1481         }, {
1482                 /* pin-controller instance 1 BUS0 data */
1483                 .pin_banks      = exynos7_pin_banks1,
1484                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks1),
1485                 .eint_gpio_init = exynos_eint_gpio_init,
1486         }, {
1487                 /* pin-controller instance 2 NFC data */
1488                 .pin_banks      = exynos7_pin_banks2,
1489                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks2),
1490                 .eint_gpio_init = exynos_eint_gpio_init,
1491         }, {
1492                 /* pin-controller instance 3 TOUCH data */
1493                 .pin_banks      = exynos7_pin_banks3,
1494                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks3),
1495                 .eint_gpio_init = exynos_eint_gpio_init,
1496         }, {
1497                 /* pin-controller instance 4 FF data */
1498                 .pin_banks      = exynos7_pin_banks4,
1499                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks4),
1500                 .eint_gpio_init = exynos_eint_gpio_init,
1501         }, {
1502                 /* pin-controller instance 5 ESE data */
1503                 .pin_banks      = exynos7_pin_banks5,
1504                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks5),
1505                 .eint_gpio_init = exynos_eint_gpio_init,
1506         }, {
1507                 /* pin-controller instance 6 FSYS0 data */
1508                 .pin_banks      = exynos7_pin_banks6,
1509                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks6),
1510                 .eint_gpio_init = exynos_eint_gpio_init,
1511         }, {
1512                 /* pin-controller instance 7 FSYS1 data */
1513                 .pin_banks      = exynos7_pin_banks7,
1514                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
1515                 .eint_gpio_init = exynos_eint_gpio_init,
1516         }, {
1517                 /* pin-controller instance 8 BUS1 data */
1518                 .pin_banks      = exynos7_pin_banks8,
1519                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
1520                 .eint_gpio_init = exynos_eint_gpio_init,
1521         }, {
1522                 /* pin-controller instance 9 AUD data */
1523                 .pin_banks      = exynos7_pin_banks9,
1524                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks9),
1525                 .eint_gpio_init = exynos_eint_gpio_init,
1526         },
1527 };