2 * SuperH Pin Function Controller support.
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #define DRV_NAME "sh-pfc"
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
29 static int sh_pfc_map_resources(struct sh_pfc
*pfc
,
30 struct platform_device
*pdev
)
32 unsigned int num_windows
= 0;
33 unsigned int num_irqs
= 0;
34 struct sh_pfc_window
*windows
;
35 unsigned int *irqs
= NULL
;
39 /* Count the MEM and IRQ resources. */
40 for (i
= 0; i
< pdev
->num_resources
; ++i
) {
41 switch (resource_type(&pdev
->resource
[i
])) {
55 /* Allocate memory windows and IRQs arrays. */
56 windows
= devm_kzalloc(pfc
->dev
, num_windows
* sizeof(*windows
),
61 pfc
->num_windows
= num_windows
;
62 pfc
->windows
= windows
;
65 irqs
= devm_kzalloc(pfc
->dev
, num_irqs
* sizeof(*irqs
),
70 pfc
->num_irqs
= num_irqs
;
75 for (i
= 0, res
= pdev
->resource
; i
< pdev
->num_resources
; i
++, res
++) {
76 switch (resource_type(res
)) {
78 windows
->phys
= res
->start
;
79 windows
->size
= resource_size(res
);
80 windows
->virt
= devm_ioremap_resource(pfc
->dev
, res
);
81 if (IS_ERR(windows
->virt
))
95 static void __iomem
*sh_pfc_phys_to_virt(struct sh_pfc
*pfc
, u32 reg
)
97 struct sh_pfc_window
*window
;
98 phys_addr_t address
= reg
;
101 /* scan through physical windows and convert address */
102 for (i
= 0; i
< pfc
->num_windows
; i
++) {
103 window
= pfc
->windows
+ i
;
105 if (address
< window
->phys
)
108 if (address
>= (window
->phys
+ window
->size
))
111 return window
->virt
+ (address
- window
->phys
);
118 int sh_pfc_get_pin_index(struct sh_pfc
*pfc
, unsigned int pin
)
123 for (i
= 0, offset
= 0; i
< pfc
->nr_ranges
; ++i
) {
124 const struct sh_pfc_pin_range
*range
= &pfc
->ranges
[i
];
126 if (pin
<= range
->end
)
127 return pin
>= range
->start
128 ? offset
+ pin
- range
->start
: -1;
130 offset
+= range
->end
- range
->start
+ 1;
136 static int sh_pfc_enum_in_range(u16 enum_id
, const struct pinmux_range
*r
)
138 if (enum_id
< r
->begin
)
141 if (enum_id
> r
->end
)
147 u32
sh_pfc_read_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
)
151 return ioread8(mapped_reg
);
153 return ioread16(mapped_reg
);
155 return ioread32(mapped_reg
);
162 void sh_pfc_write_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
,
167 iowrite8(data
, mapped_reg
);
170 iowrite16(data
, mapped_reg
);
173 iowrite32(data
, mapped_reg
);
180 static void sh_pfc_config_reg_helper(struct sh_pfc
*pfc
,
181 const struct pinmux_cfg_reg
*crp
,
183 void __iomem
**mapped_regp
, u32
*maskp
,
188 *mapped_regp
= sh_pfc_phys_to_virt(pfc
, crp
->reg
);
190 if (crp
->field_width
) {
191 *maskp
= (1 << crp
->field_width
) - 1;
192 *posp
= crp
->reg_width
- ((in_pos
+ 1) * crp
->field_width
);
194 *maskp
= (1 << crp
->var_field_width
[in_pos
]) - 1;
195 *posp
= crp
->reg_width
;
196 for (k
= 0; k
<= in_pos
; k
++)
197 *posp
-= crp
->var_field_width
[k
];
201 static void sh_pfc_write_config_reg(struct sh_pfc
*pfc
,
202 const struct pinmux_cfg_reg
*crp
,
203 unsigned int field
, u32 value
)
205 void __iomem
*mapped_reg
;
209 sh_pfc_config_reg_helper(pfc
, crp
, field
, &mapped_reg
, &mask
, &pos
);
211 dev_dbg(pfc
->dev
, "write_reg addr = %x, value = 0x%x, field = %u, "
212 "r_width = %u, f_width = %u\n",
213 crp
->reg
, value
, field
, crp
->reg_width
, crp
->field_width
);
215 mask
= ~(mask
<< pos
);
216 value
= value
<< pos
;
218 data
= sh_pfc_read_raw_reg(mapped_reg
, crp
->reg_width
);
222 if (pfc
->info
->unlock_reg
)
223 sh_pfc_write_raw_reg(
224 sh_pfc_phys_to_virt(pfc
, pfc
->info
->unlock_reg
), 32,
227 sh_pfc_write_raw_reg(mapped_reg
, crp
->reg_width
, data
);
230 static int sh_pfc_get_config_reg(struct sh_pfc
*pfc
, u16 enum_id
,
231 const struct pinmux_cfg_reg
**crp
,
232 unsigned int *fieldp
, u32
*valuep
)
237 const struct pinmux_cfg_reg
*config_reg
=
238 pfc
->info
->cfg_regs
+ k
;
239 unsigned int r_width
= config_reg
->reg_width
;
240 unsigned int f_width
= config_reg
->field_width
;
241 unsigned int curr_width
;
242 unsigned int bit_pos
;
243 unsigned int pos
= 0;
249 for (bit_pos
= 0; bit_pos
< r_width
; bit_pos
+= curr_width
) {
254 curr_width
= f_width
;
256 curr_width
= config_reg
->var_field_width
[m
];
258 ncomb
= 1 << curr_width
;
259 for (n
= 0; n
< ncomb
; n
++) {
260 if (config_reg
->enum_ids
[pos
+ n
] == enum_id
) {
276 static int sh_pfc_mark_to_enum(struct sh_pfc
*pfc
, u16 mark
, int pos
,
279 const u16
*data
= pfc
->info
->gpio_data
;
283 *enum_idp
= data
[pos
+ 1];
287 for (k
= 0; k
< pfc
->info
->gpio_data_size
; k
++) {
288 if (data
[k
] == mark
) {
289 *enum_idp
= data
[k
+ 1];
294 dev_err(pfc
->dev
, "cannot locate data/mark enum_id for mark %d\n",
299 int sh_pfc_config_mux(struct sh_pfc
*pfc
, unsigned mark
, int pinmux_type
)
301 const struct pinmux_range
*range
;
304 switch (pinmux_type
) {
305 case PINMUX_TYPE_GPIO
:
306 case PINMUX_TYPE_FUNCTION
:
310 case PINMUX_TYPE_OUTPUT
:
311 range
= &pfc
->info
->output
;
314 case PINMUX_TYPE_INPUT
:
315 range
= &pfc
->info
->input
;
322 /* Iterate over all the configuration fields we need to update. */
324 const struct pinmux_cfg_reg
*cr
;
331 pos
= sh_pfc_mark_to_enum(pfc
, mark
, pos
, &enum_id
);
338 /* Check if the configuration field selects a function. If it
339 * doesn't, skip the field if it's not applicable to the
340 * requested pinmux type.
342 in_range
= sh_pfc_enum_in_range(enum_id
, &pfc
->info
->function
);
344 if (pinmux_type
== PINMUX_TYPE_FUNCTION
) {
345 /* Functions are allowed to modify all
349 } else if (pinmux_type
!= PINMUX_TYPE_GPIO
) {
350 /* Input/output types can only modify fields
351 * that correspond to their respective ranges.
353 in_range
= sh_pfc_enum_in_range(enum_id
, range
);
356 * special case pass through for fixed
357 * input-only or output-only pins without
358 * function enum register association.
360 if (in_range
&& enum_id
== range
->force
)
363 /* GPIOs are only allowed to modify function fields. */
369 ret
= sh_pfc_get_config_reg(pfc
, enum_id
, &cr
, &field
, &value
);
373 sh_pfc_write_config_reg(pfc
, cr
, field
, value
);
379 static int sh_pfc_init_ranges(struct sh_pfc
*pfc
)
381 struct sh_pfc_pin_range
*range
;
382 unsigned int nr_ranges
;
385 if (pfc
->info
->pins
[0].pin
== (u16
)-1) {
386 /* Pin number -1 denotes that the SoC doesn't report pin numbers
387 * in its pin arrays yet. Consider the pin numbers range as
388 * continuous and allocate a single range.
391 pfc
->ranges
= devm_kzalloc(pfc
->dev
, sizeof(*pfc
->ranges
),
393 if (pfc
->ranges
== NULL
)
396 pfc
->ranges
->start
= 0;
397 pfc
->ranges
->end
= pfc
->info
->nr_pins
- 1;
398 pfc
->nr_gpio_pins
= pfc
->info
->nr_pins
;
403 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
404 * be sorted by pin numbers, and pins without a GPIO port must come
407 for (i
= 1, nr_ranges
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
408 if (pfc
->info
->pins
[i
-1].pin
!= pfc
->info
->pins
[i
].pin
- 1)
412 pfc
->nr_ranges
= nr_ranges
;
413 pfc
->ranges
= devm_kzalloc(pfc
->dev
, sizeof(*pfc
->ranges
) * nr_ranges
,
415 if (pfc
->ranges
== NULL
)
419 range
->start
= pfc
->info
->pins
[0].pin
;
421 for (i
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
422 if (pfc
->info
->pins
[i
-1].pin
== pfc
->info
->pins
[i
].pin
- 1)
425 range
->end
= pfc
->info
->pins
[i
-1].pin
;
426 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
427 pfc
->nr_gpio_pins
= range
->end
+ 1;
430 range
->start
= pfc
->info
->pins
[i
].pin
;
433 range
->end
= pfc
->info
->pins
[i
-1].pin
;
434 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
435 pfc
->nr_gpio_pins
= range
->end
+ 1;
441 static const struct of_device_id sh_pfc_of_table
[] = {
442 #ifdef CONFIG_PINCTRL_PFC_EMEV2
444 .compatible
= "renesas,pfc-emev2",
445 .data
= &emev2_pinmux_info
,
448 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
450 .compatible
= "renesas,pfc-r8a73a4",
451 .data
= &r8a73a4_pinmux_info
,
454 #ifdef CONFIG_PINCTRL_PFC_R8A7740
456 .compatible
= "renesas,pfc-r8a7740",
457 .data
= &r8a7740_pinmux_info
,
460 #ifdef CONFIG_PINCTRL_PFC_R8A7778
462 .compatible
= "renesas,pfc-r8a7778",
463 .data
= &r8a7778_pinmux_info
,
466 #ifdef CONFIG_PINCTRL_PFC_R8A7779
468 .compatible
= "renesas,pfc-r8a7779",
469 .data
= &r8a7779_pinmux_info
,
472 #ifdef CONFIG_PINCTRL_PFC_R8A7790
474 .compatible
= "renesas,pfc-r8a7790",
475 .data
= &r8a7790_pinmux_info
,
478 #ifdef CONFIG_PINCTRL_PFC_R8A7791
480 .compatible
= "renesas,pfc-r8a7791",
481 .data
= &r8a7791_pinmux_info
,
484 #ifdef CONFIG_PINCTRL_PFC_SH73A0
486 .compatible
= "renesas,pfc-sh73a0",
487 .data
= &sh73a0_pinmux_info
,
492 MODULE_DEVICE_TABLE(of
, sh_pfc_of_table
);
495 static int sh_pfc_probe(struct platform_device
*pdev
)
497 const struct platform_device_id
*platid
= platform_get_device_id(pdev
);
499 struct device_node
*np
= pdev
->dev
.of_node
;
501 const struct sh_pfc_soc_info
*info
;
507 info
= of_match_device(sh_pfc_of_table
, &pdev
->dev
)->data
;
510 info
= platid
? (const void *)platid
->driver_data
: NULL
;
515 pfc
= devm_kzalloc(&pdev
->dev
, sizeof(*pfc
), GFP_KERNEL
);
520 pfc
->dev
= &pdev
->dev
;
522 ret
= sh_pfc_map_resources(pfc
, pdev
);
523 if (unlikely(ret
< 0))
526 spin_lock_init(&pfc
->lock
);
528 if (info
->ops
&& info
->ops
->init
) {
529 ret
= info
->ops
->init(pfc
);
534 pinctrl_provide_dummies();
536 ret
= sh_pfc_init_ranges(pfc
);
541 * Initialize pinctrl bindings first
543 ret
= sh_pfc_register_pinctrl(pfc
);
544 if (unlikely(ret
!= 0))
547 #ifdef CONFIG_GPIO_SH_PFC
551 ret
= sh_pfc_register_gpiochip(pfc
);
552 if (unlikely(ret
!= 0)) {
554 * If the GPIO chip fails to come up we still leave the
555 * PFC state as it is, given that there are already
556 * extant users of it that have succeeded by this point.
558 dev_notice(pfc
->dev
, "failed to init GPIO chip, ignoring...\n");
562 platform_set_drvdata(pdev
, pfc
);
564 dev_info(pfc
->dev
, "%s support registered\n", info
->name
);
569 static int sh_pfc_remove(struct platform_device
*pdev
)
571 struct sh_pfc
*pfc
= platform_get_drvdata(pdev
);
573 #ifdef CONFIG_GPIO_SH_PFC
574 sh_pfc_unregister_gpiochip(pfc
);
576 sh_pfc_unregister_pinctrl(pfc
);
581 static const struct platform_device_id sh_pfc_id_table
[] = {
582 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
583 { "pfc-r8a73a4", (kernel_ulong_t
)&r8a73a4_pinmux_info
},
585 #ifdef CONFIG_PINCTRL_PFC_R8A7740
586 { "pfc-r8a7740", (kernel_ulong_t
)&r8a7740_pinmux_info
},
588 #ifdef CONFIG_PINCTRL_PFC_R8A7778
589 { "pfc-r8a7778", (kernel_ulong_t
)&r8a7778_pinmux_info
},
591 #ifdef CONFIG_PINCTRL_PFC_R8A7779
592 { "pfc-r8a7779", (kernel_ulong_t
)&r8a7779_pinmux_info
},
594 #ifdef CONFIG_PINCTRL_PFC_R8A7790
595 { "pfc-r8a7790", (kernel_ulong_t
)&r8a7790_pinmux_info
},
597 #ifdef CONFIG_PINCTRL_PFC_SH7203
598 { "pfc-sh7203", (kernel_ulong_t
)&sh7203_pinmux_info
},
600 #ifdef CONFIG_PINCTRL_PFC_SH7264
601 { "pfc-sh7264", (kernel_ulong_t
)&sh7264_pinmux_info
},
603 #ifdef CONFIG_PINCTRL_PFC_SH7269
604 { "pfc-sh7269", (kernel_ulong_t
)&sh7269_pinmux_info
},
606 #ifdef CONFIG_PINCTRL_PFC_SH73A0
607 { "pfc-sh73a0", (kernel_ulong_t
)&sh73a0_pinmux_info
},
609 #ifdef CONFIG_PINCTRL_PFC_SH7720
610 { "pfc-sh7720", (kernel_ulong_t
)&sh7720_pinmux_info
},
612 #ifdef CONFIG_PINCTRL_PFC_SH7722
613 { "pfc-sh7722", (kernel_ulong_t
)&sh7722_pinmux_info
},
615 #ifdef CONFIG_PINCTRL_PFC_SH7723
616 { "pfc-sh7723", (kernel_ulong_t
)&sh7723_pinmux_info
},
618 #ifdef CONFIG_PINCTRL_PFC_SH7724
619 { "pfc-sh7724", (kernel_ulong_t
)&sh7724_pinmux_info
},
621 #ifdef CONFIG_PINCTRL_PFC_SH7734
622 { "pfc-sh7734", (kernel_ulong_t
)&sh7734_pinmux_info
},
624 #ifdef CONFIG_PINCTRL_PFC_SH7757
625 { "pfc-sh7757", (kernel_ulong_t
)&sh7757_pinmux_info
},
627 #ifdef CONFIG_PINCTRL_PFC_SH7785
628 { "pfc-sh7785", (kernel_ulong_t
)&sh7785_pinmux_info
},
630 #ifdef CONFIG_PINCTRL_PFC_SH7786
631 { "pfc-sh7786", (kernel_ulong_t
)&sh7786_pinmux_info
},
633 #ifdef CONFIG_PINCTRL_PFC_SHX3
634 { "pfc-shx3", (kernel_ulong_t
)&shx3_pinmux_info
},
639 MODULE_DEVICE_TABLE(platform
, sh_pfc_id_table
);
641 static struct platform_driver sh_pfc_driver
= {
642 .probe
= sh_pfc_probe
,
643 .remove
= sh_pfc_remove
,
644 .id_table
= sh_pfc_id_table
,
647 .of_match_table
= of_match_ptr(sh_pfc_of_table
),
651 static int __init
sh_pfc_init(void)
653 return platform_driver_register(&sh_pfc_driver
);
655 postcore_initcall(sh_pfc_init
);
657 static void __exit
sh_pfc_exit(void)
659 platform_driver_unregister(&sh_pfc_driver
);
661 module_exit(sh_pfc_exit
);
663 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
664 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
665 MODULE_LICENSE("GPL v2");