drivers/pinctrl/sh-pfc/pfc-r8a7790.c

   1 /*
   2  * R8A7790 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Magnus Damm
   6  * Copyright (C) 2012  Renesas Solutions Corp.
   7  * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/platform_data/gpio-rcar.h>
  26
  27 #include "core.h"
  28 #include "sh_pfc.h"
  29
  30 #define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
  31
  32 #define PORT_GP_32(bank, fn, sfx)                                       \
  33         PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
  34         PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
  35         PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
  36         PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
  37         PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
  38         PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
  39         PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
  40         PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
  41         PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
  42         PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
  43         PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
  44         PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
  45         PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
  46         PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
  47         PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
  48         PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
  49
  50 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
  51         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
  52         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
  53         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
  54         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
  55         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
  56         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
  57         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
  58         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
  59         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
  60         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
  61         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
  62         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
  63         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
  64         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
  65         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
  66         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
  67
  68 #define CPU_ALL_PORT(fn, sfx)                                           \
  69         PORT_GP_32(0, fn, sfx),                                         \
  70         PORT_GP_32(1, fn, sfx),                                         \
  71         PORT_GP_32(2, fn, sfx),                                         \
  72         PORT_GP_32(3, fn, sfx),                                         \
  73         PORT_GP_32(4, fn, sfx),                                         \
  74         PORT_GP_32(5, fn, sfx)
  75
  76 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
  77
  78 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
  79         [(bank * 32) + pin] = {                                         \
  80                 .name = __stringify(_name),                             \
  81                 .enum_id = _name##_DATA,                                \
  82         }
  83
  84 #define _GP_DATA(bank, pin, name, sfx)                                  \
  85         PINMUX_DATA(name##_DATA, name##_FN)
  86
  87 #define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
  88 #define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
  89 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
  90
  91 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  92 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  93                                                           FN_##ipsr, FN_##fn)
  94
  95 enum {
  96         PINMUX_RESERVED = 0,
  97
  98         PINMUX_DATA_BEGIN,
  99         GP_ALL(DATA),
 100         PINMUX_DATA_END,
 101
 102         PINMUX_FUNCTION_BEGIN,
 103         GP_ALL(FN),
 104
 105         /* GPSR0 */
 106         FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
 107         FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
 108         FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
 109         FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
 110         FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
 111         FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
 112         FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
 113         FN_IP3_14_12, FN_IP3_17_15,
 114
 115         /* GPSR1 */
 116         FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
 117         FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
 118         FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
 119         FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
 120         FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
 121         FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
 122         FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
 123
 124         /* GPSR2 */
 125         FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
 126         FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
 127         FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
 128         FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
 129         FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
 130         FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
 131         FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
 132
 133         /* GPSR3 */
 134         FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
 135         FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
 136         FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
 137         FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
 138         FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
 139         FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
 140         FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
 141
 142         /* GPSR4 */
 143         FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
 144         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
 145         FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
 146         FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
 147         FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
 148         FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
 149         FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
 150         FN_IP14_15_12, FN_IP14_18_16,
 151
 152         /* GPSR5 */
 153         FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
 154         FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
 155         FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
 156         FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
 157         FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
 158         FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
 159         FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
 160
 161         /* IPSR0 */
 162         FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
 163         FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
 164         FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
 165         FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
 166         FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
 167         FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
 168         FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
 169         FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
 170         FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
 171         FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
 172         FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
 173         FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
 174         FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
 175         FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
 176
 177         /* IPSR1 */
 178         FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
 179         FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
 180         FN_SCIFA1_TXD_C, FN_AVB_TXD2,
 181         FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
 182         FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
 183         FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
 184         FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
 185         FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
 186         FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
 187         FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
 188         FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
 189         FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
 190         FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
 191         FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
 192         FN_A0, FN_PWM3, FN_A1, FN_PWM4,
 193
 194         /* IPSR2 */
 195         FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
 196         FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
 197         FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
 198         FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
 199         FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
 200         FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
 201         FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
 202         FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
 203         FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
 204         FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
 205         FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
 206
 207         /* IPSR3 */
 208         FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
 209         FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
 210         FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
 211         FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
 212         FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
 213         FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
 214         FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
 215         FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
 216         FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
 217         FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
 218         FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
 219         FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
 220         FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
 221
 222         /* IPSR4 */
 223         FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
 224         FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
 225         FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
 226         FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
 227         FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
 228         FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
 229         FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
 230         FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
 231         FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
 232         FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
 233         FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
 234         FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
 235         FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
 236         FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
 237         FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
 238
 239         /* IPSR5 */
 240         FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
 241         FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
 242         FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
 243         FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
 244         FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
 245         FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
 246         FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
 247         FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
 248         FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
 249         FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
 250         FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
 251         FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
 252         FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 253         FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
 254         FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
 255         FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
 256         FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
 257         FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
 258         FN_SSI_WS78_B,
 259
 260         /* IPSR6 */
 261         FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
 262         FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
 263         FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 264         FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
 265         FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
 266         FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
 267         FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
 268         FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
 269         FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
 270         FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 271         FN_I2C2_SCL_E, FN_ETH_RX_ER,
 272         FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
 273         FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
 274         FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
 275         FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
 276         FN_HRX0_E, FN_STP_ISSYNC_0_B,
 277         FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
 278         FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
 279         FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
 280         FN_ETH_REF_CLK, FN_HCTS0_N_E,
 281         FN_STP_IVCXO27_1_B, FN_HRX0_F,
 282
 283         /* IPSR7 */
 284         FN_ETH_MDIO, FN_HRTS0_N_E,
 285         FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
 286         FN_HTX0_F, FN_BPFCLK_G,
 287         FN_ETH_TX_EN, FN_SIM0_CLK_C,
 288         FN_HRTS0_N_F, FN_ETH_MAGIC,
 289         FN_SIM0_RST_C, FN_ETH_TXD0,
 290         FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
 291         FN_ETH_MDC, FN_STP_ISD_1_B,
 292         FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
 293         FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
 294         FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
 295         FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
 296         FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
 297         FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
 298         FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
 299         FN_ATACS00_N, FN_AVB_RXD1,
 300         FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
 301
 302         /* IPSR8 */
 303         FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
 304         FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
 305         FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
 306         FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
 307         FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
 308         FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
 309         FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
 310         FN_VI1_CLK, FN_AVB_RX_DV,
 311         FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
 312         FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
 313         FN_SCIFA1_RXD_D, FN_AVB_MDC,
 314         FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
 315         FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
 316         FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
 317         FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
 318         FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
 319         FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
 320         FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
 321
 322         /* IPSR9 */
 323         FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
 324         FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
 325         FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
 326         FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
 327         FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
 328         FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
 329         FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
 330         FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
 331         FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
 332         FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
 333         FN_AVB_TX_EN, FN_SD1_CMD,
 334         FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
 335         FN_SD1_DAT0, FN_AVB_TX_CLK,
 336         FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
 337         FN_SCIFB0_TXD_B, FN_SD1_DAT2,
 338         FN_AVB_COL, FN_SCIFB0_CTS_N_B,
 339         FN_SD1_DAT3, FN_AVB_RXD0,
 340         FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
 341         FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
 342         FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
 343         FN_VI3_CLK_B,
 344
 345         /* IPSR10 */
 346         FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
 347         FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
 348         FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
 349         FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
 350         FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
 351         FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
 352         FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
 353         FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
 354         FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
 355         FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
 356         FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
 357         FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
 358         FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
 359         FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
 360         FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
 361         FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
 362         FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
 363         FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
 364         FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
 365         FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
 366         FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
 367         FN_GLO_I0_B, FN_VI3_DATA6_B,
 368
 369         /* IPSR11 */
 370         FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
 371         FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
 372         FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
 373         FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
 374         FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
 375         FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
 376         FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
 377         FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
 378         FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
 379         FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
 380         FN_FMIN_E, FN_FMIN_F,
 381         FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
 382         FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
 383         FN_I2C2_SDA_B, FN_MLB_DAT,
 384         FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
 385         FN_SSI_SCK0129, FN_CAN_CLK_B,
 386         FN_MOUT0,
 387
 388         /* IPSR12 */
 389         FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
 390         FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
 391         FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
 392         FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
 393         FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
 394         FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
 395         FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
 396         FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
 397         FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
 398         FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
 399         FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
 400         FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
 401         FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
 402         FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
 403         FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
 404         FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
 405         FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
 406         FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
 407         FN_CAN_DEBUGOUT4,
 408
 409         /* IPSR13 */
 410         FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
 411         FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
 412         FN_SCIFB1_CTS_N, FN_BPFCLK_D,
 413         FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
 414         FN_BPFCLK_F, FN_SSI_WS6,
 415         FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
 416         FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
 417         FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
 418         FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
 419         FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
 420         FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
 421         FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
 422         FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
 423         FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
 424         FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
 425         FN_BPFCLK_E, FN_SSI_SDATA7_B,
 426         FN_FMIN_G, FN_SSI_SDATA8,
 427         FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
 428         FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
 429         FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
 430         FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
 431         FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
 432
 433         /* IPSR14 */
 434         FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
 435         FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
 436         FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
 437         FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
 438         FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
 439         FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
 440         FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
 441         FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
 442         FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
 443         FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
 444         FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
 445         FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
 446         FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
 447         FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
 448         FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
 449         FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
 450         FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
 451         FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
 452         FN_HRTS0_N_C,
 453
 454         /* IPSR15 */
 455         FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
 456         FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
 457         FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
 458         FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
 459         FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
 460         FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
 461         FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
 462         FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
 463         FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
 464         FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
 465         FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
 466         FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
 467         FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
 468         FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
 469         FN_DU2_DG6, FN_LCDOUT14,
 470
 471         /* IPSR16 */
 472         FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
 473         FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
 474         FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
 475         FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
 476         FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
 477         FN_TCLK1_B,
 478
 479         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 480         FN_SEL_SCIF1_4,
 481         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
 482         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
 483         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 484         FN_SEL_SCIFB1_4,
 485         FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
 486         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
 487         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
 488         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 489         FN_SEL_SOF1_0, FN_SEL_SOF1_1,
 490         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 491         FN_SEL_SSI6_0, FN_SEL_SSI6_1,
 492         FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
 493         FN_SEL_VI3_0, FN_SEL_VI3_1,
 494         FN_SEL_VI2_0, FN_SEL_VI2_1,
 495         FN_SEL_VI1_0, FN_SEL_VI1_1,
 496         FN_SEL_VI0_0, FN_SEL_VI0_1,
 497         FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
 498         FN_SEL_LBS_0, FN_SEL_LBS_1,
 499         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 500         FN_SEL_SOF3_0, FN_SEL_SOF3_1,
 501         FN_SEL_SOF0_0, FN_SEL_SOF0_1,
 502
 503         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 504         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 505         FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
 506         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 507         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
 508         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
 509         FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 510         FN_SEL_ADI_0, FN_SEL_ADI_1,
 511         FN_SEL_SSP_0, FN_SEL_SSP_1,
 512         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
 513         FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
 514         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
 515         FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
 516         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
 517         FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
 518         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 519
 520         FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
 521         FN_SEL_IIC0_0, FN_SEL_IIC0_1,
 522         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 523         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 524         FN_SEL_IIC2_4,
 525         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 526         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 527         FN_SEL_I2C2_4,
 528         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
 529         PINMUX_FUNCTION_END,
 530
 531         PINMUX_MARK_BEGIN,
 532
 533         VI1_DATA7_VI1_B7_MARK,
 534
 535         USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
 536         USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
 537         DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
 538
 539         D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
 540         D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
 541         VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
 542         VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
 543         VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
 544         SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
 545         VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
 546         SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
 547         VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
 548         IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
 549         I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
 550         VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK,
 551         D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
 552         VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
 553
 554         D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
 555         VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
 556         SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
 557         VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
 558         SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
 559         VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
 560         D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
 561         VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
 562         D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
 563         VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
 564         SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
 565         VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
 566         D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
 567         VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
 568         A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
 569
 570         A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
 571         PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
 572         TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
 573         A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
 574         SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
 575         A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
 576         VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
 577         A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
 578         VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
 579         A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
 580         VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
 581
 582         A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
 583         VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
 584         A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
 585         VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
 586         A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
 587         MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
 588         VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
 589         ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
 590         ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
 591         A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
 592         AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
 593         ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
 594         VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
 595
 596         A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
 597         A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
 598         VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
 599         VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
 600         VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
 601         VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
 602         VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
 603         VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
 604         CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
 605         VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
 606         VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
 607         MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
 608         HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
 609         VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
 610         VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
 611
 612         EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
 613         VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
 614         EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
 615         VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
 616         INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
 617         MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
 618         VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
 619         I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
 620         CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
 621         CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
 622         VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
 623         INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
 624         VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
 625         WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
 626         VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
 627         IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
 628         VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
 629         MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
 630         VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
 631         SSI_WS78_B_MARK,
 632
 633         DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
 634         VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
 635         DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
 636         SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
 637         INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
 638         DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
 639         MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
 640         SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
 641         ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
 642         TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
 643         I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
 644         STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
 645         IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
 646         STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
 647         SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
 648         HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
 649         TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
 650         RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
 651         STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
 652         ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
 653         STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
 654
 655         ETH_MDIO_MARK, HRTS0_N_E_MARK,
 656         SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
 657         HTX0_F_MARK, BPFCLK_G_MARK,
 658         ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
 659         HRTS0_N_F_MARK, ETH_MAGIC_MARK,
 660         SIM0_RST_C_MARK, ETH_TXD0_MARK,
 661         STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
 662         ETH_MDC_MARK, STP_ISD_1_B_MARK,
 663         TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
 664         SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
 665         GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
 666         STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
 667         PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
 668         PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
 669         AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
 670         ATACS00_N_MARK, AVB_RXD1_MARK,
 671         VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
 672
 673         VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
 674         VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
 675         AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
 676         AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
 677         AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
 678         AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
 679         VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
 680         VI1_CLK_MARK, AVB_RX_DV_MARK,
 681         VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
 682         AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
 683         SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
 684         VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
 685         VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
 686         AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
 687         AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
 688         AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
 689         SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
 690         SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
 691
 692         SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
 693         SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
 694         SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
 695         SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
 696         SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
 697         GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
 698         I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
 699         MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
 700         GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
 701         I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
 702         AVB_TX_EN_MARK, SD1_CMD_MARK,
 703         AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
 704         SD1_DAT0_MARK, AVB_TX_CLK_MARK,
 705         SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
 706         SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
 707         AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
 708         SD1_DAT3_MARK, AVB_RXD0_MARK,
 709         SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
 710         TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
 711         IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
 712         VI3_CLK_B_MARK,
 713
 714         SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
 715         GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
 716         SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
 717         VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
 718         VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
 719         VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
 720         TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
 721         SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
 722         VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
 723         TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
 724         SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
 725         VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
 726         TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
 727         SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
 728         VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
 729         GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
 730         MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
 731         HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
 732         VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
 733         TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
 734         VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
 735         GLO_I0_B_MARK, VI3_DATA6_B_MARK,
 736
 737         SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
 738         GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
 739         TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
 740         SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
 741         MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
 742         SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
 743         MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
 744         SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
 745         VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
 746         MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
 747         FMIN_E_MARK, FMIN_F_MARK,
 748         MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
 749         MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
 750         I2C2_SDA_B_MARK, MLB_DAT_MARK,
 751         SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
 752         SSI_SCK0129_MARK, CAN_CLK_B_MARK,
 753         MOUT0_MARK,
 754
 755         SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
 756         SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
 757         SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
 758         SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
 759         SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
 760         MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
 761         STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
 762         CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
 763         SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
 764         SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
 765         MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
 766         SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
 767         MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
 768         SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
 769         CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
 770         IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
 771         CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
 772         IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
 773         CAN_DEBUGOUT4_MARK,
 774
 775         SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
 776         LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
 777         SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
 778         DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
 779         BPFCLK_F_MARK, SSI_WS6_MARK,
 780         SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
 781         LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
 782         FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
 783         CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
 784         SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
 785         CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
 786         SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
 787         LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
 788         STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
 789         TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
 790         BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
 791         FMIN_G_MARK, SSI_SDATA8_MARK,
 792         STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
 793         CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
 794         STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
 795         SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
 796         SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
 797
 798         AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
 799         DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
 800         REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
 801         MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
 802         I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
 803         DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
 804         TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
 805         HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
 806         LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
 807         SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
 808         MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
 809         SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
 810         DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 811         SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
 812         LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
 813         CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
 814         SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
 815         MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
 816         HRTS0_N_C_MARK,
 817
 818         SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
 819         LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
 820         DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
 821         SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
 822         IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
 823         DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
 824         DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
 825         LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
 826         LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
 827         LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
 828         DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
 829         SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
 830         HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
 831         DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
 832         DU2_DG6_MARK, LCDOUT14_MARK,
 833
 834         MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
 835         DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
 836         MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
 837         ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
 838         USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 839         TCLK1_B_MARK,
 840         PINMUX_MARK_END,
 841 };
 842
 843 static const pinmux_enum_t pinmux_data[] = {
 844         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 845
 846         PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
 847         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 848         PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
 849         PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
 850         PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
 851         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 852         PINMUX_DATA(AVS2_MARK, FN_AVS2),
 853         PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
 854         PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
 855
 856         PINMUX_IPSR_DATA(IP0_2_0, D0),
 857         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
 858         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
 859         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
 860         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
 861         PINMUX_IPSR_DATA(IP0_5_3, D1),
 862         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
 863         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
 864         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
 865         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
 866         PINMUX_IPSR_DATA(IP0_8_6, D2),
 867         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
 868         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
 869         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
 870         PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
 871         PINMUX_IPSR_DATA(IP0_11_9, D3),
 872         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
 873         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
 874         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
 875         PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
 876         PINMUX_IPSR_DATA(IP0_15_12, D4),
 877         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
 878         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
 879         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
 880         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
 881         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
 882         PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
 883         PINMUX_IPSR_DATA(IP0_19_16, D5),
 884         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
 885         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
 886         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
 887         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
 888         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
 889         PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
 890         PINMUX_IPSR_DATA(IP0_22_20, D6),
 891         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
 892         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
 893         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
 894         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
 895         PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
 896         PINMUX_IPSR_DATA(IP0_26_23, D7),
 897         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
 898         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
 899         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
 900         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
 901         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
 902         PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
 903         PINMUX_IPSR_DATA(IP0_30_27, D8),
 904         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
 905         PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
 906         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
 907         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
 908         PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
 909
 910         PINMUX_IPSR_DATA(IP1_3_0, D9),
 911         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
 912         PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
 913         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
 914         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
 915         PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
 916         PINMUX_IPSR_DATA(IP1_7_4, D10),
 917         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
 918         PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
 919         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
 920         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
 921         PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
 922         PINMUX_IPSR_DATA(IP1_11_8, D11),
 923         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
 924         PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
 925         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
 926         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
 927         PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
 928         PINMUX_IPSR_DATA(IP1_14_12, D12),
 929         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
 930         PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
 931         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
 932         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
 933         PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
 934         PINMUX_IPSR_DATA(IP1_17_15, D13),
 935         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
 936         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
 937         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
 938         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
 939         PINMUX_IPSR_DATA(IP1_21_18, D14),
 940         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
 941         PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
 942         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
 943         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
 944         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
 945         PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
 946         PINMUX_IPSR_DATA(IP1_25_22, D15),
 947         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
 948         PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
 949         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
 950         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
 951         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
 952         PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
 953         PINMUX_IPSR_DATA(IP1_27_26, A0),
 954         PINMUX_IPSR_DATA(IP1_27_26, PWM3),
 955         PINMUX_IPSR_DATA(IP1_29_28, A1),
 956         PINMUX_IPSR_DATA(IP1_29_28, PWM4),
 957
 958         PINMUX_IPSR_DATA(IP2_2_0, A2),
 959         PINMUX_IPSR_DATA(IP2_2_0, PWM5),
 960         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
 961         PINMUX_IPSR_DATA(IP2_5_3, A3),
 962         PINMUX_IPSR_DATA(IP2_5_3, PWM6),
 963         PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
 964         PINMUX_IPSR_DATA(IP2_8_6, A4),
 965         PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
 966         PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
 967         PINMUX_IPSR_DATA(IP2_11_9, A5),
 968         PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
 969         PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
 970         PINMUX_IPSR_DATA(IP2_14_12, A6),
 971         PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
 972         PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
 973         PINMUX_IPSR_DATA(IP2_17_15, A7),
 974         PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
 975         PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
 976         PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
 977         PINMUX_IPSR_DATA(IP2_21_18, A8),
 978         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
 979         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
 980         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
 981         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
 982         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
 983         PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
 984         PINMUX_IPSR_DATA(IP2_25_22, A9),
 985         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
 986         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
 987         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
 988         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
 989         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
 990         PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
 991         PINMUX_IPSR_DATA(IP2_28_26, A10),
 992         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
 993         PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
 994         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
 995         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
 996         PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
 997
 998         PINMUX_IPSR_DATA(IP3_3_0, A11),
 999         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1000         PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
1001         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
1002         PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
1003         PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
1004         PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
1005         PINMUX_IPSR_DATA(IP3_7_4, A12),
1006         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
1007         PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
1008         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
1009         PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
1010         PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
1011         PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
1012         PINMUX_IPSR_DATA(IP3_11_8, A13),
1013         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1014         PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
1015         PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
1016         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
1017         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
1018         PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
1019         PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
1020         PINMUX_IPSR_DATA(IP3_14_12, A14),
1021         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
1022         PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
1023         PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
1024         PINMUX_IPSR_DATA(IP3_17_15, A15),
1025         PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
1026         PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
1027         PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
1028         PINMUX_IPSR_DATA(IP3_19_18, A16),
1029         PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
1030         PINMUX_IPSR_DATA(IP3_22_20, A17),
1031         PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
1032         PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
1033         PINMUX_IPSR_DATA(IP3_25_23, A18),
1034         PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
1035         PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
1036         PINMUX_IPSR_DATA(IP3_28_26, A19),
1037         PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
1038         PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
1039         PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
1040         PINMUX_IPSR_DATA(IP3_31_29, A20),
1041         PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
1042         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
1043         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
1044         PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
1045
1046         PINMUX_IPSR_DATA(IP4_2_0, A21),
1047         PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
1048         PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
1049         PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1050         PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1051         PINMUX_IPSR_DATA(IP4_5_3, A22),
1052         PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1053         PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1054         PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1055         PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1056         PINMUX_IPSR_DATA(IP4_8_6, A23),
1057         PINMUX_IPSR_DATA(IP4_8_6, IO2),
1058         PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1059         PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1060         PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1061         PINMUX_IPSR_DATA(IP4_11_9, A24),
1062         PINMUX_IPSR_DATA(IP4_11_9, IO3),
1063         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1064         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1065         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1066         PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1067         PINMUX_IPSR_DATA(IP4_14_12, A25),
1068         PINMUX_IPSR_DATA(IP4_14_12, SSL),
1069         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1070         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1071         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1072         PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1073         PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1074         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1075         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1076         PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1077         PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1078         PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1079         PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1080         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1081         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1082         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1083         PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1084         PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1085         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1086         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1087         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1088         PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1089         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1090         PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1091         PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1092         PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1093         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1094         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1095         PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1096         PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1097         PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1098         PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1099         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1100         PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1101         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1102         PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1103         PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1104
1105         PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1106         PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1107         PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1108         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1109         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1110         PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1111         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
1112         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1113         PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1114         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1115         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1116         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1117         PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1118         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1119         PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1120         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1121         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1122         PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1123         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1124         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1125         PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1126         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1127         PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1128         PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1129         PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1130         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1131         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1132         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1133         PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1134         PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1135         PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1136         PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1137         PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1138         PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1139         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1140         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1141         PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1142         PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1143         PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1144         PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1145         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1146         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1147         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1148         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1149         PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1150         PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1151         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1152         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1153         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1154         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1155         PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1156         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1157         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1158         PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
1159         PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1160         PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1161         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1162         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1163         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1164         PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1165         PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1166         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1167         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1168         PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1169         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1170         PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1171
1172         PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1173         PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1174         PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1175         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1176         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1177         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1178         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1179         PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1180         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1181         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1182         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1183         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1184         PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1185         PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1186         PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1187         PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1188         PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1189         PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1190         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1191         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1192         PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1193         PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1194         PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1195         PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1196         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1197         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1198         PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1199         PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1200         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1201         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1202         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1203         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1204         PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1205         PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1206         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1207         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1208         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1209         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1210         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1211         PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1212         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1213         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1214         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1215         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1216         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1217         PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1218         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1219         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1220         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1221         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1222         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1223         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1224         PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1225         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1226         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1227         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1228         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1229         PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1230         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1231         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1232         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1233
1234         PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1235         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1236         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1237         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1238         PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1239         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
1240         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
1241         PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1242         PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1243         PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1244         PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1245         PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1246         PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1247         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1248         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1249         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1250         PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1251         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1252         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1253         PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1254         PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1255         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1256         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1257         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1258         PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1259         PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1260         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1261         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1262         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1263         PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1264         PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1265         PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1266         PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1267         PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1268         PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1269         PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
1270         PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
1271         PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1272         PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1273         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1274         PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1275         PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1276         PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1277         PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1278         PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1279
1280         PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1281         PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1282         PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1283         PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1284         PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1285         PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1286         PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1287         PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1288         PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1289         PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1290         PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1291         PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1292         PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1293         PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1294         PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1295         PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1296         PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1297         PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1298         PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1299         PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1300         PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1301         PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1302         PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1303         PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1304         PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1305         PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1306         PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1307         PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1308         PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1309         PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1310         PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1311         PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1312         PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1313         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1314         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1315         PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1316         PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1317         PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
1318         PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1319         PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1320         PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1321         PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1322         PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1323         PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1324         PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1325
1326         PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1327         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1328         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1329         PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1330         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1331         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1332         PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1333         PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1334         PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1335         PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1336         PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1337         PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1338         PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1339         PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1340         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1341         PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1342         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1343         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1344         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1345         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1346         PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1347         PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1348         PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1349         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1350         PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1351         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1352         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1353         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1354         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1355         PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1356         PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1357         PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1358         PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1359         PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1360         PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1361         PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1362         PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1363         PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1364         PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1365         PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1366         PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1367         PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1368         PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1369         PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1370         PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1371         PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1372         PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1373         PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1374         PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1375         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1376         PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1377         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1378         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1379         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1380         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1381         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1382         PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1383
1384         PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1385         PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1386         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1387         PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1388         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1389         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1390         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1391         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1392         PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1393         PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1394         PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1395         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1396         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1397         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1398         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1399         PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1400         PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1401         PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1402         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1403         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1404         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1405         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1406         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1407         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1408         PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1409         PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1410         PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1411         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1412         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1413         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1414         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1415         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1416         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1417         PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1418         PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1419         PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1420         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1421         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1422         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1423         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1424         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1425         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1426         PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1427         PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1428         PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1429         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1430         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1431         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1432         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1433         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1434         PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1435         PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1436         PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1437         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1438         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1439         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1440         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1441         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1442         PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1443         PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1444         PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1445         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1446         PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1447         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1448         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1449         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1450         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1451         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1452         PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1453
1454         PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1455         PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1456         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1457         PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1458         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1459         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1460         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1461         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1462         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1463         PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1464         PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1465         PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1466         PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1467         PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1468         PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1469         PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1470         PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1471         PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1472         PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1473         PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1474         PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1475         PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1476         PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1477         PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1478         PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1479         PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1480         PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1481         PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1482         PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1483         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1484         PINMUX_IPSR_DATA(IP11_17_15, VSP),
1485         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1486         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1487         PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1488         PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1489         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1490         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1491         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1492         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1493         PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1494         PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1495         PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1496         PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1497         PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1498         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1499         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1500         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1501         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1502         PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1503         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1504         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1505         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1506         PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1507         PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1508         PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1509
1510         PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1511         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1512         PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1513         PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1514         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1515         PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1516         PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1517         PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1518         PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1519         PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1520         PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1521         PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
1522         PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1523         PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1524         PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1525         PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1526         PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1527         PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1528         PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1529         PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1530         PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1531         PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1532         PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1533         PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1534         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1535         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1536         PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1537         PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1538         PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1539         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1540         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1541         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1542         PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1543         PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1544         PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1545         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1546         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1547         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1548         PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1549         PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1550         PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1551         PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1552         PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1553         PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1554         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1555         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1556         PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1557         PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1558         PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1559         PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1560         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1561         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1562         PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1563         PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1564         PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1565         PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1566
1567         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1568         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1569         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1570         PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1571         PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1572         PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1573         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1574         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1575         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1576         PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1577         PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1578         PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1579         PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1580         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1581         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1582         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1583         PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1584         PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1585         PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1586         PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1587         PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1588         PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1589         PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1590         PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1591         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1592         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1593         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1594         PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1595         PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1596         PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1597         PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1598         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1599         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1600         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1601         PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1602         PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1603         PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1604         PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1605         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1606         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1607         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1608         PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1609         PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1610         PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1611         PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1612         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1613         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1614         PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1615         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1616         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1617         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1618         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1619         PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1620         PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1621         PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1622         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1623         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1624         PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1625         PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1626         PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1627         PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1628         PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1629         PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1630
1631         PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1632         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1633         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1634         PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1635         PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1636         PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1637         PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1638         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1639         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1640         PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1641         PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1642         PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1643         PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1644         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1645         PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1646         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1647         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1648         PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1649         PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1650         PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1651         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1652         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1653         PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1654         PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1655         PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1656         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1657         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1658         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
1659         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1660         PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1661         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
1662         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
1663         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1664         PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1665         PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1666         PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1667         PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
1668         PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1669         PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1670         PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1671         PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1672         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1673         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1674         PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1675         PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1676         PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1677         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1678         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1679         PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1680         PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1681         PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1682         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1683         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1684         PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1685         PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1686         PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1687         PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1688         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1689         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1690         PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
1691         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1692         PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1693         PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1694         PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1695
1696         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1697         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1698         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1699         PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1700         PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1701         PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
1702         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1703         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1704         PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1705         PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1706         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1707         PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1708         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1709         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1710         PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1711         PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1712         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1713         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1714         PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1715         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1716         PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1717         PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1718         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
1719         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, I2C2_SDA, SEL_I2C2_0),
1720         PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1721         PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1722         PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1723         PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1724         PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1725         PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1726         PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1727         PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1728         PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1729         PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1730         PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1731         PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1732         PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1733         PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1734         PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1735         PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1736         PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1737         PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1738         PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1739         PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1740         PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1741         PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1742         PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1743         PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1744         PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1745         PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1746         PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1747         PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1748         PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1749         PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1750         PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1751         PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1752         PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1753         PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1754
1755         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1756         PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1757         PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1758         PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1759         PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1760         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1761         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1762         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1763         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1764         PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1765         PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1766         PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1767         PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1768         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1769         PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1770         PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1771         PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1772         PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1773 };
1774
1775 static struct sh_pfc_pin pinmux_pins[] = {
1776         PINMUX_GPIO_GP_ALL(),
1777 };
1778
1779 /* - ETH -------------------------------------------------------------------- */
1780 static const unsigned int eth_link_pins[] = {
1781         /* LINK */
1782         RCAR_GP_PIN(2, 22),
1783 };
1784 static const unsigned int eth_link_mux[] = {
1785         ETH_LINK_MARK,
1786 };
1787 static const unsigned int eth_magic_pins[] = {
1788         /* MAGIC */
1789         RCAR_GP_PIN(2, 27),
1790 };
1791 static const unsigned int eth_magic_mux[] = {
1792         ETH_MAGIC_MARK,
1793 };
1794 static const unsigned int eth_mdio_pins[] = {
1795         /* MDC, MDIO */
1796         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1797 };
1798 static const unsigned int eth_mdio_mux[] = {
1799         ETH_MDC_MARK, ETH_MDIO_MARK,
1800 };
1801 static const unsigned int eth_rmii_pins[] = {
1802         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1803         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1804         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1805         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1806 };
1807 static const unsigned int eth_rmii_mux[] = {
1808         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1809         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1810 };
1811 /* - INTC ------------------------------------------------------------------- */
1812 static const unsigned int intc_irq0_pins[] = {
1813         /* IRQ */
1814         RCAR_GP_PIN(1, 25),
1815 };
1816 static const unsigned int intc_irq0_mux[] = {
1817         IRQ0_MARK,
1818 };
1819 static const unsigned int intc_irq1_pins[] = {
1820         /* IRQ */
1821         RCAR_GP_PIN(1, 27),
1822 };
1823 static const unsigned int intc_irq1_mux[] = {
1824         IRQ1_MARK,
1825 };
1826 static const unsigned int intc_irq2_pins[] = {
1827         /* IRQ */
1828         RCAR_GP_PIN(1, 29),
1829 };
1830 static const unsigned int intc_irq2_mux[] = {
1831         IRQ2_MARK,
1832 };
1833 static const unsigned int intc_irq3_pins[] = {
1834         /* IRQ */
1835         RCAR_GP_PIN(1, 23),
1836 };
1837 static const unsigned int intc_irq3_mux[] = {
1838         IRQ3_MARK,
1839 };
1840 /* - SCIF0 ----------------------------------------------------------------- */
1841 static const unsigned int scif0_data_pins[] = {
1842         /* RX, TX */
1843         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1844 };
1845 static const unsigned int scif0_data_mux[] = {
1846         RX0_MARK, TX0_MARK,
1847 };
1848 static const unsigned int scif0_clk_pins[] = {
1849         /* SCK */
1850         RCAR_GP_PIN(4, 27),
1851 };
1852 static const unsigned int scif0_clk_mux[] = {
1853         SCK0_MARK,
1854 };
1855 static const unsigned int scif0_ctrl_pins[] = {
1856         /* RTS, CTS */
1857         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
1858 };
1859 static const unsigned int scif0_ctrl_mux[] = {
1860         RTS0_N_MARK, CTS0_N_MARK,
1861 };
1862 static const unsigned int scif0_data_b_pins[] = {
1863         /* RX, TX */
1864         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1865 };
1866 static const unsigned int scif0_data_b_mux[] = {
1867         RX0_B_MARK, TX0_B_MARK,
1868 };
1869 /* - SCIF1 ----------------------------------------------------------------- */
1870 static const unsigned int scif1_data_pins[] = {
1871         /* RX, TX */
1872         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1873 };
1874 static const unsigned int scif1_data_mux[] = {
1875         RX1_MARK, TX1_MARK,
1876 };
1877 static const unsigned int scif1_clk_pins[] = {
1878         /* SCK */
1879         RCAR_GP_PIN(4, 20),
1880 };
1881 static const unsigned int scif1_clk_mux[] = {
1882         SCK1_MARK,
1883 };
1884 static const unsigned int scif1_ctrl_pins[] = {
1885         /* RTS, CTS */
1886         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
1887 };
1888 static const unsigned int scif1_ctrl_mux[] = {
1889         RTS1_N_MARK, CTS1_N_MARK,
1890 };
1891 static const unsigned int scif1_data_b_pins[] = {
1892         /* RX, TX */
1893         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1894 };
1895 static const unsigned int scif1_data_b_mux[] = {
1896         RX1_B_MARK, TX1_B_MARK,
1897 };
1898 static const unsigned int scif1_data_c_pins[] = {
1899         /* RX, TX */
1900         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
1901 };
1902 static const unsigned int scif1_data_c_mux[] = {
1903         RX1_C_MARK, TX1_C_MARK,
1904 };
1905 static const unsigned int scif1_data_d_pins[] = {
1906         /* RX, TX */
1907         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1908 };
1909 static const unsigned int scif1_data_d_mux[] = {
1910         RX1_D_MARK, TX1_D_MARK,
1911 };
1912 static const unsigned int scif1_clk_d_pins[] = {
1913         /* SCK */
1914         RCAR_GP_PIN(3, 17),
1915 };
1916 static const unsigned int scif1_clk_d_mux[] = {
1917         SCK1_D_MARK,
1918 };
1919 static const unsigned int scif1_data_e_pins[] = {
1920         /* RX, TX */
1921         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1922 };
1923 static const unsigned int scif1_data_e_mux[] = {
1924         RX1_E_MARK, TX1_E_MARK,
1925 };
1926 static const unsigned int scif1_clk_e_pins[] = {
1927         /* SCK */
1928         RCAR_GP_PIN(2, 20),
1929 };
1930 static const unsigned int scif1_clk_e_mux[] = {
1931         SCK1_E_MARK,
1932 };
1933 /* - HSCIF0 ----------------------------------------------------------------- */
1934 static const unsigned int hscif0_data_pins[] = {
1935         /* RX, TX */
1936         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1937 };
1938 static const unsigned int hscif0_data_mux[] = {
1939         HRX0_MARK, HTX0_MARK,
1940 };
1941 static const unsigned int hscif0_clk_pins[] = {
1942         /* SCK */
1943         RCAR_GP_PIN(5, 7),
1944 };
1945 static const unsigned int hscif0_clk_mux[] = {
1946         HSCK0_MARK,
1947 };
1948 static const unsigned int hscif0_ctrl_pins[] = {
1949         /* RTS, CTS */
1950         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1951 };
1952 static const unsigned int hscif0_ctrl_mux[] = {
1953         HRTS0_N_MARK, HCTS0_N_MARK,
1954 };
1955 static const unsigned int hscif0_data_b_pins[] = {
1956         /* RX, TX */
1957         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
1958 };
1959 static const unsigned int hscif0_data_b_mux[] = {
1960         HRX0_B_MARK, HTX0_B_MARK,
1961 };
1962 static const unsigned int hscif0_ctrl_b_pins[] = {
1963         /* RTS, CTS */
1964         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
1965 };
1966 static const unsigned int hscif0_ctrl_b_mux[] = {
1967         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1968 };
1969 static const unsigned int hscif0_data_c_pins[] = {
1970         /* RX, TX */
1971         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
1972 };
1973 static const unsigned int hscif0_data_c_mux[] = {
1974         HRX0_C_MARK, HTX0_C_MARK,
1975 };
1976 static const unsigned int hscif0_ctrl_c_pins[] = {
1977         /* RTS, CTS */
1978         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
1979 };
1980 static const unsigned int hscif0_ctrl_c_mux[] = {
1981         HRTS0_N_C_MARK, HCTS0_N_C_MARK,
1982 };
1983 static const unsigned int hscif0_data_d_pins[] = {
1984         /* RX, TX */
1985         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1986 };
1987 static const unsigned int hscif0_data_d_mux[] = {
1988         HRX0_D_MARK, HTX0_D_MARK,
1989 };
1990 static const unsigned int hscif0_ctrl_d_pins[] = {
1991         /* RTS, CTS */
1992         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
1993 };
1994 static const unsigned int hscif0_ctrl_d_mux[] = {
1995         HRTS0_N_D_MARK, HCTS0_N_D_MARK,
1996 };
1997 static const unsigned int hscif0_data_e_pins[] = {
1998         /* RX, TX */
1999         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2000 };
2001 static const unsigned int hscif0_data_e_mux[] = {
2002         HRX0_E_MARK, HTX0_E_MARK,
2003 };
2004 static const unsigned int hscif0_ctrl_e_pins[] = {
2005         /* RTS, CTS */
2006         RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2007 };
2008 static const unsigned int hscif0_ctrl_e_mux[] = {
2009         HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2010 };
2011 static const unsigned int hscif0_data_f_pins[] = {
2012         /* RX, TX */
2013         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2014 };
2015 static const unsigned int hscif0_data_f_mux[] = {
2016         HRX0_F_MARK, HTX0_F_MARK,
2017 };
2018 static const unsigned int hscif0_ctrl_f_pins[] = {
2019         /* RTS, CTS */
2020         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2021 };
2022 static const unsigned int hscif0_ctrl_f_mux[] = {
2023         HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2024 };
2025 /* - HSCIF1 ----------------------------------------------------------------- */
2026 static const unsigned int hscif1_data_pins[] = {
2027         /* RX, TX */
2028         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2029 };
2030 static const unsigned int hscif1_data_mux[] = {
2031         HRX1_MARK, HTX1_MARK,
2032 };
2033 static const unsigned int hscif1_clk_pins[] = {
2034         /* SCK */
2035         RCAR_GP_PIN(4, 27),
2036 };
2037 static const unsigned int hscif1_clk_mux[] = {
2038         HSCK1_MARK,
2039 };
2040 static const unsigned int hscif1_ctrl_pins[] = {
2041         /* RTS, CTS */
2042         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2043 };
2044 static const unsigned int hscif1_ctrl_mux[] = {
2045         HRTS1_N_MARK, HCTS1_N_MARK,
2046 };
2047 static const unsigned int hscif1_data_b_pins[] = {
2048         /* RX, TX */
2049         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2050 };
2051 static const unsigned int hscif1_data_b_mux[] = {
2052         HRX1_B_MARK, HTX1_B_MARK,
2053 };
2054 static const unsigned int hscif1_clk_b_pins[] = {
2055         /* SCK */
2056         RCAR_GP_PIN(1, 28),
2057 };
2058 static const unsigned int hscif1_clk_b_mux[] = {
2059         HSCK1_B_MARK,
2060 };
2061 static const unsigned int hscif1_ctrl_b_pins[] = {
2062         /* RTS, CTS */
2063         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2064 };
2065 static const unsigned int hscif1_ctrl_b_mux[] = {
2066         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2067 };
2068 /* - SCIFA0 ----------------------------------------------------------------- */
2069 static const unsigned int scifa0_data_pins[] = {
2070         /* RXD, TXD */
2071         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2072 };
2073 static const unsigned int scifa0_data_mux[] = {
2074         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2075 };
2076 static const unsigned int scifa0_clk_pins[] = {
2077         /* SCK */
2078         RCAR_GP_PIN(4, 27),
2079 };
2080 static const unsigned int scifa0_clk_mux[] = {
2081         SCIFA0_SCK_MARK,
2082 };
2083 static const unsigned int scifa0_ctrl_pins[] = {
2084         /* RTS, CTS */
2085         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2086 };
2087 static const unsigned int scifa0_ctrl_mux[] = {
2088         SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2089 };
2090 static const unsigned int scifa0_data_b_pins[] = {
2091         /* RXD, TXD */
2092         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2093 };
2094 static const unsigned int scifa0_data_b_mux[] = {
2095         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2096 };
2097 static const unsigned int scifa0_clk_b_pins[] = {
2098         /* SCK */
2099         RCAR_GP_PIN(1, 19),
2100 };
2101 static const unsigned int scifa0_clk_b_mux[] = {
2102         SCIFA0_SCK_B_MARK,
2103 };
2104 static const unsigned int scifa0_ctrl_b_pins[] = {
2105         /* RTS, CTS */
2106         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2107 };
2108 static const unsigned int scifa0_ctrl_b_mux[] = {
2109         SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2110 };
2111 /* - SCIFA1 ----------------------------------------------------------------- */
2112 static const unsigned int scifa1_data_pins[] = {
2113         /* RXD, TXD */
2114         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2115 };
2116 static const unsigned int scifa1_data_mux[] = {
2117         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2118 };
2119 static const unsigned int scifa1_clk_pins[] = {
2120         /* SCK */
2121         RCAR_GP_PIN(4, 20),
2122 };
2123 static const unsigned int scifa1_clk_mux[] = {
2124         SCIFA1_SCK_MARK,
2125 };
2126 static const unsigned int scifa1_ctrl_pins[] = {
2127         /* RTS, CTS */
2128         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2129 };
2130 static const unsigned int scifa1_ctrl_mux[] = {
2131         SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2132 };
2133 static const unsigned int scifa1_data_b_pins[] = {
2134         /* RXD, TXD */
2135         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2136 };
2137 static const unsigned int scifa1_data_b_mux[] = {
2138         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2139 };
2140 static const unsigned int scifa1_clk_b_pins[] = {
2141         /* SCK */
2142         RCAR_GP_PIN(0, 23),
2143 };
2144 static const unsigned int scifa1_clk_b_mux[] = {
2145         SCIFA1_SCK_B_MARK,
2146 };
2147 static const unsigned int scifa1_ctrl_b_pins[] = {
2148         /* RTS, CTS */
2149         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2150 };
2151 static const unsigned int scifa1_ctrl_b_mux[] = {
2152         SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2153 };
2154 static const unsigned int scifa1_data_c_pins[] = {
2155         /* RXD, TXD */
2156         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2157 };
2158 static const unsigned int scifa1_data_c_mux[] = {
2159         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2160 };
2161 static const unsigned int scifa1_clk_c_pins[] = {
2162         /* SCK */
2163         RCAR_GP_PIN(0, 8),
2164 };
2165 static const unsigned int scifa1_clk_c_mux[] = {
2166         SCIFA1_SCK_C_MARK,
2167 };
2168 static const unsigned int scifa1_ctrl_c_pins[] = {
2169         /* RTS, CTS */
2170         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2171 };
2172 static const unsigned int scifa1_ctrl_c_mux[] = {
2173         SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2174 };
2175 static const unsigned int scifa1_data_d_pins[] = {
2176         /* RXD, TXD */
2177         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2178 };
2179 static const unsigned int scifa1_data_d_mux[] = {
2180         SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2181 };
2182 static const unsigned int scifa1_clk_d_pins[] = {
2183         /* SCK */
2184         RCAR_GP_PIN(2, 10),
2185 };
2186 static const unsigned int scifa1_clk_d_mux[] = {
2187         SCIFA1_SCK_D_MARK,
2188 };
2189 static const unsigned int scifa1_ctrl_d_pins[] = {
2190         /* RTS, CTS */
2191         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2192 };
2193 static const unsigned int scifa1_ctrl_d_mux[] = {
2194         SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2195 };
2196 /* - SCIFA2 ----------------------------------------------------------------- */
2197 static const unsigned int scifa2_data_pins[] = {
2198         /* RXD, TXD */
2199         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2200 };
2201 static const unsigned int scifa2_data_mux[] = {
2202         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2203 };
2204 static const unsigned int scifa2_clk_pins[] = {
2205         /* SCK */
2206         RCAR_GP_PIN(5, 4),
2207 };
2208 static const unsigned int scifa2_clk_mux[] = {
2209         SCIFA2_SCK_MARK,
2210 };
2211 static const unsigned int scifa2_ctrl_pins[] = {
2212         /* RTS, CTS */
2213         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2214 };
2215 static const unsigned int scifa2_ctrl_mux[] = {
2216         SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2217 };
2218 static const unsigned int scifa2_data_b_pins[] = {
2219         /* RXD, TXD */
2220         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2221 };
2222 static const unsigned int scifa2_data_b_mux[] = {
2223         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2224 };
2225 static const unsigned int scifa2_data_c_pins[] = {
2226         /* RXD, TXD */
2227         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2228 };
2229 static const unsigned int scifa2_data_c_mux[] = {
2230         SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2231 };
2232 static const unsigned int scifa2_clk_c_pins[] = {
2233         /* SCK */
2234         RCAR_GP_PIN(5, 29),
2235 };
2236 static const unsigned int scifa2_clk_c_mux[] = {
2237         SCIFA2_SCK_C_MARK,
2238 };
2239 /* - SCIFB0 ----------------------------------------------------------------- */
2240 static const unsigned int scifb0_data_pins[] = {
2241         /* RXD, TXD */
2242         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2243 };
2244 static const unsigned int scifb0_data_mux[] = {
2245         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2246 };
2247 static const unsigned int scifb0_clk_pins[] = {
2248         /* SCK */
2249         RCAR_GP_PIN(4, 8),
2250 };
2251 static const unsigned int scifb0_clk_mux[] = {
2252         SCIFB0_SCK_MARK,
2253 };
2254 static const unsigned int scifb0_ctrl_pins[] = {
2255         /* RTS, CTS */
2256         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2257 };
2258 static const unsigned int scifb0_ctrl_mux[] = {
2259         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2260 };
2261 static const unsigned int scifb0_data_b_pins[] = {
2262         /* RXD, TXD */
2263         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2264 };
2265 static const unsigned int scifb0_data_b_mux[] = {
2266         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2267 };
2268 static const unsigned int scifb0_clk_b_pins[] = {
2269         /* SCK */
2270         RCAR_GP_PIN(3, 9),
2271 };
2272 static const unsigned int scifb0_clk_b_mux[] = {
2273         SCIFB0_SCK_B_MARK,
2274 };
2275 static const unsigned int scifb0_ctrl_b_pins[] = {
2276         /* RTS, CTS */
2277         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2278 };
2279 static const unsigned int scifb0_ctrl_b_mux[] = {
2280         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2281 };
2282 static const unsigned int scifb0_data_c_pins[] = {
2283         /* RXD, TXD */
2284         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2285 };
2286 static const unsigned int scifb0_data_c_mux[] = {
2287         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2288 };
2289 /* - SCIFB1 ----------------------------------------------------------------- */
2290 static const unsigned int scifb1_data_pins[] = {
2291         /* RXD, TXD */
2292         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2293 };
2294 static const unsigned int scifb1_data_mux[] = {
2295         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2296 };
2297 static const unsigned int scifb1_clk_pins[] = {
2298         /* SCK */
2299         RCAR_GP_PIN(4, 14),
2300 };
2301 static const unsigned int scifb1_clk_mux[] = {
2302         SCIFB1_SCK_MARK,
2303 };
2304 static const unsigned int scifb1_ctrl_pins[] = {
2305         /* RTS, CTS */
2306         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2307 };
2308 static const unsigned int scifb1_ctrl_mux[] = {
2309         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2310 };
2311 static const unsigned int scifb1_data_b_pins[] = {
2312         /* RXD, TXD */
2313         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2314 };
2315 static const unsigned int scifb1_data_b_mux[] = {
2316         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2317 };
2318 static const unsigned int scifb1_clk_b_pins[] = {
2319         /* SCK */
2320         RCAR_GP_PIN(3, 1),
2321 };
2322 static const unsigned int scifb1_clk_b_mux[] = {
2323         SCIFB1_SCK_B_MARK,
2324 };
2325 static const unsigned int scifb1_ctrl_b_pins[] = {
2326         /* RTS, CTS */
2327         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2328 };
2329 static const unsigned int scifb1_ctrl_b_mux[] = {
2330         SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2331 };
2332 static const unsigned int scifb1_data_c_pins[] = {
2333         /* RXD, TXD */
2334         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2335 };
2336 static const unsigned int scifb1_data_c_mux[] = {
2337         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2338 };
2339 static const unsigned int scifb1_data_d_pins[] = {
2340         /* RXD, TXD */
2341         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2342 };
2343 static const unsigned int scifb1_data_d_mux[] = {
2344         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2345 };
2346 static const unsigned int scifb1_data_e_pins[] = {
2347         /* RXD, TXD */
2348         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2349 };
2350 static const unsigned int scifb1_data_e_mux[] = {
2351         SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
2352 };
2353 static const unsigned int scifb1_clk_e_pins[] = {
2354         /* SCK */
2355         RCAR_GP_PIN(3, 17),
2356 };
2357 static const unsigned int scifb1_clk_e_mux[] = {
2358         SCIFB1_SCK_E_MARK,
2359 };
2360 static const unsigned int scifb1_data_f_pins[] = {
2361         /* RXD, TXD */
2362         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2363 };
2364 static const unsigned int scifb1_data_f_mux[] = {
2365         SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
2366 };
2367 static const unsigned int scifb1_data_g_pins[] = {
2368         /* RXD, TXD */
2369         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2370 };
2371 static const unsigned int scifb1_data_g_mux[] = {
2372         SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
2373 };
2374 static const unsigned int scifb1_clk_g_pins[] = {
2375         /* SCK */
2376         RCAR_GP_PIN(2, 20),
2377 };
2378 static const unsigned int scifb1_clk_g_mux[] = {
2379         SCIFB1_SCK_G_MARK,
2380 };
2381 /* - SCIFB2 ----------------------------------------------------------------- */
2382 static const unsigned int scifb2_data_pins[] = {
2383         /* RXD, TXD */
2384         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2385 };
2386 static const unsigned int scifb2_data_mux[] = {
2387         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2388 };
2389 static const unsigned int scifb2_clk_pins[] = {
2390         /* SCK */
2391         RCAR_GP_PIN(4, 21),
2392 };
2393 static const unsigned int scifb2_clk_mux[] = {
2394         SCIFB2_SCK_MARK,
2395 };
2396 static const unsigned int scifb2_ctrl_pins[] = {
2397         /* RTS, CTS */
2398         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
2399 };
2400 static const unsigned int scifb2_ctrl_mux[] = {
2401         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2402 };
2403 static const unsigned int scifb2_data_b_pins[] = {
2404         /* RXD, TXD */
2405         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
2406 };
2407 static const unsigned int scifb2_data_b_mux[] = {
2408         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2409 };
2410 static const unsigned int scifb2_clk_b_pins[] = {
2411         /* SCK */
2412         RCAR_GP_PIN(0, 31),
2413 };
2414 static const unsigned int scifb2_clk_b_mux[] = {
2415         SCIFB2_SCK_B_MARK,
2416 };
2417 static const unsigned int scifb2_ctrl_b_pins[] = {
2418         /* RTS, CTS */
2419         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
2420 };
2421 static const unsigned int scifb2_ctrl_b_mux[] = {
2422         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2423 };
2424 static const unsigned int scifb2_data_c_pins[] = {
2425         /* RXD, TXD */
2426         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2427 };
2428 static const unsigned int scifb2_data_c_mux[] = {
2429         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2430 };
2431 /* - TPU0 ------------------------------------------------------------------- */
2432 static const unsigned int tpu0_to0_pins[] = {
2433         /* TO */
2434         RCAR_GP_PIN(0, 20),
2435 };
2436 static const unsigned int tpu0_to0_mux[] = {
2437         TPU0TO0_MARK,
2438 };
2439 static const unsigned int tpu0_to1_pins[] = {
2440         /* TO */
2441         RCAR_GP_PIN(0, 21),
2442 };
2443 static const unsigned int tpu0_to1_mux[] = {
2444         TPU0TO1_MARK,
2445 };
2446 static const unsigned int tpu0_to2_pins[] = {
2447         /* TO */
2448         RCAR_GP_PIN(0, 22),
2449 };
2450 static const unsigned int tpu0_to2_mux[] = {
2451         TPU0TO2_MARK,
2452 };
2453 static const unsigned int tpu0_to3_pins[] = {
2454         /* TO */
2455         RCAR_GP_PIN(0, 23),
2456 };
2457 static const unsigned int tpu0_to3_mux[] = {
2458         TPU0TO3_MARK,
2459 };
2460 /* - MMCIF0 ----------------------------------------------------------------- */
2461 static const unsigned int mmc0_data1_pins[] = {
2462         /* D[0] */
2463         RCAR_GP_PIN(3, 18),
2464 };
2465 static const unsigned int mmc0_data1_mux[] = {
2466         MMC0_D0_MARK,
2467 };
2468 static const unsigned int mmc0_data4_pins[] = {
2469         /* D[0:3] */
2470         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2471         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2472 };
2473 static const unsigned int mmc0_data4_mux[] = {
2474         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2475 };
2476 static const unsigned int mmc0_data8_pins[] = {
2477         /* D[0:7] */
2478         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2479         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2480         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2481         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2482 };
2483 static const unsigned int mmc0_data8_mux[] = {
2484         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2485         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2486 };
2487 static const unsigned int mmc0_ctrl_pins[] = {
2488         /* CLK, CMD */
2489         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2490 };
2491 static const unsigned int mmc0_ctrl_mux[] = {
2492         MMC0_CLK_MARK, MMC0_CMD_MARK,
2493 };
2494 /* - MMCIF1 ----------------------------------------------------------------- */
2495 static const unsigned int mmc1_data1_pins[] = {
2496         /* D[0] */
2497         RCAR_GP_PIN(3, 26),
2498 };
2499 static const unsigned int mmc1_data1_mux[] = {
2500         MMC1_D0_MARK,
2501 };
2502 static const unsigned int mmc1_data4_pins[] = {
2503         /* D[0:3] */
2504         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2505         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2506 };
2507 static const unsigned int mmc1_data4_mux[] = {
2508         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2509 };
2510 static const unsigned int mmc1_data8_pins[] = {
2511         /* D[0:7] */
2512         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2513         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2514         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2515         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2516 };
2517 static const unsigned int mmc1_data8_mux[] = {
2518         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2519         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2520 };
2521 static const unsigned int mmc1_ctrl_pins[] = {
2522         /* CLK, CMD */
2523         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2524 };
2525 static const unsigned int mmc1_ctrl_mux[] = {
2526         MMC1_CLK_MARK, MMC1_CMD_MARK,
2527 };
2528 /* - SDHI0 ------------------------------------------------------------------ */
2529 static const unsigned int sdhi0_data1_pins[] = {
2530         /* D0 */
2531         RCAR_GP_PIN(3, 2),
2532 };
2533 static const unsigned int sdhi0_data1_mux[] = {
2534         SD0_DAT0_MARK,
2535 };
2536 static const unsigned int sdhi0_data4_pins[] = {
2537         /* D[0:3] */
2538         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2539 };
2540 static const unsigned int sdhi0_data4_mux[] = {
2541         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2542 };
2543 static const unsigned int sdhi0_ctrl_pins[] = {
2544         /* CLK, CMD */
2545         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2546 };
2547 static const unsigned int sdhi0_ctrl_mux[] = {
2548         SD0_CLK_MARK, SD0_CMD_MARK,
2549 };
2550 static const unsigned int sdhi0_cd_pins[] = {
2551         /* CD */
2552         RCAR_GP_PIN(3, 6),
2553 };
2554 static const unsigned int sdhi0_cd_mux[] = {
2555         SD0_CD_MARK,
2556 };
2557 static const unsigned int sdhi0_wp_pins[] = {
2558         /* WP */
2559         RCAR_GP_PIN(3, 7),
2560 };
2561 static const unsigned int sdhi0_wp_mux[] = {
2562         SD0_WP_MARK,
2563 };
2564 /* - SDHI1 ------------------------------------------------------------------ */
2565 static const unsigned int sdhi1_data1_pins[] = {
2566         /* D0 */
2567         RCAR_GP_PIN(3, 10),
2568 };
2569 static const unsigned int sdhi1_data1_mux[] = {
2570         SD1_DAT0_MARK,
2571 };
2572 static const unsigned int sdhi1_data4_pins[] = {
2573         /* D[0:3] */
2574         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2575 };
2576 static const unsigned int sdhi1_data4_mux[] = {
2577         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2578 };
2579 static const unsigned int sdhi1_ctrl_pins[] = {
2580         /* CLK, CMD */
2581         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2582 };
2583 static const unsigned int sdhi1_ctrl_mux[] = {
2584         SD1_CLK_MARK, SD1_CMD_MARK,
2585 };
2586 static const unsigned int sdhi1_cd_pins[] = {
2587         /* CD */
2588         RCAR_GP_PIN(3, 14),
2589 };
2590 static const unsigned int sdhi1_cd_mux[] = {
2591         SD1_CD_MARK,
2592 };
2593 static const unsigned int sdhi1_wp_pins[] = {
2594         /* WP */
2595         RCAR_GP_PIN(3, 15),
2596 };
2597 static const unsigned int sdhi1_wp_mux[] = {
2598         SD1_WP_MARK,
2599 };
2600 /* - SDHI2 ------------------------------------------------------------------ */
2601 static const unsigned int sdhi2_data1_pins[] = {
2602         /* D0 */
2603         RCAR_GP_PIN(3, 18),
2604 };
2605 static const unsigned int sdhi2_data1_mux[] = {
2606         SD2_DAT0_MARK,
2607 };
2608 static const unsigned int sdhi2_data4_pins[] = {
2609         /* D[0:3] */
2610         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2611 };
2612 static const unsigned int sdhi2_data4_mux[] = {
2613         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2614 };
2615 static const unsigned int sdhi2_ctrl_pins[] = {
2616         /* CLK, CMD */
2617         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2618 };
2619 static const unsigned int sdhi2_ctrl_mux[] = {
2620         SD2_CLK_MARK, SD2_CMD_MARK,
2621 };
2622 static const unsigned int sdhi2_cd_pins[] = {
2623         /* CD */
2624         RCAR_GP_PIN(3, 22),
2625 };
2626 static const unsigned int sdhi2_cd_mux[] = {
2627         SD2_CD_MARK,
2628 };
2629 static const unsigned int sdhi2_wp_pins[] = {
2630         /* WP */
2631         RCAR_GP_PIN(3, 23),
2632 };
2633 static const unsigned int sdhi2_wp_mux[] = {
2634         SD2_WP_MARK,
2635 };
2636 /* - SDHI3 ------------------------------------------------------------------ */
2637 static const unsigned int sdhi3_data1_pins[] = {
2638         /* D0 */
2639         RCAR_GP_PIN(3, 26),
2640 };
2641 static const unsigned int sdhi3_data1_mux[] = {
2642         SD3_DAT0_MARK,
2643 };
2644 static const unsigned int sdhi3_data4_pins[] = {
2645         /* D[0:3] */
2646         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2647 };
2648 static const unsigned int sdhi3_data4_mux[] = {
2649         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2650 };
2651 static const unsigned int sdhi3_ctrl_pins[] = {
2652         /* CLK, CMD */
2653         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2654 };
2655 static const unsigned int sdhi3_ctrl_mux[] = {
2656         SD3_CLK_MARK, SD3_CMD_MARK,
2657 };
2658 static const unsigned int sdhi3_cd_pins[] = {
2659         /* CD */
2660         RCAR_GP_PIN(3, 30),
2661 };
2662 static const unsigned int sdhi3_cd_mux[] = {
2663         SD3_CD_MARK,
2664 };
2665 static const unsigned int sdhi3_wp_pins[] = {
2666         /* WP */
2667         RCAR_GP_PIN(3, 31),
2668 };
2669 static const unsigned int sdhi3_wp_mux[] = {
2670         SD3_WP_MARK,
2671 };
2672
2673 static const struct sh_pfc_pin_group pinmux_groups[] = {
2674         SH_PFC_PIN_GROUP(eth_link),
2675         SH_PFC_PIN_GROUP(eth_magic),
2676         SH_PFC_PIN_GROUP(eth_mdio),
2677         SH_PFC_PIN_GROUP(eth_rmii),
2678         SH_PFC_PIN_GROUP(hscif0_data),
2679         SH_PFC_PIN_GROUP(hscif0_clk),
2680         SH_PFC_PIN_GROUP(hscif0_ctrl),
2681         SH_PFC_PIN_GROUP(hscif0_data_b),
2682         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2683         SH_PFC_PIN_GROUP(hscif0_data_c),
2684         SH_PFC_PIN_GROUP(hscif0_ctrl_c),
2685         SH_PFC_PIN_GROUP(hscif0_data_d),
2686         SH_PFC_PIN_GROUP(hscif0_ctrl_d),
2687         SH_PFC_PIN_GROUP(hscif0_data_e),
2688         SH_PFC_PIN_GROUP(hscif0_ctrl_e),
2689         SH_PFC_PIN_GROUP(hscif0_data_f),
2690         SH_PFC_PIN_GROUP(hscif0_ctrl_f),
2691         SH_PFC_PIN_GROUP(hscif1_data),
2692         SH_PFC_PIN_GROUP(hscif1_clk),
2693         SH_PFC_PIN_GROUP(hscif1_ctrl),
2694         SH_PFC_PIN_GROUP(hscif1_data_b),
2695         SH_PFC_PIN_GROUP(hscif1_clk_b),
2696         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2697         SH_PFC_PIN_GROUP(intc_irq0),
2698         SH_PFC_PIN_GROUP(intc_irq1),
2699         SH_PFC_PIN_GROUP(intc_irq2),
2700         SH_PFC_PIN_GROUP(intc_irq3),
2701         SH_PFC_PIN_GROUP(mmc0_data1),
2702         SH_PFC_PIN_GROUP(mmc0_data4),
2703         SH_PFC_PIN_GROUP(mmc0_data8),
2704         SH_PFC_PIN_GROUP(mmc0_ctrl),
2705         SH_PFC_PIN_GROUP(mmc1_data1),
2706         SH_PFC_PIN_GROUP(mmc1_data4),
2707         SH_PFC_PIN_GROUP(mmc1_data8),
2708         SH_PFC_PIN_GROUP(mmc1_ctrl),
2709         SH_PFC_PIN_GROUP(scif0_data),
2710         SH_PFC_PIN_GROUP(scif0_clk),
2711         SH_PFC_PIN_GROUP(scif0_ctrl),
2712         SH_PFC_PIN_GROUP(scif0_data_b),
2713         SH_PFC_PIN_GROUP(scif1_data),
2714         SH_PFC_PIN_GROUP(scif1_clk),
2715         SH_PFC_PIN_GROUP(scif1_ctrl),
2716         SH_PFC_PIN_GROUP(scif1_data_b),
2717         SH_PFC_PIN_GROUP(scif1_data_c),
2718         SH_PFC_PIN_GROUP(scif1_data_d),
2719         SH_PFC_PIN_GROUP(scif1_clk_d),
2720         SH_PFC_PIN_GROUP(scif1_data_e),
2721         SH_PFC_PIN_GROUP(scif1_clk_e),
2722         SH_PFC_PIN_GROUP(scifa0_data),
2723         SH_PFC_PIN_GROUP(scifa0_clk),
2724         SH_PFC_PIN_GROUP(scifa0_ctrl),
2725         SH_PFC_PIN_GROUP(scifa0_data_b),
2726         SH_PFC_PIN_GROUP(scifa0_clk_b),
2727         SH_PFC_PIN_GROUP(scifa0_ctrl_b),
2728         SH_PFC_PIN_GROUP(scifa1_data),
2729         SH_PFC_PIN_GROUP(scifa1_clk),
2730         SH_PFC_PIN_GROUP(scifa1_ctrl),
2731         SH_PFC_PIN_GROUP(scifa1_data_b),
2732         SH_PFC_PIN_GROUP(scifa1_clk_b),
2733         SH_PFC_PIN_GROUP(scifa1_ctrl_b),
2734         SH_PFC_PIN_GROUP(scifa1_data_c),
2735         SH_PFC_PIN_GROUP(scifa1_clk_c),
2736         SH_PFC_PIN_GROUP(scifa1_ctrl_c),
2737         SH_PFC_PIN_GROUP(scifa1_data_d),
2738         SH_PFC_PIN_GROUP(scifa1_clk_d),
2739         SH_PFC_PIN_GROUP(scifa1_ctrl_d),
2740         SH_PFC_PIN_GROUP(scifa2_data),
2741         SH_PFC_PIN_GROUP(scifa2_clk),
2742         SH_PFC_PIN_GROUP(scifa2_ctrl),
2743         SH_PFC_PIN_GROUP(scifa2_data_b),
2744         SH_PFC_PIN_GROUP(scifa2_data_c),
2745         SH_PFC_PIN_GROUP(scifa2_clk_c),
2746         SH_PFC_PIN_GROUP(scifb0_data),
2747         SH_PFC_PIN_GROUP(scifb0_clk),
2748         SH_PFC_PIN_GROUP(scifb0_ctrl),
2749         SH_PFC_PIN_GROUP(scifb0_data_b),
2750         SH_PFC_PIN_GROUP(scifb0_clk_b),
2751         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
2752         SH_PFC_PIN_GROUP(scifb0_data_c),
2753         SH_PFC_PIN_GROUP(scifb1_data),
2754         SH_PFC_PIN_GROUP(scifb1_clk),
2755         SH_PFC_PIN_GROUP(scifb1_ctrl),
2756         SH_PFC_PIN_GROUP(scifb1_data_b),
2757         SH_PFC_PIN_GROUP(scifb1_clk_b),
2758         SH_PFC_PIN_GROUP(scifb1_ctrl_b),
2759         SH_PFC_PIN_GROUP(scifb1_data_c),
2760         SH_PFC_PIN_GROUP(scifb1_data_d),
2761         SH_PFC_PIN_GROUP(scifb1_data_e),
2762         SH_PFC_PIN_GROUP(scifb1_clk_e),
2763         SH_PFC_PIN_GROUP(scifb1_data_f),
2764         SH_PFC_PIN_GROUP(scifb1_data_g),
2765         SH_PFC_PIN_GROUP(scifb1_clk_g),
2766         SH_PFC_PIN_GROUP(scifb2_data),
2767         SH_PFC_PIN_GROUP(scifb2_clk),
2768         SH_PFC_PIN_GROUP(scifb2_ctrl),
2769         SH_PFC_PIN_GROUP(scifb2_data_b),
2770         SH_PFC_PIN_GROUP(scifb2_clk_b),
2771         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
2772         SH_PFC_PIN_GROUP(scifb2_data_c),
2773         SH_PFC_PIN_GROUP(sdhi0_data1),
2774         SH_PFC_PIN_GROUP(sdhi0_data4),
2775         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2776         SH_PFC_PIN_GROUP(sdhi0_cd),
2777         SH_PFC_PIN_GROUP(sdhi0_wp),
2778         SH_PFC_PIN_GROUP(sdhi1_data1),
2779         SH_PFC_PIN_GROUP(sdhi1_data4),
2780         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2781         SH_PFC_PIN_GROUP(sdhi1_cd),
2782         SH_PFC_PIN_GROUP(sdhi1_wp),
2783         SH_PFC_PIN_GROUP(sdhi2_data1),
2784         SH_PFC_PIN_GROUP(sdhi2_data4),
2785         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2786         SH_PFC_PIN_GROUP(sdhi2_cd),
2787         SH_PFC_PIN_GROUP(sdhi2_wp),
2788         SH_PFC_PIN_GROUP(sdhi3_data1),
2789         SH_PFC_PIN_GROUP(sdhi3_data4),
2790         SH_PFC_PIN_GROUP(sdhi3_ctrl),
2791         SH_PFC_PIN_GROUP(sdhi3_cd),
2792         SH_PFC_PIN_GROUP(sdhi3_wp),
2793         SH_PFC_PIN_GROUP(tpu0_to0),
2794         SH_PFC_PIN_GROUP(tpu0_to1),
2795         SH_PFC_PIN_GROUP(tpu0_to2),
2796         SH_PFC_PIN_GROUP(tpu0_to3),
2797 };
2798
2799 static const char * const eth_groups[] = {
2800         "eth_link",
2801         "eth_magic",
2802         "eth_mdio",
2803         "eth_rmii",
2804 };
2805
2806 static const char * const intc_groups[] = {
2807         "intc_irq0",
2808         "intc_irq1",
2809         "intc_irq2",
2810         "intc_irq3",
2811 };
2812
2813 static const char * const scif0_groups[] = {
2814         "scif0_data",
2815         "scif0_clk",
2816         "scif0_ctrl",
2817         "scif0_data_b",
2818 };
2819
2820 static const char * const scif1_groups[] = {
2821         "scif1_data",
2822         "scif1_clk",
2823         "scif1_ctrl",
2824         "scif1_data_b",
2825         "scif1_data_c",
2826         "scif1_data_d",
2827         "scif1_clk_d",
2828         "scif1_data_e",
2829         "scif1_clk_e",
2830 };
2831
2832 static const char * const hscif0_groups[] = {
2833         "hscif0_data",
2834         "hscif0_clk",
2835         "hscif0_ctrl",
2836         "hscif0_data_b",
2837         "hscif0_ctrl_b",
2838         "hscif0_data_c",
2839         "hscif0_ctrl_c",
2840         "hscif0_data_d",
2841         "hscif0_ctrl_d",
2842         "hscif0_data_e",
2843         "hscif0_ctrl_e",
2844         "hscif0_data_f",
2845         "hscif0_ctrl_f",
2846 };
2847
2848 static const char * const hscif1_groups[] = {
2849         "hscif1_data",
2850         "hscif1_clk",
2851         "hscif1_ctrl",
2852         "hscif1_data_b",
2853         "hscif1_clk_b",
2854         "hscif1_ctrl_b",
2855 };
2856
2857 static const char * const scifa0_groups[] = {
2858         "scifa0_data",
2859         "scifa0_clk",
2860         "scifa0_ctrl",
2861         "scifa0_data_b",
2862         "scifa0_clk_b",
2863         "scifa0_ctrl_b",
2864 };
2865
2866 static const char * const scifa1_groups[] = {
2867         "scifa1_data",
2868         "scifa1_clk",
2869         "scifa1_ctrl",
2870         "scifa1_data_b",
2871         "scifa1_clk_b",
2872         "scifa1_ctrl_b",
2873         "scifa1_data_c",
2874         "scifa1_clk_c",
2875         "scifa1_ctrl_c",
2876         "scifa1_data_d",
2877         "scifa1_clk_d",
2878         "scifa1_ctrl_d",
2879 };
2880
2881 static const char * const scifa2_groups[] = {
2882         "scifa2_data",
2883         "scifa2_clk",
2884         "scifa2_ctrl",
2885         "scifa2_data_b",
2886         "scifa2_data_c",
2887         "scifa2_clk_c",
2888 };
2889
2890 static const char * const scifb0_groups[] = {
2891         "scifb0_data",
2892         "scifb0_clk",
2893         "scifb0_ctrl",
2894         "scifb0_data_b",
2895         "scifb0_clk_b",
2896         "scifb0_ctrl_b",
2897         "scifb0_data_c",
2898 };
2899
2900 static const char * const scifb1_groups[] = {
2901         "scifb1_data",
2902         "scifb1_clk",
2903         "scifb1_ctrl",
2904         "scifb1_data_b",
2905         "scifb1_clk_b",
2906         "scifb1_ctrl_b",
2907         "scifb1_data_c",
2908         "scifb1_data_d",
2909         "scifb1_data_e",
2910         "scifb1_clk_e",
2911         "scifb1_data_f",
2912         "scifb1_data_g",
2913         "scifb1_clk_g",
2914 };
2915
2916 static const char * const scifb2_groups[] = {
2917         "scifb2_data",
2918         "scifb2_clk",
2919         "scifb2_ctrl",
2920         "scifb2_data_b",
2921         "scifb2_clk_b",
2922         "scifb2_ctrl_b",
2923         "scifb2_data_c",
2924 };
2925
2926 static const char * const tpu0_groups[] = {
2927         "tpu0_to0",
2928         "tpu0_to1",
2929         "tpu0_to2",
2930         "tpu0_to3",
2931 };
2932
2933 static const char * const mmc0_groups[] = {
2934         "mmc0_data1",
2935         "mmc0_data4",
2936         "mmc0_data8",
2937         "mmc0_ctrl",
2938 };
2939
2940 static const char * const mmc1_groups[] = {
2941         "mmc1_data1",
2942         "mmc1_data4",
2943         "mmc1_data8",
2944         "mmc1_ctrl",
2945 };
2946
2947 static const char * const sdhi0_groups[] = {
2948         "sdhi0_data1",
2949         "sdhi0_data4",
2950         "sdhi0_ctrl",
2951         "sdhi0_cd",
2952         "sdhi0_wp",
2953 };
2954
2955 static const char * const sdhi1_groups[] = {
2956         "sdhi1_data1",
2957         "sdhi1_data4",
2958         "sdhi1_ctrl",
2959         "sdhi1_cd",
2960         "sdhi1_wp",
2961 };
2962
2963 static const char * const sdhi2_groups[] = {
2964         "sdhi2_data1",
2965         "sdhi2_data4",
2966         "sdhi2_ctrl",
2967         "sdhi2_cd",
2968         "sdhi2_wp",
2969 };
2970
2971 static const char * const sdhi3_groups[] = {
2972         "sdhi3_data1",
2973         "sdhi3_data4",
2974         "sdhi3_ctrl",
2975         "sdhi3_cd",
2976         "sdhi3_wp",
2977 };
2978
2979 static const struct sh_pfc_function pinmux_functions[] = {
2980         SH_PFC_FUNCTION(eth),
2981         SH_PFC_FUNCTION(hscif0),
2982         SH_PFC_FUNCTION(hscif1),
2983         SH_PFC_FUNCTION(intc),
2984         SH_PFC_FUNCTION(mmc0),
2985         SH_PFC_FUNCTION(mmc1),
2986         SH_PFC_FUNCTION(scif0),
2987         SH_PFC_FUNCTION(scif1),
2988         SH_PFC_FUNCTION(scifa0),
2989         SH_PFC_FUNCTION(scifa1),
2990         SH_PFC_FUNCTION(scifa2),
2991         SH_PFC_FUNCTION(scifb0),
2992         SH_PFC_FUNCTION(scifb1),
2993         SH_PFC_FUNCTION(scifb2),
2994         SH_PFC_FUNCTION(sdhi0),
2995         SH_PFC_FUNCTION(sdhi1),
2996         SH_PFC_FUNCTION(sdhi2),
2997         SH_PFC_FUNCTION(sdhi3),
2998         SH_PFC_FUNCTION(tpu0),
2999 };
3000
3001 static struct pinmux_cfg_reg pinmux_config_regs[] = {
3002         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3003                 GP_0_31_FN, FN_IP3_17_15,
3004                 GP_0_30_FN, FN_IP3_14_12,
3005                 GP_0_29_FN, FN_IP3_11_8,
3006                 GP_0_28_FN, FN_IP3_7_4,
3007                 GP_0_27_FN, FN_IP3_3_0,
3008                 GP_0_26_FN, FN_IP2_28_26,
3009                 GP_0_25_FN, FN_IP2_25_22,
3010                 GP_0_24_FN, FN_IP2_21_18,
3011                 GP_0_23_FN, FN_IP2_17_15,
3012                 GP_0_22_FN, FN_IP2_14_12,
3013                 GP_0_21_FN, FN_IP2_11_9,
3014                 GP_0_20_FN, FN_IP2_8_6,
3015                 GP_0_19_FN, FN_IP2_5_3,
3016                 GP_0_18_FN, FN_IP2_2_0,
3017                 GP_0_17_FN, FN_IP1_29_28,
3018                 GP_0_16_FN, FN_IP1_27_26,
3019                 GP_0_15_FN, FN_IP1_25_22,
3020                 GP_0_14_FN, FN_IP1_21_18,
3021                 GP_0_13_FN, FN_IP1_17_15,
3022                 GP_0_12_FN, FN_IP1_14_12,
3023                 GP_0_11_FN, FN_IP1_11_8,
3024                 GP_0_10_FN, FN_IP1_7_4,
3025                 GP_0_9_FN, FN_IP1_3_0,
3026                 GP_0_8_FN, FN_IP0_30_27,
3027                 GP_0_7_FN, FN_IP0_26_23,
3028                 GP_0_6_FN, FN_IP0_22_20,
3029                 GP_0_5_FN, FN_IP0_19_16,
3030                 GP_0_4_FN, FN_IP0_15_12,
3031                 GP_0_3_FN, FN_IP0_11_9,
3032                 GP_0_2_FN, FN_IP0_8_6,
3033                 GP_0_1_FN, FN_IP0_5_3,
3034                 GP_0_0_FN, FN_IP0_2_0 }
3035         },
3036         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3037                 0, 0,
3038                 0, 0,
3039                 GP_1_29_FN, FN_IP6_13_11,
3040                 GP_1_28_FN, FN_IP6_10_9,
3041                 GP_1_27_FN, FN_IP6_8_6,
3042                 GP_1_26_FN, FN_IP6_5_3,
3043                 GP_1_25_FN, FN_IP6_2_0,
3044                 GP_1_24_FN, FN_IP5_29_27,
3045                 GP_1_23_FN, FN_IP5_26_24,
3046                 GP_1_22_FN, FN_IP5_23_21,
3047                 GP_1_21_FN, FN_IP5_20_18,
3048                 GP_1_20_FN, FN_IP5_17_15,
3049                 GP_1_19_FN, FN_IP5_14_13,
3050                 GP_1_18_FN, FN_IP5_12_10,
3051                 GP_1_17_FN, FN_IP5_9_6,
3052                 GP_1_16_FN, FN_IP5_5_3,
3053                 GP_1_15_FN, FN_IP5_2_0,
3054                 GP_1_14_FN, FN_IP4_29_27,
3055                 GP_1_13_FN, FN_IP4_26_24,
3056                 GP_1_12_FN, FN_IP4_23_21,
3057                 GP_1_11_FN, FN_IP4_20_18,
3058                 GP_1_10_FN, FN_IP4_17_15,
3059                 GP_1_9_FN, FN_IP4_14_12,
3060                 GP_1_8_FN, FN_IP4_11_9,
3061                 GP_1_7_FN, FN_IP4_8_6,
3062                 GP_1_6_FN, FN_IP4_5_3,
3063                 GP_1_5_FN, FN_IP4_2_0,
3064                 GP_1_4_FN, FN_IP3_31_29,
3065                 GP_1_3_FN, FN_IP3_28_26,
3066                 GP_1_2_FN, FN_IP3_25_23,
3067                 GP_1_1_FN, FN_IP3_22_20,
3068                 GP_1_0_FN, FN_IP3_19_18, }
3069         },
3070         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3071                 0, 0,
3072                 0, 0,
3073                 GP_2_29_FN, FN_IP7_15_13,
3074                 GP_2_28_FN, FN_IP7_12_10,
3075                 GP_2_27_FN, FN_IP7_9_8,
3076                 GP_2_26_FN, FN_IP7_7_6,
3077                 GP_2_25_FN, FN_IP7_5_3,
3078                 GP_2_24_FN, FN_IP7_2_0,
3079                 GP_2_23_FN, FN_IP6_31_29,
3080                 GP_2_22_FN, FN_IP6_28_26,
3081                 GP_2_21_FN, FN_IP6_25_23,
3082                 GP_2_20_FN, FN_IP6_22_20,
3083                 GP_2_19_FN, FN_IP6_19_17,
3084                 GP_2_18_FN, FN_IP6_16_14,
3085                 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
3086                 GP_2_16_FN, FN_IP8_27,
3087                 GP_2_15_FN, FN_IP8_26,
3088                 GP_2_14_FN, FN_IP8_25_24,
3089                 GP_2_13_FN, FN_IP8_23_22,
3090                 GP_2_12_FN, FN_IP8_21_20,
3091                 GP_2_11_FN, FN_IP8_19_18,
3092                 GP_2_10_FN, FN_IP8_17_16,
3093                 GP_2_9_FN, FN_IP8_15_14,
3094                 GP_2_8_FN, FN_IP8_13_12,
3095                 GP_2_7_FN, FN_IP8_11_10,
3096                 GP_2_6_FN, FN_IP8_9_8,
3097                 GP_2_5_FN, FN_IP8_7_6,
3098                 GP_2_4_FN, FN_IP8_5_4,
3099                 GP_2_3_FN, FN_IP8_3_2,
3100                 GP_2_2_FN, FN_IP8_1_0,
3101                 GP_2_1_FN, FN_IP7_30_29,
3102                 GP_2_0_FN, FN_IP7_28_27 }
3103         },
3104         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3105                 GP_3_31_FN, FN_IP11_21_18,
3106                 GP_3_30_FN, FN_IP11_17_15,
3107                 GP_3_29_FN, FN_IP11_14_13,
3108                 GP_3_28_FN, FN_IP11_12_11,
3109                 GP_3_27_FN, FN_IP11_10_9,
3110                 GP_3_26_FN, FN_IP11_8_7,
3111                 GP_3_25_FN, FN_IP11_6_5,
3112                 GP_3_24_FN, FN_IP11_4,
3113                 GP_3_23_FN, FN_IP11_3_0,
3114                 GP_3_22_FN, FN_IP10_29_26,
3115                 GP_3_21_FN, FN_IP10_25_23,
3116                 GP_3_20_FN, FN_IP10_22_19,
3117                 GP_3_19_FN, FN_IP10_18_15,
3118                 GP_3_18_FN, FN_IP10_14_11,
3119                 GP_3_17_FN, FN_IP10_10_7,
3120                 GP_3_16_FN, FN_IP10_6_4,
3121                 GP_3_15_FN, FN_IP10_3_0,
3122                 GP_3_14_FN, FN_IP9_31_28,
3123                 GP_3_13_FN, FN_IP9_27_26,
3124                 GP_3_12_FN, FN_IP9_25_24,
3125                 GP_3_11_FN, FN_IP9_23_22,
3126                 GP_3_10_FN, FN_IP9_21_20,
3127                 GP_3_9_FN, FN_IP9_19_18,
3128                 GP_3_8_FN, FN_IP9_17_16,
3129                 GP_3_7_FN, FN_IP9_15_12,
3130                 GP_3_6_FN, FN_IP9_11_8,
3131                 GP_3_5_FN, FN_IP9_7_6,
3132                 GP_3_4_FN, FN_IP9_5_4,
3133                 GP_3_3_FN, FN_IP9_3_2,
3134                 GP_3_2_FN, FN_IP9_1_0,
3135                 GP_3_1_FN, FN_IP8_30_29,
3136                 GP_3_0_FN, FN_IP8_28 }
3137         },
3138         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3139                 GP_4_31_FN, FN_IP14_18_16,
3140                 GP_4_30_FN, FN_IP14_15_12,
3141                 GP_4_29_FN, FN_IP14_11_9,
3142                 GP_4_28_FN, FN_IP14_8_6,
3143                 GP_4_27_FN, FN_IP14_5_3,
3144                 GP_4_26_FN, FN_IP14_2_0,
3145                 GP_4_25_FN, FN_IP13_30_29,
3146                 GP_4_24_FN, FN_IP13_28_26,
3147                 GP_4_23_FN, FN_IP13_25_23,
3148                 GP_4_22_FN, FN_IP13_22_19,
3149                 GP_4_21_FN, FN_IP13_18_16,
3150                 GP_4_20_FN, FN_IP13_15_13,
3151                 GP_4_19_FN, FN_IP13_12_10,
3152                 GP_4_18_FN, FN_IP13_9_7,
3153                 GP_4_17_FN, FN_IP13_6_3,
3154                 GP_4_16_FN, FN_IP13_2_0,
3155                 GP_4_15_FN, FN_IP12_30_28,
3156                 GP_4_14_FN, FN_IP12_27_25,
3157                 GP_4_13_FN, FN_IP12_24_23,
3158                 GP_4_12_FN, FN_IP12_22_20,
3159                 GP_4_11_FN, FN_IP12_19_17,
3160                 GP_4_10_FN, FN_IP12_16_14,
3161                 GP_4_9_FN, FN_IP12_13_11,
3162                 GP_4_8_FN, FN_IP12_10_8,
3163                 GP_4_7_FN, FN_IP12_7_6,
3164                 GP_4_6_FN, FN_IP12_5_4,
3165                 GP_4_5_FN, FN_IP12_3_2,
3166                 GP_4_4_FN, FN_IP12_1_0,
3167                 GP_4_3_FN, FN_IP11_31_30,
3168                 GP_4_2_FN, FN_IP11_29_27,
3169                 GP_4_1_FN, FN_IP11_26_24,
3170                 GP_4_0_FN, FN_IP11_23_22 }
3171         },
3172         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3173                 GP_5_31_FN, FN_IP7_24_22,
3174                 GP_5_30_FN, FN_IP7_21_19,
3175                 GP_5_29_FN, FN_IP7_18_16,
3176                 GP_5_28_FN, FN_DU_DOTCLKIN2,
3177                 GP_5_27_FN, FN_IP7_26_25,
3178                 GP_5_26_FN, FN_DU_DOTCLKIN0,
3179                 GP_5_25_FN, FN_AVS2,
3180                 GP_5_24_FN, FN_AVS1,
3181                 GP_5_23_FN, FN_USB2_OVC,
3182                 GP_5_22_FN, FN_USB2_PWEN,
3183                 GP_5_21_FN, FN_IP16_7,
3184                 GP_5_20_FN, FN_IP16_6,
3185                 GP_5_19_FN, FN_USB0_OVC_VBUS,
3186                 GP_5_18_FN, FN_USB0_PWEN,
3187                 GP_5_17_FN, FN_IP16_5_3,
3188                 GP_5_16_FN, FN_IP16_2_0,
3189                 GP_5_15_FN, FN_IP15_29_28,
3190                 GP_5_14_FN, FN_IP15_27_26,
3191                 GP_5_13_FN, FN_IP15_25_23,
3192                 GP_5_12_FN, FN_IP15_22_20,
3193                 GP_5_11_FN, FN_IP15_19_18,
3194                 GP_5_10_FN, FN_IP15_17_16,
3195                 GP_5_9_FN, FN_IP15_15_14,
3196                 GP_5_8_FN, FN_IP15_13_12,
3197                 GP_5_7_FN, FN_IP15_11_9,
3198                 GP_5_6_FN, FN_IP15_8_6,
3199                 GP_5_5_FN, FN_IP15_5_3,
3200                 GP_5_4_FN, FN_IP15_2_0,
3201                 GP_5_3_FN, FN_IP14_30_28,
3202                 GP_5_2_FN, FN_IP14_27_25,
3203                 GP_5_1_FN, FN_IP14_24_22,
3204                 GP_5_0_FN, FN_IP14_21_19 }
3205         },
3206         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3207                              1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
3208                 /* IP0_31 [1] */
3209                 0, 0,
3210                 /* IP0_30_27 [4] */
3211                 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
3212                 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
3213                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3214                 /* IP0_26_23 [4] */
3215                 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
3216                 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
3217                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3218                 /* IP0_22_20 [3] */
3219                 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
3220                 FN_I2C2_SCL_C, 0, 0,
3221                 /* IP0_19_16 [4] */
3222                 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
3223                 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
3224                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3225                 /* IP0_15_12 [4] */
3226                 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
3227                 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
3228                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3229                 /* IP0_11_9 [3] */
3230                 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
3231                 0, 0, 0,
3232                 /* IP0_8_6 [3] */
3233                 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
3234                 0, 0, 0,
3235                 /* IP0_5_3 [3] */
3236                 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
3237                 0, 0, 0,
3238                 /* IP0_2_0 [3] */
3239                 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
3240                 0, 0, 0, }
3241         },
3242         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3243                              2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
3244                 /* IP1_31_30 [2] */
3245                 0, 0, 0, 0,
3246                 /* IP1_29_28 [2] */
3247                 FN_A1, FN_PWM4, 0, 0,
3248                 /* IP1_27_26 [2] */
3249                 FN_A0, FN_PWM3, 0, 0,
3250                 /* IP1_25_22 [4] */
3251                 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
3252                 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
3253                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3254                 /* IP1_21_18 [4] */
3255                 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
3256                 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
3257                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3258                 /* IP1_17_15 [3] */
3259                 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
3260                 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
3261                 0, 0, 0,
3262                 /* IP1_14_12 [3] */
3263                 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
3264                 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
3265                 0, 0,
3266                 /* IP1_11_8 [4] */
3267                 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
3268                 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
3269                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3270                 /* IP1_7_4 [4] */
3271                 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
3272                 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
3273                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3274                 /* IP1_3_0 [4] */
3275                 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
3276                 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
3277                 0, 0, 0, 0, 0, 0, 0, 0, 0, }
3278         },
3279         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3280                              3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
3281                 /* IP2_31_29 [3] */
3282                 0, 0, 0, 0, 0, 0, 0, 0,
3283                 /* IP2_28_26 [3] */
3284                 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
3285                 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
3286                 /* IP2_25_22 [4] */
3287                 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
3288                 FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
3289                 0, 0, 0, 0, 0, 0, 0, 0,
3290                 /* IP2_21_18 [4] */
3291                 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
3292                 FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
3293                 0, 0, 0, 0, 0, 0, 0, 0,
3294                 /* IP2_17_15 [3] */
3295                 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
3296                 0, 0, 0, 0,
3297                 /* IP2_14_12 [3] */
3298                 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
3299                 /* IP2_11_9 [3] */
3300                 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
3301                 /* IP2_8_6 [3] */
3302                 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
3303                 /* IP2_5_3 [3] */
3304                 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
3305                 /* IP2_2_0 [3] */
3306                 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
3307         },
3308         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3309                              3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
3310                 /* IP3_31_29 [3] */
3311                 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
3312                 0, 0, 0,
3313                 /* IP3_28_26 [3] */
3314                 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
3315                 0, 0, 0, 0,
3316                 /* IP3_25_23 [3] */
3317                 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
3318                 /* IP3_22_20 [3] */
3319                 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
3320                 /* IP3_19_18 [2] */
3321                 FN_A16, FN_ATAWR1_N, 0, 0,
3322                 /* IP3_17_15 [3] */
3323                 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
3324                 0, 0, 0, 0,
3325                 /* IP3_14_12 [3] */
3326                 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
3327                 0, 0, 0, 0,
3328                 /* IP3_11_8 [4] */
3329                 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
3330                 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
3331                 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
3332                 /* IP3_7_4 [4] */
3333                 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
3334                 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
3335                 0, 0, 0, 0, 0, 0, 0, 0, 0,
3336                 /* IP3_3_0 [4] */
3337                 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
3338                 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
3339                 0, 0, 0, 0, 0, 0, 0, 0, }
3340         },
3341         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3342                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3343                 /* IP4_31_30 [2] */
3344                 0, 0, 0, 0,
3345                 /* IP4_29_27 [3] */
3346                 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
3347                 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
3348                 /* IP4_26_24 [3] */
3349                 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
3350                 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
3351                 /* IP4_23_21 [3] */
3352                 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
3353                 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
3354                 /* IP4_20_18 [3] */
3355                 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
3356                 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
3357                 /* IP4_17_15 [3] */
3358                 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
3359                 0, 0, 0,
3360                 /* IP4_14_12 [3] */
3361                 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
3362                 FN_VI2_FIELD_B, 0, 0,
3363                 /* IP4_11_9 [3] */
3364                 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
3365                 FN_VI2_CLKENB_B, 0, 0,
3366                 /* IP4_8_6 [3] */
3367                 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
3368                 /* IP4_5_3 [3] */
3369                 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
3370                 /* IP4_2_0 [3] */
3371                 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
3372                 }
3373         },
3374         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3375                              2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
3376                 /* IP5_31_30 [2] */
3377                 0, 0, 0, 0,
3378                 /* IP5_29_27 [3] */
3379                 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
3380                 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
3381                 /* IP5_26_24 [3] */
3382                 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
3383                 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
3384                 FN_MSIOF0_SCK_B, 0,
3385                 /* IP5_23_21 [3] */
3386                 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
3387                 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
3388                 FN_IERX_C, 0,
3389                 /* IP5_20_18 [3] */
3390                 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
3391                 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
3392                 /* IP5_17_15 [3] */
3393                 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
3394                 FN_INTC_IRQ4_N, 0, 0,
3395                 /* IP5_14_13 [2] */
3396                 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
3397                 /* IP5_12_10 [3] */
3398                 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
3399                 0, 0,
3400                 /* IP5_9_6 [4] */
3401                 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
3402                 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
3403                 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
3404                 /* IP5_5_3 [3] */
3405                 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
3406                 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
3407                 FN_INTC_EN0_N, FN_I2C1_SCL,
3408                 /* IP5_2_0 [3] */
3409                 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
3410                 FN_VI2_R3, 0, 0, }
3411         },
3412         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3413                              3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
3414                 /* IP6_31_29 [3] */
3415                 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
3416                 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
3417                 /* IP6_28_26 [3] */
3418                 FN_ETH_LINK, 0, FN_HTX0_E,
3419                 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
3420                 /* IP6_25_23 [3] */
3421                 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
3422                 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
3423                 /* IP6_22_20 [3] */
3424                 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
3425                 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
3426                 /* IP6_19_17 [3] */
3427                 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
3428                 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
3429                 /* IP6_16_14 [3] */
3430                 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
3431                 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
3432                 FN_I2C2_SCL_E, 0,
3433                 /* IP6_13_11 [3] */
3434                 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
3435                 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
3436                 /* IP6_10_9 [2] */
3437                 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
3438                 /* IP6_8_6 [3] */
3439                 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
3440                 FN_SSI_SDATA8_C, 0, 0, 0,
3441                 /* IP6_5_3 [3] */
3442                 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
3443                 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
3444                 /* IP6_2_0 [3] */
3445                 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
3446                 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
3447         },
3448         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3449                              1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
3450                 /* IP7_31 [1] */
3451                 0, 0,
3452                 /* IP7_30_29 [2] */
3453                 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
3454                 /* IP7_28_27 [2] */
3455                 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
3456                 /* IP7_26_25 [2] */
3457                 FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
3458                 /* IP7_24_22 [3] */
3459                 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
3460                 0, 0, 0,
3461                 /* IP7_21_19 [3] */
3462                 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
3463                 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
3464                 /* IP7_18_16 [3] */
3465                 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
3466                 FN_GLO_SS_C, 0, 0, 0,
3467                 /* IP7_15_13 [3] */
3468                 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
3469                 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
3470                 /* IP7_12_10 [3] */
3471                 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
3472                 FN_GLO_SCLK_C, 0, 0, 0,
3473                 /* IP7_9_8 [2] */
3474                 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
3475                 /* IP7_7_6 [2] */
3476                 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
3477                 /* IP7_5_3 [3] */
3478                 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
3479                 /* IP7_2_0 [3] */
3480                 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
3481                 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
3482         },
3483         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3484                              1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
3485                              2, 2, 2, 2, 2, 2, 2) {
3486                 /* IP8_31 [1] */
3487                 0, 0,
3488                 /* IP8_30_29 [2] */
3489                 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
3490                 /* IP8_28 [1] */
3491                 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
3492                 /* IP8_27 [1] */
3493                 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
3494                 /* IP8_26 [1] */
3495                 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
3496                 /* IP8_25_24 [2] */
3497                 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
3498                 FN_AVB_MAGIC, 0,
3499                 /* IP8_23_22 [2] */
3500                 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
3501                 /* IP8_21_20 [2] */
3502                 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
3503                 /* IP8_19_18 [2] */
3504                 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
3505                 /* IP8_17_16 [2] */
3506                 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
3507                 /* IP8_15_14 [2] */
3508                 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
3509                 /* IP8_13_12 [2] */
3510                 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
3511                 /* IP8_11_10 [2] */
3512                 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
3513                 /* IP8_9_8 [2] */
3514                 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
3515                 /* IP8_7_6 [2] */
3516                 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
3517                 /* IP8_5_4 [2] */
3518                 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
3519                 /* IP8_3_2 [2] */
3520                 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
3521                 /* IP8_1_0 [2] */
3522                 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
3523         },
3524         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3525                              4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
3526                 /* IP9_31_28 [4] */
3527                 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
3528                 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
3529                 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
3530                 /* IP9_27_26 [2] */
3531                 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
3532                 /* IP9_25_24 [2] */
3533                 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
3534                 /* IP9_23_22 [2] */
3535                 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
3536                 /* IP9_21_20 [2] */
3537                 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
3538                 /* IP9_19_18 [2] */
3539                 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
3540                 /* IP9_17_16 [2] */
3541                 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
3542                 /* IP9_15_12 [4] */
3543                 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
3544                 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
3545                 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
3546                 /* IP9_11_8 [4] */
3547                 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
3548                 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
3549                 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
3550                 /* IP9_7_6 [2] */
3551                 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
3552                 /* IP9_5_4 [2] */
3553                 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
3554                 /* IP9_3_2 [2] */
3555                 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
3556                 /* IP9_1_0 [2] */
3557                 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
3558         },
3559         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3560                              2, 4, 3, 4, 4, 4, 4, 3, 4) {
3561                 /* IP10_31_30 [2] */
3562                 0, 0, 0, 0,
3563                 /* IP10_29_26 [4] */
3564                 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
3565                 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
3566                 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
3567                 /* IP10_25_23 [3] */
3568                 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
3569                 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
3570                 /* IP10_22_19 [4] */
3571                 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
3572                 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
3573                 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
3574                 /* IP10_18_15 [4] */
3575                 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
3576                 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
3577                 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
3578                 0, 0, 0, 0, 0, 0,
3579                 /* IP10_14_11 [4] */
3580                 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
3581                 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
3582                 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
3583                 0, 0, 0, 0, 0, 0, 0,
3584                 /* IP10_10_7 [4] */
3585                 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
3586                 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
3587                 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
3588                 0, 0, 0, 0, 0, 0, 0,
3589                 /* IP10_6_4 [3] */
3590                 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
3591                 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
3592                 FN_VI3_DATA0_B, 0,
3593                 /* IP10_3_0 [4] */
3594                 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
3595                 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
3596                 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
3597         },
3598         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3599                              2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
3600                 /* IP11_31_30 [2] */
3601                 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
3602                 /* IP11_29_27 [3] */
3603                 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
3604                 0, 0, 0,
3605                 /* IP11_26_24 [3] */
3606                 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
3607                 0, 0, 0,
3608                 /* IP11_23_22 [2] */
3609                 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
3610                 /* IP11_21_18 [4] */
3611                 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
3612                 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
3613                 /* IP11_17_15 [3] */
3614                 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
3615                 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
3616                 /* IP11_14_13 [2] */
3617                 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
3618                 /* IP11_12_11 [2] */
3619                 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
3620                 /* IP11_10_9 [2] */
3621                 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
3622                 /* IP11_8_7 [2] */
3623                 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
3624                 /* IP11_6_5 [2] */
3625                 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
3626                 /* IP11_4 [1] */
3627                 FN_SD3_CLK, FN_MMC1_CLK,
3628                 /* IP11_3_0 [4] */
3629                 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
3630                 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
3631                 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
3632         },
3633         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3634                              1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
3635                 /* IP12_31 [1] */
3636                 0, 0,
3637                 /* IP12_30_28 [3] */
3638                 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
3639                 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
3640                 FN_CAN_DEBUGOUT4, 0, 0,
3641                 /* IP12_27_25 [3] */
3642                 FN_SSI_SCK5, FN_SCIFB1_SCK,
3643                 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
3644                 FN_CAN_DEBUGOUT3, 0, 0,
3645                 /* IP12_24_23 [2] */
3646                 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
3647                 FN_CAN_DEBUGOUT2,
3648                 /* IP12_22_20 [3] */
3649                 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
3650                 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
3651                 /* IP12_19_17 [3] */
3652                 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
3653                 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
3654                 /* IP12_16_14 [3] */
3655                 FN_SSI_SDATA3, FN_STP_ISCLK_0,
3656                 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
3657                 /* IP12_13_11 [3] */
3658                 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
3659                 FN_CAN_STEP0, 0, 0, 0,
3660                 /* IP12_10_8 [3] */
3661                 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
3662                 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
3663                 /* IP12_7_6 [2] */
3664                 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
3665                 /* IP12_5_4 [2] */
3666                 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
3667                 /* IP12_3_2 [2] */
3668                 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
3669                 /* IP12_1_0 [2] */
3670                 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
3671         },
3672         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
3673                              1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
3674                 /* IP13_31 [1] */
3675                 0, 0,
3676                 /* IP13_30_29 [2] */
3677                 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
3678                 /* IP13_28_26 [3] */
3679                 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
3680                 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
3681                 /* IP13_25_23 [3] */
3682                 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
3683                 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
3684                 /* IP13_22_19 [4] */
3685                 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
3686                 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
3687                 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
3688                 /* IP13_18_16 [3] */
3689                 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
3690                 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
3691                 /* IP13_15_13 [3] */
3692                 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
3693                 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
3694                 /* IP13_12_10 [3] */
3695                 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
3696                 FN_CAN_DEBUGOUT8, 0, 0,
3697                 /* IP13_9_7 [3] */
3698                 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
3699                 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
3700                 /* IP13_6_3 [4] */
3701                 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
3702                 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
3703                 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
3704                 /* IP13_2_0 [3] */
3705                 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
3706                 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
3707         },
3708         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
3709                              1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
3710                 /* IP14_30 [1] */
3711                 0, 0,
3712                 /* IP14_30_28 [3] */
3713                 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
3714                 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
3715                 FN_HRTS0_N_C, 0,
3716                 /* IP14_27_25 [3] */
3717                 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
3718                 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
3719                 /* IP14_24_22 [3] */
3720                 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
3721                 FN_LCDOUT9, 0, 0, 0,
3722                 /* IP14_21_19 [3] */
3723                 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
3724                 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
3725                 /* IP14_18_16 [3] */
3726                 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
3727                 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
3728                 /* IP14_15_12 [4] */
3729                 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
3730                 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
3731                 0, 0, 0, 0, 0, 0, 0,
3732                 /* IP14_11_9 [3] */
3733                 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
3734                 0, 0, 0,
3735                 /* IP14_8_6 [3] */
3736                 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
3737                 0, 0, 0,
3738                 /* IP14_5_3 [3] */
3739                 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
3740                 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
3741                 /* IP14_2_0 [3] */
3742                 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
3743                 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
3744                 FN_REMOCON, 0, }
3745         },
3746         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
3747                              2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
3748                 /* IP15_31_30 [2] */
3749                 0, 0, 0, 0,
3750                 /* IP15_29_28 [2] */
3751                 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
3752                 /* IP15_27_26 [2] */
3753                 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
3754                 /* IP15_25_23 [3] */
3755                 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
3756                 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
3757                 /* IP15_22_20 [3] */
3758                 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
3759                 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
3760                 /* IP15_19_18 [2] */
3761                 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
3762                 /* IP15_17_16 [2] */
3763                 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
3764                 /* IP15_15_14 [2] */
3765                 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
3766                 /* IP15_13_12 [2] */
3767                 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
3768                 /* IP15_11_9 [3] */
3769                 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
3770                 0, 0, 0,
3771                 /* IP15_8_6 [3] */
3772                 FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
3773                 FN_IIC2_SDA, FN_I2C2_SDA, 0,
3774                 /* IP15_5_3 [3] */
3775                 FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
3776                 FN_IIC2_SCL, FN_I2C2_SCL, 0,
3777                 /* IP15_2_0 [3] */
3778                 FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
3779                 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
3780         },
3781         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
3782                              4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
3783                 /* IP16_31_28 [4] */
3784                 0, 0, 0, 0, 0, 0, 0, 0,
3785                 0, 0, 0, 0, 0, 0, 0, 0,
3786                 /* IP16_27_24 [4] */
3787                 0, 0, 0, 0, 0, 0, 0, 0,
3788                 0, 0, 0, 0, 0, 0, 0, 0,
3789                 /* IP16_23_20 [4] */
3790                 0, 0, 0, 0, 0, 0, 0, 0,
3791                 0, 0, 0, 0, 0, 0, 0, 0,
3792                 /* IP16_19_16 [4] */
3793                 0, 0, 0, 0, 0, 0, 0, 0,
3794                 0, 0, 0, 0, 0, 0, 0, 0,
3795                 /* IP16_15_12 [4] */
3796                 0, 0, 0, 0, 0, 0, 0, 0,
3797                 0, 0, 0, 0, 0, 0, 0, 0,
3798                 /* IP16_11_8 [4] */
3799                 0, 0, 0, 0, 0, 0, 0, 0,
3800                 0, 0, 0, 0, 0, 0, 0, 0,
3801                 /* IP16_7 [1] */
3802                 FN_USB1_OVC, FN_TCLK1_B,
3803                 /* IP16_6 [1] */
3804                 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
3805                 /* IP16_5_3 [3] */
3806                 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
3807                 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
3808                 /* IP16_2_0 [3] */
3809                 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
3810                 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
3811         },
3812         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
3813                              3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
3814                              2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
3815                 /* SEL_SCIF1 [3] */
3816                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
3817                 FN_SEL_SCIF1_4, 0, 0, 0,
3818                 /* SEL_SCIFB [2] */
3819                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
3820                 /* SEL_SCIFB2 [2] */
3821                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
3822                 /* SEL_SCIFB1 [3] */
3823                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
3824                 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
3825                 FN_SEL_SCIFB1_6, 0,
3826                 /* SEL_SCIFA1 [2] */
3827                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
3828                 FN_SEL_SCIFA1_3,
3829                 /* SEL_SCIF0 [1] */
3830                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
3831                 /* SEL_SCIFA [1] */
3832                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
3833                 /* SEL_SOF1 [1] */
3834                 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
3835                 /* SEL_SSI7 [2] */
3836                 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3837                 /* SEL_SSI6 [1] */
3838                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
3839                 /* SEL_SSI5 [2] */
3840                 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
3841                 /* SEL_VI3 [1] */
3842                 FN_SEL_VI3_0, FN_SEL_VI3_1,
3843                 /* SEL_VI2 [1] */
3844                 FN_SEL_VI2_0, FN_SEL_VI2_1,
3845                 /* SEL_VI1 [1] */
3846                 FN_SEL_VI1_0, FN_SEL_VI1_1,
3847                 /* SEL_VI0 [1] */
3848                 FN_SEL_VI0_0, FN_SEL_VI0_1,
3849                 /* SEL_TSIF1 [2] */
3850                 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
3851                 /* RESERVED [1] */
3852                 0, 0,
3853                 /* SEL_LBS [1] */
3854                 FN_SEL_LBS_0, FN_SEL_LBS_1,
3855                 /* SEL_TSIF0 [2] */
3856                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
3857                 /* SEL_SOF3 [1] */
3858                 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
3859                 /* SEL_SOF0 [1] */
3860                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
3861         },
3862         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
3863                              3, 1, 1, 1, 2, 1, 2, 1, 2,
3864                              1, 1, 1, 3, 3, 2, 3, 2, 2) {
3865                 /* RESERVED [3] */
3866                 0, 0, 0, 0, 0, 0, 0, 0,
3867                 /* SEL_TMU1 [1] */
3868                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
3869                 /* SEL_HSCIF1 [1] */
3870                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3871                 /* SEL_SCIFCLK [1] */
3872                 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
3873                 /* SEL_CAN0 [2] */
3874                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
3875                 /* SEL_CANCLK [1] */
3876                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
3877                 /* SEL_SCIFA2 [2] */
3878                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
3879                 /* SEL_CAN1 [1] */
3880                 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
3881                 /* RESERVED [2] */
3882                 0, 0, 0, 0,
3883                 /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
3884                 0, 0,
3885                 /* SEL_ADI [1] */
3886                 FN_SEL_ADI_0, FN_SEL_ADI_1,
3887                 /* SEL_SSP [1] */
3888                 FN_SEL_SSP_0, FN_SEL_SSP_1,
3889                 /* SEL_FM [3] */
3890                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
3891                 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
3892                 /* SEL_HSCIF0 [3] */
3893                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
3894                 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
3895                 /* SEL_GPS [2] */
3896                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
3897                 /* RESERVED [3] */
3898                 0, 0, 0, 0, 0, 0, 0, 0,
3899                 /* SEL_SIM [2] */
3900                 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
3901                 /* SEL_SSI8 [2] */
3902                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
3903         },
3904         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
3905                              1, 1, 2, 4, 4, 2, 2,
3906                              4, 2, 3, 2, 3, 2) {
3907                 /* SEL_IICDVFS [1] */
3908                 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
3909                 /* SEL_IIC0 [1] */
3910                 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
3911                 /* RESERVED [2] */
3912                 0, 0, 0, 0,
3913                 /* RESERVED [4] */
3914                 0, 0, 0, 0, 0, 0, 0, 0,
3915                 0, 0, 0, 0, 0, 0, 0, 0,
3916                 /* RESERVED [4] */
3917                 0, 0, 0, 0, 0, 0, 0, 0,
3918                 0, 0, 0, 0, 0, 0, 0, 0,
3919                 /* RESERVED [2] */
3920                 0, 0, 0, 0,
3921                 /* SEL_IEB [2] */
3922                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
3923                 /* RESERVED [4] */
3924                 0, 0, 0, 0, 0, 0, 0, 0,
3925                 0, 0, 0, 0, 0, 0, 0, 0,
3926                 /* RESERVED [2] */
3927                 0, 0, 0, 0,
3928                 /* SEL_IIC2 [3] */
3929                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
3930                 FN_SEL_IIC2_4, 0, 0, 0,
3931                 /* SEL_IIC1 [2] */
3932                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
3933                 /* SEL_I2C2 [3] */
3934                 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3935                 FN_SEL_I2C2_4, 0, 0, 0,
3936                 /* SEL_I2C1 [2] */
3937                 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
3938         },
3939         { },
3940 };
3941
3942 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
3943         .name = "r8a77900_pfc",
3944         .unlock_reg = 0xe6060000, /* PMMR */
3945
3946         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3947
3948         .pins = pinmux_pins,
3949         .nr_pins = ARRAY_SIZE(pinmux_pins),
3950         .groups = pinmux_groups,
3951         .nr_groups = ARRAY_SIZE(pinmux_groups),
3952         .functions = pinmux_functions,
3953         .nr_functions = ARRAY_SIZE(pinmux_functions),
3954
3955         .cfg_regs = pinmux_config_regs,
3956
3957         .gpio_data = pinmux_data,
3958         .gpio_data_size = ARRAY_SIZE(pinmux_data),
3959 };