2 * Freescale FlexTimer Module (FTM) PWM Driver
4 * Copyright 2012-2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
25 #define FTM_SC_CLK_MASK_SHIFT 3
26 #define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT)
27 #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
28 #define FTM_SC_PS_MASK 0x7
33 #define FTM_CSC_BASE 0x0C
34 #define FTM_CSC_MSB BIT(5)
35 #define FTM_CSC_MSA BIT(4)
36 #define FTM_CSC_ELSB BIT(3)
37 #define FTM_CSC_ELSA BIT(2)
38 #define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8))
40 #define FTM_CV_BASE 0x10
41 #define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8))
43 #define FTM_CNTIN 0x4C
44 #define FTM_STATUS 0x50
47 #define FTM_MODE_FTMEN BIT(0)
48 #define FTM_MODE_INIT BIT(2)
49 #define FTM_MODE_PWMSYNC BIT(3)
52 #define FTM_OUTINIT 0x5C
53 #define FTM_OUTMASK 0x60
54 #define FTM_COMBINE 0x64
55 #define FTM_DEADTIME 0x68
56 #define FTM_EXTTRIG 0x6C
59 #define FTM_FILTER 0x78
60 #define FTM_FLTCTRL 0x7C
61 #define FTM_QDCTRL 0x80
63 #define FTM_FLTPOL 0x88
64 #define FTM_SYNCONF 0x8C
65 #define FTM_INVCTRL 0x90
66 #define FTM_SWOCTRL 0x94
67 #define FTM_PWMLOAD 0x98
82 unsigned int use_count
;
83 unsigned int cnt_select
;
86 struct regmap
*regmap
;
90 struct clk
*clk
[FSL_PWM_CLK_MAX
];
93 static inline struct fsl_pwm_chip
*to_fsl_chip(struct pwm_chip
*chip
)
95 return container_of(chip
, struct fsl_pwm_chip
, chip
);
98 static int fsl_pwm_request(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
100 struct fsl_pwm_chip
*fpc
= to_fsl_chip(chip
);
102 return clk_prepare_enable(fpc
->clk
[FSL_PWM_CLK_SYS
]);
105 static void fsl_pwm_free(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
107 struct fsl_pwm_chip
*fpc
= to_fsl_chip(chip
);
109 clk_disable_unprepare(fpc
->clk
[FSL_PWM_CLK_SYS
]);
112 static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip
*fpc
,
113 enum fsl_pwm_clk index
)
115 unsigned long sys_rate
, cnt_rate
;
116 unsigned long long ratio
;
118 sys_rate
= clk_get_rate(fpc
->clk
[FSL_PWM_CLK_SYS
]);
122 cnt_rate
= clk_get_rate(fpc
->clk
[fpc
->cnt_select
]);
127 case FSL_PWM_CLK_SYS
:
130 case FSL_PWM_CLK_FIX
:
131 ratio
= 2 * cnt_rate
- 1;
132 do_div(ratio
, sys_rate
);
135 case FSL_PWM_CLK_EXT
:
136 ratio
= 4 * cnt_rate
- 1;
137 do_div(ratio
, sys_rate
);
147 static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip
*fpc
,
148 unsigned long period_ns
)
150 unsigned long long c
, c0
;
152 c
= clk_get_rate(fpc
->clk
[fpc
->cnt_select
]);
154 do_div(c
, 1000000000UL);
158 do_div(c0
, (1 << fpc
->clk_ps
));
160 return (unsigned long)c0
;
161 } while (++fpc
->clk_ps
< 8);
166 static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip
*fpc
,
167 unsigned long period_ns
,
168 enum fsl_pwm_clk index
)
172 ret
= fsl_pwm_calculate_default_ps(fpc
, index
);
174 dev_err(fpc
->chip
.dev
,
175 "failed to calculate default prescaler: %d\n",
180 return fsl_pwm_calculate_cycles(fpc
, period_ns
);
183 static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip
*fpc
,
184 unsigned long period_ns
)
186 enum fsl_pwm_clk m0
, m1
;
187 unsigned long fix_rate
, ext_rate
, cycles
;
189 cycles
= fsl_pwm_calculate_period_cycles(fpc
, period_ns
,
192 fpc
->cnt_select
= FSL_PWM_CLK_SYS
;
196 fix_rate
= clk_get_rate(fpc
->clk
[FSL_PWM_CLK_FIX
]);
197 ext_rate
= clk_get_rate(fpc
->clk
[FSL_PWM_CLK_EXT
]);
199 if (fix_rate
> ext_rate
) {
200 m0
= FSL_PWM_CLK_FIX
;
201 m1
= FSL_PWM_CLK_EXT
;
203 m0
= FSL_PWM_CLK_EXT
;
204 m1
= FSL_PWM_CLK_FIX
;
207 cycles
= fsl_pwm_calculate_period_cycles(fpc
, period_ns
, m0
);
209 fpc
->cnt_select
= m0
;
213 fpc
->cnt_select
= m1
;
215 return fsl_pwm_calculate_period_cycles(fpc
, period_ns
, m1
);
218 static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip
*fpc
,
219 unsigned long period_ns
,
220 unsigned long duty_ns
)
222 unsigned long long duty
;
225 regmap_read(fpc
->regmap
, FTM_MOD
, &val
);
226 duty
= (unsigned long long)duty_ns
* (val
+ 1);
227 do_div(duty
, period_ns
);
229 return (unsigned long)duty
;
232 static int fsl_pwm_config(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
233 int duty_ns
, int period_ns
)
235 struct fsl_pwm_chip
*fpc
= to_fsl_chip(chip
);
238 mutex_lock(&fpc
->lock
);
241 * The Freescale FTM controller supports only a single period for
242 * all PWM channels, therefore incompatible changes need to be
245 if (fpc
->period_ns
&& fpc
->period_ns
!= period_ns
) {
246 dev_err(fpc
->chip
.dev
,
247 "conflicting period requested for PWM %u\n",
249 mutex_unlock(&fpc
->lock
);
253 if (!fpc
->period_ns
&& duty_ns
) {
254 period
= fsl_pwm_calculate_period(fpc
, period_ns
);
256 dev_err(fpc
->chip
.dev
, "failed to calculate period\n");
257 mutex_unlock(&fpc
->lock
);
261 regmap_update_bits(fpc
->regmap
, FTM_SC
, FTM_SC_PS_MASK
,
263 regmap_write(fpc
->regmap
, FTM_MOD
, period
- 1);
265 fpc
->period_ns
= period_ns
;
268 mutex_unlock(&fpc
->lock
);
270 duty
= fsl_pwm_calculate_duty(fpc
, period_ns
, duty_ns
);
272 regmap_write(fpc
->regmap
, FTM_CSC(pwm
->hwpwm
),
273 FTM_CSC_MSB
| FTM_CSC_ELSB
);
274 regmap_write(fpc
->regmap
, FTM_CV(pwm
->hwpwm
), duty
);
279 static int fsl_pwm_set_polarity(struct pwm_chip
*chip
,
280 struct pwm_device
*pwm
,
281 enum pwm_polarity polarity
)
283 struct fsl_pwm_chip
*fpc
= to_fsl_chip(chip
);
286 regmap_read(fpc
->regmap
, FTM_POL
, &val
);
288 if (polarity
== PWM_POLARITY_INVERSED
)
289 val
|= BIT(pwm
->hwpwm
);
291 val
&= ~BIT(pwm
->hwpwm
);
293 regmap_write(fpc
->regmap
, FTM_POL
, val
);
298 static int fsl_counter_clock_enable(struct fsl_pwm_chip
*fpc
)
302 if (fpc
->use_count
!= 0)
305 /* select counter clock source */
306 regmap_update_bits(fpc
->regmap
, FTM_SC
, FTM_SC_CLK_MASK
,
307 FTM_SC_CLK(fpc
->cnt_select
));
309 ret
= clk_prepare_enable(fpc
->clk
[fpc
->cnt_select
]);
313 ret
= clk_prepare_enable(fpc
->clk
[FSL_PWM_CLK_CNTEN
]);
315 clk_disable_unprepare(fpc
->clk
[fpc
->cnt_select
]);
324 static int fsl_pwm_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
326 struct fsl_pwm_chip
*fpc
= to_fsl_chip(chip
);
329 mutex_lock(&fpc
->lock
);
330 regmap_update_bits(fpc
->regmap
, FTM_OUTMASK
, BIT(pwm
->hwpwm
), 0);
332 ret
= fsl_counter_clock_enable(fpc
);
333 mutex_unlock(&fpc
->lock
);
338 static void fsl_counter_clock_disable(struct fsl_pwm_chip
*fpc
)
341 * already disabled, do nothing
343 if (fpc
->use_count
== 0)
346 /* there are still users, so can't disable yet */
347 if (--fpc
->use_count
> 0)
350 /* no users left, disable PWM counter clock */
351 regmap_update_bits(fpc
->regmap
, FTM_SC
, FTM_SC_CLK_MASK
, 0);
353 clk_disable_unprepare(fpc
->clk
[FSL_PWM_CLK_CNTEN
]);
354 clk_disable_unprepare(fpc
->clk
[fpc
->cnt_select
]);
357 static void fsl_pwm_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
359 struct fsl_pwm_chip
*fpc
= to_fsl_chip(chip
);
362 mutex_lock(&fpc
->lock
);
363 regmap_update_bits(fpc
->regmap
, FTM_OUTMASK
, BIT(pwm
->hwpwm
),
366 fsl_counter_clock_disable(fpc
);
368 regmap_read(fpc
->regmap
, FTM_OUTMASK
, &val
);
369 if ((val
& 0xFF) == 0xFF)
372 mutex_unlock(&fpc
->lock
);
375 static const struct pwm_ops fsl_pwm_ops
= {
376 .request
= fsl_pwm_request
,
377 .free
= fsl_pwm_free
,
378 .config
= fsl_pwm_config
,
379 .set_polarity
= fsl_pwm_set_polarity
,
380 .enable
= fsl_pwm_enable
,
381 .disable
= fsl_pwm_disable
,
382 .owner
= THIS_MODULE
,
385 static int fsl_pwm_init(struct fsl_pwm_chip
*fpc
)
389 ret
= clk_prepare_enable(fpc
->clk
[FSL_PWM_CLK_SYS
]);
393 regmap_write(fpc
->regmap
, FTM_CNTIN
, 0x00);
394 regmap_write(fpc
->regmap
, FTM_OUTINIT
, 0x00);
395 regmap_write(fpc
->regmap
, FTM_OUTMASK
, 0xFF);
397 clk_disable_unprepare(fpc
->clk
[FSL_PWM_CLK_SYS
]);
402 static const struct regmap_config fsl_pwm_regmap_config
= {
407 .max_register
= FTM_PWMLOAD
,
410 static int fsl_pwm_probe(struct platform_device
*pdev
)
412 struct fsl_pwm_chip
*fpc
;
413 struct resource
*res
;
417 fpc
= devm_kzalloc(&pdev
->dev
, sizeof(*fpc
), GFP_KERNEL
);
421 mutex_init(&fpc
->lock
);
423 fpc
->chip
.dev
= &pdev
->dev
;
425 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
426 base
= devm_ioremap_resource(&pdev
->dev
, res
);
428 return PTR_ERR(base
);
430 fpc
->regmap
= devm_regmap_init_mmio_clk(&pdev
->dev
, NULL
, base
,
431 &fsl_pwm_regmap_config
);
432 if (IS_ERR(fpc
->regmap
)) {
433 dev_err(&pdev
->dev
, "regmap init failed\n");
434 return PTR_ERR(fpc
->regmap
);
437 fpc
->clk
[FSL_PWM_CLK_SYS
] = devm_clk_get(&pdev
->dev
, "ftm_sys");
438 if (IS_ERR(fpc
->clk
[FSL_PWM_CLK_SYS
])) {
439 dev_err(&pdev
->dev
, "failed to get \"ftm_sys\" clock\n");
440 return PTR_ERR(fpc
->clk
[FSL_PWM_CLK_SYS
]);
443 fpc
->clk
[FSL_PWM_CLK_FIX
] = devm_clk_get(fpc
->chip
.dev
, "ftm_fix");
444 if (IS_ERR(fpc
->clk
[FSL_PWM_CLK_FIX
]))
445 return PTR_ERR(fpc
->clk
[FSL_PWM_CLK_FIX
]);
447 fpc
->clk
[FSL_PWM_CLK_EXT
] = devm_clk_get(fpc
->chip
.dev
, "ftm_ext");
448 if (IS_ERR(fpc
->clk
[FSL_PWM_CLK_EXT
]))
449 return PTR_ERR(fpc
->clk
[FSL_PWM_CLK_EXT
]);
451 fpc
->clk
[FSL_PWM_CLK_CNTEN
] =
452 devm_clk_get(fpc
->chip
.dev
, "ftm_cnt_clk_en");
453 if (IS_ERR(fpc
->clk
[FSL_PWM_CLK_CNTEN
]))
454 return PTR_ERR(fpc
->clk
[FSL_PWM_CLK_CNTEN
]);
456 fpc
->chip
.ops
= &fsl_pwm_ops
;
457 fpc
->chip
.of_xlate
= of_pwm_xlate_with_flags
;
458 fpc
->chip
.of_pwm_n_cells
= 3;
461 fpc
->chip
.can_sleep
= true;
463 ret
= pwmchip_add(&fpc
->chip
);
465 dev_err(&pdev
->dev
, "failed to add PWM chip: %d\n", ret
);
469 platform_set_drvdata(pdev
, fpc
);
471 return fsl_pwm_init(fpc
);
474 static int fsl_pwm_remove(struct platform_device
*pdev
)
476 struct fsl_pwm_chip
*fpc
= platform_get_drvdata(pdev
);
478 return pwmchip_remove(&fpc
->chip
);
481 static const struct of_device_id fsl_pwm_dt_ids
[] = {
482 { .compatible
= "fsl,vf610-ftm-pwm", },
485 MODULE_DEVICE_TABLE(of
, fsl_pwm_dt_ids
);
487 static struct platform_driver fsl_pwm_driver
= {
489 .name
= "fsl-ftm-pwm",
490 .of_match_table
= fsl_pwm_dt_ids
,
492 .probe
= fsl_pwm_probe
,
493 .remove
= fsl_pwm_remove
,
495 module_platform_driver(fsl_pwm_driver
);
497 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
498 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
499 MODULE_ALIAS("platform:fsl-ftm-pwm");
500 MODULE_LICENSE("GPL");